From 0f10a5d8f5be3a9dc23411fe9c05987f7f80384b Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 8 Oct 2022 10:10:30 +0200 Subject: [PATCH 01/29] Initial commit --- LICENSE | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..4818f98 --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2022 Zig Embedded Group + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. From 58cfb98e80f8826980338a7c557d6fde6f9801f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sat, 8 Oct 2022 10:16:46 +0200 Subject: [PATCH 02/29] Initial vomit: not working at all, basic docs. --- .gitattributes | 1 + .github/FUNDING.yml | 1 + .gitignore | 2 ++ .gitmodules | 3 +++ README.md | 1 + build.zig | 34 ++++++++++++++++++++++++++++++++++ docs/esp32-c3-32s-pinout.png | Bin 0 -> 228243 bytes docs/esp32-c3-32s-pinout.xcf | Bin 0 -> 937723 bytes src/main.zig | 24 ++++++++++++++++++++++++ vendor/microzig | 1 + zpm.zig | 8 ++++++++ 11 files changed, 75 insertions(+) create mode 100644 .gitattributes create mode 100644 .github/FUNDING.yml create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 README.md create mode 100644 build.zig create mode 100644 docs/esp32-c3-32s-pinout.png create mode 100644 docs/esp32-c3-32s-pinout.xcf create mode 100644 src/main.zig create mode 160000 vendor/microzig create mode 100644 zpm.zig diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..0cb064a --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +*.zig text=auto eol=lf diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 0000000..85b5393 --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1 @@ +github: MasterQ32 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e73c965 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-cache/ +zig-out/ diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..54620ef --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "vendor/microzig"] + path = vendor/microzig + url = https://github.com/ZigEmbeddedGroup/microzig diff --git a/README.md b/README.md new file mode 100644 index 0000000..2cd0dfa --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +# esp32-c3-bringup diff --git a/build.zig b/build.zig new file mode 100644 index 0000000..035b12a --- /dev/null +++ b/build.zig @@ -0,0 +1,34 @@ +const std = @import("std"); + +pub fn build(b: *std.build.Builder) void { + // Standard target options allows the person running `zig build` to choose + // what target to build for. Here we do not override the defaults, which + // means any target is allowed, and the default is native. Other options + // for restricting supported target set are available. + const target = b.standardTargetOptions(.{}); + + // Standard release options allow the person running `zig build` to select + // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall. + const mode = b.standardReleaseOptions(); + + const exe = b.addExecutable("esp32-c3-bringup", "src/main.zig"); + exe.setTarget(target); + exe.setBuildMode(mode); + exe.install(); + + const run_cmd = exe.run(); + run_cmd.step.dependOn(b.getInstallStep()); + if (b.args) |args| { + run_cmd.addArgs(args); + } + + const run_step = b.step("run", "Run the app"); + run_step.dependOn(&run_cmd.step); + + const exe_tests = b.addTest("src/main.zig"); + exe_tests.setTarget(target); + exe_tests.setBuildMode(mode); + + const test_step = b.step("test", "Run unit tests"); + test_step.dependOn(&exe_tests.step); +} diff --git a/docs/esp32-c3-32s-pinout.png b/docs/esp32-c3-32s-pinout.png new file mode 100644 index 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zmM1+N#Sj2JMSPH_&UKFNf92sH-}pD~GKa1Gjt_Ven#vXVo&){;hxYw($ELM6p6x0%
zD#43(MM(hF&>8u$hyH#0j^{V8UH#1~mwV=(;PZU`1-aws@NcaC?poaCZPQAzRZBi^XhG30WWEa$r8@{bzL>J~p6i36{*Nl3(VF_n}^8EXn_$
z{**KR#7`N&|6l&-Zq2V6|0$uqgHn;olER-ge5RU6`*S*fuO9#1!@sAE|8C@8xBUKJ
DjLf+c

literal 0
HcmV?d00001

diff --git a/src/main.zig b/src/main.zig
new file mode 100644
index 0000000..c8a3f67
--- /dev/null
+++ b/src/main.zig
@@ -0,0 +1,24 @@
+const std = @import("std");
+
+pub fn main() !void {
+    // Prints to stderr (it's a shortcut based on `std.io.getStdErr()`)
+    std.debug.print("All your {s} are belong to us.\n", .{"codebase"});
+
+    // stdout is for the actual output of your application, for example if you
+    // are implementing gzip, then only the compressed bytes should be sent to
+    // stdout, not any debugging messages.
+    const stdout_file = std.io.getStdOut().writer();
+    var bw = std.io.bufferedWriter(stdout_file);
+    const stdout = bw.writer();
+
+    try stdout.print("Run `zig build test` to run the tests.\n", .{});
+
+    try bw.flush(); // don't forget to flush!
+}
+
+test "simple test" {
+    var list = std.ArrayList(i32).init(std.testing.allocator);
+    defer list.deinit(); // try commenting this out and see if zig detects the memory leak!
+    try list.append(42);
+    try std.testing.expectEqual(@as(i32, 42), list.pop());
+}
diff --git a/vendor/microzig b/vendor/microzig
new file mode 160000
index 0000000..15bc1fc
--- /dev/null
+++ b/vendor/microzig
@@ -0,0 +1 @@
+Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1
diff --git a/zpm.zig b/zpm.zig
new file mode 100644
index 0000000..1dcd7b3
--- /dev/null
+++ b/zpm.zig
@@ -0,0 +1,8 @@
+//! This file is auto-generated by zpm-update and *should*
+//! not be changed. This file can be checked into your VCS
+//! and is able to work standalone.
+const std = @import("std");
+
+pub const sdks = struct {
+    pub const microzig = @import("vendor/microzig/src/main.zig");
+};

From e1e525a50d562ec1d1687491f7cdd0a109343ccf Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 8 Oct 2022 11:25:01 +0200
Subject: [PATCH 03/29] conflict fixed

---
 .gitignore      |     4 +-
 README.adoc     |     5 +
 esp32c3.svd     | 36932 ++++++++++++++++++++++++++++++++++++++++++++
 src/esp32c3.zig | 37956 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 74895 insertions(+), 2 deletions(-)
 create mode 100644 README.adoc
 create mode 100644 esp32c3.svd
 create mode 100644 src/esp32c3.zig

diff --git a/.gitignore b/.gitignore
index e73c965..c26d4af 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,2 @@
-zig-cache/
-zig-out/
+zig-out
+zig-cache
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 0000000..65801a9
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,5 @@
+= ESP MicroZig Package
+
+[WIP]
+
+SVD is copied from https://github.com/esp-rs/esp-pacs
diff --git a/esp32c3.svd b/esp32c3.svd
new file mode 100644
index 0000000..ab064fa
--- /dev/null
+++ b/esp32c3.svd
@@ -0,0 +1,36932 @@
+
+
+  ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
+  ESPRESSIF
+  ESP32-C3
+  ESP32-C3
+  8
+  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
+  
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+
+  
+    RV32IMC
+    r0p0
+    little
+    false
+    false
+    4
+    false
+  
+  32
+  32
+  0x00000000
+  0xFFFFFFFF
+  
+    
+      AES
+      AES (Advanced Encryption Standard) Accelerator
+      AES
+      0x6003A000
+      
+        0x0
+        0xBC
+        registers
+      
+      
+        AES
+        48
+      
+      
+        
+          KEY_0
+          Key material key_0 configure register
+          0x0
+          0x20
+          
+            
+              KEY_0
+              This bits stores key_0 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_1
+          Key material key_1 configure register
+          0x4
+          0x20
+          
+            
+              KEY_1
+              This bits stores key_1 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_2
+          Key material key_2 configure register
+          0x8
+          0x20
+          
+            
+              KEY_2
+              This bits stores key_2 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_3
+          Key material key_3 configure register
+          0xC
+          0x20
+          
+            
+              KEY_3
+              This bits stores key_3 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_4
+          Key material key_4 configure register
+          0x10
+          0x20
+          
+            
+              KEY_4
+              This bits stores key_4 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_5
+          Key material key_5 configure register
+          0x14
+          0x20
+          
+            
+              KEY_5
+              This bits stores key_5 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_6
+          Key material key_6 configure register
+          0x18
+          0x20
+          
+            
+              KEY_6
+              This bits stores key_6 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_7
+          Key material key_7 configure register
+          0x1C
+          0x20
+          
+            
+              KEY_7
+              This bits stores key_7 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_0
+          source text material text_in_0 configure register
+          0x20
+          0x20
+          
+            
+              TEXT_IN_0
+              This bits stores text_in_0 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_1
+          source text material text_in_1 configure register
+          0x24
+          0x20
+          
+            
+              TEXT_IN_1
+              This bits stores text_in_1 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_2
+          source text material text_in_2 configure register
+          0x28
+          0x20
+          
+            
+              TEXT_IN_2
+              This bits stores text_in_2 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_3
+          source text material text_in_3 configure register
+          0x2C
+          0x20
+          
+            
+              TEXT_IN_3
+              This bits stores text_in_3 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_0
+          result text material text_out_0 configure register
+          0x30
+          0x20
+          
+            
+              TEXT_OUT_0
+              This bits stores text_out_0 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_1
+          result text material text_out_1 configure register
+          0x34
+          0x20
+          
+            
+              TEXT_OUT_1
+              This bits stores text_out_1 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_2
+          result text material text_out_2 configure register
+          0x38
+          0x20
+          
+            
+              TEXT_OUT_2
+              This bits stores text_out_2 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_3
+          result text material text_out_3 configure register
+          0x3C
+          0x20
+          
+            
+              TEXT_OUT_3
+              This bits stores text_out_3 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          MODE
+          AES Mode register
+          0x40
+          0x20
+          
+            
+              MODE
+              This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          ENDIAN
+          AES Endian configure register
+          0x44
+          0x20
+          
+            
+              ENDIAN
+              endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian
+              0
+              6
+              read-write
+            
+          
+        
+        
+          TRIGGER
+          AES trigger register
+          0x48
+          0x20
+          
+            
+              TRIGGER
+              Set this bit to start AES calculation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          STATE
+          AES state register
+          0x4C
+          0x20
+          
+            
+              STATE
+              Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
+              0
+              2
+              read-only
+            
+          
+        
+        
+          16
+          0x1
+          IV_MEM[%s]
+          The memory that stores initialization vector
+          0x50
+          0x8
+        
+        
+          16
+          0x1
+          H_MEM[%s]
+          The memory that stores GCM hash subkey
+          0x60
+          0x8
+        
+        
+          16
+          0x1
+          J0_MEM[%s]
+          The memory that stores J0
+          0x70
+          0x8
+        
+        
+          16
+          0x1
+          T0_MEM[%s]
+          The memory that stores T0
+          0x80
+          0x8
+        
+        
+          DMA_ENABLE
+          DMA-AES working mode register
+          0x90
+          0x20
+          
+            
+              DMA_ENABLE
+              1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BLOCK_MODE
+          AES cipher block mode register
+          0x94
+          0x20
+          
+            
+              BLOCK_MODE
+              Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BLOCK_NUM
+          AES block number register
+          0x98
+          0x20
+          
+            
+              BLOCK_NUM
+              Those bits stores the number of Plaintext/ciphertext block.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          INC_SEL
+          Standard incrementing function configure register
+          0x9C
+          0x20
+          
+            
+              INC_SEL
+              This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          AAD_BLOCK_NUM
+          Additional Authential Data block number register
+          0xA0
+          0x20
+          
+            
+              AAD_BLOCK_NUM
+              Those bits stores the number of AAD block.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REMAINDER_BIT_NUM
+          AES remainder bit number register
+          0xA4
+          0x20
+          
+            
+              REMAINDER_BIT_NUM
+              Those bits stores the number of remainder bit.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CONTINUE
+          AES continue register
+          0xA8
+          0x20
+          
+            
+              CONTINUE
+              Set this bit to continue GCM operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_CLEAR
+          AES Interrupt clear register
+          0xAC
+          0x20
+          
+            
+              INT_CLEAR
+              Set this bit to clear the AES interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          AES Interrupt enable register
+          0xB0
+          0x20
+          
+            
+              INT_ENA
+              Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          AES version control register
+          0xB4
+          0x20
+          0x20191210
+          
+            
+              DATE
+              This bits stores the version information of AES.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          DMA_EXIT
+          AES-DMA exit config
+          0xB8
+          0x20
+          
+            
+              DMA_EXIT
+              Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
+              0
+              1
+              write-only
+            
+          
+        
+      
+    
+    
+      APB_CTRL
+      Advanced Peripheral Bus Controller
+      APB_CTRL
+      0x60026000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          SYSCLK_CONF
+          APB_CTRL_SYSCLK_CONF_REG
+          0x0
+          0x20
+          0x00000001
+          
+            
+              PRE_DIV_CNT
+              reg_pre_div_cnt
+              0
+              10
+              read-write
+            
+            
+              CLK_320M_EN
+              reg_clk_320m_en
+              10
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              11
+              1
+              read-write
+            
+            
+              RST_TICK_CNT
+              reg_rst_tick_cnt
+              12
+              1
+              read-write
+            
+          
+        
+        
+          TICK_CONF
+          APB_CTRL_TICK_CONF_REG
+          0x4
+          0x20
+          0x00010727
+          
+            
+              XTAL_TICK_NUM
+              reg_xtal_tick_num
+              0
+              8
+              read-write
+            
+            
+              CK8M_TICK_NUM
+              reg_ck8m_tick_num
+              8
+              8
+              read-write
+            
+            
+              TICK_ENABLE
+              reg_tick_enable
+              16
+              1
+              read-write
+            
+          
+        
+        
+          CLK_OUT_EN
+          APB_CTRL_CLK_OUT_EN_REG
+          0x8
+          0x20
+          0x000007FF
+          
+            
+              CLK20_OEN
+              reg_clk20_oen
+              0
+              1
+              read-write
+            
+            
+              CLK22_OEN
+              reg_clk22_oen
+              1
+              1
+              read-write
+            
+            
+              CLK44_OEN
+              reg_clk44_oen
+              2
+              1
+              read-write
+            
+            
+              CLK_BB_OEN
+              reg_clk_bb_oen
+              3
+              1
+              read-write
+            
+            
+              CLK80_OEN
+              reg_clk80_oen
+              4
+              1
+              read-write
+            
+            
+              CLK160_OEN
+              reg_clk160_oen
+              5
+              1
+              read-write
+            
+            
+              CLK_320M_OEN
+              reg_clk_320m_oen
+              6
+              1
+              read-write
+            
+            
+              CLK_ADC_INF_OEN
+              reg_clk_adc_inf_oen
+              7
+              1
+              read-write
+            
+            
+              CLK_DAC_CPU_OEN
+              reg_clk_dac_cpu_oen
+              8
+              1
+              read-write
+            
+            
+              CLK40X_BB_OEN
+              reg_clk40x_bb_oen
+              9
+              1
+              read-write
+            
+            
+              CLK_XTAL_OEN
+              reg_clk_xtal_oen
+              10
+              1
+              read-write
+            
+          
+        
+        
+          WIFI_BB_CFG
+          APB_CTRL_WIFI_BB_CFG_REG
+          0xC
+          0x20
+          
+            
+              WIFI_BB_CFG
+              reg_wifi_bb_cfg
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_BB_CFG_2
+          APB_CTRL_WIFI_BB_CFG_2_REG
+          0x10
+          0x20
+          
+            
+              WIFI_BB_CFG_2
+              reg_wifi_bb_cfg_2
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_CLK_EN
+          APB_CTRL_WIFI_CLK_EN_REG
+          0x14
+          0x20
+          0xFFFCE030
+          
+            
+              WIFI_CLK_EN
+              reg_wifi_clk_en
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_RST_EN
+          APB_CTRL_WIFI_RST_EN_REG
+          0x18
+          0x20
+          
+            
+              WIFI_RST
+              reg_wifi_rst
+              0
+              32
+              read-write
+            
+          
+        
+        
+          HOST_INF_SEL
+          APB_CTRL_HOST_INF_SEL_REG
+          0x1C
+          0x20
+          
+            
+              PERI_IO_SWAP
+              reg_peri_io_swap
+              0
+              8
+              read-write
+            
+          
+        
+        
+          EXT_MEM_PMS_LOCK
+          APB_CTRL_EXT_MEM_PMS_LOCK_REG
+          0x20
+          0x20
+          
+            
+              EXT_MEM_PMS_LOCK
+              reg_ext_mem_pms_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_ATTR
+          APB_CTRL_FLASH_ACE0_ATTR_REG
+          0x28
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE0_ATTR
+              reg_flash_ace0_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_ATTR
+          APB_CTRL_FLASH_ACE1_ATTR_REG
+          0x2C
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE1_ATTR
+              reg_flash_ace1_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_ATTR
+          APB_CTRL_FLASH_ACE2_ATTR_REG
+          0x30
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE2_ATTR
+              reg_flash_ace2_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_ATTR
+          APB_CTRL_FLASH_ACE3_ATTR_REG
+          0x34
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE3_ATTR
+              reg_flash_ace3_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_ADDR
+          APB_CTRL_FLASH_ACE0_ADDR_REG
+          0x38
+          0x20
+          
+            
+              S
+              reg_flash_ace0_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_ADDR
+          APB_CTRL_FLASH_ACE1_ADDR_REG
+          0x3C
+          0x20
+          0x00400000
+          
+            
+              S
+              reg_flash_ace1_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_ADDR
+          APB_CTRL_FLASH_ACE2_ADDR_REG
+          0x40
+          0x20
+          0x00800000
+          
+            
+              S
+              reg_flash_ace2_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_ADDR
+          APB_CTRL_FLASH_ACE3_ADDR_REG
+          0x44
+          0x20
+          0x00C00000
+          
+            
+              S
+              reg_flash_ace3_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_SIZE
+          APB_CTRL_FLASH_ACE0_SIZE_REG
+          0x48
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE0_SIZE
+              reg_flash_ace0_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_SIZE
+          APB_CTRL_FLASH_ACE1_SIZE_REG
+          0x4C
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE1_SIZE
+              reg_flash_ace1_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_SIZE
+          APB_CTRL_FLASH_ACE2_SIZE_REG
+          0x50
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE2_SIZE
+              reg_flash_ace2_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_SIZE
+          APB_CTRL_FLASH_ACE3_SIZE_REG
+          0x54
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE3_SIZE
+              reg_flash_ace3_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          SPI_MEM_PMS_CTRL
+          APB_CTRL_SPI_MEM_PMS_CTRL_REG
+          0x88
+          0x20
+          
+            
+              SPI_MEM_REJECT_INT
+              reg_spi_mem_reject_int
+              0
+              1
+              read-only
+            
+            
+              SPI_MEM_REJECT_CLR
+              reg_spi_mem_reject_clr
+              1
+              1
+              write-only
+            
+            
+              SPI_MEM_REJECT_CDE
+              reg_spi_mem_reject_cde
+              2
+              5
+              read-only
+            
+          
+        
+        
+          SPI_MEM_REJECT_ADDR
+          APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+          0x8C
+          0x20
+          
+            
+              SPI_MEM_REJECT_ADDR
+              reg_spi_mem_reject_addr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SDIO_CTRL
+          APB_CTRL_SDIO_CTRL_REG
+          0x90
+          0x20
+          
+            
+              SDIO_WIN_ACCESS_EN
+              reg_sdio_win_access_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REDCY_SIG0
+          APB_CTRL_REDCY_SIG0_REG
+          0x94
+          0x20
+          
+            
+              REDCY_SIG0
+              reg_redcy_sig0
+              0
+              31
+              read-write
+            
+            
+              REDCY_ANDOR
+              reg_redcy_andor
+              31
+              1
+              read-only
+            
+          
+        
+        
+          REDCY_SIG1
+          APB_CTRL_REDCY_SIG1_REG
+          0x98
+          0x20
+          
+            
+              REDCY_SIG1
+              reg_redcy_sig1
+              0
+              31
+              read-write
+            
+            
+              REDCY_NANDOR
+              reg_redcy_nandor
+              31
+              1
+              read-only
+            
+          
+        
+        
+          FRONT_END_MEM_PD
+          APB_CTRL_FRONT_END_MEM_PD_REG
+          0x9C
+          0x20
+          0x00000015
+          
+            
+              AGC_MEM_FORCE_PU
+              reg_agc_mem_force_pu
+              0
+              1
+              read-write
+            
+            
+              AGC_MEM_FORCE_PD
+              reg_agc_mem_force_pd
+              1
+              1
+              read-write
+            
+            
+              PBUS_MEM_FORCE_PU
+              reg_pbus_mem_force_pu
+              2
+              1
+              read-write
+            
+            
+              PBUS_MEM_FORCE_PD
+              reg_pbus_mem_force_pd
+              3
+              1
+              read-write
+            
+            
+              DC_MEM_FORCE_PU
+              reg_dc_mem_force_pu
+              4
+              1
+              read-write
+            
+            
+              DC_MEM_FORCE_PD
+              reg_dc_mem_force_pd
+              5
+              1
+              read-write
+            
+          
+        
+        
+          RETENTION_CTRL
+          APB_CTRL_RETENTION_CTRL_REG
+          0xA0
+          0x20
+          
+            
+              RETENTION_LINK_ADDR
+              reg_retention_link_addr
+              0
+              27
+              read-write
+            
+            
+              NOBYPASS_CPU_ISO_RST
+              reg_nobypass_cpu_iso_rst
+              27
+              1
+              read-write
+            
+          
+        
+        
+          CLKGATE_FORCE_ON
+          APB_CTRL_CLKGATE_FORCE_ON_REG
+          0xA4
+          0x20
+          0x0000003F
+          
+            
+              ROM_CLKGATE_FORCE_ON
+              reg_rom_clkgate_force_on
+              0
+              2
+              read-write
+            
+            
+              SRAM_CLKGATE_FORCE_ON
+              reg_sram_clkgate_force_on
+              2
+              4
+              read-write
+            
+          
+        
+        
+          MEM_POWER_DOWN
+          APB_CTRL_MEM_POWER_DOWN_REG
+          0xA8
+          0x20
+          
+            
+              ROM_POWER_DOWN
+              reg_rom_power_down
+              0
+              2
+              read-write
+            
+            
+              SRAM_POWER_DOWN
+              reg_sram_power_down
+              2
+              4
+              read-write
+            
+          
+        
+        
+          MEM_POWER_UP
+          APB_CTRL_MEM_POWER_UP_REG
+          0xAC
+          0x20
+          0x0000003F
+          
+            
+              ROM_POWER_UP
+              reg_rom_power_up
+              0
+              2
+              read-write
+            
+            
+              SRAM_POWER_UP
+              reg_sram_power_up
+              2
+              4
+              read-write
+            
+          
+        
+        
+          RND_DATA
+          APB_CTRL_RND_DATA_REG
+          0xB0
+          0x20
+          
+            
+              RND_DATA
+              reg_rnd_data
+              0
+              32
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_CONFIG
+          APB_CTRL_PERI_BACKUP_CONFIG_REG
+          0xB4
+          0x20
+          0x00006480
+          
+            
+              PERI_BACKUP_FLOW_ERR
+              reg_peri_backup_flow_err
+              1
+              2
+              read-only
+            
+            
+              PERI_BACKUP_BURST_LIMIT
+              reg_peri_backup_burst_limit
+              4
+              5
+              read-write
+            
+            
+              PERI_BACKUP_TOUT_THRES
+              reg_peri_backup_tout_thres
+              9
+              10
+              read-write
+            
+            
+              PERI_BACKUP_SIZE
+              reg_peri_backup_size
+              19
+              10
+              read-write
+            
+            
+              PERI_BACKUP_START
+              reg_peri_backup_start
+              29
+              1
+              write-only
+            
+            
+              PERI_BACKUP_TO_MEM
+              reg_peri_backup_to_mem
+              30
+              1
+              read-write
+            
+            
+              PERI_BACKUP_ENA
+              reg_peri_backup_ena
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_APB_ADDR
+          APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+          0xB8
+          0x20
+          
+            
+              BACKUP_APB_START_ADDR
+              reg_backup_apb_start_addr
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_MEM_ADDR
+          APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+          0xBC
+          0x20
+          
+            
+              BACKUP_MEM_START_ADDR
+              reg_backup_mem_start_addr
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_INT_RAW
+          APB_CTRL_PERI_BACKUP_INT_RAW_REG
+          0xC0
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_RAW
+              reg_peri_backup_done_int_raw
+              0
+              1
+              read-only
+            
+            
+              PERI_BACKUP_ERR_INT_RAW
+              reg_peri_backup_err_int_raw
+              1
+              1
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_INT_ST
+          APB_CTRL_PERI_BACKUP_INT_ST_REG
+          0xC4
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_ST
+              reg_peri_backup_done_int_st
+              0
+              1
+              read-only
+            
+            
+              PERI_BACKUP_ERR_INT_ST
+              reg_peri_backup_err_int_st
+              1
+              1
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_INT_ENA
+          APB_CTRL_PERI_BACKUP_INT_ENA_REG
+          0xC8
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_ENA
+              reg_peri_backup_done_int_ena
+              0
+              1
+              read-write
+            
+            
+              PERI_BACKUP_ERR_INT_ENA
+              reg_peri_backup_err_int_ena
+              1
+              1
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_INT_CLR
+          APB_CTRL_PERI_BACKUP_INT_CLR_REG
+          0xD0
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_CLR
+              reg_peri_backup_done_int_clr
+              0
+              1
+              write-only
+            
+            
+              PERI_BACKUP_ERR_INT_CLR
+              reg_peri_backup_err_int_clr
+              1
+              1
+              write-only
+            
+          
+        
+        
+          DATE
+          APB_CTRL_DATE_REG
+          0x3FC
+          0x20
+          0x02007210
+          
+            
+              DATE
+              reg_dateVersion control
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      APB_SARADC
+      Successive Approximation Register Analog to Digital Converter
+      APB_SARADC
+      0x60040000
+      
+        0x0
+        0x68
+        registers
+      
+      
+        APB_ADC
+        43
+      
+      
+        
+          CTRL
+          digital saradc configure register
+          0x0
+          0x20
+          0x40038240
+          
+            
+              SARADC_START_FORCE
+              select software enable saradc sample
+              0
+              1
+              read-write
+            
+            
+              SARADC_START
+              software enable saradc sample
+              1
+              1
+              read-write
+            
+            
+              SARADC_SAR_CLK_GATED
+              SAR clock gated
+              6
+              1
+              read-write
+            
+            
+              SARADC_SAR_CLK_DIV
+              SAR clock divider
+              7
+              8
+              read-write
+            
+            
+              SARADC_SAR_PATT_LEN
+              0 ~ 15 means length 1 ~ 16
+              15
+              3
+              read-write
+            
+            
+              SARADC_SAR_PATT_P_CLEAR
+              clear the pointer of pattern table for DIG ADC1 CTRL
+              23
+              1
+              read-write
+            
+            
+              SARADC_XPD_SAR_FORCE
+              force option to xpd sar blocks
+              27
+              2
+              read-write
+            
+            
+              SARADC_WAIT_ARB_CYCLE
+              wait arbit signal stable after sar_done
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CTRL2
+          digital saradc configure register
+          0x4
+          0x20
+          0x0000A1FE
+          
+            
+              SARADC_MEAS_NUM_LIMIT
+              enable max meas num
+              0
+              1
+              read-write
+            
+            
+              SARADC_MAX_MEAS_NUM
+              max conversion number
+              1
+              8
+              read-write
+            
+            
+              SARADC_SAR1_INV
+              1: data to DIG ADC1 CTRL is inverted, otherwise not
+              9
+              1
+              read-write
+            
+            
+              SARADC_SAR2_INV
+              1: data to DIG ADC2 CTRL is inverted, otherwise not
+              10
+              1
+              read-write
+            
+            
+              SARADC_TIMER_TARGET
+              to set saradc timer target
+              12
+              12
+              read-write
+            
+            
+              SARADC_TIMER_EN
+              to enable saradc timer trigger
+              24
+              1
+              read-write
+            
+          
+        
+        
+          FILTER_CTRL1
+          digital saradc configure register
+          0x8
+          0x20
+          
+            
+              APB_SARADC_FILTER_FACTOR1
+              Factor of saradc filter1
+              26
+              3
+              read-write
+            
+            
+              APB_SARADC_FILTER_FACTOR0
+              Factor of saradc filter0
+              29
+              3
+              read-write
+            
+          
+        
+        
+          FSM_WAIT
+          digital saradc configure register
+          0xC
+          0x20
+          0x00FF0808
+          
+            
+              SARADC_XPD_WAIT
+              saradc_xpd_wait
+              0
+              8
+              read-write
+            
+            
+              SARADC_RSTB_WAIT
+              saradc_rstb_wait
+              8
+              8
+              read-write
+            
+            
+              SARADC_STANDBY_WAIT
+              saradc_standby_wait
+              16
+              8
+              read-write
+            
+          
+        
+        
+          SAR1_STATUS
+          digital saradc configure register
+          0x10
+          0x20
+          
+            
+              SARADC_SAR1_STATUS
+              saradc1 status about data and channel
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SAR2_STATUS
+          digital saradc configure register
+          0x14
+          0x20
+          
+            
+              SARADC_SAR2_STATUS
+              saradc2 status about data and channel
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SAR_PATT_TAB1
+          digital saradc configure register
+          0x18
+          0x20
+          
+            
+              SARADC_SAR_PATT_TAB1
+              item 0 ~ 3 for pattern table 1 (each item one byte)
+              0
+              24
+              read-write
+            
+          
+        
+        
+          SAR_PATT_TAB2
+          digital saradc configure register
+          0x1C
+          0x20
+          
+            
+              SARADC_SAR_PATT_TAB2
+              Item 4 ~ 7 for pattern table 1 (each item one byte)
+              0
+              24
+              read-write
+            
+          
+        
+        
+          ONETIME_SAMPLE
+          digital saradc configure register
+          0x20
+          0x20
+          0x1A000000
+          
+            
+              SARADC_ONETIME_ATTEN
+              configure onetime atten
+              23
+              2
+              read-write
+            
+            
+              SARADC_ONETIME_CHANNEL
+              configure onetime channel
+              25
+              4
+              read-write
+            
+            
+              SARADC_ONETIME_START
+              trigger adc onetime sample
+              29
+              1
+              read-write
+            
+            
+              SARADC2_ONETIME_SAMPLE
+              enable adc2 onetime sample
+              30
+              1
+              read-write
+            
+            
+              SARADC1_ONETIME_SAMPLE
+              enable adc1 onetime sample
+              31
+              1
+              read-write
+            
+          
+        
+        
+          ARB_CTRL
+          digital saradc configure register
+          0x24
+          0x20
+          0x00000900
+          
+            
+              ADC_ARB_APB_FORCE
+              adc2 arbiter force to enableapb controller
+              2
+              1
+              read-write
+            
+            
+              ADC_ARB_RTC_FORCE
+              adc2 arbiter force to enable rtc controller
+              3
+              1
+              read-write
+            
+            
+              ADC_ARB_WIFI_FORCE
+              adc2 arbiter force to enable wifi controller
+              4
+              1
+              read-write
+            
+            
+              ADC_ARB_GRANT_FORCE
+              adc2 arbiter force grant
+              5
+              1
+              read-write
+            
+            
+              ADC_ARB_APB_PRIORITY
+              Set adc2 arbiterapb priority
+              6
+              2
+              read-write
+            
+            
+              ADC_ARB_RTC_PRIORITY
+              Set adc2 arbiter rtc priority
+              8
+              2
+              read-write
+            
+            
+              ADC_ARB_WIFI_PRIORITY
+              Set adc2 arbiter wifi priority
+              10
+              2
+              read-write
+            
+            
+              ADC_ARB_FIX_PRIORITY
+              adc2 arbiter uses fixed priority
+              12
+              1
+              read-write
+            
+          
+        
+        
+          FILTER_CTRL0
+          digital saradc configure register
+          0x28
+          0x20
+          0x03740000
+          
+            
+              APB_SARADC_FILTER_CHANNEL1
+              configure filter1 to adc channel
+              18
+              4
+              read-write
+            
+            
+              APB_SARADC_FILTER_CHANNEL0
+              configure filter0 to adc channel
+              22
+              4
+              read-write
+            
+            
+              APB_SARADC_FILTER_RESET
+              enable apb_adc1_filter
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SAR1DATA_STATUS
+          digital saradc configure register
+          0x2C
+          0x20
+          
+            
+              APB_SARADC1_DATA
+              saradc1 data
+              0
+              17
+              read-only
+            
+          
+        
+        
+          SAR2DATA_STATUS
+          digital saradc configure register
+          0x30
+          0x20
+          
+            
+              APB_SARADC2_DATA
+              saradc2 data
+              0
+              17
+              read-only
+            
+          
+        
+        
+          THRES0_CTRL
+          digital saradc configure register
+          0x34
+          0x20
+          0x0003FFED
+          
+            
+              APB_SARADC_THRES0_CHANNEL
+              configure thres0 to adc channel
+              0
+              4
+              read-write
+            
+            
+              APB_SARADC_THRES0_HIGH
+              saradc thres0 monitor thres
+              5
+              13
+              read-write
+            
+            
+              APB_SARADC_THRES0_LOW
+              saradc thres0 monitor thres
+              18
+              13
+              read-write
+            
+          
+        
+        
+          THRES1_CTRL
+          digital saradc configure register
+          0x38
+          0x20
+          0x0003FFED
+          
+            
+              APB_SARADC_THRES1_CHANNEL
+              configure thres1 to adc channel
+              0
+              4
+              read-write
+            
+            
+              APB_SARADC_THRES1_HIGH
+              saradc thres1 monitor thres
+              5
+              13
+              read-write
+            
+            
+              APB_SARADC_THRES1_LOW
+              saradc thres1 monitor thres
+              18
+              13
+              read-write
+            
+          
+        
+        
+          THRES_CTRL
+          digital saradc configure register
+          0x3C
+          0x20
+          
+            
+              APB_SARADC_THRES_ALL_EN
+              enable thres to all channel
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES1_EN
+              enable thres1
+              30
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_EN
+              enable thres0
+              31
+              1
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          digital saradc int register
+          0x40
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_ENA
+              saradc thres1 low  interrupt enable
+              26
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_LOW_INT_ENA
+              saradc thres0 low interrupt enable
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_ENA
+              saradc thres1 high interrupt enable
+              28
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_ENA
+              saradc thres0 high interrupt enable
+              29
+              1
+              read-write
+            
+            
+              APB_SARADC2_DONE_INT_ENA
+              saradc2 done interrupt enable
+              30
+              1
+              read-write
+            
+            
+              APB_SARADC1_DONE_INT_ENA
+              saradc1 done interrupt enable
+              31
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          digital saradc int register
+          0x44
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_RAW
+              saradc thres1 low  interrupt raw
+              26
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_RAW
+              saradc thres0 low interrupt raw
+              27
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_RAW
+              saradc thres1 high interrupt raw
+              28
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_RAW
+              saradc thres0 high interrupt raw
+              29
+              1
+              read-only
+            
+            
+              APB_SARADC2_DONE_INT_RAW
+              saradc2 done interrupt raw
+              30
+              1
+              read-only
+            
+            
+              APB_SARADC1_DONE_INT_RAW
+              saradc1 done interrupt raw
+              31
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          digital saradc int register
+          0x48
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_ST
+              saradc thres1 low  interrupt state
+              26
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_ST
+              saradc thres0 low interrupt state
+              27
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_ST
+              saradc thres1 high interrupt state
+              28
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_ST
+              saradc thres0 high interrupt state
+              29
+              1
+              read-only
+            
+            
+              APB_SARADC2_DONE_INT_ST
+              saradc2 done interrupt state
+              30
+              1
+              read-only
+            
+            
+              APB_SARADC1_DONE_INT_ST
+              saradc1 done interrupt state
+              31
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          digital saradc int register
+          0x4C
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_CLR
+              saradc thres1 low  interrupt clear
+              26
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_CLR
+              saradc thres0 low interrupt clear
+              27
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_CLR
+              saradc thres1 high interrupt clear
+              28
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_CLR
+              saradc thres0 high interrupt clear
+              29
+              1
+              write-only
+            
+            
+              APB_SARADC2_DONE_INT_CLR
+              saradc2 done interrupt clear
+              30
+              1
+              write-only
+            
+            
+              APB_SARADC1_DONE_INT_CLR
+              saradc1 done interrupt clear
+              31
+              1
+              write-only
+            
+          
+        
+        
+          DMA_CONF
+          digital saradc configure register
+          0x50
+          0x20
+          0x000000FF
+          
+            
+              APB_ADC_EOF_NUM
+              the dma_in_suc_eof gen when sample cnt = spi_eof_num
+              0
+              16
+              read-write
+            
+            
+              APB_ADC_RESET_FSM
+              reset_apb_adc_state
+              30
+              1
+              read-write
+            
+            
+              APB_ADC_TRANS
+              enable apb_adc use spi_dma
+              31
+              1
+              read-write
+            
+          
+        
+        
+          CLKM_CONF
+          digital saradc configure register
+          0x54
+          0x20
+          0x00000004
+          
+            
+              CLKM_DIV_NUM
+              Integral I2S clock divider value
+              0
+              8
+              read-write
+            
+            
+              CLKM_DIV_B
+              Fractional clock divider numerator value
+              8
+              6
+              read-write
+            
+            
+              CLKM_DIV_A
+              Fractional clock divider denominator value
+              14
+              6
+              read-write
+            
+            
+              CLK_EN
+              reg clk en
+              20
+              1
+              read-write
+            
+            
+              CLK_SEL
+              Set this bit to enable clk_apll
+              21
+              2
+              read-write
+            
+          
+        
+        
+          APB_TSENS_CTRL
+          digital tsens configure register
+          0x58
+          0x20
+          0x00018000
+          
+            
+              TSENS_OUT
+              temperature sensor data out
+              0
+              8
+              read-only
+            
+            
+              TSENS_IN_INV
+              invert temperature sensor data
+              13
+              1
+              read-write
+            
+            
+              TSENS_CLK_DIV
+              temperature sensor clock divider
+              14
+              8
+              read-write
+            
+            
+              TSENS_PU
+              temperature sensor power up
+              22
+              1
+              read-write
+            
+          
+        
+        
+          TSENS_CTRL2
+          digital tsens configure register
+          0x5C
+          0x20
+          0x00004002
+          
+            
+              TSENS_XPD_WAIT
+              the time that power up tsens need wait
+              0
+              12
+              read-write
+            
+            
+              TSENS_XPD_FORCE
+              force power up tsens
+              12
+              2
+              read-write
+            
+            
+              TSENS_CLK_INV
+              inv tsens clk
+              14
+              1
+              read-write
+            
+            
+              TSENS_CLK_SEL
+              tsens clk select
+              15
+              1
+              read-write
+            
+          
+        
+        
+          CALI
+          digital saradc configure register
+          0x60
+          0x20
+          0x00008000
+          
+            
+              APB_SARADC_CALI_CFG
+              saradc cali factor
+              0
+              17
+              read-write
+            
+          
+        
+        
+          CTRL_DATE
+          version
+          0x3FC
+          0x20
+          0x02007171
+          
+            
+              DATE
+              version
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      ASSIST_DEBUG
+      Debug Assist
+      ASSIST_DEBUG
+      0x600CE000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        ASSIST_DEBUG
+        54
+      
+      
+        
+          C0RE_0_MONTR_ENA
+          ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+          0x0
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_ENA
+              reg_core_0_area_dram0_0_rd_ena
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_ENA
+              reg_core_0_area_dram0_0_wr_ena
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_ENA
+              reg_core_0_area_dram0_1_rd_ena
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_ENA
+              reg_core_0_area_dram0_1_wr_ena
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_ENA
+              reg_core_0_area_pif_0_rd_ena
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_ENA
+              reg_core_0_area_pif_0_wr_ena
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_ENA
+              reg_core_0_area_pif_1_rd_ena
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_ENA
+              reg_core_0_area_pif_1_wr_ena
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_ENA
+              reg_core_0_sp_spill_min_ena
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_ENA
+              reg_core_0_sp_spill_max_ena
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_ENA
+              reg_core_0_iram0_exception_monitor_ena
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_ENA
+              reg_core_0_dram0_exception_monitor_ena
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_INTR_RAW
+          ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+          0x4
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_RAW
+              reg_core_0_area_dram0_0_rd_raw
+              0
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_RAW
+              reg_core_0_area_dram0_0_wr_raw
+              1
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_RAW
+              reg_core_0_area_dram0_1_rd_raw
+              2
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_RAW
+              reg_core_0_area_dram0_1_wr_raw
+              3
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_0_RD_RAW
+              reg_core_0_area_pif_0_rd_raw
+              4
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_0_WR_RAW
+              reg_core_0_area_pif_0_wr_raw
+              5
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_1_RD_RAW
+              reg_core_0_area_pif_1_rd_raw
+              6
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_1_WR_RAW
+              reg_core_0_area_pif_1_wr_raw
+              7
+              1
+              read-only
+            
+            
+              CORE_0_SP_SPILL_MIN_RAW
+              reg_core_0_sp_spill_min_raw
+              8
+              1
+              read-only
+            
+            
+              CORE_0_SP_SPILL_MAX_RAW
+              reg_core_0_sp_spill_max_raw
+              9
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_RAW
+              reg_core_0_iram0_exception_monitor_raw
+              10
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_RAW
+              reg_core_0_dram0_exception_monitor_raw
+              11
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_INTR_ENA
+          ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+          0x8
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_INTR_ENA
+              reg_core_0_area_dram0_0_rd_intr_ena
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_INTR_ENA
+              reg_core_0_area_dram0_0_wr_intr_ena
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_INTR_ENA
+              reg_core_0_area_dram0_1_rd_intr_ena
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_INTR_ENA
+              reg_core_0_area_dram0_1_wr_intr_ena
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_INTR_ENA
+              reg_core_0_area_pif_0_rd_intr_ena
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_INTR_ENA
+              reg_core_0_area_pif_0_wr_intr_ena
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_INTR_ENA
+              reg_core_0_area_pif_1_rd_intr_ena
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_INTR_ENA
+              reg_core_0_area_pif_1_wr_intr_ena
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_INTR_ENA
+              reg_core_0_sp_spill_min_intr_ena
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_INTR_ENA
+              reg_core_0_sp_spill_max_intr_ena
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_RLS
+              reg_core_0_iram0_exception_monitor_ena
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_RLS
+              reg_core_0_dram0_exception_monitor_ena
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_INTR_CLR
+          ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+          0xC
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_CLR
+              reg_core_0_area_dram0_0_rd_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_CLR
+              reg_core_0_area_dram0_0_wr_clr
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_CLR
+              reg_core_0_area_dram0_1_rd_clr
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_CLR
+              reg_core_0_area_dram0_1_wr_clr
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_CLR
+              reg_core_0_area_pif_0_rd_clr
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_CLR
+              reg_core_0_area_pif_0_wr_clr
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_CLR
+              reg_core_0_area_pif_1_rd_clr
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_CLR
+              reg_core_0_area_pif_1_wr_clr
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_CLR
+              reg_core_0_sp_spill_min_clr
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_CLR
+              reg_core_0_sp_spill_max_clr
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_CLR
+              reg_core_0_iram0_exception_monitor_clr
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_CLR
+              reg_core_0_dram0_exception_monitor_clr
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_0_MIN
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+          0x10
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_DRAM0_0_MIN
+              reg_core_0_area_dram0_0_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_0_MAX
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+          0x14
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_MAX
+              reg_core_0_area_dram0_0_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_1_MIN
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+          0x18
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_DRAM0_1_MIN
+              reg_core_0_area_dram0_1_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_1_MAX
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+          0x1C
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_1_MAX
+              reg_core_0_area_dram0_1_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_0_MIN
+          ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+          0x20
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_PIF_0_MIN
+              reg_core_0_area_pif_0_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_0_MAX
+          ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+          0x24
+          0x20
+          
+            
+              CORE_0_AREA_PIF_0_MAX
+              reg_core_0_area_pif_0_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_1_MIN
+          ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+          0x28
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_PIF_1_MIN
+              reg_core_0_area_pif_1_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_1_MAX
+          ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+          0x2C
+          0x20
+          
+            
+              CORE_0_AREA_PIF_1_MAX
+              reg_core_0_area_pif_1_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PC
+          ASSIST_DEBUG_CORE_0_AREA_PC_REG
+          0x30
+          0x20
+          
+            
+              CORE_0_AREA_PC
+              reg_core_0_area_pc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_AREA_SP
+          ASSIST_DEBUG_CORE_0_AREA_SP_REG
+          0x34
+          0x20
+          
+            
+              CORE_0_AREA_SP
+              reg_core_0_area_sp
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_SP_MIN
+          ASSIST_DEBUG_CORE_0_SP_MIN_REG
+          0x38
+          0x20
+          
+            
+              CORE_0_SP_MIN
+              reg_core_0_sp_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_SP_MAX
+          ASSIST_DEBUG_CORE_0_SP_MAX_REG
+          0x3C
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_SP_MAX
+              reg_core_0_sp_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_SP_PC
+          ASSIST_DEBUG_CORE_0_SP_PC_REG
+          0x40
+          0x20
+          
+            
+              CORE_0_SP_PC
+              reg_core_0_sp_pc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_RCD_EN
+          ASSIST_DEBUG_CORE_0_RCD_EN_REG
+          0x44
+          0x20
+          
+            
+              CORE_0_RCD_RECORDEN
+              reg_core_0_rcd_recorden
+              0
+              1
+              read-write
+            
+            
+              CORE_0_RCD_PDEBUGEN
+              reg_core_0_rcd_pdebugen
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_RCD_PDEBUGPC
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+          0x48
+          0x20
+          
+            
+              CORE_0_RCD_PDEBUGPC
+              reg_core_0_rcd_pdebugpc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_RCD_PDEBUGSP
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+          0x4C
+          0x20
+          
+            
+              CORE_0_RCD_PDEBUGSP
+              reg_core_0_rcd_pdebugsp
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_IRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+          0x50
+          0x20
+          
+            
+              CORE_0_IRAM0_RECORDING_ADDR_0
+              reg_core_0_iram0_recording_addr_0
+              0
+              24
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_WR_0
+              reg_core_0_iram0_recording_wr_0
+              24
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_LOADSTORE_0
+              reg_core_0_iram0_recording_loadstore_0
+              25
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_IRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+          0x54
+          0x20
+          
+            
+              CORE_0_IRAM0_RECORDING_ADDR_1
+              reg_core_0_iram0_recording_addr_1
+              0
+              24
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_WR_1
+              reg_core_0_iram0_recording_wr_1
+              24
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_LOADSTORE_1
+              reg_core_0_iram0_recording_loadstore_1
+              25
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+          0x58
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_ADDR_0
+              reg_core_0_dram0_recording_addr_0
+              0
+              24
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_WR_0
+              reg_core_0_dram0_recording_wr_0
+              24
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_BYTEEN_0
+              reg_core_0_dram0_recording_byteen_0
+              25
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x5C
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_PC_0
+              reg_core_0_dram0_recording_pc_0
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_2
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x60
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_ADDR_1
+              reg_core_0_dram0_recording_addr_1
+              0
+              24
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_WR_1
+              reg_core_0_dram0_recording_wr_1
+              24
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_BYTEEN_1
+              reg_core_0_dram0_recording_byteen_1
+              25
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_3
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+          0x64
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_PC_1
+              reg_core_0_dram0_recording_pc_1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+          0x68
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0
+              reg_core_x_iram0_dram0_limit_cycle_0
+              0
+              20
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x6C
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1
+              reg_core_x_iram0_dram0_limit_cycle_1
+              0
+              20
+              read-write
+            
+          
+        
+        
+          LOG_SETTING
+          ASSIST_DEBUG_LOG_SETTING
+          0x70
+          0x20
+          0x00000080
+          
+            
+              LOG_ENA
+              reg_log_ena
+              0
+              3
+              read-write
+            
+            
+              LOG_MODE
+              reg_log_mode
+              3
+              4
+              read-write
+            
+            
+              LOG_MEM_LOOP_ENABLE
+              reg_log_mem_loop_enable
+              7
+              1
+              read-write
+            
+          
+        
+        
+          LOG_DATA_0
+          ASSIST_DEBUG_LOG_DATA_0_REG
+          0x74
+          0x20
+          
+            
+              LOG_DATA_0
+              reg_log_data_0
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_DATA_MASK
+          ASSIST_DEBUG_LOG_DATA_MASK_REG
+          0x78
+          0x20
+          
+            
+              LOG_DATA_SIZE
+              reg_log_data_size
+              0
+              16
+              read-write
+            
+          
+        
+        
+          LOG_MIN
+          ASSIST_DEBUG_LOG_MIN_REG
+          0x7C
+          0x20
+          
+            
+              LOG_MIN
+              reg_log_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MAX
+          ASSIST_DEBUG_LOG_MAX_REG
+          0x80
+          0x20
+          
+            
+              LOG_MAX
+              reg_log_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_START
+          ASSIST_DEBUG_LOG_MEM_START_REG
+          0x84
+          0x20
+          
+            
+              LOG_MEM_START
+              reg_log_mem_start
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_END
+          ASSIST_DEBUG_LOG_MEM_END_REG
+          0x88
+          0x20
+          
+            
+              LOG_MEM_END
+              reg_log_mem_end
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_WRITING_ADDR
+          ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+          0x8C
+          0x20
+          
+            
+              LOG_MEM_WRITING_ADDR
+              reg_log_mem_writing_addr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          LOG_MEM_FULL_FLAG
+          ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+          0x90
+          0x20
+          
+            
+              LOG_MEM_FULL_FLAG
+              reg_log_mem_full_flag
+              0
+              1
+              read-only
+            
+            
+              CLR_LOG_MEM_FULL_FLAG
+              reg_clr_log_mem_full_flag
+              1
+              1
+              read-write
+            
+          
+        
+        
+          C0RE_0_LASTPC_BEFORE_EXCEPTION
+          ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+          0x94
+          0x20
+          
+            
+              CORE_0_LASTPC_BEFORE_EXC
+              reg_core_0_lastpc_before_exc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          C0RE_0_DEBUG_MODE
+          ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+          0x98
+          0x20
+          
+            
+              CORE_0_DEBUG_MODE
+              reg_core_0_debug_mode
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DEBUG_MODULE_ACTIVE
+              reg_core_0_debug_module_active
+              1
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          ASSIST_DEBUG_DATE_REG
+          0x1FC
+          0x20
+          0x02008010
+          
+            
+              ASSIST_DEBUG_DATE
+              reg_assist_debug_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      DMA
+      DMA (Direct Memory Access) Controller
+      DMA
+      0x6003F000
+      
+        0x0
+        0x174
+        registers
+      
+      
+        DMA_CH0
+        44
+      
+      
+        DMA_CH1
+        45
+      
+      
+        DMA_CH2
+        46
+      
+      
+        
+          INT_RAW_CH0
+          DMA_INT_RAW_CH0_REG.
+          0x0
+          0x20
+          
+            
+              IN_DONE_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH0
+          DMA_INT_ST_CH0_REG.
+          0x4
+          0x20
+          
+            
+              IN_DONE_CH0_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH0_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH0_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH0_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH0_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH0_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH0_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH0
+          DMA_INT_ENA_CH0_REG.
+          0x8
+          0x20
+          
+            
+              IN_DONE_CH0_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH0_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH0_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH0_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH0_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH0_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH0_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH0_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH0_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH0_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH0_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH0
+          DMA_INT_CLR_CH0_REG.
+          0xC
+          0x20
+          
+            
+              IN_DONE_CH0_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH0_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH0_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH0_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH0_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH0_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH0_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW_CH1
+          DMA_INT_RAW_CH1_REG.
+          0x10
+          0x20
+          
+            
+              IN_DONE_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH1
+          DMA_INT_ST_CH1_REG.
+          0x14
+          0x20
+          
+            
+              IN_DONE_CH1_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH1_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH1_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH1_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH1_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH1_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH1_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH1
+          DMA_INT_ENA_CH1_REG.
+          0x18
+          0x20
+          
+            
+              IN_DONE_CH1_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH1_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH1_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH1_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH1_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH1_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH1_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH1_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH1_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH1_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH1_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH1
+          DMA_INT_CLR_CH1_REG.
+          0x1C
+          0x20
+          
+            
+              IN_DONE_CH1_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH1_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH1_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH1_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH1_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH1_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH1_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW_CH2
+          DMA_INT_RAW_CH2_REG.
+          0x20
+          0x20
+          
+            
+              IN_DONE_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH2
+          DMA_INT_ST_CH2_REG.
+          0x24
+          0x20
+          
+            
+              IN_DONE_CH2_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH2_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH2_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH2_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH2_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH2_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH2_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH2
+          DMA_INT_ENA_CH2_REG.
+          0x28
+          0x20
+          
+            
+              IN_DONE_CH2_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH2_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH2_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH2_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH2_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH2_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH2_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH2_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH2_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH2_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH2_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH2
+          DMA_INT_CLR_CH2_REG.
+          0x2C
+          0x20
+          
+            
+              IN_DONE_CH2_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH2_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH2_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH2_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH2_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH2_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH2_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          AHB_TEST
+          DMA_AHB_TEST_REG.
+          0x40
+          0x20
+          
+            
+              AHB_TESTMODE
+              reserved
+              0
+              3
+              read-write
+            
+            
+              AHB_TESTADDR
+              reserved
+              4
+              2
+              read-write
+            
+          
+        
+        
+          MISC_CONF
+          DMA_MISC_CONF_REG.
+          0x44
+          0x20
+          
+            
+              AHBM_RST_INTER
+              Set this bit, then clear this bit to reset the internal ahb FSM.
+              0
+              1
+              read-write
+            
+            
+              ARB_PRI_DIS
+              Set this bit to disable priority arbitration function.
+              2
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              3
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          DMA_DATE_REG.
+          0x48
+          0x20
+          0x02008250
+          
+            
+              DATE
+              register version.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH0
+          DMA_IN_CONF0_CH0_REG.
+          0x70
+          0x20
+          
+            
+              IN_RST_CH0
+              This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH0
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH0
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH0
+          DMA_IN_CONF1_CH0_REG.
+          0x74
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH0
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH0
+          DMA_INFIFO_STATUS_CH0_REG.
+          0x78
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH0
+              L1 Rx FIFO full signal for Rx channel 0.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH0
+              L1 Rx FIFO empty signal for Rx channel 0.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH0
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH0
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH0
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH0
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH0
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH0
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH0
+          DMA_IN_POP_CH0_REG.
+          0x7C
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH0
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH0
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH0
+          DMA_IN_LINK_CH0_REG.
+          0x80
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH0
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH0
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH0
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH0
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH0
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH0
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH0
+          DMA_IN_STATE_CH0_REG.
+          0x84
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH0
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH0
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH0
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH0
+          DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+          0x88
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH0
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH0
+          DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+          0x8C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH0
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH0
+          DMA_IN_DSCR_CH0_REG.
+          0x90
+          0x20
+          
+            
+              INLINK_DSCR_CH0
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH0
+          DMA_IN_DSCR_BF0_CH0_REG.
+          0x94
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH0
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH0
+          DMA_IN_DSCR_BF1_CH0_REG.
+          0x98
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH0
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH0
+          DMA_IN_PRI_CH0_REG.
+          0x9C
+          0x20
+          
+            
+              RX_PRI_CH0
+              The priority of Rx channel 0. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH0
+          DMA_IN_PERI_SEL_CH0_REG.
+          0xA0
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH0
+              This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH0
+          DMA_OUT_CONF0_CH0_REG.
+          0xD0
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH0
+              This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH0
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH0
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH0
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH0
+          DMA_OUT_CONF1_CH0_REG.
+          0xD4
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH0
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH0
+          DMA_OUTFIFO_STATUS_CH0_REG.
+          0xD8
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH0
+              L1 Tx FIFO full signal for Tx channel 0.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH0
+              L1 Tx FIFO empty signal for Tx channel 0.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH0
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH0
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH0
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH0
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH0
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH0
+          DMA_OUT_PUSH_CH0_REG.
+          0xDC
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH0
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH0
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH0
+          DMA_OUT_LINK_CH0_REG.
+          0xE0
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH0
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH0
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH0
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH0
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH0
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH0
+          DMA_OUT_STATE_CH0_REG.
+          0xE4
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH0
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH0
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH0
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH0
+          DMA_OUT_EOF_DES_ADDR_CH0_REG.
+          0xE8
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH0
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH0
+          DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+          0xEC
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH0
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH0
+          DMA_OUT_DSCR_CH0_REG.
+          0xF0
+          0x20
+          
+            
+              OUTLINK_DSCR_CH0
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH0
+          DMA_OUT_DSCR_BF0_CH0_REG.
+          0xF4
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH0
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH0
+          DMA_OUT_DSCR_BF1_CH0_REG.
+          0xF8
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH0
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH0
+          DMA_OUT_PRI_CH0_REG.
+          0xFC
+          0x20
+          
+            
+              TX_PRI_CH0
+              The priority of Tx channel 0. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH0
+          DMA_OUT_PERI_SEL_CH0_REG.
+          0x100
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH0
+              This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH1
+          DMA_IN_CONF0_CH1_REG.
+          0x130
+          0x20
+          
+            
+              IN_RST_CH1
+              This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH1
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH1
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH1
+          DMA_IN_CONF1_CH1_REG.
+          0x134
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH1
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH1
+          DMA_INFIFO_STATUS_CH1_REG.
+          0x138
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH1
+              L1 Rx FIFO full signal for Rx channel 1.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH1
+              L1 Rx FIFO empty signal for Rx channel 1.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH1
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH1
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH1
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH1
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH1
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH1
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH1
+          DMA_IN_POP_CH1_REG.
+          0x13C
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH1
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH1
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH1
+          DMA_IN_LINK_CH1_REG.
+          0x140
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH1
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH1
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH1
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH1
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH1
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH1
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH1
+          DMA_IN_STATE_CH1_REG.
+          0x144
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH1
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH1
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH1
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH1
+          DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+          0x148
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH1
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH1
+          DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+          0x14C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH1
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH1
+          DMA_IN_DSCR_CH1_REG.
+          0x150
+          0x20
+          
+            
+              INLINK_DSCR_CH1
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH1
+          DMA_IN_DSCR_BF0_CH1_REG.
+          0x154
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH1
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH1
+          DMA_IN_DSCR_BF1_CH1_REG.
+          0x158
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH1
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH1
+          DMA_IN_PRI_CH1_REG.
+          0x15C
+          0x20
+          
+            
+              RX_PRI_CH1
+              The priority of Rx channel 1. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH1
+          DMA_IN_PERI_SEL_CH1_REG.
+          0x160
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH1
+              This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH1
+          DMA_OUT_CONF0_CH1_REG.
+          0x190
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH1
+              This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH1
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH1
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH1
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH1
+          DMA_OUT_CONF1_CH1_REG.
+          0x194
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH1
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH1
+          DMA_OUTFIFO_STATUS_CH1_REG.
+          0x198
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH1
+              L1 Tx FIFO full signal for Tx channel 1.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH1
+              L1 Tx FIFO empty signal for Tx channel 1.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH1
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH1
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH1
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH1
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH1
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH1
+          DMA_OUT_PUSH_CH1_REG.
+          0x19C
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH1
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH1
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH1
+          DMA_OUT_LINK_CH1_REG.
+          0x1A0
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH1
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH1
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH1
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH1
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH1
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH1
+          DMA_OUT_STATE_CH1_REG.
+          0x1A4
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH1
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH1
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH1
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH1
+          DMA_OUT_EOF_DES_ADDR_CH1_REG.
+          0x1A8
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH1
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH1
+          DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+          0x1AC
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH1
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH1
+          DMA_OUT_DSCR_CH1_REG.
+          0x1B0
+          0x20
+          
+            
+              OUTLINK_DSCR_CH1
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH1
+          DMA_OUT_DSCR_BF0_CH1_REG.
+          0x1B4
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH1
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH1
+          DMA_OUT_DSCR_BF1_CH1_REG.
+          0x1B8
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH1
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH1
+          DMA_OUT_PRI_CH1_REG.
+          0x1BC
+          0x20
+          
+            
+              TX_PRI_CH1
+              The priority of Tx channel 1. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH1
+          DMA_OUT_PERI_SEL_CH1_REG.
+          0x1C0
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH1
+              This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH2
+          DMA_IN_CONF0_CH2_REG.
+          0x1F0
+          0x20
+          
+            
+              IN_RST_CH2
+              This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH2
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH2
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH2
+          DMA_IN_CONF1_CH2_REG.
+          0x1F4
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH2
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH2
+          DMA_INFIFO_STATUS_CH2_REG.
+          0x1F8
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH2
+              L1 Rx FIFO full signal for Rx channel 2.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH2
+              L1 Rx FIFO empty signal for Rx channel 2.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH2
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH2
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH2
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH2
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH2
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH2
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH2
+          DMA_IN_POP_CH2_REG.
+          0x1FC
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH2
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH2
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH2
+          DMA_IN_LINK_CH2_REG.
+          0x200
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH2
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH2
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH2
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH2
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH2
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH2
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH2
+          DMA_IN_STATE_CH2_REG.
+          0x204
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH2
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH2
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH2
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH2
+          DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+          0x208
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH2
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH2
+          DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+          0x20C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH2
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH2
+          DMA_IN_DSCR_CH2_REG.
+          0x210
+          0x20
+          
+            
+              INLINK_DSCR_CH2
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH2
+          DMA_IN_DSCR_BF0_CH2_REG.
+          0x214
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH2
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH2
+          DMA_IN_DSCR_BF1_CH2_REG.
+          0x218
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH2
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH2
+          DMA_IN_PRI_CH2_REG.
+          0x21C
+          0x20
+          
+            
+              RX_PRI_CH2
+              The priority of Rx channel 2. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH2
+          DMA_IN_PERI_SEL_CH2_REG.
+          0x220
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH2
+              This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH2
+          DMA_OUT_CONF0_CH2_REG.
+          0x250
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH2
+              This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH2
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH2
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH2
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH2
+          DMA_OUT_CONF1_CH2_REG.
+          0x254
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH2
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH2
+          DMA_OUTFIFO_STATUS_CH2_REG.
+          0x258
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH2
+              L1 Tx FIFO full signal for Tx channel 2.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH2
+              L1 Tx FIFO empty signal for Tx channel 2.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH2
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH2
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH2
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH2
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH2
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH2
+          DMA_OUT_PUSH_CH2_REG.
+          0x25C
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH2
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH2
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH2
+          DMA_OUT_LINK_CH2_REG.
+          0x260
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH2
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH2
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH2
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH2
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH2
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH2
+          DMA_OUT_STATE_CH2_REG.
+          0x264
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH2
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH2
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH2
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH2
+          DMA_OUT_EOF_DES_ADDR_CH2_REG.
+          0x268
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH2
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH2
+          DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+          0x26C
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH2
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH2
+          DMA_OUT_DSCR_CH2_REG.
+          0x270
+          0x20
+          
+            
+              OUTLINK_DSCR_CH2
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH2
+          DMA_OUT_DSCR_BF0_CH2_REG.
+          0x274
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH2
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH2
+          DMA_OUT_DSCR_BF1_CH2_REG.
+          0x278
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH2
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH2
+          DMA_OUT_PRI_CH2_REG.
+          0x27C
+          0x20
+          
+            
+              TX_PRI_CH2
+              The priority of Tx channel 2. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH2
+          DMA_OUT_PERI_SEL_CH2_REG.
+          0x280
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH2
+              This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+      
+    
+    
+      DS
+      Digital Signature
+      DS
+      0x6003D000
+      
+        0x0
+        0xA4C
+        registers
+      
+      
+        
+          512
+          0x1
+          Y_MEM[%s]
+          memory that stores Y
+          0x0
+          0x8
+        
+        
+          512
+          0x1
+          M_MEM[%s]
+          memory that stores M
+          0x200
+          0x8
+        
+        
+          512
+          0x1
+          RB_MEM[%s]
+          memory that stores Rb
+          0x400
+          0x8
+        
+        
+          48
+          0x1
+          BOX_MEM[%s]
+          memory that stores BOX
+          0x600
+          0x8
+        
+        
+          512
+          0x1
+          X_MEM[%s]
+          memory that stores X
+          0x800
+          0x8
+        
+        
+          512
+          0x1
+          Z_MEM[%s]
+          memory that stores Z
+          0xA00
+          0x8
+        
+        
+          SET_START
+          DS start control register
+          0xE00
+          0x20
+          
+            
+              SET_START
+              set this bit to start DS operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_CONTINUE
+          DS continue control register
+          0xE04
+          0x20
+          
+            
+              SET_CONTINUE
+              set this bit to continue DS operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_FINISH
+          DS finish control register
+          0xE08
+          0x20
+          
+            
+              SET_FINISH
+              Set this bit to finish DS process.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_BUSY
+          DS query busy register
+          0xE0C
+          0x20
+          
+            
+              QUERY_BUSY
+              digital signature state. 1'b0: idle, 1'b1: busy
+              0
+              1
+              read-only
+            
+          
+        
+        
+          QUERY_KEY_WRONG
+          DS query key-wrong counter register
+          0xE10
+          0x20
+          
+            
+              QUERY_KEY_WRONG
+              digital signature key wrong counter
+              0
+              4
+              read-only
+            
+          
+        
+        
+          QUERY_CHECK
+          DS query check result register
+          0xE14
+          0x20
+          
+            
+              MD_ERROR
+              MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+              0
+              1
+              read-only
+            
+            
+              PADDING_BAD
+              padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+              1
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          DS version control register
+          0xE20
+          0x20
+          0x20200618
+          
+            
+              DATE
+              ds version information
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+    
+      EFUSE
+      eFuse Controller
+      EFUSE
+      0x60008800
+      
+        0x0
+        0x1CC
+        registers
+      
+      
+        EFUSE
+        24
+      
+      
+        
+          PGM_DATA0
+          Register 0 that stores data to be programmed.
+          0x0
+          0x20
+          
+            
+              PGM_DATA_0
+              The content of the 0th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA1
+          Register 1 that stores data to be programmed.
+          0x4
+          0x20
+          
+            
+              PGM_DATA_1
+              The content of the 1st 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA2
+          Register 2 that stores data to be programmed.
+          0x8
+          0x20
+          
+            
+              PGM_DATA_2
+              The content of the 2nd 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA3
+          Register 3 that stores data to be programmed.
+          0xC
+          0x20
+          
+            
+              PGM_DATA_3
+              The content of the 3rd 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA4
+          Register 4 that stores data to be programmed.
+          0x10
+          0x20
+          
+            
+              PGM_DATA_4
+              The content of the 4th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA5
+          Register 5 that stores data to be programmed.
+          0x14
+          0x20
+          
+            
+              PGM_DATA_5
+              The content of the 5th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA6
+          Register 6 that stores data to be programmed.
+          0x18
+          0x20
+          
+            
+              PGM_DATA_6
+              The content of the 6th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA7
+          Register 7 that stores data to be programmed.
+          0x1C
+          0x20
+          
+            
+              PGM_DATA_7
+              The content of the 7th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE0
+          Register 0 that stores the RS code to be programmed.
+          0x20
+          0x20
+          
+            
+              PGM_RS_DATA_0
+              The content of the 0th 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE1
+          Register 1 that stores the RS code to be programmed.
+          0x24
+          0x20
+          
+            
+              PGM_RS_DATA_1
+              The content of the 1st 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE2
+          Register 2 that stores the RS code to be programmed.
+          0x28
+          0x20
+          
+            
+              PGM_RS_DATA_2
+              The content of the 2nd 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          RD_WR_DIS
+          BLOCK0 data register 0.
+          0x2C
+          0x20
+          
+            
+              WR_DIS
+              Disable programming of individual eFuses.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA0
+          BLOCK0 data register 1.
+          0x30
+          0x20
+          
+            
+              RD_DIS
+              Set this bit to disable reading from BlOCK4-10.
+              0
+              7
+              read-only
+            
+            
+              DIS_RTC_RAM_BOOT
+              Set this bit to disable boot from RTC RAM.
+              7
+              1
+              read-only
+            
+            
+              DIS_ICACHE
+              Set this bit to disable Icache.
+              8
+              1
+              read-only
+            
+            
+              DIS_USB_JTAG
+              Set this bit to disable function of usb switch to jtag in module of usb device.
+              9
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_ICACHE
+              Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
+              10
+              1
+              read-only
+            
+            
+              DIS_USB_DEVICE
+              Set this bit to disable usb device.
+              11
+              1
+              read-only
+            
+            
+              DIS_FORCE_DOWNLOAD
+              Set this bit to disable the function that forces chip into download mode.
+              12
+              1
+              read-only
+            
+            
+              RPT4_RESERVED6
+              Reserved (used for four backups method).
+              13
+              1
+              read-only
+            
+            
+              DIS_CAN
+              Set this bit to disable CAN function.
+              14
+              1
+              read-only
+            
+            
+              JTAG_SEL_ENABLE
+              Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+              15
+              1
+              read-only
+            
+            
+              SOFT_DIS_JTAG
+              Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
+              16
+              3
+              read-only
+            
+            
+              DIS_PAD_JTAG
+              Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+              19
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_MANUAL_ENCRYPT
+              Set this bit to disable flash encryption when in download boot modes.
+              20
+              1
+              read-only
+            
+            
+              USB_DREFH
+              Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
+              21
+              2
+              read-only
+            
+            
+              USB_DREFL
+              Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
+              23
+              2
+              read-only
+            
+            
+              USB_EXCHG_PINS
+              Set this bit to exchange USB D+ and D- pins.
+              25
+              1
+              read-only
+            
+            
+              VDD_SPI_AS_GPIO
+              Set this bit to vdd spi pin function as gpio.
+              26
+              1
+              read-only
+            
+            
+              BTLC_GPIO_ENABLE
+              Enable btlc gpio.
+              27
+              2
+              read-only
+            
+            
+              POWERGLITCH_EN
+              Set this bit to enable power glitch function.
+              29
+              1
+              read-only
+            
+            
+              POWER_GLITCH_DSENSE
+              Sample delay configuration of power glitch.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA1
+          BLOCK0 data register 2.
+          0x34
+          0x20
+          
+            
+              RPT4_RESERVED2
+              Reserved (used for four backups method).
+              0
+              16
+              read-only
+            
+            
+              WDT_DELAY_SEL
+              Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
+              16
+              2
+              read-only
+            
+            
+              SPI_BOOT_CRYPT_CNT
+              Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
+              18
+              3
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE0
+              Set this bit to enable revoking first secure boot key.
+              21
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE1
+              Set this bit to enable revoking second secure boot key.
+              22
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE2
+              Set this bit to enable revoking third secure boot key.
+              23
+              1
+              read-only
+            
+            
+              KEY_PURPOSE_0
+              Purpose of Key0.
+              24
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_1
+              Purpose of Key1.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA2
+          BLOCK0 data register 3.
+          0x38
+          0x20
+          
+            
+              KEY_PURPOSE_2
+              Purpose of Key2.
+              0
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_3
+              Purpose of Key3.
+              4
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_4
+              Purpose of Key4.
+              8
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_5
+              Purpose of Key5.
+              12
+              4
+              read-only
+            
+            
+              RPT4_RESERVED3
+              Reserved (used for four backups method).
+              16
+              4
+              read-only
+            
+            
+              SECURE_BOOT_EN
+              Set this bit to enable secure boot.
+              20
+              1
+              read-only
+            
+            
+              SECURE_BOOT_AGGRESSIVE_REVOKE
+              Set this bit to enable revoking aggressive secure boot.
+              21
+              1
+              read-only
+            
+            
+              RPT4_RESERVED0
+              Reserved (used for four backups method).
+              22
+              6
+              read-only
+            
+            
+              FLASH_TPUW
+              Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA3
+          BLOCK0 data register 4.
+          0x3C
+          0x20
+          
+            
+              DIS_DOWNLOAD_MODE
+              Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+              0
+              1
+              read-only
+            
+            
+              DIS_LEGACY_SPI_BOOT
+              Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+              1
+              1
+              read-only
+            
+            
+              UART_PRINT_CHANNEL
+              Selectes the default UART print channel. 0: UART0. 1: UART1.
+              2
+              1
+              read-only
+            
+            
+              FLASH_ECC_MODE
+              Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
+              3
+              1
+              read-only
+            
+            
+              DIS_USB_DOWNLOAD_MODE
+              Set this bit to disable UART download mode through USB.
+              4
+              1
+              read-only
+            
+            
+              ENABLE_SECURITY_DOWNLOAD
+              Set this bit to enable secure UART download mode.
+              5
+              1
+              read-only
+            
+            
+              UART_PRINT_CONTROL
+              Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+              6
+              2
+              read-only
+            
+            
+              PIN_POWER_SELECTION
+              GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+              8
+              1
+              read-only
+            
+            
+              FLASH_TYPE
+              Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+              9
+              1
+              read-only
+            
+            
+              FLASH_PAGE_SIZE
+              Set Flash page size.
+              10
+              2
+              read-only
+            
+            
+              FLASH_ECC_EN
+              Set 1 to enable ECC for flash boot.
+              12
+              1
+              read-only
+            
+            
+              FORCE_SEND_RESUME
+              Set this bit to force ROM code to send a resume command during SPI boot.
+              13
+              1
+              read-only
+            
+            
+              SECURE_VERSION
+              Secure version (used by ESP-IDF anti-rollback feature).
+              14
+              16
+              read-only
+            
+            
+              RPT4_RESERVED1
+              Reserved (used for four backups method).
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA4
+          BLOCK0 data register 5.
+          0x40
+          0x20
+          
+            
+              RPT4_RESERVED4
+              Reserved (used for four backups method).
+              0
+              24
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_0
+          BLOCK1 data register 0.
+          0x44
+          0x20
+          
+            
+              MAC_0
+              Stores the low 32 bits of MAC address.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_1
+          BLOCK1 data register 1.
+          0x48
+          0x20
+          
+            
+              MAC_1
+              Stores the high 16 bits of MAC address.
+              0
+              16
+              read-only
+            
+            
+              SPI_PAD_CONF_0
+              Stores the zeroth part of SPI_PAD_CONF.
+              16
+              16
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_2
+          BLOCK1 data register 2.
+          0x4C
+          0x20
+          
+            
+              SPI_PAD_CONF_1
+              Stores the first part of SPI_PAD_CONF.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_3
+          BLOCK1 data register 3.
+          0x50
+          0x20
+          
+            
+              SPI_PAD_CONF_2
+              Stores the second part of SPI_PAD_CONF.
+              0
+              18
+              read-only
+            
+            
+              SYS_DATA_PART0_0
+              Stores the fist 14 bits of the zeroth part of system data.
+              18
+              14
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_4
+          BLOCK1 data register 4.
+          0x54
+          0x20
+          
+            
+              SYS_DATA_PART0_1
+              Stores the fist 32 bits of the zeroth part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_5
+          BLOCK1 data register 5.
+          0x58
+          0x20
+          
+            
+              SYS_DATA_PART0_2
+              Stores the second 32 bits of the zeroth part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA0
+          Register 0 of BLOCK2 (system).
+          0x5C
+          0x20
+          
+            
+              SYS_DATA_PART1_0
+              Stores the zeroth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA1
+          Register 1 of BLOCK2 (system).
+          0x60
+          0x20
+          
+            
+              SYS_DATA_PART1_1
+              Stores the first 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA2
+          Register 2 of BLOCK2 (system).
+          0x64
+          0x20
+          
+            
+              SYS_DATA_PART1_2
+              Stores the second 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA3
+          Register 3 of BLOCK2 (system).
+          0x68
+          0x20
+          
+            
+              SYS_DATA_PART1_3
+              Stores the third 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA4
+          Register 4 of BLOCK2 (system).
+          0x6C
+          0x20
+          
+            
+              SYS_DATA_PART1_4
+              Stores the fourth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA5
+          Register 5 of BLOCK2 (system).
+          0x70
+          0x20
+          
+            
+              SYS_DATA_PART1_5
+              Stores the fifth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA6
+          Register 6 of BLOCK2 (system).
+          0x74
+          0x20
+          
+            
+              SYS_DATA_PART1_6
+              Stores the sixth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA7
+          Register 7 of BLOCK2 (system).
+          0x78
+          0x20
+          
+            
+              SYS_DATA_PART1_7
+              Stores the seventh 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA0
+          Register 0 of BLOCK3 (user).
+          0x7C
+          0x20
+          
+            
+              USR_DATA0
+              Stores the zeroth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA1
+          Register 1 of BLOCK3 (user).
+          0x80
+          0x20
+          
+            
+              USR_DATA1
+              Stores the first 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA2
+          Register 2 of BLOCK3 (user).
+          0x84
+          0x20
+          
+            
+              USR_DATA2
+              Stores the second 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA3
+          Register 3 of BLOCK3 (user).
+          0x88
+          0x20
+          
+            
+              USR_DATA3
+              Stores the third 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA4
+          Register 4 of BLOCK3 (user).
+          0x8C
+          0x20
+          
+            
+              USR_DATA4
+              Stores the fourth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA5
+          Register 5 of BLOCK3 (user).
+          0x90
+          0x20
+          
+            
+              USR_DATA5
+              Stores the fifth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA6
+          Register 6 of BLOCK3 (user).
+          0x94
+          0x20
+          
+            
+              USR_DATA6
+              Stores the sixth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA7
+          Register 7 of BLOCK3 (user).
+          0x98
+          0x20
+          
+            
+              USR_DATA7
+              Stores the seventh 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA0
+          Register 0 of BLOCK4 (KEY0).
+          0x9C
+          0x20
+          
+            
+              KEY0_DATA0
+              Stores the zeroth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA1
+          Register 1 of BLOCK4 (KEY0).
+          0xA0
+          0x20
+          
+            
+              KEY0_DATA1
+              Stores the first 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA2
+          Register 2 of BLOCK4 (KEY0).
+          0xA4
+          0x20
+          
+            
+              KEY0_DATA2
+              Stores the second 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA3
+          Register 3 of BLOCK4 (KEY0).
+          0xA8
+          0x20
+          
+            
+              KEY0_DATA3
+              Stores the third 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA4
+          Register 4 of BLOCK4 (KEY0).
+          0xAC
+          0x20
+          
+            
+              KEY0_DATA4
+              Stores the fourth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA5
+          Register 5 of BLOCK4 (KEY0).
+          0xB0
+          0x20
+          
+            
+              KEY0_DATA5
+              Stores the fifth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA6
+          Register 6 of BLOCK4 (KEY0).
+          0xB4
+          0x20
+          
+            
+              KEY0_DATA6
+              Stores the sixth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA7
+          Register 7 of BLOCK4 (KEY0).
+          0xB8
+          0x20
+          
+            
+              KEY0_DATA7
+              Stores the seventh 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA0
+          Register 0 of BLOCK5 (KEY1).
+          0xBC
+          0x20
+          
+            
+              KEY1_DATA0
+              Stores the zeroth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA1
+          Register 1 of BLOCK5 (KEY1).
+          0xC0
+          0x20
+          
+            
+              KEY1_DATA1
+              Stores the first 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA2
+          Register 2 of BLOCK5 (KEY1).
+          0xC4
+          0x20
+          
+            
+              KEY1_DATA2
+              Stores the second 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA3
+          Register 3 of BLOCK5 (KEY1).
+          0xC8
+          0x20
+          
+            
+              KEY1_DATA3
+              Stores the third 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA4
+          Register 4 of BLOCK5 (KEY1).
+          0xCC
+          0x20
+          
+            
+              KEY1_DATA4
+              Stores the fourth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA5
+          Register 5 of BLOCK5 (KEY1).
+          0xD0
+          0x20
+          
+            
+              KEY1_DATA5
+              Stores the fifth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA6
+          Register 6 of BLOCK5 (KEY1).
+          0xD4
+          0x20
+          
+            
+              KEY1_DATA6
+              Stores the sixth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA7
+          Register 7 of BLOCK5 (KEY1).
+          0xD8
+          0x20
+          
+            
+              KEY1_DATA7
+              Stores the seventh 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA0
+          Register 0 of BLOCK6 (KEY2).
+          0xDC
+          0x20
+          
+            
+              KEY2_DATA0
+              Stores the zeroth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA1
+          Register 1 of BLOCK6 (KEY2).
+          0xE0
+          0x20
+          
+            
+              KEY2_DATA1
+              Stores the first 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA2
+          Register 2 of BLOCK6 (KEY2).
+          0xE4
+          0x20
+          
+            
+              KEY2_DATA2
+              Stores the second 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA3
+          Register 3 of BLOCK6 (KEY2).
+          0xE8
+          0x20
+          
+            
+              KEY2_DATA3
+              Stores the third 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA4
+          Register 4 of BLOCK6 (KEY2).
+          0xEC
+          0x20
+          
+            
+              KEY2_DATA4
+              Stores the fourth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA5
+          Register 5 of BLOCK6 (KEY2).
+          0xF0
+          0x20
+          
+            
+              KEY2_DATA5
+              Stores the fifth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA6
+          Register 6 of BLOCK6 (KEY2).
+          0xF4
+          0x20
+          
+            
+              KEY2_DATA6
+              Stores the sixth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA7
+          Register 7 of BLOCK6 (KEY2).
+          0xF8
+          0x20
+          
+            
+              KEY2_DATA7
+              Stores the seventh 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA0
+          Register 0 of BLOCK7 (KEY3).
+          0xFC
+          0x20
+          
+            
+              KEY3_DATA0
+              Stores the zeroth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA1
+          Register 1 of BLOCK7 (KEY3).
+          0x100
+          0x20
+          
+            
+              KEY3_DATA1
+              Stores the first 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA2
+          Register 2 of BLOCK7 (KEY3).
+          0x104
+          0x20
+          
+            
+              KEY3_DATA2
+              Stores the second 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA3
+          Register 3 of BLOCK7 (KEY3).
+          0x108
+          0x20
+          
+            
+              KEY3_DATA3
+              Stores the third 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA4
+          Register 4 of BLOCK7 (KEY3).
+          0x10C
+          0x20
+          
+            
+              KEY3_DATA4
+              Stores the fourth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA5
+          Register 5 of BLOCK7 (KEY3).
+          0x110
+          0x20
+          
+            
+              KEY3_DATA5
+              Stores the fifth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA6
+          Register 6 of BLOCK7 (KEY3).
+          0x114
+          0x20
+          
+            
+              KEY3_DATA6
+              Stores the sixth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA7
+          Register 7 of BLOCK7 (KEY3).
+          0x118
+          0x20
+          
+            
+              KEY3_DATA7
+              Stores the seventh 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA0
+          Register 0 of BLOCK8 (KEY4).
+          0x11C
+          0x20
+          
+            
+              KEY4_DATA0
+              Stores the zeroth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA1
+          Register 1 of BLOCK8 (KEY4).
+          0x120
+          0x20
+          
+            
+              KEY4_DATA1
+              Stores the first 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA2
+          Register 2 of BLOCK8 (KEY4).
+          0x124
+          0x20
+          
+            
+              KEY4_DATA2
+              Stores the second 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA3
+          Register 3 of BLOCK8 (KEY4).
+          0x128
+          0x20
+          
+            
+              KEY4_DATA3
+              Stores the third 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA4
+          Register 4 of BLOCK8 (KEY4).
+          0x12C
+          0x20
+          
+            
+              KEY4_DATA4
+              Stores the fourth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA5
+          Register 5 of BLOCK8 (KEY4).
+          0x130
+          0x20
+          
+            
+              KEY4_DATA5
+              Stores the fifth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA6
+          Register 6 of BLOCK8 (KEY4).
+          0x134
+          0x20
+          
+            
+              KEY4_DATA6
+              Stores the sixth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA7
+          Register 7 of BLOCK8 (KEY4).
+          0x138
+          0x20
+          
+            
+              KEY4_DATA7
+              Stores the seventh 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA0
+          Register 0 of BLOCK9 (KEY5).
+          0x13C
+          0x20
+          
+            
+              KEY5_DATA0
+              Stores the zeroth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA1
+          Register 1 of BLOCK9 (KEY5).
+          0x140
+          0x20
+          
+            
+              KEY5_DATA1
+              Stores the first 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA2
+          Register 2 of BLOCK9 (KEY5).
+          0x144
+          0x20
+          
+            
+              KEY5_DATA2
+              Stores the second 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA3
+          Register 3 of BLOCK9 (KEY5).
+          0x148
+          0x20
+          
+            
+              KEY5_DATA3
+              Stores the third 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA4
+          Register 4 of BLOCK9 (KEY5).
+          0x14C
+          0x20
+          
+            
+              KEY5_DATA4
+              Stores the fourth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA5
+          Register 5 of BLOCK9 (KEY5).
+          0x150
+          0x20
+          
+            
+              KEY5_DATA5
+              Stores the fifth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA6
+          Register 6 of BLOCK9 (KEY5).
+          0x154
+          0x20
+          
+            
+              KEY5_DATA6
+              Stores the sixth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA7
+          Register 7 of BLOCK9 (KEY5).
+          0x158
+          0x20
+          
+            
+              KEY5_DATA7
+              Stores the seventh 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA0
+          Register 0 of BLOCK10 (system).
+          0x15C
+          0x20
+          
+            
+              SYS_DATA_PART2_0
+              Stores the 0th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA1
+          Register 1 of BLOCK9 (KEY5).
+          0x160
+          0x20
+          
+            
+              SYS_DATA_PART2_1
+              Stores the 1st 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA2
+          Register 2 of BLOCK10 (system).
+          0x164
+          0x20
+          
+            
+              SYS_DATA_PART2_2
+              Stores the 2nd 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA3
+          Register 3 of BLOCK10 (system).
+          0x168
+          0x20
+          
+            
+              SYS_DATA_PART2_3
+              Stores the 3rd 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA4
+          Register 4 of BLOCK10 (system).
+          0x16C
+          0x20
+          
+            
+              SYS_DATA_PART2_4
+              Stores the 4th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA5
+          Register 5 of BLOCK10 (system).
+          0x170
+          0x20
+          
+            
+              SYS_DATA_PART2_5
+              Stores the 5th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA6
+          Register 6 of BLOCK10 (system).
+          0x174
+          0x20
+          
+            
+              SYS_DATA_PART2_6
+              Stores the 6th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA7
+          Register 7 of BLOCK10 (system).
+          0x178
+          0x20
+          
+            
+              SYS_DATA_PART2_7
+              Stores the 7th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR0
+          Programming error record register 0 of BLOCK0.
+          0x17C
+          0x20
+          
+            
+              RD_DIS_ERR
+              If any bit in RD_DIS is 1, then it indicates a programming error.
+              0
+              7
+              read-only
+            
+            
+              DIS_RTC_RAM_BOOT_ERR
+              If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+              7
+              1
+              read-only
+            
+            
+              DIS_ICACHE_ERR
+              If DIS_ICACHE is 1, then it indicates a programming error.
+              8
+              1
+              read-only
+            
+            
+              DIS_USB_JTAG_ERR
+              If DIS_USB_JTAG is 1, then it indicates a programming error.
+              9
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_ICACHE_ERR
+              If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+              10
+              1
+              read-only
+            
+            
+              DIS_USB_DEVICE_ERR
+              If DIS_USB_DEVICE is 1, then it indicates a programming error.
+              11
+              1
+              read-only
+            
+            
+              DIS_FORCE_DOWNLOAD_ERR
+              If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+              12
+              1
+              read-only
+            
+            
+              RPT4_RESERVED6_ERR
+              Reserved.
+              13
+              1
+              read-only
+            
+            
+              DIS_CAN_ERR
+              If DIS_CAN is 1, then it indicates a programming error.
+              14
+              1
+              read-only
+            
+            
+              JTAG_SEL_ENABLE_ERR
+              If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+              15
+              1
+              read-only
+            
+            
+              SOFT_DIS_JTAG_ERR
+              If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+              16
+              3
+              read-only
+            
+            
+              DIS_PAD_JTAG_ERR
+              If DIS_PAD_JTAG is 1, then it indicates a programming error.
+              19
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR
+              If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+              20
+              1
+              read-only
+            
+            
+              USB_DREFH_ERR
+              If any bit in USB_DREFH is 1, then it indicates a programming error.
+              21
+              2
+              read-only
+            
+            
+              USB_DREFL_ERR
+              If any bit in USB_DREFL is 1, then it indicates a programming error.
+              23
+              2
+              read-only
+            
+            
+              USB_EXCHG_PINS_ERR
+              If USB_EXCHG_PINS is 1, then it indicates a programming error.
+              25
+              1
+              read-only
+            
+            
+              VDD_SPI_AS_GPIO_ERR
+              If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+              26
+              1
+              read-only
+            
+            
+              BTLC_GPIO_ENABLE_ERR
+              If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+              27
+              2
+              read-only
+            
+            
+              POWERGLITCH_EN_ERR
+              If POWERGLITCH_EN is 1, then it indicates a programming error.
+              29
+              1
+              read-only
+            
+            
+              POWER_GLITCH_DSENSE_ERR
+              If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR1
+          Programming error record register 1 of BLOCK0.
+          0x180
+          0x20
+          
+            
+              RPT4_RESERVED2_ERR
+              Reserved.
+              0
+              16
+              read-only
+            
+            
+              WDT_DELAY_SEL_ERR
+              If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+              16
+              2
+              read-only
+            
+            
+              SPI_BOOT_CRYPT_CNT_ERR
+              If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+              18
+              3
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE0_ERR
+              If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+              21
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE1_ERR
+              If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+              22
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE2_ERR
+              If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+              23
+              1
+              read-only
+            
+            
+              KEY_PURPOSE_0_ERR
+              If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+              24
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_1_ERR
+              If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR2
+          Programming error record register 2 of BLOCK0.
+          0x184
+          0x20
+          
+            
+              KEY_PURPOSE_2_ERR
+              If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+              0
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_3_ERR
+              If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+              4
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_4_ERR
+              If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+              8
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_5_ERR
+              If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+              12
+              4
+              read-only
+            
+            
+              RPT4_RESERVED3_ERR
+              Reserved.
+              16
+              4
+              read-only
+            
+            
+              SECURE_BOOT_EN_ERR
+              If SECURE_BOOT_EN is 1, then it indicates a programming error.
+              20
+              1
+              read-only
+            
+            
+              SECURE_BOOT_AGGRESSIVE_REVOKE_ERR
+              If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+              21
+              1
+              read-only
+            
+            
+              RPT4_RESERVED0_ERR
+              Reserved.
+              22
+              6
+              read-only
+            
+            
+              FLASH_TPUW_ERR
+              If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR3
+          Programming error record register 3 of BLOCK0.
+          0x188
+          0x20
+          
+            
+              DIS_DOWNLOAD_MODE_ERR
+              If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+              0
+              1
+              read-only
+            
+            
+              DIS_LEGACY_SPI_BOOT_ERR
+              If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+              1
+              1
+              read-only
+            
+            
+              UART_PRINT_CHANNEL_ERR
+              If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+              2
+              1
+              read-only
+            
+            
+              FLASH_ECC_MODE_ERR
+              If FLASH_ECC_MODE is 1, then it indicates a programming error.
+              3
+              1
+              read-only
+            
+            
+              DIS_USB_DOWNLOAD_MODE_ERR
+              If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+              4
+              1
+              read-only
+            
+            
+              ENABLE_SECURITY_DOWNLOAD_ERR
+              If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+              5
+              1
+              read-only
+            
+            
+              UART_PRINT_CONTROL_ERR
+              If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+              6
+              2
+              read-only
+            
+            
+              PIN_POWER_SELECTION_ERR
+              If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+              8
+              1
+              read-only
+            
+            
+              FLASH_TYPE_ERR
+              If FLASH_TYPE is 1, then it indicates a programming error.
+              9
+              1
+              read-only
+            
+            
+              FLASH_PAGE_SIZE_ERR
+              If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+              10
+              2
+              read-only
+            
+            
+              FLASH_ECC_EN_ERR
+              If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+              12
+              1
+              read-only
+            
+            
+              FORCE_SEND_RESUME_ERR
+              If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+              13
+              1
+              read-only
+            
+            
+              SECURE_VERSION_ERR
+              If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+              14
+              16
+              read-only
+            
+            
+              RPT4_RESERVED1_ERR
+              Reserved.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR4
+          Programming error record register 4 of BLOCK0.
+          0x190
+          0x20
+          
+            
+              RPT4_RESERVED4_ERR
+              Reserved.
+              0
+              24
+              read-only
+            
+          
+        
+        
+          RD_RS_ERR0
+          Programming error record register 0 of BLOCK1-10.
+          0x1C0
+          0x20
+          
+            
+              MAC_SPI_8M_ERR_NUM
+              The value of this signal means the number of error bytes.
+              0
+              3
+              read-only
+            
+            
+              MAC_SPI_8M_FAIL
+              0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              3
+              1
+              read-only
+            
+            
+              SYS_PART1_NUM
+              The value of this signal means the number of error bytes.
+              4
+              3
+              read-only
+            
+            
+              SYS_PART1_FAIL
+              0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              7
+              1
+              read-only
+            
+            
+              USR_DATA_ERR_NUM
+              The value of this signal means the number of error bytes.
+              8
+              3
+              read-only
+            
+            
+              USR_DATA_FAIL
+              0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              11
+              1
+              read-only
+            
+            
+              KEY0_ERR_NUM
+              The value of this signal means the number of error bytes.
+              12
+              3
+              read-only
+            
+            
+              KEY0_FAIL
+              0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
+              15
+              1
+              read-only
+            
+            
+              KEY1_ERR_NUM
+              The value of this signal means the number of error bytes.
+              16
+              3
+              read-only
+            
+            
+              KEY1_FAIL
+              0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
+              19
+              1
+              read-only
+            
+            
+              KEY2_ERR_NUM
+              The value of this signal means the number of error bytes.
+              20
+              3
+              read-only
+            
+            
+              KEY2_FAIL
+              0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
+              23
+              1
+              read-only
+            
+            
+              KEY3_ERR_NUM
+              The value of this signal means the number of error bytes.
+              24
+              3
+              read-only
+            
+            
+              KEY3_FAIL
+              0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
+              27
+              1
+              read-only
+            
+            
+              KEY4_ERR_NUM
+              The value of this signal means the number of error bytes.
+              28
+              3
+              read-only
+            
+            
+              KEY4_FAIL
+              0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
+              31
+              1
+              read-only
+            
+          
+        
+        
+          RD_RS_ERR1
+          Programming error record register 1 of BLOCK1-10.
+          0x1C4
+          0x20
+          
+            
+              KEY5_ERR_NUM
+              The value of this signal means the number of error bytes.
+              0
+              3
+              read-only
+            
+            
+              KEY5_FAIL
+              0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              3
+              1
+              read-only
+            
+            
+              SYS_PART2_ERR_NUM
+              The value of this signal means the number of error bytes.
+              4
+              3
+              read-only
+            
+            
+              SYS_PART2_FAIL
+              0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              7
+              1
+              read-only
+            
+          
+        
+        
+          CLK
+          eFuse clcok configuration register.
+          0x1C8
+          0x20
+          0x00000002
+          
+            
+              EFUSE_MEM_FORCE_PD
+              Set this bit to force eFuse SRAM into power-saving mode.
+              0
+              1
+              read-write
+            
+            
+              MEM_CLK_FORCE_ON
+              Set this bit and force to activate clock signal of eFuse SRAM.
+              1
+              1
+              read-write
+            
+            
+              EFUSE_MEM_FORCE_PU
+              Set this bit to force eFuse SRAM into working mode.
+              2
+              1
+              read-write
+            
+            
+              EN
+              Set this bit and force to enable clock signal of eFuse memory.
+              16
+              1
+              read-write
+            
+          
+        
+        
+          CONF
+          eFuse operation mode configuraiton register;
+          0x1CC
+          0x20
+          
+            
+              OP_CODE
+              0x5A5A: Operate programming command 0x5AA5: Operate read command.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          STATUS
+          eFuse status register.
+          0x1D0
+          0x20
+          
+            
+              STATE
+              Indicates the state of the eFuse state machine.
+              0
+              4
+              read-only
+            
+            
+              OTP_LOAD_SW
+              The value of OTP_LOAD_SW.
+              4
+              1
+              read-only
+            
+            
+              OTP_VDDQ_C_SYNC2
+              The value of OTP_VDDQ_C_SYNC2.
+              5
+              1
+              read-only
+            
+            
+              OTP_STROBE_SW
+              The value of OTP_STROBE_SW.
+              6
+              1
+              read-only
+            
+            
+              OTP_CSB_SW
+              The value of OTP_CSB_SW.
+              7
+              1
+              read-only
+            
+            
+              OTP_PGENB_SW
+              The value of OTP_PGENB_SW.
+              8
+              1
+              read-only
+            
+            
+              OTP_VDDQ_IS_SW
+              The value of OTP_VDDQ_IS_SW.
+              9
+              1
+              read-only
+            
+            
+              REPEAT_ERR_CNT
+              Indicates the number of error bits during programming BLOCK0.
+              10
+              8
+              read-only
+            
+          
+        
+        
+          CMD
+          eFuse command register.
+          0x1D4
+          0x20
+          
+            
+              READ_CMD
+              Set this bit to send read command.
+              0
+              1
+              read-write
+            
+            
+              PGM_CMD
+              Set this bit to send programming command.
+              1
+              1
+              read-write
+            
+            
+              BLK_NUM
+              The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
+              2
+              4
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          eFuse raw interrupt register.
+          0x1D8
+          0x20
+          
+            
+              READ_DONE_INT_RAW
+              The raw bit signal for read_done interrupt.
+              0
+              1
+              read-write
+            
+            
+              PGM_DONE_INT_RAW
+              The raw bit signal for pgm_done interrupt.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_ST
+          eFuse interrupt status register.
+          0x1DC
+          0x20
+          
+            
+              READ_DONE_INT_ST
+              The status signal for read_done interrupt.
+              0
+              1
+              read-only
+            
+            
+              PGM_DONE_INT_ST
+              The status signal for pgm_done interrupt.
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          eFuse interrupt enable register.
+          0x1E0
+          0x20
+          
+            
+              READ_DONE_INT_ENA
+              The enable signal for read_done interrupt.
+              0
+              1
+              read-write
+            
+            
+              PGM_DONE_INT_ENA
+              The enable signal for pgm_done interrupt.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          eFuse interrupt clear register.
+          0x1E4
+          0x20
+          
+            
+              READ_DONE_INT_CLR
+              The clear signal for read_done interrupt.
+              0
+              1
+              write-only
+            
+            
+              PGM_DONE_INT_CLR
+              The clear signal for pgm_done interrupt.
+              1
+              1
+              write-only
+            
+          
+        
+        
+          DAC_CONF
+          Controls the eFuse programming voltage.
+          0x1E8
+          0x20
+          0x0001FE1C
+          
+            
+              DAC_CLK_DIV
+              Controls the division factor of the rising clock of the programming voltage.
+              0
+              8
+              read-write
+            
+            
+              DAC_CLK_PAD_SEL
+              Don't care.
+              8
+              1
+              read-write
+            
+            
+              DAC_NUM
+              Controls the rising period of the programming voltage.
+              9
+              8
+              read-write
+            
+            
+              OE_CLR
+              Reduces the power supply of the programming voltage.
+              17
+              1
+              read-write
+            
+          
+        
+        
+          RD_TIM_CONF
+          Configures read timing parameters.
+          0x1EC
+          0x20
+          0x12000000
+          
+            
+              READ_INIT_NUM
+              Configures the initial read time of eFuse.
+              24
+              8
+              read-write
+            
+          
+        
+        
+          WR_TIM_CONF1
+          Configurarion register 1 of eFuse programming timing parameters.
+          0x1F0
+          0x20
+          0x00288000
+          
+            
+              PWR_ON_NUM
+              Configures the power up time for VDDQ.
+              8
+              16
+              read-write
+            
+          
+        
+        
+          WR_TIM_CONF2
+          Configurarion register 2 of eFuse programming timing parameters.
+          0x1F4
+          0x20
+          0x00000190
+          
+            
+              PWR_OFF_NUM
+              Configures the power outage time for VDDQ.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          DATE
+          eFuse version register.
+          0x1FC
+          0x20
+          0x02007200
+          
+            
+              DATE
+              Stores eFuse version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      EXTMEM
+      External Memory
+      EXTMEM
+      0x600C4000
+      
+        0x0
+        0x108
+        registers
+      
+      
+        
+          ICACHE_CTRL
+          This description will be updated in the near future.
+          0x0
+          0x20
+          
+            
+              ICACHE_ENABLE
+              The bit is used to activate the data cache. 0: disable, 1: enable
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_CTRL1
+          This description will be updated in the near future.
+          0x4
+          0x20
+          0x00000003
+          
+            
+              ICACHE_SHUT_IBUS
+              The bit is used to disable core0 ibus, 0: enable, 1: disable
+              0
+              1
+              read-write
+            
+            
+              ICACHE_SHUT_DBUS
+              The bit is used to disable core1 ibus, 0: enable, 1: disable
+              1
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_TAG_POWER_CTRL
+          This description will be updated in the near future.
+          0x8
+          0x20
+          0x00000005
+          
+            
+              ICACHE_TAG_MEM_FORCE_ON
+              The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_TAG_MEM_FORCE_PD
+              The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down
+              1
+              1
+              read-write
+            
+            
+              ICACHE_TAG_MEM_FORCE_PU
+              The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_CTRL
+          This description will be updated in the near future.
+          0xC
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT0_EN
+              The bit is used to enable the first section of prelock function.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOCK_SCT1_EN
+              The bit is used to enable the second section of prelock function.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT0_ADDR
+          This description will be updated in the near future.
+          0x10
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT0_ADDR
+              The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT1_ADDR
+          This description will be updated in the near future.
+          0x14
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT1_ADDR
+              The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT_SIZE
+          This description will be updated in the near future.
+          0x18
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT1_SIZE
+              The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+              0
+              16
+              read-write
+            
+            
+              ICACHE_PRELOCK_SCT0_SIZE
+              The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+              16
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_LOCK_CTRL
+          This description will be updated in the near future.
+          0x1C
+          0x20
+          0x00000004
+          
+            
+              ICACHE_LOCK_ENA
+              The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_UNLOCK_ENA
+              The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_LOCK_DONE
+              The bit is used to indicate unlock/lock operation is finished.
+              2
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_LOCK_ADDR
+          This description will be updated in the near future.
+          0x20
+          0x20
+          
+            
+              ICACHE_LOCK_ADDR
+              The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_LOCK_SIZE
+          This description will be updated in the near future.
+          0x24
+          0x20
+          
+            
+              ICACHE_LOCK_SIZE
+              The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_CTRL
+          This description will be updated in the near future.
+          0x28
+          0x20
+          0x00000001
+          
+            
+              ICACHE_INVALIDATE_ENA
+              The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_SYNC_DONE
+              The bit is used to indicate invalidate operation is finished.
+              1
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_SYNC_ADDR
+          This description will be updated in the near future.
+          0x2C
+          0x20
+          
+            
+              ICACHE_SYNC_ADDR
+              The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_SIZE
+          This description will be updated in the near future.
+          0x30
+          0x20
+          
+            
+              ICACHE_SYNC_SIZE
+              The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_CTRL
+          This description will be updated in the near future.
+          0x34
+          0x20
+          0x00000002
+          
+            
+              ICACHE_PRELOAD_ENA
+              The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_DONE
+              The bit is used to indicate preload operation is finished.
+              1
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_ORDER
+              The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_ADDR
+          This description will be updated in the near future.
+          0x38
+          0x20
+          
+            
+              ICACHE_PRELOAD_ADDR
+              The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_SIZE
+          This description will be updated in the near future.
+          0x3C
+          0x20
+          
+            
+              ICACHE_PRELOAD_SIZE
+              The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
+              0
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_CTRL
+          This description will be updated in the near future.
+          0x40
+          0x20
+          0x00000008
+          
+            
+              ICACHE_AUTOLOAD_SCT0_ENA
+              The bits are used to enable the first section for autoload operation.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_SCT1_ENA
+              The bits are used to enable the second section for autoload operation.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_ENA
+              The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
+              2
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_DONE
+              The bit is used to indicate autoload operation is finished.
+              3
+              1
+              read-only
+            
+            
+              ICACHE_AUTOLOAD_ORDER
+              The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
+              4
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_RQST
+              The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
+              5
+              2
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT0_ADDR
+          This description will be updated in the near future.
+          0x44
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT0_ADDR
+              The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT0_SIZE
+          This description will be updated in the near future.
+          0x48
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT0_SIZE
+              The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+              0
+              27
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT1_ADDR
+          This description will be updated in the near future.
+          0x4C
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT1_ADDR
+              The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT1_SIZE
+          This description will be updated in the near future.
+          0x50
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT1_SIZE
+              The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+              0
+              27
+              read-write
+            
+          
+        
+        
+          IBUS_TO_FLASH_START_VADDR
+          This description will be updated in the near future.
+          0x54
+          0x20
+          0x42000000
+          
+            
+              IBUS_TO_FLASH_START_VADDR
+              The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          IBUS_TO_FLASH_END_VADDR
+          This description will be updated in the near future.
+          0x58
+          0x20
+          0x427FFFFF
+          
+            
+              IBUS_TO_FLASH_END_VADDR
+              The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          DBUS_TO_FLASH_START_VADDR
+          This description will be updated in the near future.
+          0x5C
+          0x20
+          0x3C000000
+          
+            
+              DBUS_TO_FLASH_START_VADDR
+              The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          DBUS_TO_FLASH_END_VADDR
+          This description will be updated in the near future.
+          0x60
+          0x20
+          0x3C7FFFFF
+          
+            
+              DBUS_TO_FLASH_END_VADDR
+              The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CACHE_ACS_CNT_CLR
+          This description will be updated in the near future.
+          0x64
+          0x20
+          
+            
+              IBUS_ACS_CNT_CLR
+              The bit is used to clear ibus counter.
+              0
+              1
+              write-only
+            
+            
+              DBUS_ACS_CNT_CLR
+              The bit is used to clear dbus counter.
+              1
+              1
+              write-only
+            
+          
+        
+        
+          IBUS_ACS_MISS_CNT
+          This description will be updated in the near future.
+          0x68
+          0x20
+          
+            
+              IBUS_ACS_MISS_CNT
+              The bits are used to count the number of the cache miss caused by ibus access flash.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IBUS_ACS_CNT
+          This description will be updated in the near future.
+          0x6C
+          0x20
+          
+            
+              IBUS_ACS_CNT
+              The bits are used to count the number of ibus access flash through icache.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          DBUS_ACS_FLASH_MISS_CNT
+          This description will be updated in the near future.
+          0x70
+          0x20
+          
+            
+              DBUS_ACS_FLASH_MISS_CNT
+              The bits are used to count the number of the cache miss caused by dbus access flash.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          DBUS_ACS_CNT
+          This description will be updated in the near future.
+          0x74
+          0x20
+          
+            
+              DBUS_ACS_CNT
+              The bits are used to count the number of dbus access flash through icache.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_ILG_INT_ENA
+          This description will be updated in the near future.
+          0x78
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_INT_ENA
+              The bit is used to enable interrupt by sync configurations fault.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_INT_ENA
+              The bit is used to enable interrupt by preload configurations fault.
+              1
+              1
+              read-write
+            
+            
+              MMU_ENTRY_FAULT_INT_ENA
+              The bit is used to enable interrupt by mmu entry fault.
+              5
+              1
+              read-write
+            
+            
+              IBUS_CNT_OVF_INT_ENA
+              The bit is used to enable interrupt by ibus counter overflow.
+              7
+              1
+              read-write
+            
+            
+              DBUS_CNT_OVF_INT_ENA
+              The bit is used to enable interrupt by dbus counter overflow.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_ILG_INT_CLR
+          This description will be updated in the near future.
+          0x7C
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_INT_CLR
+              The bit is used to clear interrupt by sync configurations fault.
+              0
+              1
+              write-only
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_INT_CLR
+              The bit is used to clear interrupt by preload configurations fault.
+              1
+              1
+              write-only
+            
+            
+              MMU_ENTRY_FAULT_INT_CLR
+              The bit is used to clear interrupt by mmu entry fault.
+              5
+              1
+              write-only
+            
+            
+              IBUS_CNT_OVF_INT_CLR
+              The bit is used to clear interrupt by ibus counter overflow.
+              7
+              1
+              write-only
+            
+            
+              DBUS_CNT_OVF_INT_CLR
+              The bit is used to clear interrupt by dbus counter overflow.
+              8
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_ILG_INT_ST
+          This description will be updated in the near future.
+          0x80
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_ST
+              The bit is used to indicate interrupt by sync configurations fault.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_ST
+              The bit is used to indicate interrupt by preload configurations fault.
+              1
+              1
+              read-only
+            
+            
+              MMU_ENTRY_FAULT_ST
+              The bit is used to indicate interrupt by mmu entry fault.
+              5
+              1
+              read-only
+            
+            
+              IBUS_ACS_CNT_OVF_ST
+              The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
+              7
+              1
+              read-only
+            
+            
+              IBUS_ACS_MISS_CNT_OVF_ST
+              The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
+              8
+              1
+              read-only
+            
+            
+              DBUS_ACS_CNT_OVF_ST
+              The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
+              9
+              1
+              read-only
+            
+            
+              DBUS_ACS_FLASH_MISS_CNT_OVF_ST
+              The bit is used to indicate interrupt by dbus access flash miss counter overflow.
+              10
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_ENA
+          This description will be updated in the near future.
+          0x84
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_IC_INT_ENA
+              The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
+              0
+              1
+              read-write
+            
+            
+              CORE0_IBUS_WR_IC_INT_ENA
+              The bit is used to enable interrupt by ibus trying to write icache
+              1
+              1
+              read-write
+            
+            
+              CORE0_IBUS_REJECT_INT_ENA
+              The bit is used to enable interrupt by authentication fail.
+              2
+              1
+              read-write
+            
+            
+              CORE0_DBUS_ACS_MSK_IC_INT_ENA
+              The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
+              3
+              1
+              read-write
+            
+            
+              CORE0_DBUS_REJECT_INT_ENA
+              The bit is used to enable interrupt by authentication fail.
+              4
+              1
+              read-write
+            
+            
+              CORE0_DBUS_WR_IC_INT_ENA
+              The bit is used to enable interrupt by dbus trying to write icache
+              5
+              1
+              read-write
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_CLR
+          This description will be updated in the near future.
+          0x88
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_IC_INT_CLR
+              The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
+              0
+              1
+              write-only
+            
+            
+              CORE0_IBUS_WR_IC_INT_CLR
+              The bit is used to clear interrupt by ibus trying to write icache
+              1
+              1
+              write-only
+            
+            
+              CORE0_IBUS_REJECT_INT_CLR
+              The bit is used to clear interrupt by authentication fail.
+              2
+              1
+              write-only
+            
+            
+              CORE0_DBUS_ACS_MSK_IC_INT_CLR
+              The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
+              3
+              1
+              write-only
+            
+            
+              CORE0_DBUS_REJECT_INT_CLR
+              The bit is used to clear interrupt by authentication fail.
+              4
+              1
+              write-only
+            
+            
+              CORE0_DBUS_WR_IC_INT_CLR
+              The bit is used to clear interrupt by dbus trying to write icache
+              5
+              1
+              write-only
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_ST
+          This description will be updated in the near future.
+          0x8C
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_ICACHE_ST
+              The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.
+              0
+              1
+              read-only
+            
+            
+              CORE0_IBUS_WR_ICACHE_ST
+              The bit is used to indicate interrupt by ibus trying to write icache
+              1
+              1
+              read-only
+            
+            
+              CORE0_IBUS_REJECT_ST
+              The bit is used to indicate interrupt by authentication fail.
+              2
+              1
+              read-only
+            
+            
+              CORE0_DBUS_ACS_MSK_ICACHE_ST
+              The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
+              3
+              1
+              read-only
+            
+            
+              CORE0_DBUS_REJECT_ST
+              The bit is used to indicate interrupt by authentication fail.
+              4
+              1
+              read-only
+            
+            
+              CORE0_DBUS_WR_ICACHE_ST
+              The bit is used to indicate interrupt by dbus trying to write icache
+              5
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_DBUS_REJECT_ST
+          This description will be updated in the near future.
+          0x90
+          0x20
+          
+            
+              CORE0_DBUS_ATTR
+              The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
+              0
+              3
+              read-only
+            
+            
+              CORE0_DBUS_WORLD
+              The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
+              3
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_DBUS_REJECT_VADDR
+          This description will be updated in the near future.
+          0x94
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE0_DBUS_VADDR
+              The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE0_IBUS_REJECT_ST
+          This description will be updated in the near future.
+          0x98
+          0x20
+          
+            
+              CORE0_IBUS_ATTR
+              The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+              0
+              3
+              read-only
+            
+            
+              CORE0_IBUS_WORLD
+              The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
+              3
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_IBUS_REJECT_VADDR
+          This description will be updated in the near future.
+          0x9C
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE0_IBUS_VADDR
+              The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_MMU_FAULT_CONTENT
+          This description will be updated in the near future.
+          0xA0
+          0x20
+          
+            
+              CACHE_MMU_FAULT_CONTENT
+              The bits are used to indicate the content of mmu entry which cause mmu fault..
+              0
+              10
+              read-only
+            
+            
+              CACHE_MMU_FAULT_CODE
+              The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
+              10
+              4
+              read-only
+            
+          
+        
+        
+          CACHE_MMU_FAULT_VADDR
+          This description will be updated in the near future.
+          0xA4
+          0x20
+          
+            
+              CACHE_MMU_FAULT_VADDR
+              The bits are used to indicate the virtual address which cause mmu fault..
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_WRAP_AROUND_CTRL
+          This description will be updated in the near future.
+          0xA8
+          0x20
+          
+            
+              CACHE_FLASH_WRAP_AROUND
+              The bit is used to enable wrap around mode when read data from flash.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_POWER_CTRL
+          This description will be updated in the near future.
+          0xAC
+          0x20
+          0x00000005
+          
+            
+              CACHE_MMU_MEM_FORCE_ON
+              The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
+              0
+              1
+              read-write
+            
+            
+              CACHE_MMU_MEM_FORCE_PD
+              The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+              1
+              1
+              read-write
+            
+            
+              CACHE_MMU_MEM_FORCE_PU
+              The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_STATE
+          This description will be updated in the near future.
+          0xB0
+          0x20
+          0x00000001
+          
+            
+              ICACHE_STATE
+              The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state
+              0
+              12
+              read-only
+            
+          
+        
+        
+          CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE
+          This description will be updated in the near future.
+          0xB4
+          0x20
+          
+            
+              RECORD_DISABLE_DB_ENCRYPT
+              Reserved.
+              0
+              1
+              read-write
+            
+            
+              RECORD_DISABLE_G0CB_DECRYPT
+              Reserved.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON
+          This description will be updated in the near future.
+          0xB8
+          0x20
+          0x00000007
+          
+            
+              CLK_FORCE_ON_MANUAL_CRYPT
+              The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
+              0
+              1
+              read-write
+            
+            
+              CLK_FORCE_ON_AUTO_CRYPT
+              The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
+              1
+              1
+              read-write
+            
+            
+              CLK_FORCE_ON_CRYPT
+              The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_PRELOAD_INT_CTRL
+          This description will be updated in the near future.
+          0xBC
+          0x20
+          
+            
+              ICACHE_PRELOAD_INT_ST
+              The bit is used to indicate the interrupt by  icache pre-load done.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_INT_ENA
+              The bit is used to enable the interrupt by  icache pre-load done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_INT_CLR
+              The bit is used to clear the interrupt by  icache pre-load done.
+              2
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_SYNC_INT_CTRL
+          This description will be updated in the near future.
+          0xC0
+          0x20
+          
+            
+              ICACHE_SYNC_INT_ST
+              The bit is used to indicate the interrupt by  icache sync done.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_SYNC_INT_ENA
+              The bit is used to enable the interrupt by  icache sync done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_SYNC_INT_CLR
+              The bit is used to clear the interrupt by  icache sync done.
+              2
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_MMU_OWNER
+          This description will be updated in the near future.
+          0xC4
+          0x20
+          
+            
+              CACHE_MMU_OWNER
+              The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CACHE_CONF_MISC
+          This description will be updated in the near future.
+          0xC8
+          0x20
+          0x00000007
+          
+            
+              CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT
+              The bit is used to disable checking mmu entry fault by preload operation.
+              0
+              1
+              read-write
+            
+            
+              CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT
+              The bit is used to disable checking mmu entry fault by sync operation.
+              1
+              1
+              read-write
+            
+            
+              CACHE_TRACE_ENA
+              The bit is used to enable cache trace function.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_FREEZE
+          This description will be updated in the near future.
+          0xCC
+          0x20
+          
+            
+              ENA
+              The bit is used to enable icache freeze mode
+              0
+              1
+              read-write
+            
+            
+              MODE
+              The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss
+              1
+              1
+              read-write
+            
+            
+              DONE
+              The bit is used to indicate icache freeze success
+              2
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_ATOMIC_OPERATE_ENA
+          This description will be updated in the near future.
+          0xD0
+          0x20
+          0x00000001
+          
+            
+              ICACHE_ATOMIC_OPERATE_ENA
+              The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_REQUEST
+          This description will be updated in the near future.
+          0xD4
+          0x20
+          
+            
+              BYPASS
+              The bit is used to disable request recording which could cause performance issue
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_LOCK
+          This description will be updated in the near future.
+          0xD8
+          0x20
+          
+            
+              IBUS_PMS_LOCK
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY0
+          This description will be updated in the near future.
+          0xDC
+          0x20
+          
+            
+              IBUS_PMS_BOUNDARY0
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY1
+          This description will be updated in the near future.
+          0xE0
+          0x20
+          0x00000800
+          
+            
+              IBUS_PMS_BOUNDARY1
+              The bit is used to configure the ibus permission control section boundary1
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY2
+          This description will be updated in the near future.
+          0xE4
+          0x20
+          0x00000800
+          
+            
+              IBUS_PMS_BOUNDARY2
+              The bit is used to configure the ibus permission control section boundary2
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_ATTR
+          This description will be updated in the near future.
+          0xE8
+          0x20
+          0x000000FF
+          
+            
+              IBUS_PMS_SCT1_ATTR
+              The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+              0
+              4
+              read-write
+            
+            
+              IBUS_PMS_SCT2_ATTR
+              The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+              4
+              4
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_LOCK
+          This description will be updated in the near future.
+          0xEC
+          0x20
+          
+            
+              DBUS_PMS_LOCK
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY0
+          This description will be updated in the near future.
+          0xF0
+          0x20
+          
+            
+              DBUS_PMS_BOUNDARY0
+              The bit is used to configure the dbus permission control section boundary0
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY1
+          This description will be updated in the near future.
+          0xF4
+          0x20
+          0x00000800
+          
+            
+              DBUS_PMS_BOUNDARY1
+              The bit is used to configure the dbus permission control section boundary1
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY2
+          This description will be updated in the near future.
+          0xF8
+          0x20
+          0x00000800
+          
+            
+              DBUS_PMS_BOUNDARY2
+              The bit is used to configure the dbus permission control section boundary2
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_ATTR
+          This description will be updated in the near future.
+          0xFC
+          0x20
+          0x0000000F
+          
+            
+              DBUS_PMS_SCT1_ATTR
+              The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
+              0
+              2
+              read-write
+            
+            
+              DBUS_PMS_SCT2_ATTR
+              The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
+              2
+              2
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          This description will be updated in the near future.
+          0x100
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              clock gate enable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REG_DATE
+          This description will be updated in the near future.
+          0x3FC
+          0x20
+          0x02007160
+          
+            
+              DATE
+              version information
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      GPIO
+      General Purpose Input/Output
+      GPIO
+      0x60004000
+      
+        0x0
+        0x31C
+        registers
+      
+      
+        GPIO
+        16
+      
+      
+        GPIO_NMI
+        17
+      
+      
+        
+          BT_SELECT
+          GPIO bit select register
+          0x0
+          0x20
+          
+            
+              BT_SEL
+              GPIO bit select register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          OUT
+          GPIO output register
+          0x4
+          0x20
+          
+            
+              DATA_ORIG
+              GPIO output register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          OUT_W1TS
+          GPIO output set register
+          0x8
+          0x20
+          
+            
+              OUT_W1TS
+              GPIO output set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          OUT_W1TC
+          GPIO output clear register
+          0xC
+          0x20
+          
+            
+              OUT_W1TC
+              GPIO output clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          SDIO_SELECT
+          GPIO sdio select register
+          0x1C
+          0x20
+          
+            
+              SDIO_SEL
+              GPIO sdio select register
+              0
+              8
+              read-write
+            
+          
+        
+        
+          ENABLE
+          GPIO output enable register
+          0x20
+          0x20
+          
+            
+              DATA
+              GPIO output enable register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          ENABLE_W1TS
+          GPIO output enable set register
+          0x24
+          0x20
+          
+            
+              ENABLE_W1TS
+              GPIO output enable set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          ENABLE_W1TC
+          GPIO output enable clear register
+          0x28
+          0x20
+          
+            
+              ENABLE_W1TC
+              GPIO output enable clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          STRAP
+          pad strapping register
+          0x38
+          0x20
+          
+            
+              STRAPPING
+              pad strapping register
+              0
+              16
+              read-only
+            
+          
+        
+        
+          IN
+          GPIO input register
+          0x3C
+          0x20
+          
+            
+              DATA_NEXT
+              GPIO input register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          STATUS
+          GPIO interrupt status register
+          0x44
+          0x20
+          
+            
+              INTERRUPT
+              GPIO interrupt status register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          STATUS_W1TS
+          GPIO interrupt status set register
+          0x48
+          0x20
+          
+            
+              STATUS_W1TS
+              GPIO interrupt status set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          STATUS_W1TC
+          GPIO interrupt status clear register
+          0x4C
+          0x20
+          
+            
+              STATUS_W1TC
+              GPIO interrupt status clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          PCPU_INT
+          GPIO PRO_CPU interrupt status register
+          0x5C
+          0x20
+          
+            
+              PROCPU_INT
+              GPIO PRO_CPU interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          PCPU_NMI_INT
+          GPIO PRO_CPU(not shielded) interrupt status register
+          0x60
+          0x20
+          
+            
+              PROCPU_NMI_INT
+              GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          CPUSDIO_INT
+          GPIO CPUSDIO interrupt status register
+          0x64
+          0x20
+          
+            
+              SDIO_INT
+              GPIO CPUSDIO interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          26
+          0x4
+          PIN%s
+          GPIO pin configuration register
+          0x74
+          0x20
+          
+            
+              PIN_SYNC2_BYPASS
+              set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+              0
+              2
+              read-write
+            
+            
+              PIN_PAD_DRIVER
+              set this bit to select pad driver. 1:open-drain. :normal.
+              2
+              1
+              read-write
+            
+            
+              PIN_SYNC1_BYPASS
+              set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+              3
+              2
+              read-write
+            
+            
+              PIN_INT_TYPE
+              set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
+              7
+              3
+              read-write
+            
+            
+              PIN_WAKEUP_ENABLE
+              set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+              10
+              1
+              read-write
+            
+            
+              PIN_CONFIG
+              reserved
+              11
+              2
+              read-write
+            
+            
+              PIN_INT_ENA
+              set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
+              13
+              5
+              read-write
+            
+          
+        
+        
+          STATUS_NEXT
+          GPIO interrupt source register
+          0x14C
+          0x20
+          
+            
+              STATUS_INTERRUPT_NEXT
+              GPIO interrupt source register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          128
+          0x4
+          FUNC%s_IN_SEL_CFG
+          GPIO input function configuration register
+          0x154
+          0x20
+          
+            
+              IN_SEL
+              set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
+              0
+              5
+              read-write
+            
+            
+              IN_INV_SEL
+              set this bit to invert input signal. 1:invert. :not invert.
+              5
+              1
+              read-write
+            
+            
+              SEL
+              set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+              6
+              1
+              read-write
+            
+          
+        
+        
+          26
+          0x4
+          FUNC%s_OUT_SEL_CFG
+          GPIO output function select register
+          0x554
+          0x20
+          0x00000080
+          
+            
+              OUT_SEL
+              The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
+              0
+              8
+              read-write
+            
+            
+              INV_SEL
+              set this bit to invert output signal.1:invert.:not invert.
+              8
+              1
+              read-write
+            
+            
+              OEN_SEL
+              set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
+              9
+              1
+              read-write
+            
+            
+              OEN_INV_SEL
+              set this bit to invert output enable signal.1:invert.:not invert.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          GPIO clock gate register
+          0x62C
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              set this bit to enable GPIO clock gate
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REG_DATE
+          GPIO version register
+          0x6FC
+          0x20
+          0x02006130
+          
+            
+              REG_DATE
+              version register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      GPIOSD
+      Sigma-Delta Modulation
+      GPIOSD
+      0x60004F00
+      
+        0x0
+        0x1C
+        registers
+      
+      
+        
+          4
+          0x4
+          SIGMADELTA%s
+          Duty Cycle Configure Register of SDM%s
+          0x0
+          0x20
+          0x0000FF00
+          
+            
+              SD0_IN
+              This field is used to configure the duty cycle of sigma delta modulation output.
+              0
+              8
+              read-write
+            
+            
+              SD0_PRESCALE
+              This field is used to set a divider value to divide APB clock.
+              8
+              8
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_CG
+          Clock Gating Configure Register
+          0x20
+          0x20
+          
+            
+              CLK_EN
+              Clock enable bit of configuration registers for sigma delta modulation.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_MISC
+          MISC Register
+          0x24
+          0x20
+          
+            
+              FUNCTION_CLK_EN
+              Clock enable bit of sigma delta modulation.
+              30
+              1
+              read-write
+            
+            
+              SPI_SWAP
+              Reserved.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_VERSION
+          Version Control Register
+          0x28
+          0x20
+          0x02006230
+          
+            
+              GPIO_SD_DATE
+              Version control register.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      HMAC
+      HMAC (Hash-based Message Authentication Code) Accelerator
+      HMAC
+      0x6003E000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          SET_START
+          Process control register 0.
+          0x40
+          0x20
+          
+            
+              SET_START
+              Start hmac operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_PARA_PURPOSE
+          Configure purpose.
+          0x44
+          0x20
+          
+            
+              PURPOSE_SET
+              Set hmac parameter purpose.
+              0
+              4
+              write-only
+            
+          
+        
+        
+          SET_PARA_KEY
+          Configure key.
+          0x48
+          0x20
+          
+            
+              KEY_SET
+              Set hmac parameter key.
+              0
+              3
+              write-only
+            
+          
+        
+        
+          SET_PARA_FINISH
+          Finish initial configuration.
+          0x4C
+          0x20
+          
+            
+              SET_PARA_END
+              Finish hmac configuration.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_ONE
+          Process control register 1.
+          0x50
+          0x20
+          
+            
+              SET_TEXT_ONE
+              Call SHA to calculate one message block.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_ING
+          Process control register 2.
+          0x54
+          0x20
+          
+            
+              SET_TEXT_ING
+              Continue typical hmac.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_END
+          Process control register 3.
+          0x58
+          0x20
+          
+            
+              SET_TEXT_END
+              Start hardware padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_RESULT_FINISH
+          Process control register 4.
+          0x5C
+          0x20
+          
+            
+              SET_RESULT_END
+              After read result from upstream, then let hmac back to idle.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_INVALIDATE_JTAG
+          Invalidate register 0.
+          0x60
+          0x20
+          
+            
+              SET_INVALIDATE_JTAG
+              Clear result from hmac downstream JTAG.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_INVALIDATE_DS
+          Invalidate register 1.
+          0x64
+          0x20
+          
+            
+              SET_INVALIDATE_DS
+              Clear result from hmac downstream DS.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_ERROR
+          Error register.
+          0x68
+          0x20
+          
+            
+              QUREY_CHECK
+              Hmac configuration state. 0: key are agree with purpose. 1: error
+              0
+              1
+              read-only
+            
+          
+        
+        
+          QUERY_BUSY
+          Busy register.
+          0x6C
+          0x20
+          
+            
+              BUSY_STATE
+              Hmac state. 1'b0: idle. 1'b1: busy
+              0
+              1
+              read-only
+            
+          
+        
+        
+          64
+          0x1
+          WR_MESSAGE_MEM[%s]
+          Message block memory.
+          0x80
+          0x8
+        
+        
+          32
+          0x1
+          RD_RESULT_MEM[%s]
+          Result from upstream.
+          0xC0
+          0x8
+        
+        
+          SET_MESSAGE_PAD
+          Process control register 5.
+          0xF0
+          0x20
+          
+            
+              SET_TEXT_PAD
+              Start software padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          ONE_BLOCK
+          Process control register 6.
+          0xF4
+          0x20
+          
+            
+              SET_ONE_BLOCK
+              Don't have to do padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SOFT_JTAG_CTRL
+          Jtag register 0.
+          0xF8
+          0x20
+          
+            
+              SOFT_JTAG_CTRL
+              Turn on JTAG verification.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          WR_JTAG
+          Jtag register 1.
+          0xFC
+          0x20
+          
+            
+              WR_JTAG
+              32-bit of key to be compared.
+              0
+              32
+              write-only
+            
+          
+        
+      
+    
+    
+      I2C0
+      I2C (Inter-Integrated Circuit) Controller
+      I2C
+      0x60013000
+      
+        0x0
+        0x90
+        registers
+      
+      
+        I2C_EXT0
+        29
+      
+      
+        
+          SCL_LOW_PERIOD
+          I2C_SCL_LOW_PERIOD_REG
+          0x0
+          0x20
+          
+            
+              SCL_LOW_PERIOD
+              reg_scl_low_period
+              0
+              9
+              read-write
+            
+          
+        
+        
+          CTR
+          I2C_CTR_REG
+          0x4
+          0x20
+          0x0000020B
+          
+            
+              SDA_FORCE_OUT
+              reg_sda_force_out
+              0
+              1
+              read-write
+            
+            
+              SCL_FORCE_OUT
+              reg_scl_force_out
+              1
+              1
+              read-write
+            
+            
+              SAMPLE_SCL_LEVEL
+              reg_sample_scl_level
+              2
+              1
+              read-write
+            
+            
+              RX_FULL_ACK_LEVEL
+              reg_rx_full_ack_level
+              3
+              1
+              read-write
+            
+            
+              MS_MODE
+              reg_ms_mode
+              4
+              1
+              read-write
+            
+            
+              TRANS_START
+              reg_trans_start
+              5
+              1
+              write-only
+            
+            
+              TX_LSB_FIRST
+              reg_tx_lsb_first
+              6
+              1
+              read-write
+            
+            
+              RX_LSB_FIRST
+              reg_rx_lsb_first
+              7
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              8
+              1
+              read-write
+            
+            
+              ARBITRATION_EN
+              reg_arbitration_en
+              9
+              1
+              read-write
+            
+            
+              FSM_RST
+              reg_fsm_rst
+              10
+              1
+              write-only
+            
+            
+              CONF_UPGATE
+              reg_conf_upgate
+              11
+              1
+              write-only
+            
+            
+              SLV_TX_AUTO_START_EN
+              reg_slv_tx_auto_start_en
+              12
+              1
+              read-write
+            
+            
+              ADDR_10BIT_RW_CHECK_EN
+              reg_addr_10bit_rw_check_en
+              13
+              1
+              read-write
+            
+            
+              ADDR_BROADCASTING_EN
+              reg_addr_broadcasting_en
+              14
+              1
+              read-write
+            
+          
+        
+        
+          SR
+          I2C_SR_REG
+          0x8
+          0x20
+          0x0000C000
+          
+            
+              RESP_REC
+              reg_resp_rec
+              0
+              1
+              read-only
+            
+            
+              SLAVE_RW
+              reg_slave_rw
+              1
+              1
+              read-only
+            
+            
+              ARB_LOST
+              reg_arb_lost
+              3
+              1
+              read-only
+            
+            
+              BUS_BUSY
+              reg_bus_busy
+              4
+              1
+              read-only
+            
+            
+              SLAVE_ADDRESSED
+              reg_slave_addressed
+              5
+              1
+              read-only
+            
+            
+              RXFIFO_CNT
+              reg_rxfifo_cnt
+              8
+              6
+              read-only
+            
+            
+              STRETCH_CAUSE
+              reg_stretch_cause
+              14
+              2
+              read-only
+            
+            
+              TXFIFO_CNT
+              reg_txfifo_cnt
+              18
+              6
+              read-only
+            
+            
+              SCL_MAIN_STATE_LAST
+              reg_scl_main_state_last
+              24
+              3
+              read-only
+            
+            
+              SCL_STATE_LAST
+              reg_scl_state_last
+              28
+              3
+              read-only
+            
+          
+        
+        
+          TO
+          I2C_TO_REG
+          0xC
+          0x20
+          0x00000010
+          
+            
+              TIME_OUT_VALUE
+              reg_time_out_value
+              0
+              5
+              read-write
+            
+            
+              TIME_OUT_EN
+              reg_time_out_en
+              5
+              1
+              read-write
+            
+          
+        
+        
+          SLAVE_ADDR
+          I2C_SLAVE_ADDR_REG
+          0x10
+          0x20
+          
+            
+              SLAVE_ADDR
+              reg_slave_addr
+              0
+              15
+              read-write
+            
+            
+              ADDR_10BIT_EN
+              reg_addr_10bit_en
+              31
+              1
+              read-write
+            
+          
+        
+        
+          FIFO_ST
+          I2C_FIFO_ST_REG
+          0x14
+          0x20
+          
+            
+              RXFIFO_RADDR
+              reg_rxfifo_raddr
+              0
+              5
+              read-only
+            
+            
+              RXFIFO_WADDR
+              reg_rxfifo_waddr
+              5
+              5
+              read-only
+            
+            
+              TXFIFO_RADDR
+              reg_txfifo_raddr
+              10
+              5
+              read-only
+            
+            
+              TXFIFO_WADDR
+              reg_txfifo_waddr
+              15
+              5
+              read-only
+            
+            
+              SLAVE_RW_POINT
+              reg_slave_rw_point
+              22
+              8
+              read-only
+            
+          
+        
+        
+          FIFO_CONF
+          I2C_FIFO_CONF_REG
+          0x18
+          0x20
+          0x0000408B
+          
+            
+              RXFIFO_WM_THRHD
+              reg_rxfifo_wm_thrhd
+              0
+              5
+              read-write
+            
+            
+              TXFIFO_WM_THRHD
+              reg_txfifo_wm_thrhd
+              5
+              5
+              read-write
+            
+            
+              NONFIFO_EN
+              reg_nonfifo_en
+              10
+              1
+              read-write
+            
+            
+              FIFO_ADDR_CFG_EN
+              reg_fifo_addr_cfg_en
+              11
+              1
+              read-write
+            
+            
+              RX_FIFO_RST
+              reg_rx_fifo_rst
+              12
+              1
+              read-write
+            
+            
+              TX_FIFO_RST
+              reg_tx_fifo_rst
+              13
+              1
+              read-write
+            
+            
+              FIFO_PRT_EN
+              reg_fifo_prt_en
+              14
+              1
+              read-write
+            
+          
+        
+        
+          DATA
+          I2C_FIFO_DATA_REG
+          0x1C
+          0x20
+          
+            
+              FIFO_RDATA
+              reg_fifo_rdata
+              0
+              8
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          I2C_INT_RAW_REG
+          0x20
+          0x20
+          0x00000002
+          
+            
+              RXFIFO_WM_INT_RAW
+              reg_rxfifo_wm_int_raw
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_WM_INT_RAW
+              reg_txfifo_wm_int_raw
+              1
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_RAW
+              reg_rxfifo_ovf_int_raw
+              2
+              1
+              read-only
+            
+            
+              END_DETECT_INT_RAW
+              reg_end_detect_int_raw
+              3
+              1
+              read-only
+            
+            
+              BYTE_TRANS_DONE_INT_RAW
+              reg_byte_trans_done_int_raw
+              4
+              1
+              read-only
+            
+            
+              ARBITRATION_LOST_INT_RAW
+              reg_arbitration_lost_int_raw
+              5
+              1
+              read-only
+            
+            
+              MST_TXFIFO_UDF_INT_RAW
+              reg_mst_txfifo_udf_int_raw
+              6
+              1
+              read-only
+            
+            
+              TRANS_COMPLETE_INT_RAW
+              reg_trans_complete_int_raw
+              7
+              1
+              read-only
+            
+            
+              TIME_OUT_INT_RAW
+              reg_time_out_int_raw
+              8
+              1
+              read-only
+            
+            
+              TRANS_START_INT_RAW
+              reg_trans_start_int_raw
+              9
+              1
+              read-only
+            
+            
+              NACK_INT_RAW
+              reg_nack_int_raw
+              10
+              1
+              read-only
+            
+            
+              TXFIFO_OVF_INT_RAW
+              reg_txfifo_ovf_int_raw
+              11
+              1
+              read-only
+            
+            
+              RXFIFO_UDF_INT_RAW
+              reg_rxfifo_udf_int_raw
+              12
+              1
+              read-only
+            
+            
+              SCL_ST_TO_INT_RAW
+              reg_scl_st_to_int_raw
+              13
+              1
+              read-only
+            
+            
+              SCL_MAIN_ST_TO_INT_RAW
+              reg_scl_main_st_to_int_raw
+              14
+              1
+              read-only
+            
+            
+              DET_START_INT_RAW
+              reg_det_start_int_raw
+              15
+              1
+              read-only
+            
+            
+              SLAVE_STRETCH_INT_RAW
+              reg_slave_stretch_int_raw
+              16
+              1
+              read-only
+            
+            
+              GENERAL_CALL_INT_RAW
+              reg_general_call_int_raw
+              17
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          I2C_INT_CLR_REG
+          0x24
+          0x20
+          
+            
+              RXFIFO_WM_INT_CLR
+              reg_rxfifo_wm_int_clr
+              0
+              1
+              write-only
+            
+            
+              TXFIFO_WM_INT_CLR
+              reg_txfifo_wm_int_clr
+              1
+              1
+              write-only
+            
+            
+              RXFIFO_OVF_INT_CLR
+              reg_rxfifo_ovf_int_clr
+              2
+              1
+              write-only
+            
+            
+              END_DETECT_INT_CLR
+              reg_end_detect_int_clr
+              3
+              1
+              write-only
+            
+            
+              BYTE_TRANS_DONE_INT_CLR
+              reg_byte_trans_done_int_clr
+              4
+              1
+              write-only
+            
+            
+              ARBITRATION_LOST_INT_CLR
+              reg_arbitration_lost_int_clr
+              5
+              1
+              write-only
+            
+            
+              MST_TXFIFO_UDF_INT_CLR
+              reg_mst_txfifo_udf_int_clr
+              6
+              1
+              write-only
+            
+            
+              TRANS_COMPLETE_INT_CLR
+              reg_trans_complete_int_clr
+              7
+              1
+              write-only
+            
+            
+              TIME_OUT_INT_CLR
+              reg_time_out_int_clr
+              8
+              1
+              write-only
+            
+            
+              TRANS_START_INT_CLR
+              reg_trans_start_int_clr
+              9
+              1
+              write-only
+            
+            
+              NACK_INT_CLR
+              reg_nack_int_clr
+              10
+              1
+              write-only
+            
+            
+              TXFIFO_OVF_INT_CLR
+              reg_txfifo_ovf_int_clr
+              11
+              1
+              write-only
+            
+            
+              RXFIFO_UDF_INT_CLR
+              reg_rxfifo_udf_int_clr
+              12
+              1
+              write-only
+            
+            
+              SCL_ST_TO_INT_CLR
+              reg_scl_st_to_int_clr
+              13
+              1
+              write-only
+            
+            
+              SCL_MAIN_ST_TO_INT_CLR
+              reg_scl_main_st_to_int_clr
+              14
+              1
+              write-only
+            
+            
+              DET_START_INT_CLR
+              reg_det_start_int_clr
+              15
+              1
+              write-only
+            
+            
+              SLAVE_STRETCH_INT_CLR
+              reg_slave_stretch_int_clr
+              16
+              1
+              write-only
+            
+            
+              GENERAL_CALL_INT_CLR
+              reg_general_call_int_clr
+              17
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          I2C_INT_ENA_REG
+          0x28
+          0x20
+          
+            
+              RXFIFO_WM_INT_ENA
+              reg_rxfifo_wm_int_ena
+              0
+              1
+              read-write
+            
+            
+              TXFIFO_WM_INT_ENA
+              reg_txfifo_wm_int_ena
+              1
+              1
+              read-write
+            
+            
+              RXFIFO_OVF_INT_ENA
+              reg_rxfifo_ovf_int_ena
+              2
+              1
+              read-write
+            
+            
+              END_DETECT_INT_ENA
+              reg_end_detect_int_ena
+              3
+              1
+              read-write
+            
+            
+              BYTE_TRANS_DONE_INT_ENA
+              reg_byte_trans_done_int_ena
+              4
+              1
+              read-write
+            
+            
+              ARBITRATION_LOST_INT_ENA
+              reg_arbitration_lost_int_ena
+              5
+              1
+              read-write
+            
+            
+              MST_TXFIFO_UDF_INT_ENA
+              reg_mst_txfifo_udf_int_ena
+              6
+              1
+              read-write
+            
+            
+              TRANS_COMPLETE_INT_ENA
+              reg_trans_complete_int_ena
+              7
+              1
+              read-write
+            
+            
+              TIME_OUT_INT_ENA
+              reg_time_out_int_ena
+              8
+              1
+              read-write
+            
+            
+              TRANS_START_INT_ENA
+              reg_trans_start_int_ena
+              9
+              1
+              read-write
+            
+            
+              NACK_INT_ENA
+              reg_nack_int_ena
+              10
+              1
+              read-write
+            
+            
+              TXFIFO_OVF_INT_ENA
+              reg_txfifo_ovf_int_ena
+              11
+              1
+              read-write
+            
+            
+              RXFIFO_UDF_INT_ENA
+              reg_rxfifo_udf_int_ena
+              12
+              1
+              read-write
+            
+            
+              SCL_ST_TO_INT_ENA
+              reg_scl_st_to_int_ena
+              13
+              1
+              read-write
+            
+            
+              SCL_MAIN_ST_TO_INT_ENA
+              reg_scl_main_st_to_int_ena
+              14
+              1
+              read-write
+            
+            
+              DET_START_INT_ENA
+              reg_det_start_int_ena
+              15
+              1
+              read-write
+            
+            
+              SLAVE_STRETCH_INT_ENA
+              reg_slave_stretch_int_ena
+              16
+              1
+              read-write
+            
+            
+              GENERAL_CALL_INT_ENA
+              reg_general_call_int_ena
+              17
+              1
+              read-write
+            
+          
+        
+        
+          INT_STATUS
+          I2C_INT_STATUS_REG
+          0x2C
+          0x20
+          
+            
+              RXFIFO_WM_INT_ST
+              reg_rxfifo_wm_int_st
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_WM_INT_ST
+              reg_txfifo_wm_int_st
+              1
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_ST
+              reg_rxfifo_ovf_int_st
+              2
+              1
+              read-only
+            
+            
+              END_DETECT_INT_ST
+              reg_end_detect_int_st
+              3
+              1
+              read-only
+            
+            
+              BYTE_TRANS_DONE_INT_ST
+              reg_byte_trans_done_int_st
+              4
+              1
+              read-only
+            
+            
+              ARBITRATION_LOST_INT_ST
+              reg_arbitration_lost_int_st
+              5
+              1
+              read-only
+            
+            
+              MST_TXFIFO_UDF_INT_ST
+              reg_mst_txfifo_udf_int_st
+              6
+              1
+              read-only
+            
+            
+              TRANS_COMPLETE_INT_ST
+              reg_trans_complete_int_st
+              7
+              1
+              read-only
+            
+            
+              TIME_OUT_INT_ST
+              reg_time_out_int_st
+              8
+              1
+              read-only
+            
+            
+              TRANS_START_INT_ST
+              reg_trans_start_int_st
+              9
+              1
+              read-only
+            
+            
+              NACK_INT_ST
+              reg_nack_int_st
+              10
+              1
+              read-only
+            
+            
+              TXFIFO_OVF_INT_ST
+              reg_txfifo_ovf_int_st
+              11
+              1
+              read-only
+            
+            
+              RXFIFO_UDF_INT_ST
+              reg_rxfifo_udf_int_st
+              12
+              1
+              read-only
+            
+            
+              SCL_ST_TO_INT_ST
+              reg_scl_st_to_int_st
+              13
+              1
+              read-only
+            
+            
+              SCL_MAIN_ST_TO_INT_ST
+              reg_scl_main_st_to_int_st
+              14
+              1
+              read-only
+            
+            
+              DET_START_INT_ST
+              reg_det_start_int_st
+              15
+              1
+              read-only
+            
+            
+              SLAVE_STRETCH_INT_ST
+              reg_slave_stretch_int_st
+              16
+              1
+              read-only
+            
+            
+              GENERAL_CALL_INT_ST
+              reg_general_call_int_st
+              17
+              1
+              read-only
+            
+          
+        
+        
+          SDA_HOLD
+          I2C_SDA_HOLD_REG
+          0x30
+          0x20
+          
+            
+              TIME
+              reg_sda_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SDA_SAMPLE
+          I2C_SDA_SAMPLE_REG
+          0x34
+          0x20
+          
+            
+              TIME
+              reg_sda_sample_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_HIGH_PERIOD
+          I2C_SCL_HIGH_PERIOD_REG
+          0x38
+          0x20
+          
+            
+              SCL_HIGH_PERIOD
+              reg_scl_high_period
+              0
+              9
+              read-write
+            
+            
+              SCL_WAIT_HIGH_PERIOD
+              reg_scl_wait_high_period
+              9
+              7
+              read-write
+            
+          
+        
+        
+          SCL_START_HOLD
+          I2C_SCL_START_HOLD_REG
+          0x40
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_start_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_RSTART_SETUP
+          I2C_SCL_RSTART_SETUP_REG
+          0x44
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_rstart_setup_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_STOP_HOLD
+          I2C_SCL_STOP_HOLD_REG
+          0x48
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_stop_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_STOP_SETUP
+          I2C_SCL_STOP_SETUP_REG
+          0x4C
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_stop_setup_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          FILTER_CFG
+          I2C_FILTER_CFG_REG
+          0x50
+          0x20
+          0x00000300
+          
+            
+              SCL_FILTER_THRES
+              reg_scl_filter_thres
+              0
+              4
+              read-write
+            
+            
+              SDA_FILTER_THRES
+              reg_sda_filter_thres
+              4
+              4
+              read-write
+            
+            
+              SCL_FILTER_EN
+              reg_scl_filter_en
+              8
+              1
+              read-write
+            
+            
+              SDA_FILTER_EN
+              reg_sda_filter_en
+              9
+              1
+              read-write
+            
+          
+        
+        
+          CLK_CONF
+          I2C_CLK_CONF_REG
+          0x54
+          0x20
+          0x00200000
+          
+            
+              SCLK_DIV_NUM
+              reg_sclk_div_num
+              0
+              8
+              read-write
+            
+            
+              SCLK_DIV_A
+              reg_sclk_div_a
+              8
+              6
+              read-write
+            
+            
+              SCLK_DIV_B
+              reg_sclk_div_b
+              14
+              6
+              read-write
+            
+            
+              SCLK_SEL
+              reg_sclk_sel
+              20
+              1
+              read-write
+            
+            
+              SCLK_ACTIVE
+              reg_sclk_active
+              21
+              1
+              read-write
+            
+          
+        
+        
+          8
+          0x4
+          COMD%s
+          I2C_COMD%s_REG
+          0x58
+          0x20
+          
+            
+              COMMAND
+              reg_command
+              0
+              14
+              read-write
+            
+            
+              COMMAND_DONE
+              reg_command_done
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SCL_ST_TIME_OUT
+          I2C_SCL_ST_TIME_OUT_REG
+          0x78
+          0x20
+          0x00000010
+          
+            
+              SCL_ST_TO_I2C
+              reg_scl_st_to_regno more than 23
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SCL_MAIN_ST_TIME_OUT
+          I2C_SCL_MAIN_ST_TIME_OUT_REG
+          0x7C
+          0x20
+          0x00000010
+          
+            
+              SCL_MAIN_ST_TO_I2C
+              reg_scl_main_st_to_regno more than 23
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SCL_SP_CONF
+          I2C_SCL_SP_CONF_REG
+          0x80
+          0x20
+          
+            
+              SCL_RST_SLV_EN
+              reg_scl_rst_slv_en
+              0
+              1
+              read-write
+            
+            
+              SCL_RST_SLV_NUM
+              reg_scl_rst_slv_num
+              1
+              5
+              read-write
+            
+            
+              SCL_PD_EN
+              reg_scl_pd_en
+              6
+              1
+              read-write
+            
+            
+              SDA_PD_EN
+              reg_sda_pd_en
+              7
+              1
+              read-write
+            
+          
+        
+        
+          SCL_STRETCH_CONF
+          I2C_SCL_STRETCH_CONF_REG
+          0x84
+          0x20
+          
+            
+              STRETCH_PROTECT_NUM
+              reg_stretch_protect_num
+              0
+              10
+              read-write
+            
+            
+              SLAVE_SCL_STRETCH_EN
+              reg_slave_scl_stretch_en
+              10
+              1
+              read-write
+            
+            
+              SLAVE_SCL_STRETCH_CLR
+              reg_slave_scl_stretch_clr
+              11
+              1
+              write-only
+            
+            
+              SLAVE_BYTE_ACK_CTL_EN
+              reg_slave_byte_ack_ctl_en
+              12
+              1
+              read-write
+            
+            
+              SLAVE_BYTE_ACK_LVL
+              reg_slave_byte_ack_lvl
+              13
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          I2C_DATE_REG
+          0xF8
+          0x20
+          0x20070201
+          
+            
+              DATE
+              reg_date
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TXFIFO_START_ADDR
+          I2C_TXFIFO_START_ADDR_REG
+          0x100
+          0x20
+          
+            
+              TXFIFO_START_ADDR
+              reg_txfifo_start_addr.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RXFIFO_START_ADDR
+          I2C_RXFIFO_START_ADDR_REG
+          0x180
+          0x20
+          
+            
+              RXFIFO_START_ADDR
+              reg_rxfifo_start_addr.
+              0
+              32
+              read-only
+            
+          
+        
+      
+    
+    
+      I2S
+      I2S (Inter-IC Sound) Controller
+      I2S
+      0x6002D000
+      
+        0x0
+        0x5C
+        registers
+      
+      
+        I2S
+        20
+      
+      
+        
+          INT_RAW
+          I2S interrupt raw register, valid in level.
+          0xC
+          0x20
+          
+            
+              RX_DONE_INT_RAW
+              The raw interrupt status bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-only
+            
+            
+              TX_DONE_INT_RAW
+              The raw interrupt status bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_RAW
+              The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_RAW
+              The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          I2S interrupt status register.
+          0x10
+          0x20
+          
+            
+              RX_DONE_INT_ST
+              The masked interrupt status bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-only
+            
+            
+              TX_DONE_INT_ST
+              The masked interrupt status bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_ST
+              The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_ST
+              The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          I2S interrupt enable register.
+          0x14
+          0x20
+          
+            
+              RX_DONE_INT_ENA
+              The interrupt enable bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-write
+            
+            
+              TX_DONE_INT_ENA
+              The interrupt enable bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-write
+            
+            
+              RX_HUNG_INT_ENA
+              The interrupt enable bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-write
+            
+            
+              TX_HUNG_INT_ENA
+              The interrupt enable bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          I2S interrupt clear register.
+          0x18
+          0x20
+          
+            
+              RX_DONE_INT_CLR
+              Set this bit to clear the i2s_rx_done_int interrupt
+              0
+              1
+              write-only
+            
+            
+              TX_DONE_INT_CLR
+              Set this bit to clear the i2s_tx_done_int interrupt
+              1
+              1
+              write-only
+            
+            
+              RX_HUNG_INT_CLR
+              Set this bit to clear the i2s_rx_hung_int interrupt
+              2
+              1
+              write-only
+            
+            
+              TX_HUNG_INT_CLR
+              Set this bit to clear the i2s_tx_hung_int interrupt
+              3
+              1
+              write-only
+            
+          
+        
+        
+          RX_CONF
+          I2S RX configure register
+          0x20
+          0x20
+          0x00009600
+          
+            
+              RX_RESET
+              Set this bit to reset receiver
+              0
+              1
+              write-only
+            
+            
+              RX_FIFO_RESET
+              Set this bit to reset Rx AFIFO
+              1
+              1
+              write-only
+            
+            
+              RX_START
+              Set this bit to start receiving data
+              2
+              1
+              read-write
+            
+            
+              RX_SLAVE_MOD
+              Set this bit to enable slave receiver mode
+              3
+              1
+              read-write
+            
+            
+              RX_MONO
+              Set this bit to enable receiver  in mono mode
+              5
+              1
+              read-write
+            
+            
+              RX_BIG_ENDIAN
+              I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+              7
+              1
+              read-write
+            
+            
+              RX_UPDATE
+              Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
+              8
+              1
+              read-write
+            
+            
+              RX_MONO_FST_VLD
+              1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.
+              9
+              1
+              read-write
+            
+            
+              RX_PCM_CONF
+              I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+              10
+              2
+              read-write
+            
+            
+              RX_PCM_BYPASS
+              Set this bit to bypass Compress/Decompress module for received data.
+              12
+              1
+              read-write
+            
+            
+              RX_STOP_MODE
+              0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+              13
+              2
+              read-write
+            
+            
+              RX_LEFT_ALIGN
+              1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+              15
+              1
+              read-write
+            
+            
+              RX_24_FILL_EN
+              1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+              16
+              1
+              read-write
+            
+            
+              RX_WS_IDLE_POL
+              0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+              17
+              1
+              read-write
+            
+            
+              RX_BIT_ORDER
+              I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
+              18
+              1
+              read-write
+            
+            
+              RX_TDM_EN
+              1: Enable I2S TDM Rx mode . 0: Disable.
+              19
+              1
+              read-write
+            
+            
+              RX_PDM_EN
+              1: Enable I2S PDM Rx mode . 0: Disable.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          TX_CONF
+          I2S TX configure register
+          0x24
+          0x20
+          0x0000B200
+          
+            
+              TX_RESET
+              Set this bit to reset transmitter
+              0
+              1
+              write-only
+            
+            
+              TX_FIFO_RESET
+              Set this bit to reset Tx AFIFO
+              1
+              1
+              write-only
+            
+            
+              TX_START
+              Set this bit to start transmitting data
+              2
+              1
+              read-write
+            
+            
+              TX_SLAVE_MOD
+              Set this bit to enable slave transmitter mode
+              3
+              1
+              read-write
+            
+            
+              TX_MONO
+              Set this bit to enable transmitter in mono mode
+              5
+              1
+              read-write
+            
+            
+              TX_CHAN_EQUAL
+              1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+              6
+              1
+              read-write
+            
+            
+              TX_BIG_ENDIAN
+              I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.
+              7
+              1
+              read-write
+            
+            
+              TX_UPDATE
+              Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
+              8
+              1
+              read-write
+            
+            
+              TX_MONO_FST_VLD
+              1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.
+              9
+              1
+              read-write
+            
+            
+              TX_PCM_CONF
+              I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+              10
+              2
+              read-write
+            
+            
+              TX_PCM_BYPASS
+              Set this bit to bypass  Compress/Decompress module for transmitted data.
+              12
+              1
+              read-write
+            
+            
+              TX_STOP_EN
+              Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+              13
+              1
+              read-write
+            
+            
+              TX_LEFT_ALIGN
+              1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+              15
+              1
+              read-write
+            
+            
+              TX_24_FILL_EN
+              1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+              16
+              1
+              read-write
+            
+            
+              TX_WS_IDLE_POL
+              0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+              17
+              1
+              read-write
+            
+            
+              TX_BIT_ORDER
+              I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
+              18
+              1
+              read-write
+            
+            
+              TX_TDM_EN
+              1: Enable I2S TDM Tx mode . 0: Disable.
+              19
+              1
+              read-write
+            
+            
+              TX_PDM_EN
+              1: Enable I2S PDM Tx mode . 0: Disable.
+              20
+              1
+              read-write
+            
+            
+              TX_CHAN_MOD
+              I2S transmitter channel mode configuration bits.
+              24
+              3
+              read-write
+            
+            
+              SIG_LOOPBACK
+              Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          RX_CONF1
+          I2S RX configure register 1
+          0x28
+          0x20
+          0x2F3DE300
+          
+            
+              RX_TDM_WS_WIDTH
+              The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+              0
+              7
+              read-write
+            
+            
+              RX_BCK_DIV_NUM
+              Bit clock configuration bits in receiver mode.
+              7
+              6
+              read-write
+            
+            
+              RX_BITS_MOD
+              Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+              13
+              5
+              read-write
+            
+            
+              RX_HALF_SAMPLE_BITS
+              I2S Rx half sample bits -1.
+              18
+              6
+              read-write
+            
+            
+              RX_TDM_CHAN_BITS
+              The Rx bit number for each channel minus 1in TDM mode.
+              24
+              5
+              read-write
+            
+            
+              RX_MSB_SHIFT
+              Set this bit to enable receiver in Phillips standard mode
+              29
+              1
+              read-write
+            
+          
+        
+        
+          TX_CONF1
+          I2S TX configure register 1
+          0x2C
+          0x20
+          0x6F3DE300
+          
+            
+              TX_TDM_WS_WIDTH
+              The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+              0
+              7
+              read-write
+            
+            
+              TX_BCK_DIV_NUM
+              Bit clock configuration bits in transmitter mode.
+              7
+              6
+              read-write
+            
+            
+              TX_BITS_MOD
+              Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+              13
+              5
+              read-write
+            
+            
+              TX_HALF_SAMPLE_BITS
+              I2S Tx half sample bits -1.
+              18
+              6
+              read-write
+            
+            
+              TX_TDM_CHAN_BITS
+              The Tx bit number for each channel minus 1in TDM mode.
+              24
+              5
+              read-write
+            
+            
+              TX_MSB_SHIFT
+              Set this bit to enable transmitter in Phillips standard mode
+              29
+              1
+              read-write
+            
+            
+              TX_BCK_NO_DLY
+              1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
+              30
+              1
+              read-write
+            
+          
+        
+        
+          RX_CLKM_CONF
+          I2S RX clock configure register
+          0x30
+          0x20
+          0x00000002
+          
+            
+              RX_CLKM_DIV_NUM
+              Integral I2S clock divider value
+              0
+              8
+              read-write
+            
+            
+              RX_CLK_ACTIVE
+              I2S Rx module clock enable signal.
+              26
+              1
+              read-write
+            
+            
+              RX_CLK_SEL
+              Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+              27
+              2
+              read-write
+            
+            
+              MCLK_SEL
+              0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          TX_CLKM_CONF
+          I2S TX clock configure register
+          0x34
+          0x20
+          0x00000002
+          
+            
+              TX_CLKM_DIV_NUM
+              Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
+              0
+              8
+              read-write
+            
+            
+              TX_CLK_ACTIVE
+              I2S Tx module clock enable signal.
+              26
+              1
+              read-write
+            
+            
+              TX_CLK_SEL
+              Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+              27
+              2
+              read-write
+            
+            
+              CLK_EN
+              Set this bit to enable clk gate
+              29
+              1
+              read-write
+            
+          
+        
+        
+          RX_CLKM_DIV_CONF
+          I2S RX module clock divider configure register
+          0x38
+          0x20
+          0x00000200
+          
+            
+              RX_CLKM_DIV_Z
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
+              0
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_Y
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+              9
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_X
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+              18
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_YN1
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          TX_CLKM_DIV_CONF
+          I2S TX module clock divider configure register
+          0x3C
+          0x20
+          0x00000200
+          
+            
+              TX_CLKM_DIV_Z
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
+              0
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_Y
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+              9
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_X
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+              18
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_YN1
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          TX_PCM2PDM_CONF
+          I2S TX PCM2PDM configuration register
+          0x40
+          0x20
+          0x004AA004
+          
+            
+              TX_PDM_HP_BYPASS
+              I2S TX PDM bypass hp filter or not. The option has been removed.
+              0
+              1
+              read-write
+            
+            
+              TX_PDM_SINC_OSR2
+              I2S TX PDM OSR2 value
+              1
+              4
+              read-write
+            
+            
+              TX_PDM_PRESCALE
+              I2S TX PDM prescale for sigmadelta
+              5
+              8
+              read-write
+            
+            
+              TX_PDM_HP_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              13
+              2
+              read-write
+            
+            
+              TX_PDM_LP_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              15
+              2
+              read-write
+            
+            
+              TX_PDM_SINC_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              17
+              2
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              19
+              2
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_DITHER2
+              I2S TX PDM sigmadelta dither2 value
+              21
+              1
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_DITHER
+              I2S TX PDM sigmadelta dither value
+              22
+              1
+              read-write
+            
+            
+              TX_PDM_DAC_2OUT_EN
+              I2S TX PDM dac mode enable
+              23
+              1
+              read-write
+            
+            
+              TX_PDM_DAC_MODE_EN
+              I2S TX PDM dac 2channel enable
+              24
+              1
+              read-write
+            
+            
+              PCM2PDM_CONV_EN
+              I2S TX PDM Converter enable
+              25
+              1
+              read-write
+            
+          
+        
+        
+          TX_PCM2PDM_CONF1
+          I2S TX PCM2PDM configuration register
+          0x44
+          0x20
+          0x03F783C0
+          
+            
+              TX_PDM_FP
+              I2S TX PDM Fp
+              0
+              10
+              read-write
+            
+            
+              TX_PDM_FS
+              I2S TX PDM Fs
+              10
+              10
+              read-write
+            
+            
+              TX_IIR_HP_MULT12_5
+              The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
+              20
+              3
+              read-write
+            
+            
+              TX_IIR_HP_MULT12_0
+              The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
+              23
+              3
+              read-write
+            
+          
+        
+        
+          RX_TDM_CTRL
+          I2S TX TDM mode control register
+          0x50
+          0x20
+          0x0000FFFF
+          
+            
+              RX_TDM_PDM_CHAN0_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.
+              0
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN1_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.
+              1
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN2_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.
+              2
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN3_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.
+              3
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN4_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.
+              4
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN5_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.
+              5
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN6_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.
+              6
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN7_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.
+              7
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN8_EN
+              1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.
+              8
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN9_EN
+              1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.
+              9
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN10_EN
+              1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.
+              10
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN11_EN
+              1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.
+              11
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN12_EN
+              1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.
+              12
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN13_EN
+              1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.
+              13
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN14_EN
+              1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.
+              14
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN15_EN
+              1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.
+              15
+              1
+              read-write
+            
+            
+              RX_TDM_TOT_CHAN_NUM
+              The total channel number of I2S TX TDM mode.
+              16
+              4
+              read-write
+            
+          
+        
+        
+          TX_TDM_CTRL
+          I2S TX TDM mode control register
+          0x54
+          0x20
+          0x0000FFFF
+          
+            
+              TX_TDM_CHAN0_EN
+              1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.
+              0
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN1_EN
+              1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.
+              1
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN2_EN
+              1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.
+              2
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN3_EN
+              1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.
+              3
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN4_EN
+              1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.
+              4
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN5_EN
+              1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.
+              5
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN6_EN
+              1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.
+              6
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN7_EN
+              1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.
+              7
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN8_EN
+              1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.
+              8
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN9_EN
+              1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.
+              9
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN10_EN
+              1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.
+              10
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN11_EN
+              1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.
+              11
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN12_EN
+              1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.
+              12
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN13_EN
+              1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.
+              13
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN14_EN
+              1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.
+              14
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN15_EN
+              1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.
+              15
+              1
+              read-write
+            
+            
+              TX_TDM_TOT_CHAN_NUM
+              The total channel number of I2S TX TDM mode.
+              16
+              4
+              read-write
+            
+            
+              TX_TDM_SKIP_MSK_EN
+              When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          RX_TIMING
+          I2S RX timing control register
+          0x58
+          0x20
+          
+            
+              RX_SD_IN_DM
+              The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              0
+              2
+              read-write
+            
+            
+              RX_WS_OUT_DM
+              The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              16
+              2
+              read-write
+            
+            
+              RX_BCK_OUT_DM
+              The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              20
+              2
+              read-write
+            
+            
+              RX_WS_IN_DM
+              The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              24
+              2
+              read-write
+            
+            
+              RX_BCK_IN_DM
+              The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              28
+              2
+              read-write
+            
+          
+        
+        
+          TX_TIMING
+          I2S TX timing control register
+          0x5C
+          0x20
+          
+            
+              TX_SD_OUT_DM
+              The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              0
+              2
+              read-write
+            
+            
+              TX_SD1_OUT_DM
+              The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              4
+              2
+              read-write
+            
+            
+              TX_WS_OUT_DM
+              The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              16
+              2
+              read-write
+            
+            
+              TX_BCK_OUT_DM
+              The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              20
+              2
+              read-write
+            
+            
+              TX_WS_IN_DM
+              The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              24
+              2
+              read-write
+            
+            
+              TX_BCK_IN_DM
+              The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              28
+              2
+              read-write
+            
+          
+        
+        
+          LC_HUNG_CONF
+          I2S HUNG configure register.
+          0x60
+          0x20
+          0x00000810
+          
+            
+              LC_FIFO_TIMEOUT
+              the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
+              0
+              8
+              read-write
+            
+            
+              LC_FIFO_TIMEOUT_SHIFT
+              The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+              8
+              3
+              read-write
+            
+            
+              LC_FIFO_TIMEOUT_ENA
+              The enable bit for FIFO timeout
+              11
+              1
+              read-write
+            
+          
+        
+        
+          RXEOF_NUM
+          I2S RX data number control register.
+          0x64
+          0x20
+          0x00000040
+          
+            
+              RX_EOF_NUM
+              The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+              0
+              12
+              read-write
+            
+          
+        
+        
+          CONF_SIGLE_DATA
+          I2S signal data register
+          0x68
+          0x20
+          
+            
+              SINGLE_DATA
+              The configured constant channel data to be sent out.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STATE
+          I2S TX status register
+          0x6C
+          0x20
+          0x00000001
+          
+            
+              TX_IDLE
+              1: i2s_tx is idle state. 0: i2s_tx is working.
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x80
+          0x20
+          0x02007220
+          
+            
+              DATE
+              I2S version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      INTERRUPT_CORE0
+      Interrupt Core
+      INTERRUPT_CORE0
+      0x600C2000
+      
+        0x0
+        0x19C
+        registers
+      
+      
+        
+          MAC_INTR_MAP
+          mac intr map register
+          0x0
+          0x20
+          
+            
+              MAC_INTR_MAP
+              core0_mac_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          MAC_NMI_MAP
+          mac nmi_intr map register
+          0x4
+          0x20
+          
+            
+              MAC_NMI_MAP
+              reg_core0_mac_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          PWR_INTR_MAP
+          pwr intr map register
+          0x8
+          0x20
+          
+            
+              PWR_INTR_MAP
+              reg_core0_pwr_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BB_INT_MAP
+          bb intr map register
+          0xC
+          0x20
+          
+            
+              BB_INT_MAP
+              reg_core0_bb_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_MAC_INT_MAP
+          bt intr map register
+          0x10
+          0x20
+          
+            
+              BT_MAC_INT_MAP
+              reg_core0_bt_mac_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_BB_INT_MAP
+          bb_bt intr map register
+          0x14
+          0x20
+          
+            
+              BT_BB_INT_MAP
+              reg_core0_bt_bb_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_BB_NMI_MAP
+          bb_bt_nmi intr map register
+          0x18
+          0x20
+          
+            
+              BT_BB_NMI_MAP
+              reg_core0_bt_bb_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBT_IRQ_MAP
+          rwbt intr map register
+          0x1C
+          0x20
+          
+            
+              RWBT_IRQ_MAP
+              reg_core0_rwbt_irq_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBLE_IRQ_MAP
+          rwble intr map register
+          0x20
+          0x20
+          
+            
+              RWBLE_IRQ_MAP
+              reg_core0_rwble_irq_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBT_NMI_MAP
+          rwbt_nmi intr map register
+          0x24
+          0x20
+          
+            
+              RWBT_NMI_MAP
+              reg_core0_rwbt_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBLE_NMI_MAP
+          rwble_nmi intr map register
+          0x28
+          0x20
+          
+            
+              RWBLE_NMI_MAP
+              reg_core0_rwble_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2C_MST_INT_MAP
+          i2c intr map register
+          0x2C
+          0x20
+          
+            
+              I2C_MST_INT_MAP
+              reg_core0_i2c_mst_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SLC0_INTR_MAP
+          slc0 intr map register
+          0x30
+          0x20
+          
+            
+              SLC0_INTR_MAP
+              reg_core0_slc0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SLC1_INTR_MAP
+          slc1 intr map register
+          0x34
+          0x20
+          
+            
+              SLC1_INTR_MAP
+              reg_core0_slc1_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          APB_CTRL_INTR_MAP
+          apb_ctrl intr map register
+          0x38
+          0x20
+          
+            
+              APB_CTRL_INTR_MAP
+              reg_core0_apb_ctrl_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UHCI0_INTR_MAP
+          uchi0 intr map register
+          0x3C
+          0x20
+          
+            
+              UHCI0_INTR_MAP
+              reg_core0_uhci0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          GPIO_INTERRUPT_PRO_MAP
+          gpio intr map register
+          0x40
+          0x20
+          
+            
+              GPIO_INTERRUPT_PRO_MAP
+              reg_core0_gpio_interrupt_pro_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          GPIO_INTERRUPT_PRO_NMI_MAP
+          gpio_pro intr map register
+          0x44
+          0x20
+          
+            
+              GPIO_INTERRUPT_PRO_NMI_MAP
+              reg_core0_gpio_interrupt_pro_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_INTR_1_MAP
+          gpio_pro_nmi intr map register
+          0x48
+          0x20
+          
+            
+              SPI_INTR_1_MAP
+              reg_core0_spi_intr_1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_INTR_2_MAP
+          spi1 intr map register
+          0x4C
+          0x20
+          
+            
+              SPI_INTR_2_MAP
+              reg_core0_spi_intr_2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2S1_INT_MAP
+          spi2 intr map register
+          0x50
+          0x20
+          
+            
+              I2S1_INT_MAP
+              reg_core0_i2s1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UART_INTR_MAP
+          i2s1 intr map register
+          0x54
+          0x20
+          
+            
+              UART_INTR_MAP
+              reg_core0_uart_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UART1_INTR_MAP
+          uart1 intr map register
+          0x58
+          0x20
+          
+            
+              UART1_INTR_MAP
+              reg_core0_uart1_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          LEDC_INT_MAP
+          ledc intr map register
+          0x5C
+          0x20
+          
+            
+              LEDC_INT_MAP
+              reg_core0_ledc_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          EFUSE_INT_MAP
+          efuse intr map register
+          0x60
+          0x20
+          
+            
+              EFUSE_INT_MAP
+              reg_core0_efuse_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CAN_INT_MAP
+          can intr map register
+          0x64
+          0x20
+          
+            
+              CAN_INT_MAP
+              reg_core0_can_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          USB_INTR_MAP
+          usb intr map register
+          0x68
+          0x20
+          
+            
+              USB_INTR_MAP
+              reg_core0_usb_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RTC_CORE_INTR_MAP
+          rtc intr map register
+          0x6C
+          0x20
+          
+            
+              RTC_CORE_INTR_MAP
+              reg_core0_rtc_core_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RMT_INTR_MAP
+          rmt intr map register
+          0x70
+          0x20
+          
+            
+              RMT_INTR_MAP
+              reg_core0_rmt_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2C_EXT0_INTR_MAP
+          i2c intr map register
+          0x74
+          0x20
+          
+            
+              I2C_EXT0_INTR_MAP
+              reg_core0_i2c_ext0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TIMER_INT1_MAP
+          timer1 intr map register
+          0x78
+          0x20
+          
+            
+              TIMER_INT1_MAP
+              reg_core0_timer_int1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TIMER_INT2_MAP
+          timer2 intr map register
+          0x7C
+          0x20
+          
+            
+              TIMER_INT2_MAP
+              reg_core0_timer_int2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG_T0_INT_MAP
+          tg to intr map register
+          0x80
+          0x20
+          
+            
+              TG_T0_INT_MAP
+              reg_core0_tg_t0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG_WDT_INT_MAP
+          tg wdt intr map register
+          0x84
+          0x20
+          
+            
+              TG_WDT_INT_MAP
+              reg_core0_tg_wdt_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG1_T0_INT_MAP
+          tg1 to intr map register
+          0x88
+          0x20
+          
+            
+              TG1_T0_INT_MAP
+              reg_core0_tg1_t0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG1_WDT_INT_MAP
+          tg1 wdt intr map register
+          0x8C
+          0x20
+          
+            
+              TG1_WDT_INT_MAP
+              reg_core0_tg1_wdt_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CACHE_IA_INT_MAP
+          cache ia intr map register
+          0x90
+          0x20
+          
+            
+              CACHE_IA_INT_MAP
+              reg_core0_cache_ia_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET0_INT_MAP
+          systimer intr map register
+          0x94
+          0x20
+          
+            
+              SYSTIMER_TARGET0_INT_MAP
+              reg_core0_systimer_target0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET1_INT_MAP
+          systimer target1 intr map register
+          0x98
+          0x20
+          
+            
+              SYSTIMER_TARGET1_INT_MAP
+              reg_core0_systimer_target1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET2_INT_MAP
+          systimer target2 intr map register
+          0x9C
+          0x20
+          
+            
+              SYSTIMER_TARGET2_INT_MAP
+              reg_core0_systimer_target2_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_MEM_REJECT_INTR_MAP
+          spi mem reject intr map register
+          0xA0
+          0x20
+          
+            
+              SPI_MEM_REJECT_INTR_MAP
+              reg_core0_spi_mem_reject_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_INT_MAP
+          icache perload intr map register
+          0xA4
+          0x20
+          
+            
+              ICACHE_PRELOAD_INT_MAP
+              reg_core0_icache_preload_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_INT_MAP
+          icache sync intr map register
+          0xA8
+          0x20
+          
+            
+              ICACHE_SYNC_INT_MAP
+              reg_core0_icache_sync_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          APB_ADC_INT_MAP
+          adc intr map register
+          0xAC
+          0x20
+          
+            
+              APB_ADC_INT_MAP
+              reg_core0_apb_adc_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH0_INT_MAP
+          dma ch0 intr map register
+          0xB0
+          0x20
+          
+            
+              DMA_CH0_INT_MAP
+              reg_core0_dma_ch0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH1_INT_MAP
+          dma ch1 intr map register
+          0xB4
+          0x20
+          
+            
+              DMA_CH1_INT_MAP
+              reg_core0_dma_ch1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH2_INT_MAP
+          dma ch2 intr map register
+          0xB8
+          0x20
+          
+            
+              DMA_CH2_INT_MAP
+              reg_core0_dma_ch2_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RSA_INT_MAP
+          rsa intr map register
+          0xBC
+          0x20
+          
+            
+              RSA_INT_MAP
+              reg_core0_rsa_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          AES_INT_MAP
+          aes intr map register
+          0xC0
+          0x20
+          
+            
+              AES_INT_MAP
+              reg_core0_aes_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SHA_INT_MAP
+          sha intr map register
+          0xC4
+          0x20
+          
+            
+              SHA_INT_MAP
+              reg_core0_sha_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_0_MAP
+          cpu from cpu 0 intr map register
+          0xC8
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_0_MAP
+              reg_core0_cpu_intr_from_cpu_0_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_1_MAP
+          cpu from cpu 0 intr map register
+          0xCC
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_1_MAP
+              reg_core0_cpu_intr_from_cpu_1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_2_MAP
+          cpu from cpu 1 intr map register
+          0xD0
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_2_MAP
+              reg_core0_cpu_intr_from_cpu_2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_3_MAP
+          cpu from cpu 3 intr map register
+          0xD4
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_3_MAP
+              reg_core0_cpu_intr_from_cpu_3_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ASSIST_DEBUG_INTR_MAP
+          assist debug intr map register
+          0xD8
+          0x20
+          
+            
+              ASSIST_DEBUG_INTR_MAP
+              reg_core0_assist_debug_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP
+          dma pms violatile intr map register
+          0xDC
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_dma_apbperi_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+          iram0 pms violatile intr map register
+          0xE0
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_iram0_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+          mac intr map register
+          0xE4
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_dram0_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP
+          mac intr map register
+          0xE8
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_pif_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP
+          mac intr map register
+          0xEC
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP
+              reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BACKUP_PMS_VIOLATE_INTR_MAP
+          mac intr map register
+          0xF0
+          0x20
+          
+            
+              BACKUP_PMS_VIOLATE_INTR_MAP
+              reg_core0_backup_pms_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CACHE_CORE0_ACS_INT_MAP
+          mac intr map register
+          0xF4
+          0x20
+          
+            
+              CACHE_CORE0_ACS_INT_MAP
+              reg_core0_cache_core0_acs_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          INTR_STATUS_REG_0
+          mac intr map register
+          0xF8
+          0x20
+          
+            
+              INTR_STATUS_0
+              reg_core0_intr_status_0
+              0
+              32
+              read-only
+            
+          
+        
+        
+          INTR_STATUS_REG_1
+          mac intr map register
+          0xFC
+          0x20
+          
+            
+              INTR_STATUS_1
+              reg_core0_intr_status_1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          mac intr map register
+          0x100
+          0x20
+          0x00000001
+          
+            
+              REG_CLK_EN
+              reg_core0_reg_clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INT_ENABLE
+          mac intr map register
+          0x104
+          0x20
+          
+            
+              CPU_INT_ENABLE
+              reg_core0_cpu_int_enable
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_TYPE
+          mac intr map register
+          0x108
+          0x20
+          
+            
+              CPU_INT_TYPE
+              reg_core0_cpu_int_type
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_CLEAR
+          mac intr map register
+          0x10C
+          0x20
+          
+            
+              CPU_INT_CLEAR
+              reg_core0_cpu_int_clear
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_EIP_STATUS
+          mac intr map register
+          0x110
+          0x20
+          
+            
+              CPU_INT_EIP_STATUS
+              reg_core0_cpu_int_eip_status
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CPU_INT_PRI_0
+          mac intr map register
+          0x114
+          0x20
+          
+            
+              CPU_PRI_0_MAP
+              reg_core0_cpu_pri_0_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_1
+          mac intr map register
+          0x118
+          0x20
+          
+            
+              CPU_PRI_1_MAP
+              reg_core0_cpu_pri_1_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_2
+          mac intr map register
+          0x11C
+          0x20
+          
+            
+              CPU_PRI_2_MAP
+              reg_core0_cpu_pri_2_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_3
+          mac intr map register
+          0x120
+          0x20
+          
+            
+              CPU_PRI_3_MAP
+              reg_core0_cpu_pri_3_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_4
+          mac intr map register
+          0x124
+          0x20
+          
+            
+              CPU_PRI_4_MAP
+              reg_core0_cpu_pri_4_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_5
+          mac intr map register
+          0x128
+          0x20
+          
+            
+              CPU_PRI_5_MAP
+              reg_core0_cpu_pri_5_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_6
+          mac intr map register
+          0x12C
+          0x20
+          
+            
+              CPU_PRI_6_MAP
+              reg_core0_cpu_pri_6_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_7
+          mac intr map register
+          0x130
+          0x20
+          
+            
+              CPU_PRI_7_MAP
+              reg_core0_cpu_pri_7_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_8
+          mac intr map register
+          0x134
+          0x20
+          
+            
+              CPU_PRI_8_MAP
+              reg_core0_cpu_pri_8_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_9
+          mac intr map register
+          0x138
+          0x20
+          
+            
+              CPU_PRI_9_MAP
+              reg_core0_cpu_pri_9_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_10
+          mac intr map register
+          0x13C
+          0x20
+          
+            
+              CPU_PRI_10_MAP
+              reg_core0_cpu_pri_10_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_11
+          mac intr map register
+          0x140
+          0x20
+          
+            
+              CPU_PRI_11_MAP
+              reg_core0_cpu_pri_11_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_12
+          mac intr map register
+          0x144
+          0x20
+          
+            
+              CPU_PRI_12_MAP
+              reg_core0_cpu_pri_12_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_13
+          mac intr map register
+          0x148
+          0x20
+          
+            
+              CPU_PRI_13_MAP
+              reg_core0_cpu_pri_13_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_14
+          mac intr map register
+          0x14C
+          0x20
+          
+            
+              CPU_PRI_14_MAP
+              reg_core0_cpu_pri_14_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_15
+          mac intr map register
+          0x150
+          0x20
+          
+            
+              CPU_PRI_15_MAP
+              reg_core0_cpu_pri_15_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_16
+          mac intr map register
+          0x154
+          0x20
+          
+            
+              CPU_PRI_16_MAP
+              reg_core0_cpu_pri_16_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_17
+          mac intr map register
+          0x158
+          0x20
+          
+            
+              CPU_PRI_17_MAP
+              reg_core0_cpu_pri_17_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_18
+          mac intr map register
+          0x15C
+          0x20
+          
+            
+              CPU_PRI_18_MAP
+              reg_core0_cpu_pri_18_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_19
+          mac intr map register
+          0x160
+          0x20
+          
+            
+              CPU_PRI_19_MAP
+              reg_core0_cpu_pri_19_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_20
+          mac intr map register
+          0x164
+          0x20
+          
+            
+              CPU_PRI_20_MAP
+              reg_core0_cpu_pri_20_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_21
+          mac intr map register
+          0x168
+          0x20
+          
+            
+              CPU_PRI_21_MAP
+              reg_core0_cpu_pri_21_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_22
+          mac intr map register
+          0x16C
+          0x20
+          
+            
+              CPU_PRI_22_MAP
+              reg_core0_cpu_pri_22_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_23
+          mac intr map register
+          0x170
+          0x20
+          
+            
+              CPU_PRI_23_MAP
+              reg_core0_cpu_pri_23_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_24
+          mac intr map register
+          0x174
+          0x20
+          
+            
+              CPU_PRI_24_MAP
+              reg_core0_cpu_pri_24_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_25
+          mac intr map register
+          0x178
+          0x20
+          
+            
+              CPU_PRI_25_MAP
+              reg_core0_cpu_pri_25_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_26
+          mac intr map register
+          0x17C
+          0x20
+          
+            
+              CPU_PRI_26_MAP
+              reg_core0_cpu_pri_26_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_27
+          mac intr map register
+          0x180
+          0x20
+          
+            
+              CPU_PRI_27_MAP
+              reg_core0_cpu_pri_27_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_28
+          mac intr map register
+          0x184
+          0x20
+          
+            
+              CPU_PRI_28_MAP
+              reg_core0_cpu_pri_28_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_29
+          mac intr map register
+          0x188
+          0x20
+          
+            
+              CPU_PRI_29_MAP
+              reg_core0_cpu_pri_29_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_30
+          mac intr map register
+          0x18C
+          0x20
+          
+            
+              CPU_PRI_30_MAP
+              reg_core0_cpu_pri_30_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_31
+          mac intr map register
+          0x190
+          0x20
+          
+            
+              CPU_PRI_31_MAP
+              reg_core0_cpu_pri_31_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_THRESH
+          mac intr map register
+          0x194
+          0x20
+          
+            
+              CPU_INT_THRESH
+              reg_core0_cpu_int_thresh
+              0
+              4
+              read-write
+            
+          
+        
+        
+          INTERRUPT_REG_DATE
+          mac intr map register
+          0x7FC
+          0x20
+          0x02007210
+          
+            
+              INTERRUPT_REG_DATE
+              reg_core0_interrupt_reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      IO_MUX
+      Input/Output Multiplexer
+      IO_MUX
+      0x60009000
+      
+        0x0
+        0x60
+        registers
+      
+      
+        
+          PIN_CTRL
+          Clock Output Configuration Register
+          0x0
+          0x20
+          0x000007FF
+          
+            
+              CLK_OUT1
+              If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
+              0
+              4
+              read-write
+            
+            
+              CLK_OUT2
+              If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
+              4
+              4
+              read-write
+            
+            
+              CLK_OUT3
+              If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
+              8
+              4
+              read-write
+            
+          
+        
+        
+          22
+          0x4
+          GPIO%s
+          IO MUX Configure Register for pad XTAL_32K_P
+          0x4
+          0x20
+          0x00000B00
+          
+            
+              MCU_OE
+              Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+              0
+              1
+              read-write
+            
+            
+              SLP_SEL
+              Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+              1
+              1
+              read-write
+            
+            
+              MCU_WPD
+              Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
+              2
+              1
+              read-write
+            
+            
+              MCU_WPU
+              Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
+              3
+              1
+              read-write
+            
+            
+              MCU_IE
+              Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+              4
+              1
+              read-write
+            
+            
+              FUN_WPD
+              Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
+              7
+              1
+              read-write
+            
+            
+              FUN_WPU
+              Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
+              8
+              1
+              read-write
+            
+            
+              FUN_IE
+              Input enable of the pad. 1: input enabled; 0: input disabled.
+              9
+              1
+              read-write
+            
+            
+              FUN_DRV
+              Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+              10
+              2
+              read-write
+            
+            
+              MCU_SEL
+              Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
+              12
+              3
+              read-write
+            
+            
+              FILTER_EN
+              Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+              15
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          IO MUX Version Control Register
+          0xFC
+          0x20
+          0x02006050
+          
+            
+              REG_DATE
+              Version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      LEDC
+      LED Control PWM (Pulse Width Modulation)
+      LEDC
+      0x60019000
+      
+        0x0
+        0xB0
+        registers
+      
+      
+        LEDC
+        23
+      
+      
+        
+          LSCH0_CONF0
+          LEDC_LSCH0_CONF0.
+          0x0
+          0x20
+          
+            
+              TIMER_SEL_LSCH0
+              reg_timer_sel_lsch0.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH0
+              reg_sig_out_en_lsch0.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH0
+              reg_idle_lv_lsch0.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH0
+              reg_para_up_lsch0.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH0
+              reg_ovf_num_lsch0.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH0
+              reg_ovf_cnt_en_lsch0.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH0
+              reg_ovf_cnt_reset_lsch0.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH0_HPOINT
+          LEDC_LSCH0_HPOINT.
+          0x4
+          0x20
+          
+            
+              HPOINT_LSCH0
+              reg_hpoint_lsch0.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH0_DUTY
+          LEDC_LSCH0_DUTY.
+          0x8
+          0x20
+          
+            
+              DUTY_LSCH0
+              reg_duty_lsch0.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH0_CONF1
+          LEDC_LSCH0_CONF1.
+          0xC
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH0
+              reg_duty_scale_lsch0.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH0
+              reg_duty_cycle_lsch0.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH0
+              reg_duty_num_lsch0.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH0
+              reg_duty_inc_lsch0.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH0
+              reg_duty_start_lsch0.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH0_DUTY_R
+          LEDC_LSCH0_DUTY_R.
+          0x10
+          0x20
+          
+            
+              DUTY_LSCH0_R
+              reg_duty_lsch0_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH1_CONF0
+          LEDC_LSCH1_CONF0.
+          0x14
+          0x20
+          
+            
+              TIMER_SEL_LSCH1
+              reg_timer_sel_lsch1.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH1
+              reg_sig_out_en_lsch1.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH1
+              reg_idle_lv_lsch1.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH1
+              reg_para_up_lsch1.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH1
+              reg_ovf_num_lsch1.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH1
+              reg_ovf_cnt_en_lsch1.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH1
+              reg_ovf_cnt_reset_lsch1.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH1_HPOINT
+          LEDC_LSCH1_HPOINT.
+          0x18
+          0x20
+          
+            
+              HPOINT_LSCH1
+              reg_hpoint_lsch1.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH1_DUTY
+          LEDC_LSCH1_DUTY.
+          0x1C
+          0x20
+          
+            
+              DUTY_LSCH1
+              reg_duty_lsch1.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH1_CONF1
+          LEDC_LSCH1_CONF1.
+          0x20
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH1
+              reg_duty_scale_lsch1.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH1
+              reg_duty_cycle_lsch1.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH1
+              reg_duty_num_lsch1.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH1
+              reg_duty_inc_lsch1.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH1
+              reg_duty_start_lsch1.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH1_DUTY_R
+          LEDC_LSCH1_DUTY_R.
+          0x24
+          0x20
+          
+            
+              DUTY_LSCH1_R
+              reg_duty_lsch1_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH2_CONF0
+          LEDC_LSCH2_CONF0.
+          0x28
+          0x20
+          
+            
+              TIMER_SEL_LSCH2
+              reg_timer_sel_lsch2.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH2
+              reg_sig_out_en_lsch2.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH2
+              reg_idle_lv_lsch2.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH2
+              reg_para_up_lsch2.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH2
+              reg_ovf_num_lsch2.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH2
+              reg_ovf_cnt_en_lsch2.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH2
+              reg_ovf_cnt_reset_lsch2.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH2_HPOINT
+          LEDC_LSCH2_HPOINT.
+          0x2C
+          0x20
+          
+            
+              HPOINT_LSCH2
+              reg_hpoint_lsch2.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH2_DUTY
+          LEDC_LSCH2_DUTY.
+          0x30
+          0x20
+          
+            
+              DUTY_LSCH2
+              reg_duty_lsch2.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH2_CONF1
+          LEDC_LSCH2_CONF1.
+          0x34
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH2
+              reg_duty_scale_lsch2.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH2
+              reg_duty_cycle_lsch2.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH2
+              reg_duty_num_lsch2.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH2
+              reg_duty_inc_lsch2.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH2
+              reg_duty_start_lsch2.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH2_DUTY_R
+          LEDC_LSCH2_DUTY_R.
+          0x38
+          0x20
+          
+            
+              DUTY_LSCH2_R
+              reg_duty_lsch2_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH3_CONF0
+          LEDC_LSCH3_CONF0.
+          0x3C
+          0x20
+          
+            
+              TIMER_SEL_LSCH3
+              reg_timer_sel_lsch3.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH3
+              reg_sig_out_en_lsch3.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH3
+              reg_idle_lv_lsch3.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH3
+              reg_para_up_lsch3.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH3
+              reg_ovf_num_lsch3.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH3
+              reg_ovf_cnt_en_lsch3.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH3
+              reg_ovf_cnt_reset_lsch3.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH3_HPOINT
+          LEDC_LSCH3_HPOINT.
+          0x40
+          0x20
+          
+            
+              HPOINT_LSCH3
+              reg_hpoint_lsch3.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH3_DUTY
+          LEDC_LSCH3_DUTY.
+          0x44
+          0x20
+          
+            
+              DUTY_LSCH3
+              reg_duty_lsch3.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH3_CONF1
+          LEDC_LSCH3_CONF1.
+          0x48
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH3
+              reg_duty_scale_lsch3.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH3
+              reg_duty_cycle_lsch3.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH3
+              reg_duty_num_lsch3.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH3
+              reg_duty_inc_lsch3.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH3
+              reg_duty_start_lsch3.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH3_DUTY_R
+          LEDC_LSCH3_DUTY_R.
+          0x4C
+          0x20
+          
+            
+              DUTY_LSCH3_R
+              reg_duty_lsch3_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH4_CONF0
+          LEDC_LSCH4_CONF0.
+          0x50
+          0x20
+          
+            
+              TIMER_SEL_LSCH4
+              reg_timer_sel_lsch4.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH4
+              reg_sig_out_en_lsch4.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH4
+              reg_idle_lv_lsch4.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH4
+              reg_para_up_lsch4.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH4
+              reg_ovf_num_lsch4.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH4
+              reg_ovf_cnt_en_lsch4.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH4
+              reg_ovf_cnt_reset_lsch4.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH4_HPOINT
+          LEDC_LSCH4_HPOINT.
+          0x54
+          0x20
+          
+            
+              HPOINT_LSCH4
+              reg_hpoint_lsch4.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH4_DUTY
+          LEDC_LSCH4_DUTY.
+          0x58
+          0x20
+          
+            
+              DUTY_LSCH4
+              reg_duty_lsch4.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH4_CONF1
+          LEDC_LSCH4_CONF1.
+          0x5C
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH4
+              reg_duty_scale_lsch4.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH4
+              reg_duty_cycle_lsch4.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH4
+              reg_duty_num_lsch4.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH4
+              reg_duty_inc_lsch4.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH4
+              reg_duty_start_lsch4.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH4_DUTY_R
+          LEDC_LSCH4_DUTY_R.
+          0x60
+          0x20
+          
+            
+              DUTY_LSCH4_R
+              reg_duty_lsch4_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH5_CONF0
+          LEDC_LSCH5_CONF0.
+          0x64
+          0x20
+          
+            
+              TIMER_SEL_LSCH5
+              reg_timer_sel_lsch5.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH5
+              reg_sig_out_en_lsch5.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH5
+              reg_idle_lv_lsch5.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH5
+              reg_para_up_lsch5.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH5
+              reg_ovf_num_lsch5.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH5
+              reg_ovf_cnt_en_lsch5.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH5
+              reg_ovf_cnt_reset_lsch5.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH5_HPOINT
+          LEDC_LSCH5_HPOINT.
+          0x68
+          0x20
+          
+            
+              HPOINT_LSCH5
+              reg_hpoint_lsch5.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH5_DUTY
+          LEDC_LSCH5_DUTY.
+          0x6C
+          0x20
+          
+            
+              DUTY_LSCH5
+              reg_duty_lsch5.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH5_CONF1
+          LEDC_LSCH5_CONF1.
+          0x70
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH5
+              reg_duty_scale_lsch5.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH5
+              reg_duty_cycle_lsch5.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH5
+              reg_duty_num_lsch5.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH5
+              reg_duty_inc_lsch5.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH5
+              reg_duty_start_lsch5.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH5_DUTY_R
+          LEDC_LSCH5_DUTY_R.
+          0x74
+          0x20
+          
+            
+              DUTY_LSCH5_R
+              reg_duty_lsch5_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSTIMER0_CONF
+          LEDC_LSTIMER0_CONF.
+          0xA0
+          0x20
+          0x00800000
+          
+            
+              LSTIMER0_DUTY_RES
+              reg_lstimer0_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER0
+              reg_clk_div_lstimer0.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER0_PAUSE
+              reg_lstimer0_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER0_RST
+              reg_lstimer0_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER0
+              reg_tick_sel_lstimer0.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER0_PARA_UP
+              reg_lstimer0_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER0_VALUE
+          LEDC_LSTIMER0_VALUE.
+          0xA4
+          0x20
+          
+            
+              LSTIMER0_CNT
+              reg_lstimer0_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER1_CONF
+          LEDC_LSTIMER1_CONF.
+          0xA8
+          0x20
+          0x00800000
+          
+            
+              LSTIMER1_DUTY_RES
+              reg_lstimer1_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER1
+              reg_clk_div_lstimer1.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER1_PAUSE
+              reg_lstimer1_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER1_RST
+              reg_lstimer1_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER1
+              reg_tick_sel_lstimer1.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER1_PARA_UP
+              reg_lstimer1_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER1_VALUE
+          LEDC_LSTIMER1_VALUE.
+          0xAC
+          0x20
+          
+            
+              LSTIMER1_CNT
+              reg_lstimer1_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER2_CONF
+          LEDC_LSTIMER2_CONF.
+          0xB0
+          0x20
+          0x00800000
+          
+            
+              LSTIMER2_DUTY_RES
+              reg_lstimer2_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER2
+              reg_clk_div_lstimer2.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER2_PAUSE
+              reg_lstimer2_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER2_RST
+              reg_lstimer2_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER2
+              reg_tick_sel_lstimer2.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER2_PARA_UP
+              reg_lstimer2_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER2_VALUE
+          LEDC_LSTIMER2_VALUE.
+          0xB4
+          0x20
+          
+            
+              LSTIMER2_CNT
+              reg_lstimer2_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER3_CONF
+          LEDC_LSTIMER3_CONF.
+          0xB8
+          0x20
+          0x00800000
+          
+            
+              LSTIMER3_DUTY_RES
+              reg_lstimer3_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER3
+              reg_clk_div_lstimer3.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER3_PAUSE
+              reg_lstimer3_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER3_RST
+              reg_lstimer3_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER3
+              reg_tick_sel_lstimer3.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER3_PARA_UP
+              reg_lstimer3_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER3_VALUE
+          LEDC_LSTIMER3_VALUE.
+          0xBC
+          0x20
+          
+            
+              LSTIMER3_CNT
+              reg_lstimer3_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          LEDC_INT_RAW.
+          0xC0
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_RAW
+              reg_lstimer0_ovf_int_raw.
+              0
+              1
+              read-only
+            
+            
+              LSTIMER1_OVF_INT_RAW
+              reg_lstimer1_ovf_int_raw.
+              1
+              1
+              read-only
+            
+            
+              LSTIMER2_OVF_INT_RAW
+              reg_lstimer2_ovf_int_raw.
+              2
+              1
+              read-only
+            
+            
+              LSTIMER3_OVF_INT_RAW
+              reg_lstimer3_ovf_int_raw.
+              3
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_RAW
+              reg_duty_chng_end_lsch0_int_raw.
+              4
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_RAW
+              reg_duty_chng_end_lsch1_int_raw.
+              5
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_RAW
+              reg_duty_chng_end_lsch2_int_raw.
+              6
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_RAW
+              reg_duty_chng_end_lsch3_int_raw.
+              7
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_RAW
+              reg_duty_chng_end_lsch4_int_raw.
+              8
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_RAW
+              reg_duty_chng_end_lsch5_int_raw.
+              9
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH0_INT_RAW
+              reg_ovf_cnt_lsch0_int_raw.
+              10
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH1_INT_RAW
+              reg_ovf_cnt_lsch1_int_raw.
+              11
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH2_INT_RAW
+              reg_ovf_cnt_lsch2_int_raw.
+              12
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH3_INT_RAW
+              reg_ovf_cnt_lsch3_int_raw.
+              13
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH4_INT_RAW
+              reg_ovf_cnt_lsch4_int_raw.
+              14
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH5_INT_RAW
+              reg_ovf_cnt_lsch5_int_raw.
+              15
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          LEDC_INT_ST.
+          0xC4
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_ST
+              reg_lstimer0_ovf_int_st.
+              0
+              1
+              read-only
+            
+            
+              LSTIMER1_OVF_INT_ST
+              reg_lstimer1_ovf_int_st.
+              1
+              1
+              read-only
+            
+            
+              LSTIMER2_OVF_INT_ST
+              reg_lstimer2_ovf_int_st.
+              2
+              1
+              read-only
+            
+            
+              LSTIMER3_OVF_INT_ST
+              reg_lstimer3_ovf_int_st.
+              3
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_ST
+              reg_duty_chng_end_lsch0_int_st.
+              4
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_ST
+              reg_duty_chng_end_lsch1_int_st.
+              5
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_ST
+              reg_duty_chng_end_lsch2_int_st.
+              6
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_ST
+              reg_duty_chng_end_lsch3_int_st.
+              7
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_ST
+              reg_duty_chng_end_lsch4_int_st.
+              8
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_ST
+              reg_duty_chng_end_lsch5_int_st.
+              9
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH0_INT_ST
+              reg_ovf_cnt_lsch0_int_st.
+              10
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH1_INT_ST
+              reg_ovf_cnt_lsch1_int_st.
+              11
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH2_INT_ST
+              reg_ovf_cnt_lsch2_int_st.
+              12
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH3_INT_ST
+              reg_ovf_cnt_lsch3_int_st.
+              13
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH4_INT_ST
+              reg_ovf_cnt_lsch4_int_st.
+              14
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH5_INT_ST
+              reg_ovf_cnt_lsch5_int_st.
+              15
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          LEDC_INT_ENA.
+          0xC8
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_ENA
+              reg_lstimer0_ovf_int_ena.
+              0
+              1
+              read-write
+            
+            
+              LSTIMER1_OVF_INT_ENA
+              reg_lstimer1_ovf_int_ena.
+              1
+              1
+              read-write
+            
+            
+              LSTIMER2_OVF_INT_ENA
+              reg_lstimer2_ovf_int_ena.
+              2
+              1
+              read-write
+            
+            
+              LSTIMER3_OVF_INT_ENA
+              reg_lstimer3_ovf_int_ena.
+              3
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_ENA
+              reg_duty_chng_end_lsch0_int_ena.
+              4
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_ENA
+              reg_duty_chng_end_lsch1_int_ena.
+              5
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_ENA
+              reg_duty_chng_end_lsch2_int_ena.
+              6
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_ENA
+              reg_duty_chng_end_lsch3_int_ena.
+              7
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_ENA
+              reg_duty_chng_end_lsch4_int_ena.
+              8
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_ENA
+              reg_duty_chng_end_lsch5_int_ena.
+              9
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH0_INT_ENA
+              reg_ovf_cnt_lsch0_int_ena.
+              10
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH1_INT_ENA
+              reg_ovf_cnt_lsch1_int_ena.
+              11
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH2_INT_ENA
+              reg_ovf_cnt_lsch2_int_ena.
+              12
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH3_INT_ENA
+              reg_ovf_cnt_lsch3_int_ena.
+              13
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH4_INT_ENA
+              reg_ovf_cnt_lsch4_int_ena.
+              14
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH5_INT_ENA
+              reg_ovf_cnt_lsch5_int_ena.
+              15
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          LEDC_INT_CLR.
+          0xCC
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_CLR
+              reg_lstimer0_ovf_int_clr.
+              0
+              1
+              write-only
+            
+            
+              LSTIMER1_OVF_INT_CLR
+              reg_lstimer1_ovf_int_clr.
+              1
+              1
+              write-only
+            
+            
+              LSTIMER2_OVF_INT_CLR
+              reg_lstimer2_ovf_int_clr.
+              2
+              1
+              write-only
+            
+            
+              LSTIMER3_OVF_INT_CLR
+              reg_lstimer3_ovf_int_clr.
+              3
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_CLR
+              reg_duty_chng_end_lsch0_int_clr.
+              4
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_CLR
+              reg_duty_chng_end_lsch1_int_clr.
+              5
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_CLR
+              reg_duty_chng_end_lsch2_int_clr.
+              6
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_CLR
+              reg_duty_chng_end_lsch3_int_clr.
+              7
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_CLR
+              reg_duty_chng_end_lsch4_int_clr.
+              8
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_CLR
+              reg_duty_chng_end_lsch5_int_clr.
+              9
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH0_INT_CLR
+              reg_ovf_cnt_lsch0_int_clr.
+              10
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH1_INT_CLR
+              reg_ovf_cnt_lsch1_int_clr.
+              11
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH2_INT_CLR
+              reg_ovf_cnt_lsch2_int_clr.
+              12
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH3_INT_CLR
+              reg_ovf_cnt_lsch3_int_clr.
+              13
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH4_INT_CLR
+              reg_ovf_cnt_lsch4_int_clr.
+              14
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH5_INT_CLR
+              reg_ovf_cnt_lsch5_int_clr.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CONF
+          LEDC_CONF.
+          0xD0
+          0x20
+          
+            
+              APB_CLK_SEL
+              reg_apb_clk_sel.
+              0
+              2
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          LEDC_DATE.
+          0xFC
+          0x20
+          0x19061700
+          
+            
+              LEDC_DATE
+              reg_ledc_date.
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      RMT
+      Remote Control Peripheral
+      RMT
+      0x60016000
+      
+        0x0
+        0x78
+        registers
+      
+      
+        RMT
+        28
+      
+      
+        
+          CH0DATA
+          RMT_CH0DATA_REG.
+          0x0
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH1DATA
+          RMT_CH1DATA_REG.
+          0x4
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH2DATA
+          RMT_CH2DATA_REG.
+          0x8
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH3DATA
+          RMT_CH3DATA_REG.
+          0xC
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          2
+          0x4
+          0-1
+          CH%s_TX_CONF0
+          RMT_CH%sCONF%s_REG.
+          0x10
+          0x20
+          0x00710200
+          
+            
+              TX_START
+              reg_tx_start_ch0.
+              0
+              1
+              write-only
+            
+            
+              MEM_RD_RST
+              reg_mem_rd_rst_ch0.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch0.
+              2
+              1
+              write-only
+            
+            
+              TX_CONTI_MODE
+              reg_tx_conti_mode_ch0.
+              3
+              1
+              read-write
+            
+            
+              MEM_TX_WRAP_EN
+              reg_mem_tx_wrap_en_ch0.
+              4
+              1
+              read-write
+            
+            
+              IDLE_OUT_LV
+              reg_idle_out_lv_ch0.
+              5
+              1
+              read-write
+            
+            
+              IDLE_OUT_EN
+              reg_idle_out_en_ch0.
+              6
+              1
+              read-write
+            
+            
+              TX_STOP
+              reg_tx_stop_ch0.
+              7
+              1
+              read-write
+            
+            
+              DIV_CNT
+              reg_div_cnt_ch0.
+              8
+              8
+              read-write
+            
+            
+              MEM_SIZE
+              reg_mem_size_ch0.
+              16
+              3
+              read-write
+            
+            
+              CARRIER_EFF_EN
+              reg_carrier_eff_en_ch0.
+              20
+              1
+              read-write
+            
+            
+              CARRIER_EN
+              reg_carrier_en_ch0.
+              21
+              1
+              read-write
+            
+            
+              CARRIER_OUT_LV
+              reg_carrier_out_lv_ch0.
+              22
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch0.
+              23
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_reg_conf_update_ch0.
+              24
+              1
+              write-only
+            
+          
+        
+        
+          2
+          0x8
+          2-3
+          CH%s_RX_CONF0
+          RMT_CH2CONF0_REG.
+          0x18
+          0x20
+          0x30FFFF02
+          
+            
+              DIV_CNT
+              reg_div_cnt_ch2.
+              0
+              8
+              read-write
+            
+            
+              IDLE_THRES
+              reg_idle_thres_ch2.
+              8
+              15
+              read-write
+            
+            
+              MEM_SIZE
+              reg_mem_size_ch2.
+              23
+              3
+              read-write
+            
+            
+              CARRIER_EN
+              reg_carrier_en_ch2.
+              28
+              1
+              read-write
+            
+            
+              CARRIER_OUT_LV
+              reg_carrier_out_lv_ch2.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          CH2CONF1
+          RMT_CH2CONF1_REG.
+          0x1C
+          0x20
+          0x000001E8
+          
+            
+              RX_EN
+              reg_rx_en_ch2.
+              0
+              1
+              read-write
+            
+            
+              MEM_WR_RST
+              reg_mem_wr_rst_ch2.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch2.
+              2
+              1
+              write-only
+            
+            
+              MEM_OWNER
+              reg_mem_owner_ch2.
+              3
+              1
+              read-write
+            
+            
+              RX_FILTER_EN
+              reg_rx_filter_en_ch2.
+              4
+              1
+              read-write
+            
+            
+              RX_FILTER_THRES
+              reg_rx_filter_thres_ch2.
+              5
+              8
+              read-write
+            
+            
+              MEM_RX_WRAP_EN
+              reg_mem_rx_wrap_en_ch2.
+              13
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch2.
+              14
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_conf_update_ch2.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CH3CONF1
+          RMT_CH3CONF1_REG.
+          0x24
+          0x20
+          0x000001E8
+          
+            
+              RX_EN
+              reg_rx_en_ch3.
+              0
+              1
+              read-write
+            
+            
+              MEM_WR_RST
+              reg_mem_wr_rst_ch3.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch3.
+              2
+              1
+              write-only
+            
+            
+              MEM_OWNER
+              reg_mem_owner_ch3.
+              3
+              1
+              read-write
+            
+            
+              RX_FILTER_EN
+              reg_rx_filter_en_ch3.
+              4
+              1
+              read-write
+            
+            
+              RX_FILTER_THRES
+              reg_rx_filter_thres_ch3.
+              5
+              8
+              read-write
+            
+            
+              MEM_RX_WRAP_EN
+              reg_mem_rx_wrap_en_ch3.
+              13
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch3.
+              14
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_conf_update_ch3.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CH0STATUS
+          RMT_CH0STATUS_REG.
+          0x28
+          0x20
+          
+            
+              MEM_RADDR_EX
+              reg_mem_raddr_ex_ch0.
+              0
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch0.
+              9
+              3
+              read-only
+            
+            
+              APB_MEM_WADDR
+              reg_apb_mem_waddr_ch0.
+              12
+              9
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch0.
+              21
+              1
+              read-only
+            
+            
+              MEM_EMPTY
+              reg_mem_empty_ch0.
+              22
+              1
+              read-only
+            
+            
+              APB_MEM_WR_ERR
+              reg_apb_mem_wr_err_ch0.
+              23
+              1
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch0.
+              24
+              8
+              read-only
+            
+          
+        
+        
+          CH1STATUS
+          RMT_CH1STATUS_REG.
+          0x2C
+          0x20
+          
+            
+              MEM_RADDR_EX
+              reg_mem_raddr_ex_ch1.
+              0
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch1.
+              9
+              3
+              read-only
+            
+            
+              APB_MEM_WADDR
+              reg_apb_mem_waddr_ch1.
+              12
+              9
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch1.
+              21
+              1
+              read-only
+            
+            
+              MEM_EMPTY
+              reg_mem_empty_ch1.
+              22
+              1
+              read-only
+            
+            
+              APB_MEM_WR_ERR
+              reg_apb_mem_wr_err_ch1.
+              23
+              1
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch1.
+              24
+              8
+              read-only
+            
+          
+        
+        
+          CH2STATUS
+          RMT_CH2STATUS_REG.
+          0x30
+          0x20
+          
+            
+              MEM_WADDR_EX
+              reg_mem_waddr_ex_ch2.
+              0
+              9
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch2.
+              12
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch2.
+              22
+              3
+              read-only
+            
+            
+              MEM_OWNER_ERR
+              reg_mem_owner_err_ch2.
+              25
+              1
+              read-only
+            
+            
+              MEM_FULL
+              reg_mem_full_ch2.
+              26
+              1
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch2.
+              27
+              1
+              read-only
+            
+          
+        
+        
+          CH3STATUS
+          RMT_CH3STATUS_REG.
+          0x34
+          0x20
+          
+            
+              MEM_WADDR_EX
+              reg_mem_waddr_ex_ch3.
+              0
+              9
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch3.
+              12
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch3.
+              22
+              3
+              read-only
+            
+            
+              MEM_OWNER_ERR
+              reg_mem_owner_err_ch3.
+              25
+              1
+              read-only
+            
+            
+              MEM_FULL
+              reg_mem_full_ch3.
+              26
+              1
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch3.
+              27
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          RMT_INT_RAW_REG.
+          0x38
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_RAW
+              reg_ch%s_tx_end_int_raw.
+              0
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_RAW
+              reg_ch2_rx_end_int_raw.
+              2
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_RAW
+              reg_ch%s_err_int_raw.
+              4
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_RAW
+              reg_ch2_err_int_raw.
+              6
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_RAW
+              reg_ch%s_tx_thr_event_int_raw.
+              8
+              1
+              read-only
+            
+            
+              CH2_RX_THR_EVENT_INT_RAW
+              reg_ch2_rx_thr_event_int_raw.
+              10
+              1
+              read-only
+            
+            
+              CH3_RX_THR_EVENT_INT_RAW
+              reg_ch3_rx_thr_event_int_raw.
+              11
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_RAW
+              reg_ch%s_tx_loop_int_raw.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          RMT_INT_ST_REG.
+          0x3C
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_ST
+              reg_ch%s_tx_end_int_st.
+              0
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_ST
+              reg_ch2_rx_end_int_st.
+              2
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_ST
+              reg_ch%s_err_int_st.
+              4
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_ST
+              reg_ch2_err_int_st.
+              6
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_ST
+              reg_ch%s_tx_thr_event_int_st.
+              8
+              1
+              read-only
+            
+            
+              CH2_RX_THR_EVENT_INT_ST
+              reg_ch2_rx_thr_event_int_st.
+              10
+              1
+              read-only
+            
+            
+              CH3_RX_THR_EVENT_INT_ST
+              reg_ch3_rx_thr_event_int_st.
+              11
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_ST
+              reg_ch%s_tx_loop_int_st.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          RMT_INT_ENA_REG.
+          0x40
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_ENA
+              reg_ch%s_tx_end_int_ena.
+              0
+              1
+              read-write
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_ENA
+              reg_ch2_rx_end_int_ena.
+              2
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_ENA
+              reg_ch%s_err_int_ena.
+              4
+              1
+              read-write
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_ENA
+              reg_ch2_err_int_ena.
+              6
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_ENA
+              reg_ch%s_tx_thr_event_int_ena.
+              8
+              1
+              read-write
+            
+            
+              CH2_RX_THR_EVENT_INT_ENA
+              reg_ch2_rx_thr_event_int_ena.
+              10
+              1
+              read-write
+            
+            
+              CH3_RX_THR_EVENT_INT_ENA
+              reg_ch3_rx_thr_event_int_ena.
+              11
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_ENA
+              reg_ch%s_tx_loop_int_ena.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          RMT_INT_CLR_REG.
+          0x44
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_CLR
+              reg_ch%s_tx_end_int_clr.
+              0
+              1
+              write-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_CLR
+              reg_ch2_rx_end_int_clr.
+              2
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_CLR
+              reg_ch%s_err_int_clr.
+              4
+              1
+              write-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_CLR
+              reg_ch2_err_int_clr.
+              6
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_CLR
+              reg_ch%s_tx_thr_event_int_clr.
+              8
+              1
+              write-only
+            
+            
+              CH2_RX_THR_EVENT_INT_CLR
+              reg_ch2_rx_thr_event_int_clr.
+              10
+              1
+              write-only
+            
+            
+              CH3_RX_THR_EVENT_INT_CLR
+              reg_ch3_rx_thr_event_int_clr.
+              11
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_CLR
+              reg_ch%s_tx_loop_int_clr.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          CH0CARRIER_DUTY
+          RMT_CH0CARRIER_DUTY_REG.
+          0x48
+          0x20
+          0x00400040
+          
+            
+              CARRIER_LOW
+              reg_carrier_low_ch0.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH
+              reg_carrier_high_ch0.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH1CARRIER_DUTY
+          RMT_CH1CARRIER_DUTY_REG.
+          0x4C
+          0x20
+          0x00400040
+          
+            
+              CARRIER_LOW
+              reg_carrier_low_ch1.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH
+              reg_carrier_high_ch1.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH2_RX_CARRIER_RM
+          RMT_CH2_RX_CARRIER_RM_REG.
+          0x50
+          0x20
+          
+            
+              CARRIER_LOW_THRES
+              reg_carrier_low_thres_ch2.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH_THRES
+              reg_carrier_high_thres_ch2.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH3_RX_CARRIER_RM
+          RMT_CH3_RX_CARRIER_RM_REG.
+          0x54
+          0x20
+          
+            
+              CARRIER_LOW_THRES
+              reg_carrier_low_thres_ch3.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH_THRES
+              reg_carrier_high_thres_ch3.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          2
+          0x4
+          0-1
+          CH%s_TX_LIM
+          RMT_CH%s_TX_LIM_REG.
+          0x58
+          0x20
+          0x00000080
+          
+            
+              TX_LIM
+              reg_rmt_tx_lim_ch0.
+              0
+              9
+              read-write
+            
+            
+              TX_LOOP_NUM
+              reg_rmt_tx_loop_num_ch0.
+              9
+              10
+              read-write
+            
+            
+              TX_LOOP_CNT_EN
+              reg_rmt_tx_loop_cnt_en_ch0.
+              19
+              1
+              read-write
+            
+            
+              LOOP_COUNT_RESET
+              reg_loop_count_reset_ch0.
+              20
+              1
+              write-only
+            
+          
+        
+        
+          2
+          0x4
+          2-3
+          CH%s_RX_LIM
+          RMT_CH2_RX_LIM_REG.
+          0x60
+          0x20
+          0x00000080
+          
+            
+              RX_LIM
+              reg_rmt_rx_lim_ch2.
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SYS_CONF
+          RMT_SYS_CONF_REG.
+          0x68
+          0x20
+          0x05000010
+          
+            
+              APB_FIFO_MASK
+              reg_apb_fifo_mask.
+              0
+              1
+              read-write
+            
+            
+              MEM_CLK_FORCE_ON
+              reg_mem_clk_force_on.
+              1
+              1
+              read-write
+            
+            
+              MEM_FORCE_PD
+              reg_rmt_mem_force_pd.
+              2
+              1
+              read-write
+            
+            
+              MEM_FORCE_PU
+              reg_rmt_mem_force_pu.
+              3
+              1
+              read-write
+            
+            
+              SCLK_DIV_NUM
+              reg_rmt_sclk_div_num.
+              4
+              8
+              read-write
+            
+            
+              SCLK_DIV_A
+              reg_rmt_sclk_div_a.
+              12
+              6
+              read-write
+            
+            
+              SCLK_DIV_B
+              reg_rmt_sclk_div_b.
+              18
+              6
+              read-write
+            
+            
+              SCLK_SEL
+              reg_rmt_sclk_sel.
+              24
+              2
+              read-write
+            
+            
+              SCLK_ACTIVE
+              reg_rmt_sclk_active.
+              26
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TX_SIM
+          RMT_TX_SIM_REG.
+          0x6C
+          0x20
+          
+            
+              TX_SIM_CH0
+              reg_rmt_tx_sim_ch0.
+              0
+              1
+              read-write
+            
+            
+              TX_SIM_CH1
+              reg_rmt_tx_sim_ch1.
+              1
+              1
+              read-write
+            
+            
+              TX_SIM_EN
+              reg_rmt_tx_sim_en.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          REF_CNT_RST
+          RMT_REF_CNT_RST_REG.
+          0x70
+          0x20
+          
+            
+              CH0
+              reg_ref_cnt_rst_ch0.
+              0
+              1
+              write-only
+            
+            
+              CH1
+              reg_ref_cnt_rst_ch1.
+              1
+              1
+              write-only
+            
+            
+              CH2
+              reg_ref_cnt_rst_ch2.
+              2
+              1
+              write-only
+            
+            
+              CH3
+              reg_ref_cnt_rst_ch3.
+              3
+              1
+              write-only
+            
+          
+        
+        
+          DATE
+          RMT_DATE_REG.
+          0xCC
+          0x20
+          0x02006231
+          
+            
+              DATE
+              reg_rmt_date.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      RNG
+      Hardware random number generator
+      RNG
+      0x60026000
+      
+        0x0
+        0x4
+        registers
+      
+      
+        
+          DATA
+          Random number data
+          0xB0
+          0x20
+        
+      
+    
+    
+      RSA
+      RSA (Rivest Shamir Adleman) Accelerator
+      RSA
+      0x6003C000
+      
+        0x0
+        0x74
+        registers
+      
+      
+        RSA
+        47
+      
+      
+        
+          16
+          0x1
+          M_MEM[%s]
+          The memory that stores M
+          0x0
+          0x8
+        
+        
+          16
+          0x1
+          Z_MEM[%s]
+          The memory that stores Z
+          0x200
+          0x8
+        
+        
+          16
+          0x1
+          Y_MEM[%s]
+          The memory that stores Y
+          0x400
+          0x8
+        
+        
+          16
+          0x1
+          X_MEM[%s]
+          The memory that stores X
+          0x600
+          0x8
+        
+        
+          M_PRIME
+          RSA M_prime register
+          0x800
+          0x20
+          
+            
+              M_PRIME
+              Those bits stores m'
+              0
+              32
+              read-write
+            
+          
+        
+        
+          MODE
+          RSA mode register
+          0x804
+          0x20
+          
+            
+              MODE
+              rsa mode (rsa length).
+              0
+              7
+              read-write
+            
+          
+        
+        
+          QUERY_CLEAN
+          RSA query clean register
+          0x808
+          0x20
+          
+            
+              QUERY_CLEAN
+              query clean
+              0
+              1
+              read-only
+            
+          
+        
+        
+          SET_START_MODEXP
+          RSA modular exponentiation trigger register.
+          0x80C
+          0x20
+          
+            
+              SET_START_MODEXP
+              start modular exponentiation
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_START_MODMULT
+          RSA modular multiplication trigger register.
+          0x810
+          0x20
+          
+            
+              SET_START_MODMULT
+              start modular multiplication
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_START_MULT
+          RSA normal multiplication trigger register.
+          0x814
+          0x20
+          
+            
+              SET_START_MULT
+              start multiplicaiton
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_IDLE
+          RSA query idle register
+          0x818
+          0x20
+          
+            
+              QUERY_IDLE
+              query rsa idle. 1'b0: busy, 1'b1: idle
+              0
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          RSA interrupt clear register
+          0x81C
+          0x20
+          
+            
+              CLEAR_INTERRUPT
+              set this bit to clear RSA interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          CONSTANT_TIME
+          RSA constant time option register
+          0x820
+          0x20
+          0x00000001
+          
+            
+              CONSTANT_TIME
+              Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SEARCH_ENABLE
+          RSA search option
+          0x824
+          0x20
+          
+            
+              SEARCH_ENABLE
+              Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SEARCH_POS
+          RSA search position configure register
+          0x828
+          0x20
+          
+            
+              SEARCH_POS
+              Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
+              0
+              12
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          RSA interrupt enable register
+          0x82C
+          0x20
+          
+            
+              INT_ENA
+              Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          RSA version control register
+          0x830
+          0x20
+          0x20200618
+          
+            
+              DATE
+              rsa version information
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+    
+      RTC_CNTL
+      Real-Time Clock Control
+      RTC_CNTL
+      0x60008000
+      
+        0x0
+        0x12C
+        registers
+      
+      
+        RTC_CORE
+        27
+      
+      
+        
+          OPTIONS0
+          rtc configure register
+          0x0
+          0x20
+          0x1C00A000
+          
+            
+              SW_STALL_APPCPU_C0
+              {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
+              0
+              2
+              read-write
+            
+            
+              SW_STALL_PROCPU_C0
+              {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
+              2
+              2
+              read-write
+            
+            
+              SW_APPCPU_RST
+              APP CPU SW reset
+              4
+              1
+              write-only
+            
+            
+              SW_PROCPU_RST
+              PRO CPU SW reset
+              5
+              1
+              write-only
+            
+            
+              BB_I2C_FORCE_PD
+              BB_I2C force power down
+              6
+              1
+              read-write
+            
+            
+              BB_I2C_FORCE_PU
+              BB_I2C force power up
+              7
+              1
+              read-write
+            
+            
+              BBPLL_I2C_FORCE_PD
+              BB_PLL _I2C force power down
+              8
+              1
+              read-write
+            
+            
+              BBPLL_I2C_FORCE_PU
+              BB_PLL_I2C force power up
+              9
+              1
+              read-write
+            
+            
+              BBPLL_FORCE_PD
+              BB_PLL force power down
+              10
+              1
+              read-write
+            
+            
+              BBPLL_FORCE_PU
+              BB_PLL force power up
+              11
+              1
+              read-write
+            
+            
+              XTL_FORCE_PD
+              crystall force power down
+              12
+              1
+              read-write
+            
+            
+              XTL_FORCE_PU
+              crystall force power up
+              13
+              1
+              read-write
+            
+            
+              XTL_EN_WAIT
+              wait bias_sleep and current source wakeup
+              14
+              4
+              read-write
+            
+            
+              XTL_EXT_CTR_SEL
+              analog configure
+              20
+              3
+              read-write
+            
+            
+              XTL_FORCE_ISO
+              analog configure
+              23
+              1
+              read-write
+            
+            
+              PLL_FORCE_ISO
+              analog configure
+              24
+              1
+              read-write
+            
+            
+              ANALOG_FORCE_ISO
+              analog configure
+              25
+              1
+              read-write
+            
+            
+              XTL_FORCE_NOISO
+              analog configure
+              26
+              1
+              read-write
+            
+            
+              PLL_FORCE_NOISO
+              analog configure
+              27
+              1
+              read-write
+            
+            
+              ANALOG_FORCE_NOISO
+              analog configure
+              28
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_RST
+              digital wrap force reset in deep sleep
+              29
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_NORST
+              digital core force no reset in deep sleep
+              30
+              1
+              read-write
+            
+            
+              SW_SYS_RST
+              SW system reset
+              31
+              1
+              write-only
+            
+          
+        
+        
+          SLP_TIMER0
+          rtc configure register
+          0x4
+          0x20
+          
+            
+              SLP_VAL_LO
+              configure the  sleep time
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SLP_TIMER1
+          rtc configure register
+          0x8
+          0x20
+          
+            
+              SLP_VAL_HI
+              RTC sleep timer high 16 bits
+              0
+              16
+              read-write
+            
+            
+              RTC_MAIN_TIMER_ALARM_EN
+              timer alarm enable bit
+              16
+              1
+              write-only
+            
+          
+        
+        
+          TIME_UPDATE
+          rtc configure register
+          0xC
+          0x20
+          
+            
+              TIMER_SYS_STALL
+              Enable to record system stall time
+              27
+              1
+              read-write
+            
+            
+              TIMER_XTL_OFF
+              Enable to record 40M XTAL OFF time
+              28
+              1
+              read-write
+            
+            
+              TIMER_SYS_RST
+              enable to record system reset time
+              29
+              1
+              read-write
+            
+            
+              RTC_TIME_UPDATE
+              Set 1: to update register with RTC timer
+              31
+              1
+              write-only
+            
+          
+        
+        
+          TIME_LOW0
+          rtc configure register
+          0x10
+          0x20
+          
+            
+              RTC_TIMER_VALUE0_LOW
+              RTC timer low 32 bits
+              0
+              32
+              read-only
+            
+          
+        
+        
+          TIME_HIGH0
+          rtc configure register
+          0x14
+          0x20
+          
+            
+              RTC_TIMER_VALUE0_HIGH
+              RTC timer high 16 bits
+              0
+              16
+              read-only
+            
+          
+        
+        
+          STATE0
+          rtc configure register
+          0x18
+          0x20
+          
+            
+              RTC_SW_CPU_INT
+              rtc software interrupt to main cpu
+              0
+              1
+              write-only
+            
+            
+              RTC_SLP_REJECT_CAUSE_CLR
+              clear rtc sleep reject cause
+              1
+              1
+              write-only
+            
+            
+              APB2RTC_BRIDGE_SEL
+              1: APB to RTC using bridge
+              22
+              1
+              read-write
+            
+            
+              SDIO_ACTIVE_IND
+              SDIO active indication
+              28
+              1
+              read-only
+            
+            
+              SLP_WAKEUP
+              leep wakeup bit
+              29
+              1
+              read-write
+            
+            
+              SLP_REJECT
+              leep reject bit
+              30
+              1
+              read-write
+            
+            
+              SLEEP_EN
+              sleep enable bit
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TIMER1
+          rtc configure register
+          0x1C
+          0x20
+          0x28140403
+          
+            
+              CPU_STALL_EN
+              CPU stall enable bit
+              0
+              1
+              read-write
+            
+            
+              CPU_STALL_WAIT
+              CPU stall wait cycles in fast_clk_rtc
+              1
+              5
+              read-write
+            
+            
+              CK8M_WAIT
+              CK8M wait cycles in slow_clk_rtc
+              6
+              8
+              read-write
+            
+            
+              XTL_BUF_WAIT
+              XTAL wait cycles in slow_clk_rtc
+              14
+              10
+              read-write
+            
+            
+              PLL_BUF_WAIT
+              PLL wait cycles in slow_clk_rtc
+              24
+              8
+              read-write
+            
+          
+        
+        
+          TIMER2
+          rtc configure register
+          0x20
+          0x20
+          0x01000000
+          
+            
+              MIN_TIME_CK8M_OFF
+              minimal cycles in slow_clk_rtc for CK8M in power down state
+              24
+              8
+              read-write
+            
+          
+        
+        
+          TIMER3
+          rtc configure register
+          0x24
+          0x20
+          0x0A080A08
+          
+            
+              WIFI_WAIT_TIMER
+              wifi power domain wakeup time
+              0
+              9
+              read-write
+            
+            
+              WIFI_POWERUP_TIMER
+              wifi power domain power on time
+              9
+              7
+              read-write
+            
+            
+              BT_WAIT_TIMER
+              bt power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              BT_POWERUP_TIMER
+              bt power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          TIMER4
+          rtc configure register
+          0x28
+          0x20
+          0x10200A08
+          
+            
+              CPU_TOP_WAIT_TIMER
+              cpu top power domain wakeup time
+              0
+              9
+              read-write
+            
+            
+              CPU_TOP_POWERUP_TIMER
+              cpu top power domain power on time
+              9
+              7
+              read-write
+            
+            
+              DG_WRAP_WAIT_TIMER
+              digital wrap power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              DG_WRAP_POWERUP_TIMER
+              digital wrap power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          TIMER5
+          rtc configure register
+          0x2C
+          0x20
+          0x00008000
+          
+            
+              MIN_SLP_VAL
+              minimal sleep cycles in slow_clk_rtc
+              8
+              8
+              read-write
+            
+          
+        
+        
+          TIMER6
+          rtc configure register
+          0x30
+          0x20
+          0x0A080000
+          
+            
+              DG_PERI_WAIT_TIMER
+              digital peri power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              DG_PERI_POWERUP_TIMER
+              digital peri power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          ANA_CONF
+          rtc configure register
+          0x34
+          0x20
+          0x00C40000
+          
+            
+              RESET_POR_FORCE_PD
+              force no bypass i2c power on reset
+              18
+              1
+              read-write
+            
+            
+              RESET_POR_FORCE_PU
+              force bypass i2c power on reset
+              19
+              1
+              read-write
+            
+            
+              GLITCH_RST_EN
+              enable glitch reset
+              20
+              1
+              read-write
+            
+            
+              SAR_I2C_PU
+              PLLA force power up
+              22
+              1
+              read-write
+            
+            
+              PLLA_FORCE_PD
+              PLLA force power down
+              23
+              1
+              read-write
+            
+            
+              PLLA_FORCE_PU
+              PLLA force power up
+              24
+              1
+              read-write
+            
+            
+              BBPLL_CAL_SLP_START
+              start BBPLL calibration during sleep
+              25
+              1
+              read-write
+            
+            
+              PVTMON_PU
+              1: PVTMON power up
+              26
+              1
+              read-write
+            
+            
+              TXRF_I2C_PU
+              1: TXRF_I2C power up
+              27
+              1
+              read-write
+            
+            
+              RFRX_PBUS_PU
+              1: RFRX_PBUS power up
+              28
+              1
+              read-write
+            
+            
+              CKGEN_I2C_PU
+              1: CKGEN_I2C power up
+              30
+              1
+              read-write
+            
+            
+              PLL_I2C_PU
+              power up pll i2c
+              31
+              1
+              read-write
+            
+          
+        
+        
+          RESET_STATE
+          rtc configure register
+          0x38
+          0x20
+          0x00003000
+          
+            
+              RESET_CAUSE_PROCPU
+              reset cause of PRO CPU
+              0
+              6
+              read-only
+            
+            
+              RESET_CAUSE_APPCPU
+              reset cause of APP CPU
+              6
+              6
+              read-only
+            
+            
+              STAT_VECTOR_SEL_APPCPU
+              APP CPU state vector sel
+              12
+              1
+              read-write
+            
+            
+              STAT_VECTOR_SEL_PROCPU
+              PRO CPU state vector sel
+              13
+              1
+              read-write
+            
+            
+              ALL_RESET_FLAG_PROCPU
+              PRO CPU reset_flag
+              14
+              1
+              read-only
+            
+            
+              ALL_RESET_FLAG_APPCPU
+              APP CPU reset flag
+              15
+              1
+              read-only
+            
+            
+              ALL_RESET_FLAG_CLR_PROCPU
+              clear PRO CPU reset_flag
+              16
+              1
+              write-only
+            
+            
+              ALL_RESET_FLAG_CLR_APPCPU
+              clear APP CPU reset flag
+              17
+              1
+              write-only
+            
+            
+              OCD_HALT_ON_RESET_APPCPU
+              APPCPU OcdHaltOnReset
+              18
+              1
+              read-write
+            
+            
+              OCD_HALT_ON_RESET_PROCPU
+              PROCPU OcdHaltOnReset
+              19
+              1
+              read-write
+            
+            
+              JTAG_RESET_FLAG_PROCPU
+              configure jtag reset configure
+              20
+              1
+              read-only
+            
+            
+              JTAG_RESET_FLAG_APPCPU
+              configure jtag reset configure
+              21
+              1
+              read-only
+            
+            
+              JTAG_RESET_FLAG_CLR_PROCPU
+              configure jtag reset configure
+              22
+              1
+              write-only
+            
+            
+              JTAG_RESET_FLAG_CLR_APPCPU
+              configure jtag reset configure
+              23
+              1
+              write-only
+            
+            
+              RTC_DRESET_MASK_APPCPU
+              configure dreset configure
+              24
+              1
+              read-write
+            
+            
+              RTC_DRESET_MASK_PROCPU
+              configure dreset configure
+              25
+              1
+              read-write
+            
+          
+        
+        
+          WAKEUP_STATE
+          rtc configure register
+          0x3C
+          0x20
+          0x00060000
+          
+            
+              RTC_WAKEUP_ENA
+              wakeup enable bitmap
+              15
+              17
+              read-write
+            
+          
+        
+        
+          INT_ENA_RTC
+          rtc configure register
+          0x40
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA
+              enable sleep wakeup interrupt
+              0
+              1
+              read-write
+            
+            
+              SLP_REJECT_INT_ENA
+              enable sleep reject interrupt
+              1
+              1
+              read-write
+            
+            
+              RTC_WDT_INT_ENA
+              enable RTC WDT interrupt
+              3
+              1
+              read-write
+            
+            
+              RTC_BROWN_OUT_INT_ENA
+              enable brown out interrupt
+              9
+              1
+              read-write
+            
+            
+              RTC_MAIN_TIMER_INT_ENA
+              enable RTC main timer interrupt
+              10
+              1
+              read-write
+            
+            
+              RTC_SWD_INT_ENA
+              enable super watch dog interrupt
+              15
+              1
+              read-write
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA
+              enable xtal32k_dead  interrupt
+              16
+              1
+              read-write
+            
+            
+              RTC_GLITCH_DET_INT_ENA
+              enbale gitch det interrupt
+              19
+              1
+              read-write
+            
+            
+              RTC_BBPLL_CAL_INT_ENA
+              enbale bbpll cal end interrupt
+              20
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW_RTC
+          rtc configure register
+          0x44
+          0x20
+          
+            
+              SLP_WAKEUP_INT_RAW
+              sleep wakeup interrupt raw
+              0
+              1
+              read-only
+            
+            
+              SLP_REJECT_INT_RAW
+              sleep reject interrupt raw
+              1
+              1
+              read-only
+            
+            
+              RTC_WDT_INT_RAW
+              RTC WDT interrupt raw
+              3
+              1
+              read-only
+            
+            
+              RTC_BROWN_OUT_INT_RAW
+              brown out interrupt raw
+              9
+              1
+              read-only
+            
+            
+              RTC_MAIN_TIMER_INT_RAW
+              RTC main timer interrupt raw
+              10
+              1
+              read-only
+            
+            
+              RTC_SWD_INT_RAW
+              super watch dog interrupt raw
+              15
+              1
+              read-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_RAW
+              xtal32k dead detection interrupt raw
+              16
+              1
+              read-only
+            
+            
+              RTC_GLITCH_DET_INT_RAW
+              glitch_det_interrupt_raw
+              19
+              1
+              read-only
+            
+            
+              RTC_BBPLL_CAL_INT_RAW
+              bbpll cal end interrupt state
+              20
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_RTC
+          rtc configure register
+          0x48
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ST
+              sleep wakeup interrupt state
+              0
+              1
+              read-only
+            
+            
+              SLP_REJECT_INT_ST
+              sleep reject interrupt state
+              1
+              1
+              read-only
+            
+            
+              RTC_WDT_INT_ST
+              RTC WDT interrupt state
+              3
+              1
+              read-only
+            
+            
+              RTC_BROWN_OUT_INT_ST
+              brown out interrupt state
+              9
+              1
+              read-only
+            
+            
+              RTC_MAIN_TIMER_INT_ST
+              RTC main timer interrupt state
+              10
+              1
+              read-only
+            
+            
+              RTC_SWD_INT_ST
+              super watch dog interrupt state
+              15
+              1
+              read-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ST
+              xtal32k dead detection interrupt state
+              16
+              1
+              read-only
+            
+            
+              RTC_GLITCH_DET_INT_ST
+              glitch_det_interrupt state
+              19
+              1
+              read-only
+            
+            
+              RTC_BBPLL_CAL_INT_ST
+              bbpll cal end interrupt state
+              20
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR_RTC
+          rtc configure register
+          0x4C
+          0x20
+          
+            
+              SLP_WAKEUP_INT_CLR
+              Clear sleep wakeup interrupt state
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_CLR
+              Clear sleep reject interrupt state
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_CLR
+              Clear RTC WDT interrupt state
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_CLR
+              Clear brown out interrupt state
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_CLR
+              Clear RTC main timer interrupt state
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_CLR
+              Clear super watch dog interrupt state
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_CLR
+              Clear RTC WDT interrupt state
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_CLR
+              Clear glitch det interrupt state
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_CLR
+              clear bbpll cal end interrupt state
+              20
+              1
+              write-only
+            
+          
+        
+        
+          STORE0
+          rtc configure register
+          0x50
+          0x20
+          
+            
+              RTC_SCRATCH0
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE1
+          rtc configure register
+          0x54
+          0x20
+          
+            
+              RTC_SCRATCH1
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE2
+          rtc configure register
+          0x58
+          0x20
+          
+            
+              RTC_SCRATCH2
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE3
+          rtc configure register
+          0x5C
+          0x20
+          
+            
+              RTC_SCRATCH3
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          EXT_XTL_CONF
+          rtc configure register
+          0x60
+          0x20
+          0x00066C80
+          
+            
+              XTAL32K_WDT_EN
+              xtal 32k watch dog enable
+              0
+              1
+              read-write
+            
+            
+              XTAL32K_WDT_CLK_FO
+              xtal 32k watch dog clock force on
+              1
+              1
+              read-write
+            
+            
+              XTAL32K_WDT_RESET
+              xtal 32k watch dog sw reset
+              2
+              1
+              read-write
+            
+            
+              XTAL32K_EXT_CLK_FO
+              xtal 32k external xtal clock force on
+              3
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_BACKUP
+              xtal 32k switch to back up clock when xtal is dead
+              4
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_RESTART
+              xtal 32k restart xtal when xtal is dead
+              5
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_RETURN
+              xtal 32k switch back xtal when xtal is restarted
+              6
+              1
+              read-write
+            
+            
+              XTAL32K_XPD_FORCE
+              Xtal 32k xpd control by sw or fsm
+              7
+              1
+              read-write
+            
+            
+              ENCKINIT_XTAL_32K
+              apply an internal clock to help xtal 32k to start
+              8
+              1
+              read-write
+            
+            
+              DBUF_XTAL_32K
+              0: single-end buffer 1: differential buffer
+              9
+              1
+              read-write
+            
+            
+              DGM_XTAL_32K
+              xtal_32k gm control
+              10
+              3
+              read-write
+            
+            
+              DRES_XTAL_32K
+              DRES_XTAL_32K
+              13
+              3
+              read-write
+            
+            
+              XPD_XTAL_32K
+              XPD_XTAL_32K
+              16
+              1
+              read-write
+            
+            
+              DAC_XTAL_32K
+              DAC_XTAL_32K
+              17
+              3
+              read-write
+            
+            
+              RTC_WDT_STATE
+              state of 32k_wdt
+              20
+              3
+              read-only
+            
+            
+              RTC_XTAL32K_GPIO_SEL
+              XTAL_32K sel. 0: external XTAL_32K
+              23
+              1
+              read-write
+            
+            
+              XTL_EXT_CTR_LV
+              0: power down XTAL at high level
+              30
+              1
+              read-write
+            
+            
+              XTL_EXT_CTR_EN
+              enable gpio configure xtal power on
+              31
+              1
+              read-write
+            
+          
+        
+        
+          EXT_WAKEUP_CONF
+          rtc configure register
+          0x64
+          0x20
+          
+            
+              GPIO_WAKEUP_FILTER
+              enable filter for gpio wakeup event
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SLP_REJECT_CONF
+          rtc configure register
+          0x68
+          0x20
+          
+            
+              RTC_SLEEP_REJECT_ENA
+              sleep reject enable
+              12
+              18
+              read-write
+            
+            
+              LIGHT_SLP_REJECT_EN
+              enable reject for light sleep
+              30
+              1
+              read-write
+            
+            
+              DEEP_SLP_REJECT_EN
+              enable reject for deep sleep
+              31
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PERIOD_CONF
+          rtc configure register
+          0x6C
+          0x20
+          
+            
+              RTC_CPUSEL_CONF
+              CPU sel option
+              29
+              1
+              read-write
+            
+            
+              RTC_CPUPERIOD_SEL
+              CPU clk sel option
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CLK_CONF
+          rtc configure register
+          0x70
+          0x20
+          0x11583218
+          
+            
+              EFUSE_CLK_FORCE_GATING
+              efuse_clk_force_gating
+              1
+              1
+              read-write
+            
+            
+              EFUSE_CLK_FORCE_NOGATING
+              efuse_clk_force_nogating
+              2
+              1
+              read-write
+            
+            
+              CK8M_DIV_SEL_VLD
+              used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+              3
+              1
+              read-write
+            
+            
+              CK8M_DIV
+              CK8M_D256_OUT divider. 00: div128
+              4
+              2
+              read-write
+            
+            
+              ENB_CK8M
+              disable CK8M and CK8M_D256_OUT
+              6
+              1
+              read-write
+            
+            
+              ENB_CK8M_DIV
+              1: CK8M_D256_OUT is actually CK8M
+              7
+              1
+              read-write
+            
+            
+              DIG_XTAL32K_EN
+              enable CK_XTAL_32K for digital core (no relationship with RTC core)
+              8
+              1
+              read-write
+            
+            
+              DIG_CLK8M_D256_EN
+              enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+              9
+              1
+              read-write
+            
+            
+              DIG_CLK8M_EN
+              enable CK8M for digital core (no relationship with RTC core)
+              10
+              1
+              read-write
+            
+            
+              CK8M_DIV_SEL
+              divider = reg_ck8m_div_sel + 1
+              12
+              3
+              read-write
+            
+            
+              XTAL_FORCE_NOGATING
+              XTAL force no gating during sleep
+              15
+              1
+              read-write
+            
+            
+              CK8M_FORCE_NOGATING
+              CK8M force no gating during sleep
+              16
+              1
+              read-write
+            
+            
+              CK8M_DFREQ
+              CK8M_DFREQ
+              17
+              8
+              read-write
+            
+            
+              CK8M_FORCE_PD
+              CK8M force power down
+              25
+              1
+              read-write
+            
+            
+              CK8M_FORCE_PU
+              CK8M force power up
+              26
+              1
+              read-write
+            
+            
+              XTAL_GLOBAL_FORCE_GATING
+              force enable xtal clk gating
+              27
+              1
+              read-write
+            
+            
+              XTAL_GLOBAL_FORCE_NOGATING
+              force bypass xtal clk gating
+              28
+              1
+              read-write
+            
+            
+              FAST_CLK_RTC_SEL
+              fast_clk_rtc sel. 0: XTAL div 4
+              29
+              1
+              read-write
+            
+            
+              ANA_CLK_RTC_SEL
+              slelect rtc slow clk
+              30
+              2
+              read-write
+            
+          
+        
+        
+          SLOW_CLK_CONF
+          rtc configure register
+          0x74
+          0x20
+          0x00400000
+          
+            
+              RTC_ANA_CLK_DIV_VLD
+              used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+              22
+              1
+              read-write
+            
+            
+              RTC_ANA_CLK_DIV
+              the clk divider num of RTC_CLK
+              23
+              8
+              read-write
+            
+            
+              RTC_SLOW_CLK_NEXT_EDGE
+              flag rtc_slow_clk_next_edge
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SDIO_CONF
+          rtc configure register
+          0x78
+          0x20
+          0x0AB0BE0A
+          
+            
+              SDIO_TIMER_TARGET
+              timer count to apply reg_sdio_dcap after sdio power on
+              0
+              8
+              read-write
+            
+            
+              SDIO_DTHDRV
+              Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+              9
+              2
+              read-write
+            
+            
+              SDIO_DCAP
+              ability to prevent LDO from overshoot
+              11
+              2
+              read-write
+            
+            
+              SDIO_INITI
+              add resistor from ldo output to ground. 0: no res
+              13
+              2
+              read-write
+            
+            
+              SDIO_EN_INITI
+              0 to set init[1:0]=0
+              15
+              1
+              read-write
+            
+            
+              SDIO_DCURLIM
+              tune current limit threshold when tieh = 0. About 800mA/(8+d)
+              16
+              3
+              read-write
+            
+            
+              SDIO_MODECURLIM
+              select current limit mode
+              19
+              1
+              read-write
+            
+            
+              SDIO_ENCURLIM
+              enable current limit
+              20
+              1
+              read-write
+            
+            
+              SDIO_REG_PD_EN
+              power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+              21
+              1
+              read-write
+            
+            
+              SDIO_FORCE
+              1: use SW option to control SDIO_REG
+              22
+              1
+              read-write
+            
+            
+              SDIO_TIEH
+              SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+              23
+              1
+              read-write
+            
+            
+              _1P8_READY
+              read only register for REG1P8_READY
+              24
+              1
+              read-only
+            
+            
+              DREFL_SDIO
+              SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+              25
+              2
+              read-write
+            
+            
+              DREFM_SDIO
+              SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+              27
+              2
+              read-write
+            
+            
+              DREFH_SDIO
+              SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+              29
+              2
+              read-write
+            
+            
+              XPD_SDIO
+              31
+              1
+              read-write
+            
+          
+        
+        
+          BIAS_CONF
+          rtc configure register
+          0x7C
+          0x20
+          0x00010800
+          
+            
+              DG_VDD_DRV_B_SLP
+              0
+              8
+              read-write
+            
+            
+              DG_VDD_DRV_B_SLP_EN
+              8
+              1
+              read-write
+            
+            
+              BIAS_BUF_IDLE
+              bias buf when rtc in normal work state
+              10
+              1
+              read-write
+            
+            
+              BIAS_BUF_WAKE
+              bias buf when rtc in wakeup state
+              11
+              1
+              read-write
+            
+            
+              BIAS_BUF_DEEP_SLP
+              bias buf when rtc in sleep state
+              12
+              1
+              read-write
+            
+            
+              BIAS_BUF_MONITOR
+              bias buf when rtc in monitor state
+              13
+              1
+              read-write
+            
+            
+              PD_CUR_DEEP_SLP
+              xpd cur when rtc in sleep_state
+              14
+              1
+              read-write
+            
+            
+              PD_CUR_MONITOR
+              xpd cur when rtc in monitor state
+              15
+              1
+              read-write
+            
+            
+              BIAS_SLEEP_DEEP_SLP
+              bias_sleep when rtc in sleep_state
+              16
+              1
+              read-write
+            
+            
+              BIAS_SLEEP_MONITOR
+              bias_sleep when rtc in monitor state
+              17
+              1
+              read-write
+            
+            
+              DBG_ATTEN_DEEP_SLP
+              DBG_ATTEN when rtc in sleep state
+              18
+              4
+              read-write
+            
+            
+              DBG_ATTEN_MONITOR
+              DBG_ATTEN when rtc in monitor state
+              22
+              4
+              read-write
+            
+          
+        
+        
+          RTC_CNTL
+          rtc configure register
+          0x80
+          0x20
+          0xA0000000
+          
+            
+              DIG_REG_CAL_EN
+              software enable digital regulator cali
+              7
+              1
+              read-write
+            
+            
+              SCK_DCAP
+              SCK_DCAP
+              14
+              8
+              read-write
+            
+            
+              DBOOST_FORCE_PD
+              RTC_DBOOST force power down
+              28
+              1
+              read-write
+            
+            
+              DBOOST_FORCE_PU
+              RTC_DBOOST force power up
+              29
+              1
+              read-write
+            
+            
+              REGULATOR_FORCE_PD
+              RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
+              30
+              1
+              read-write
+            
+            
+              REGULATOR_FORCE_PU
+              RTC_REG force power up
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PWC
+          rtc configure register
+          0x84
+          0x20
+          
+            
+              RTC_PAD_FORCE_HOLD
+              rtc pad force hold
+              21
+              1
+              read-write
+            
+          
+        
+        
+          DIG_PWC
+          rtc configure register
+          0x88
+          0x20
+          0x00555010
+          
+            
+              VDD_SPI_PWR_DRV
+              vdd_spi drv's software value
+              0
+              2
+              read-write
+            
+            
+              VDD_SPI_PWR_FORCE
+              vdd_spi drv use software value
+              2
+              1
+              read-write
+            
+            
+              LSLP_MEM_FORCE_PD
+              memories in digital core force PD in sleep
+              3
+              1
+              read-write
+            
+            
+              LSLP_MEM_FORCE_PU
+              memories in digital core force PU in sleep
+              4
+              1
+              read-write
+            
+            
+              BT_FORCE_PD
+              bt force power down
+              11
+              1
+              read-write
+            
+            
+              BT_FORCE_PU
+              bt force power up
+              12
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_PD
+              digital peri force power down
+              13
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_PU
+              digital peri force power up
+              14
+              1
+              read-write
+            
+            
+              RTC_FASTMEM_FORCE_LPD
+              fastmemory  retention mode in sleep
+              15
+              1
+              read-write
+            
+            
+              RTC_FASTMEM_FORCE_LPU
+              fastmemory donlt entry retention mode in sleep
+              16
+              1
+              read-write
+            
+            
+              WIFI_FORCE_PD
+              wifi force power down
+              17
+              1
+              read-write
+            
+            
+              WIFI_FORCE_PU
+              wifi force power up
+              18
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_PD
+              digital core force power down
+              19
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_PU
+              digital core force power up
+              20
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_PD
+              cpu core force power down
+              21
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_PU
+              cpu force power up
+              22
+              1
+              read-write
+            
+            
+              BT_PD_EN
+              enable power down bt in sleep
+              27
+              1
+              read-write
+            
+            
+              DG_PERI_PD_EN
+              enable power down digital peri in sleep
+              28
+              1
+              read-write
+            
+            
+              CPU_TOP_PD_EN
+              enable power down cpu in sleep
+              29
+              1
+              read-write
+            
+            
+              WIFI_PD_EN
+              enable power down wifi in sleep
+              30
+              1
+              read-write
+            
+            
+              DG_WRAP_PD_EN
+              enable power down digital wrap in sleep
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DIG_ISO
+          rtc configure register
+          0x8C
+          0x20
+          0xAA805080
+          
+            
+              FORCE_OFF
+              DIG_ISO force off
+              7
+              1
+              read-write
+            
+            
+              FORCE_ON
+              DIG_ISO force on
+              8
+              1
+              read-write
+            
+            
+              DG_PAD_AUTOHOLD
+              read only register to indicate digital pad auto-hold status
+              9
+              1
+              read-only
+            
+            
+              CLR_DG_PAD_AUTOHOLD
+              wtite only register to clear digital pad auto-hold
+              10
+              1
+              write-only
+            
+            
+              DG_PAD_AUTOHOLD_EN
+              digital pad enable auto-hold
+              11
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_NOISO
+              digital pad force no ISO
+              12
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_ISO
+              digital pad force ISO
+              13
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_UNHOLD
+              digital pad force un-hold
+              14
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_HOLD
+              digital pad force hold
+              15
+              1
+              read-write
+            
+            
+              BT_FORCE_ISO
+              bt force ISO
+              22
+              1
+              read-write
+            
+            
+              BT_FORCE_NOISO
+              bt force no ISO
+              23
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_ISO
+              Digital peri force ISO
+              24
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_NOISO
+              digital peri force no ISO
+              25
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_ISO
+              cpu force ISO
+              26
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_NOISO
+              cpu force no ISO
+              27
+              1
+              read-write
+            
+            
+              WIFI_FORCE_ISO
+              wifi force ISO
+              28
+              1
+              read-write
+            
+            
+              WIFI_FORCE_NOISO
+              wifi force no ISO
+              29
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_ISO
+              digital core force ISO
+              30
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_NOISO
+              digital core force no ISO
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG0
+          rtc configure register
+          0x90
+          0x20
+          0x00013214
+          
+            
+              WDT_CHIP_RESET_WIDTH
+              chip reset siginal pulse width
+              0
+              8
+              read-write
+            
+            
+              WDT_CHIP_RESET_EN
+              wdt reset whole chip enable
+              8
+              1
+              read-write
+            
+            
+              WDT_PAUSE_IN_SLP
+              pause WDT in sleep
+              9
+              1
+              read-write
+            
+            
+              WDT_APPCPU_RESET_EN
+              enable WDT reset APP CPU
+              10
+              1
+              read-write
+            
+            
+              WDT_PROCPU_RESET_EN
+              enable WDT reset PRO CPU
+              11
+              1
+              read-write
+            
+            
+              WDT_FLASHBOOT_MOD_EN
+              enable WDT in flash boot
+              12
+              1
+              read-write
+            
+            
+              WDT_SYS_RESET_LENGTH
+              system reset counter length
+              13
+              3
+              read-write
+            
+            
+              WDT_CPU_RESET_LENGTH
+              CPU reset counter length
+              16
+              3
+              read-write
+            
+            
+              WDT_STG3
+              1: interrupt stage en
+              19
+              3
+              read-write
+            
+            
+              WDT_STG2
+              1: interrupt stage en
+              22
+              3
+              read-write
+            
+            
+              WDT_STG1
+              1: interrupt stage en
+              25
+              3
+              read-write
+            
+            
+              WDT_STG0
+              1: interrupt stage en
+              28
+              3
+              read-write
+            
+            
+              WDT_EN
+              enable rtc wdt
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG1
+          rtc configure register
+          0x94
+          0x20
+          0x00030D40
+          
+            
+              WDT_STG0_HOLD
+              the hold time of stage0
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG2
+          rtc configure register
+          0x98
+          0x20
+          0x00013880
+          
+            
+              WDT_STG1_HOLD
+              the hold time of stage1
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG3
+          rtc configure register
+          0x9C
+          0x20
+          0x00000FFF
+          
+            
+              WDT_STG2_HOLD
+              the hold time of stage2
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG4
+          rtc configure register
+          0xA0
+          0x20
+          0x00000FFF
+          
+            
+              WDT_STG3_HOLD
+              the hold time of stage3
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTFEED
+          rtc configure register
+          0xA4
+          0x20
+          
+            
+              RTC_WDT_FEED
+              sw feed rtc wdt
+              31
+              1
+              write-only
+            
+          
+        
+        
+          WDTWPROTECT
+          rtc configure register
+          0xA8
+          0x20
+          
+            
+              WDT_WKEY
+              the key of rtc wdt
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SWD_CONF
+          rtc configure register
+          0xAC
+          0x20
+          0x04B00000
+          
+            
+              SWD_RESET_FLAG
+              swd reset flag
+              0
+              1
+              read-only
+            
+            
+              SWD_FEED_INT
+              swd interrupt for feeding
+              1
+              1
+              read-only
+            
+            
+              SWD_BYPASS_RST
+              Bypass swd rst
+              17
+              1
+              read-write
+            
+            
+              SWD_SIGNAL_WIDTH
+              adjust signal width send to swd
+              18
+              10
+              read-write
+            
+            
+              SWD_RST_FLAG_CLR
+              reset swd reset flag
+              28
+              1
+              write-only
+            
+            
+              SWD_FEED
+              Sw feed swd
+              29
+              1
+              write-only
+            
+            
+              SWD_DISABLE
+              disabel SWD
+              30
+              1
+              read-write
+            
+            
+              SWD_AUTO_FEED_EN
+              automatically feed swd when int comes
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SWD_WPROTECT
+          rtc configure register
+          0xB0
+          0x20
+          
+            
+              SWD_WKEY
+              the key of super wdt
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SW_CPU_STALL
+          rtc configure register
+          0xB4
+          0x20
+          
+            
+              SW_STALL_APPCPU_C1
+              {reg_sw_stall_appcpu_c1[5:0]
+              20
+              6
+              read-write
+            
+            
+              SW_STALL_PROCPU_C1
+              stall cpu by software
+              26
+              6
+              read-write
+            
+          
+        
+        
+          STORE4
+          rtc configure register
+          0xB8
+          0x20
+          
+            
+              RTC_SCRATCH4
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE5
+          rtc configure register
+          0xBC
+          0x20
+          
+            
+              RTC_SCRATCH5
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE6
+          rtc configure register
+          0xC0
+          0x20
+          
+            
+              RTC_SCRATCH6
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE7
+          rtc configure register
+          0xC4
+          0x20
+          
+            
+              RTC_SCRATCH7
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOW_POWER_ST
+          rtc configure register
+          0xC8
+          0x20
+          
+            
+              XPD_ROM0
+              rom0 power down
+              0
+              1
+              read-only
+            
+            
+              XPD_DIG_DCDC
+              External DCDC power down
+              2
+              1
+              read-only
+            
+            
+              RTC_PERI_ISO
+              rtc peripheral iso
+              3
+              1
+              read-only
+            
+            
+              XPD_RTC_PERI
+              rtc peripheral power down
+              4
+              1
+              read-only
+            
+            
+              WIFI_ISO
+              wifi iso
+              5
+              1
+              read-only
+            
+            
+              XPD_WIFI
+              wifi wrap power down
+              6
+              1
+              read-only
+            
+            
+              DIG_ISO
+              digital wrap iso
+              7
+              1
+              read-only
+            
+            
+              XPD_DIG
+              digital wrap power down
+              8
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_START
+              touch should start to work
+              9
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_SWITCH
+              touch is about to working. Switch rtc main state
+              10
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_SLP
+              touch is in sleep state
+              11
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_DONE
+              touch is done
+              12
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_START
+              ulp/cocpu should start to work
+              13
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_SWITCH
+              ulp/cocpu is about to working. Switch rtc main state
+              14
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_SLP
+              ulp/cocpu is in sleep state
+              15
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_DONE
+              ulp/cocpu is done
+              16
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_XTAL_ISO
+              no use any more
+              17
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_PLL_ON
+              rtc main state machine is in states that pll should be running
+              18
+              1
+              read-only
+            
+            
+              RTC_RDY_FOR_WAKEUP
+              rtc is ready to receive wake up trigger from wake up source
+              19
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_WAIT_END
+              rtc main state machine has been waited for some cycles
+              20
+              1
+              read-only
+            
+            
+              RTC_IN_WAKEUP_STATE
+              rtc main state machine is in the states of wakeup process
+              21
+              1
+              read-only
+            
+            
+              RTC_IN_LOW_POWER_STATE
+              rtc main state machine is in the states of low power
+              22
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_8M
+              rtc main state machine is in wait 8m state
+              23
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_PLL
+              rtc main state machine is in wait pll state
+              24
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_XTL
+              rtc main state machine is in wait xtal state
+              25
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_SLP
+              rtc main state machine is in sleep state
+              26
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_IDLE
+              rtc main state machine is in idle state
+              27
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE
+              rtc main state machine status
+              28
+              4
+              read-only
+            
+          
+        
+        
+          DIAG0
+          rtc configure register
+          0xCC
+          0x20
+          
+            
+              RTC_LOW_POWER_DIAG1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          PAD_HOLD
+          rtc configure register
+          0xD0
+          0x20
+          
+            
+              RTC_GPIO_PIN0_HOLD
+              the hold configure of rtc gpio0
+              0
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_HOLD
+              the hold configure of rtc gpio1
+              1
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_HOLD
+              the hold configure of rtc gpio2
+              2
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_HOLD
+              the hold configure of rtc gpio3
+              3
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_HOLD
+              the hold configure of rtc gpio4
+              4
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_HOLD
+              the hold configure of rtc gpio5
+              5
+              1
+              read-write
+            
+          
+        
+        
+          DIG_PAD_HOLD
+          rtc configure register
+          0xD4
+          0x20
+          
+            
+              DIG_PAD_HOLD
+              the configure of digital pad
+              0
+              32
+              read-write
+            
+          
+        
+        
+          BROWN_OUT
+          rtc configure register
+          0xD8
+          0x20
+          0x43FF0010
+          
+            
+              INT_WAIT
+              brown out interrupt wait cycles
+              4
+              10
+              read-write
+            
+            
+              CLOSE_FLASH_ENA
+              enable close flash when brown out happens
+              14
+              1
+              read-write
+            
+            
+              PD_RF_ENA
+              enable power down RF when brown out happens
+              15
+              1
+              read-write
+            
+            
+              RST_WAIT
+              brown out reset wait cycles
+              16
+              10
+              read-write
+            
+            
+              RST_ENA
+              enable brown out reset
+              26
+              1
+              read-write
+            
+            
+              RST_SEL
+              1:  4-pos reset
+              27
+              1
+              read-write
+            
+            
+              ANA_RST_EN
+              brown_out origin reset enable
+              28
+              1
+              read-write
+            
+            
+              CNT_CLR
+              clear brown out counter
+              29
+              1
+              write-only
+            
+            
+              ENA
+              enable brown out
+              30
+              1
+              read-write
+            
+            
+              DET
+              the flag of brown det from analog
+              31
+              1
+              read-only
+            
+          
+        
+        
+          TIME_LOW1
+          rtc configure register
+          0xDC
+          0x20
+          
+            
+              RTC_TIMER_VALUE1_LOW
+              RTC timer low 32 bits
+              0
+              32
+              read-only
+            
+          
+        
+        
+          TIME_HIGH1
+          rtc configure register
+          0xE0
+          0x20
+          
+            
+              RTC_TIMER_VALUE1_HIGH
+              RTC timer high 16 bits
+              0
+              16
+              read-only
+            
+          
+        
+        
+          XTAL32K_CLK_FACTOR
+          rtc configure register
+          0xE4
+          0x20
+          
+            
+              XTAL32K_CLK_FACTOR
+              xtal 32k watch dog backup clock factor
+              0
+              32
+              read-write
+            
+          
+        
+        
+          XTAL32K_CONF
+          rtc configure register
+          0xE8
+          0x20
+          0x0FF00000
+          
+            
+              XTAL32K_RETURN_WAIT
+              cycles to wait to return noral xtal 32k
+              0
+              4
+              read-write
+            
+            
+              XTAL32K_RESTART_WAIT
+              cycles to wait to repower on xtal 32k
+              4
+              16
+              read-write
+            
+            
+              XTAL32K_WDT_TIMEOUT
+              If no clock detected for this amount of time
+              20
+              8
+              read-write
+            
+            
+              XTAL32K_STABLE_THRES
+              if restarted xtal32k period is smaller than this
+              28
+              4
+              read-write
+            
+          
+        
+        
+          USB_CONF
+          rtc configure register
+          0xEC
+          0x20
+          
+            
+              IO_MUX_RESET_DISABLE
+              disable io_mux reset
+              18
+              1
+              read-write
+            
+          
+        
+        
+          SLP_REJECT_CAUSE
+          RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+          0xF0
+          0x20
+          
+            
+              REJECT_CAUSE
+              sleep reject cause
+              0
+              18
+              read-only
+            
+          
+        
+        
+          OPTION1
+          rtc configure register
+          0xF4
+          0x20
+          
+            
+              FORCE_DOWNLOAD_BOOT
+              force chip entry download mode
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SLP_WAKEUP_CAUSE
+          RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+          0xF8
+          0x20
+          
+            
+              WAKEUP_CAUSE
+              sleep wakeup cause
+              0
+              17
+              read-only
+            
+          
+        
+        
+          ULP_CP_TIMER_1
+          rtc configure register
+          0xFC
+          0x20
+          0x0000C800
+          
+            
+              ULP_CP_TIMER_SLP_CYCLE
+              sleep cycles for ULP-coprocessor timer
+              8
+              24
+              read-write
+            
+          
+        
+        
+          INT_ENA_RTC_W1TS
+          rtc configure register
+          0x100
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA_W1TS
+              enable sleep wakeup interrupt
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_ENA_W1TS
+              enable sleep reject interrupt
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_ENA_W1TS
+              enable RTC WDT interrupt
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_ENA_W1TS
+              enable brown out interrupt
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_ENA_W1TS
+              enable RTC main timer interrupt
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_ENA_W1TS
+              enable super watch dog interrupt
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA_W1TS
+              enable xtal32k_dead  interrupt
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_ENA_W1TS
+              enbale gitch det interrupt
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_ENA_W1TS
+              enbale bbpll cal interrupt
+              20
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA_RTC_W1TC
+          rtc configure register
+          0x104
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA_W1TC
+              clear sleep wakeup interrupt enable
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_ENA_W1TC
+              clear sleep reject interrupt enable
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_ENA_W1TC
+              clear RTC WDT interrupt enable
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_ENA_W1TC
+              clear brown out interrupt enable
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_ENA_W1TC
+              Clear RTC main timer interrupt enable
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_ENA_W1TC
+              clear super watch dog interrupt enable
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA_W1TC
+              clear xtal32k_dead  interrupt enable
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_ENA_W1TC
+              clear gitch det interrupt enable
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_ENA_W1TC
+              clear bbpll cal interrupt enable
+              20
+              1
+              write-only
+            
+          
+        
+        
+          RETENTION_CTRL
+          rtc configure register
+          0x108
+          0x20
+          0xA0D00000
+          
+            
+              RETENTION_CLK_SEL
+              Retention clk sel
+              18
+              1
+              read-write
+            
+            
+              RETENTION_DONE_WAIT
+              Retention done wait time
+              19
+              3
+              read-write
+            
+            
+              RETENTION_CLKOFF_WAIT
+              Retention clkoff wait time
+              22
+              4
+              read-write
+            
+            
+              RETENTION_EN
+              enable cpu retention when light sleep
+              26
+              1
+              read-write
+            
+            
+              RETENTION_WAIT
+              wait cycles for rention operation
+              27
+              5
+              read-write
+            
+          
+        
+        
+          FIB_SEL
+          rtc configure register
+          0x10C
+          0x20
+          0x00000007
+          
+            
+              RTC_FIB_SEL
+              select use analog fib signal
+              0
+              3
+              read-write
+            
+          
+        
+        
+          GPIO_WAKEUP
+          rtc configure register
+          0x110
+          0x20
+          
+            
+              RTC_GPIO_WAKEUP_STATUS
+              rtc gpio wakeup flag
+              0
+              6
+              read-only
+            
+            
+              RTC_GPIO_WAKEUP_STATUS_CLR
+              clear rtc gpio wakeup flag
+              6
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN_CLK_GATE
+              enable rtc io clk gate
+              7
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_INT_TYPE
+              configure gpio wakeup type
+              8
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN4_INT_TYPE
+              configure gpio wakeup type
+              11
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN3_INT_TYPE
+              configure gpio wakeup type
+              14
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN2_INT_TYPE
+              configure gpio wakeup type
+              17
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN1_INT_TYPE
+              configure gpio wakeup type
+              20
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN0_INT_TYPE
+              configure gpio wakeup type
+              23
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN5_WAKEUP_ENABLE
+              enable wakeup from rtc gpio5
+              26
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_WAKEUP_ENABLE
+              enable wakeup from rtc gpio4
+              27
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_WAKEUP_ENABLE
+              enable wakeup from rtc gpio3
+              28
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_WAKEUP_ENABLE
+              enable wakeup from rtc gpio2
+              29
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_WAKEUP_ENABLE
+              enable wakeup from rtc gpio1
+              30
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN0_WAKEUP_ENABLE
+              enable wakeup from rtc gpio0
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DBG_SEL
+          rtc configure register
+          0x114
+          0x20
+          
+            
+              RTC_DEBUG_12M_NO_GATING
+              use for debug
+              1
+              1
+              read-write
+            
+            
+              RTC_DEBUG_BIT_SEL
+              use for debug
+              2
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL0
+              use for debug
+              7
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL1
+              use for debug
+              12
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL2
+              use for debug
+              17
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL3
+              use for debug
+              22
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL4
+              use for debug
+              27
+              5
+              read-write
+            
+          
+        
+        
+          DBG_MAP
+          rtc configure register
+          0x118
+          0x20
+          
+            
+              RTC_GPIO_PIN5_MUX_SEL
+              use for debug
+              2
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_MUX_SEL
+              use for debug
+              3
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_MUX_SEL
+              use for debug
+              4
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_MUX_SEL
+              use for debug
+              5
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_MUX_SEL
+              use for debug
+              6
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN0_MUX_SEL
+              use for debug
+              7
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_FUN_SEL
+              use for debug
+              8
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN4_FUN_SEL
+              use for debug
+              12
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN3_FUN_SEL
+              use for debug
+              16
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN2_FUN_SEL
+              use for debug
+              20
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN1_FUN_SEL
+              use for debug
+              24
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN0_FUN_SEL
+              use for debug
+              28
+              4
+              read-write
+            
+          
+        
+        
+          SENSOR_CTRL
+          rtc configure register
+          0x11C
+          0x20
+          
+            
+              SAR2_PWDET_CCT
+              reg_sar2_pwdet_cct
+              27
+              3
+              read-write
+            
+            
+              FORCE_XPD_SAR
+              force power up SAR
+              30
+              2
+              read-write
+            
+          
+        
+        
+          DBG_SAR_SEL
+          rtc configure register
+          0x120
+          0x20
+          
+            
+              SAR_DEBUG_SEL
+              use for debug
+              27
+              5
+              read-write
+            
+          
+        
+        
+          PG_CTRL
+          rtc configure register
+          0x124
+          0x20
+          
+            
+              POWER_GLITCH_DSENSE
+              power glitch desense
+              26
+              2
+              read-write
+            
+            
+              POWER_GLITCH_FORCE_PD
+              force disable power glitch
+              28
+              1
+              read-write
+            
+            
+              POWER_GLITCH_FORCE_PU
+              force enable power glitch
+              29
+              1
+              read-write
+            
+            
+              POWER_GLITCH_EFUSE_SEL
+              use efuse value control power glitch enable
+              30
+              1
+              read-write
+            
+            
+              POWER_GLITCH_EN
+              enable power glitch
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          rtc configure register
+          0x1FC
+          0x20
+          0x02007270
+          
+            
+              RTC_CNTL_DATE
+              verision
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SENSITIVE
+      Sensitive
+      SENSITIVE
+      0x600C1000
+      
+        0x0
+        0x178
+        registers
+      
+      
+        
+          ROM_TABLE_LOCK
+          SENSITIVE_ROM_TABLE_LOCK_REG
+          0x0
+          0x20
+          
+            
+              ROM_TABLE_LOCK
+              rom_table_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ROM_TABLE
+          SENSITIVE_ROM_TABLE_REG
+          0x4
+          0x20
+          
+            
+              ROM_TABLE
+              rom_table
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PRIVILEGE_MODE_SEL_LOCK
+          SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+          0x8
+          0x20
+          
+            
+              PRIVILEGE_MODE_SEL_LOCK
+              privilege_mode_sel_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PRIVILEGE_MODE_SEL
+          SENSITIVE_PRIVILEGE_MODE_SEL_REG
+          0xC
+          0x20
+          
+            
+              PRIVILEGE_MODE_SEL
+              privilege_mode_sel
+              0
+              1
+              read-write
+            
+          
+        
+        
+          APB_PERIPHERAL_ACCESS_0
+          SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+          0x10
+          0x20
+          
+            
+              APB_PERIPHERAL_ACCESS_LOCK
+              apb_peripheral_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          APB_PERIPHERAL_ACCESS_1
+          SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+          0x14
+          0x20
+          0x00000001
+          
+            
+              APB_PERIPHERAL_ACCESS_SPLIT_BURST
+              apb_peripheral_access_split_burst
+              0
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_0
+          SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+          0x18
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_LOCK
+              internal_sram_usage_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_1
+          SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+          0x1C
+          0x20
+          0x0000000F
+          
+            
+              INTERNAL_SRAM_USAGE_CPU_CACHE
+              internal_sram_usage_cpu_cache
+              0
+              1
+              read-write
+            
+            
+              INTERNAL_SRAM_USAGE_CPU_SRAM
+              internal_sram_usage_cpu_sram
+              1
+              3
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_3
+          SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+          0x20
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM
+              internal_sram_usage_mac_dump_sram
+              0
+              3
+              read-write
+            
+            
+              INTERNAL_SRAM_ALLOC_MAC_DUMP
+              internal_sram_alloc_mac_dump
+              3
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_4
+          SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+          0x24
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_LOG_SRAM
+              internal_sram_usage_log_sram
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_TAG_ACCESS_0
+          SENSITIVE_CACHE_TAG_ACCESS_0_REG
+          0x28
+          0x20
+          
+            
+              CACHE_TAG_ACCESS_LOCK
+              cache_tag_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_TAG_ACCESS_1
+          SENSITIVE_CACHE_TAG_ACCESS_1_REG
+          0x2C
+          0x20
+          0x0000000F
+          
+            
+              PRO_I_TAG_RD_ACS
+              pro_i_tag_rd_acs
+              0
+              1
+              read-write
+            
+            
+              PRO_I_TAG_WR_ACS
+              pro_i_tag_wr_acs
+              1
+              1
+              read-write
+            
+            
+              PRO_D_TAG_RD_ACS
+              pro_d_tag_rd_acs
+              2
+              1
+              read-write
+            
+            
+              PRO_D_TAG_WR_ACS
+              pro_d_tag_wr_acs
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_ACCESS_0
+          SENSITIVE_CACHE_MMU_ACCESS_0_REG
+          0x30
+          0x20
+          
+            
+              CACHE_MMU_ACCESS_LOCK
+              cache_mmu_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_ACCESS_1
+          SENSITIVE_CACHE_MMU_ACCESS_1_REG
+          0x34
+          0x20
+          0x00000003
+          
+            
+              PRO_MMU_RD_ACS
+              pro_mmu_rd_acs
+              0
+              1
+              read-write
+            
+            
+              PRO_MMU_WR_ACS
+              pro_mmu_wr_acs
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SPI2_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+          0x38
+          0x20
+          
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK
+              dma_apbperi_spi2_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SPI2_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+          0x3C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+          0x40
+          0x20
+          
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK
+              dma_apbperi_uchi0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+          0x44
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_I2S0_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+          0x48
+          0x20
+          
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK
+              dma_apbperi_i2s0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_I2S0_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+          0x4C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_MAC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+          0x50
+          0x20
+          
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_mac_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_MAC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+          0x54
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+          0x58
+          0x20
+          
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK
+              dma_apbperi_backup_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+          0x5C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_LC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+          0x60
+          0x20
+          
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_lc_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_LC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+          0x64
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_AES_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+          0x68
+          0x20
+          
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK
+              dma_apbperi_aes_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_AES_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+          0x6C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SHA_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+          0x70
+          0x20
+          
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK
+              dma_apbperi_sha_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SHA_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+          0x74
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+          0x78
+          0x20
+          
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_adc_dac_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+          0x7C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_0
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+          0x80
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_LOCK
+              dma_apbperi_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_1
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+          0x84
+          0x20
+          0x00000003
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR
+              dma_apbperi_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_EN
+              dma_apbperi_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_2
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+          0x88
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR
+              dma_apbperi_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              dma_apbperi_pms_monitor_violate_status_world
+              1
+              2
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              dma_apbperi_pms_monitor_violate_status_addr
+              3
+              24
+              read-only
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_3
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+          0x8C
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR
+              dma_apbperi_pms_monitor_violate_status_wr
+              0
+              1
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN
+              dma_apbperi_pms_monitor_violate_status_byteen
+              1
+              4
+              read-only
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+          0x90
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK
+              core_x_iram0_dram0_dma_split_line_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+          0x94
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0
+              core_x_iram0_dram0_dma_sram_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1
+              core_x_iram0_dram0_dma_sram_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2
+              core_x_iram0_dram0_dma_sram_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR
+              core_x_iram0_dram0_dma_sram_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+          0x98
+          0x20
+          
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0
+              core_x_iram0_sram_line_0_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1
+              core_x_iram0_sram_line_0_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2
+              core_x_iram0_sram_line_0_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR
+              core_x_iram0_sram_line_0_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+          0x9C
+          0x20
+          
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0
+              core_x_iram0_sram_line_1_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1
+              core_x_iram0_sram_line_1_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2
+              core_x_iram0_sram_line_1_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR
+              core_x_iram0_sram_line_1_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+          0xA0
+          0x20
+          
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0
+              core_x_dram0_dma_sram_line_0_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1
+              core_x_dram0_dma_sram_line_0_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2
+              core_x_dram0_dma_sram_line_0_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR
+              core_x_dram0_dma_sram_line_0_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+          0xA4
+          0x20
+          
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0
+              core_x_dram0_dma_sram_line_1_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1
+              core_x_dram0_dma_sram_line_1_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2
+              core_x_dram0_dma_sram_line_1_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR
+              core_x_dram0_dma_sram_line_1_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+          0xA8
+          0x20
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_LOCK
+              core_x_iram0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+          0xAC
+          0x20
+          0x001C7FFF
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              core_x_iram0_pms_constrain_sram_world_1_pms_0
+              0
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              core_x_iram0_pms_constrain_sram_world_1_pms_1
+              3
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              core_x_iram0_pms_constrain_sram_world_1_pms_2
+              6
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              core_x_iram0_pms_constrain_sram_world_1_pms_3
+              9
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0
+              core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+              12
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS
+              core_x_iram0_pms_constrain_rom_world_1_pms
+              18
+              3
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_2
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+          0xB0
+          0x20
+          0x001C7FFF
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              core_x_iram0_pms_constrain_sram_world_0_pms_0
+              0
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              core_x_iram0_pms_constrain_sram_world_0_pms_1
+              3
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              core_x_iram0_pms_constrain_sram_world_0_pms_2
+              6
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              core_x_iram0_pms_constrain_sram_world_0_pms_3
+              9
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0
+              core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+              12
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS
+              core_x_iram0_pms_constrain_rom_world_0_pms
+              18
+              3
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_0
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+          0xB4
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_LOCK
+              core_0_iram0_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_1
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+          0xB8
+          0x20
+          0x00000003
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR
+              core_0_iram0_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN
+              core_0_iram0_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_2
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+          0xBC
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR
+              core_0_iram0_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR
+              core_0_iram0_pms_monitor_violate_status_wr
+              1
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE
+              core_0_iram0_pms_monitor_violate_status_loadstore
+              2
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              core_0_iram0_pms_monitor_violate_status_world
+              3
+              2
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              core_0_iram0_pms_monitor_violate_status_addr
+              5
+              24
+              read-only
+            
+          
+        
+        
+          CORE_X_DRAM0_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+          0xC0
+          0x20
+          
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_LOCK
+              core_x_dram0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_DRAM0_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+          0xC4
+          0x20
+          0x0F0FF0FF
+          
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              core_x_dram0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              core_x_dram0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              core_x_dram0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              core_x_dram0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              core_x_dram0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              core_x_dram0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              core_x_dram0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              core_x_dram0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS
+              core_x_dram0_pms_constrain_rom_world_0_pms
+              24
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS
+              core_x_dram0_pms_constrain_rom_world_1_pms
+              26
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_0
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+          0xC8
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_LOCK
+              core_0_dram0_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_1
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+          0xCC
+          0x20
+          0x00000003
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR
+              core_0_dram0_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN
+              core_0_dram0_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_2
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+          0xD0
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR
+              core_0_dram0_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK
+              core_0_dram0_pms_monitor_violate_status_lock
+              1
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              core_0_dram0_pms_monitor_violate_status_world
+              2
+              2
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              core_0_dram0_pms_monitor_violate_status_addr
+              4
+              24
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_3
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+          0xD4
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR
+              core_0_dram0_pms_monitor_violate_status_wr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN
+              core_0_dram0_pms_monitor_violate_status_byteen
+              1
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+          0xD8
+          0x20
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_LOCK
+              core_0_pif_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+          0xDC
+          0x20
+          0xCF0FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART
+              core_0_pif_pms_constrain_world_0_uart
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1
+              core_0_pif_pms_constrain_world_0_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0
+              core_0_pif_pms_constrain_world_0_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO
+              core_0_pif_pms_constrain_world_0_gpio
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2
+              core_0_pif_pms_constrain_world_0_fe2
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE
+              core_0_pif_pms_constrain_world_0_fe
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER
+              core_0_pif_pms_constrain_world_0_timer
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC
+              core_0_pif_pms_constrain_world_0_rtc
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX
+              core_0_pif_pms_constrain_world_0_io_mux
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG
+              core_0_pif_pms_constrain_world_0_wdg
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC
+              core_0_pif_pms_constrain_world_0_misc
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C
+              core_0_pif_pms_constrain_world_0_i2c
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1
+              core_0_pif_pms_constrain_world_0_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_2
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+          0xE0
+          0x20
+          0xFCC30CF3
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT
+              core_0_pif_pms_constrain_world_0_bt
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0
+              core_0_pif_pms_constrain_world_0_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0
+              core_0_pif_pms_constrain_world_0_uhci0
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT
+              core_0_pif_pms_constrain_world_0_rmt
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC
+              core_0_pif_pms_constrain_world_0_ledc
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB
+              core_0_pif_pms_constrain_world_0_bb
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP
+              core_0_pif_pms_constrain_world_0_timergroup
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1
+              core_0_pif_pms_constrain_world_0_timergroup1
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER
+              core_0_pif_pms_constrain_world_0_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_3
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+          0xE4
+          0x20
+          0x3CC0CC33
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2
+              core_0_pif_pms_constrain_world_0_spi_2
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL
+              core_0_pif_pms_constrain_world_0_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN
+              core_0_pif_pms_constrain_world_0_can
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1
+              core_0_pif_pms_constrain_world_0_i2s1
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT
+              core_0_pif_pms_constrain_world_0_rwbt
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC
+              core_0_pif_pms_constrain_world_0_wifimac
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR
+              core_0_pif_pms_constrain_world_0_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_4
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+          0xE8
+          0x20
+          0xFFFFF3FC
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP
+              core_0_pif_pms_constrain_world_0_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI
+              core_0_pif_pms_constrain_world_0_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA
+              core_0_pif_pms_constrain_world_0_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC
+              core_0_pif_pms_constrain_world_0_apb_adc
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR
+              core_0_pif_pms_constrain_world_0_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE
+              core_0_pif_pms_constrain_world_0_usb_device
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM
+              core_0_pif_pms_constrain_world_0_system
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE
+              core_0_pif_pms_constrain_world_0_sensitive
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT
+              core_0_pif_pms_constrain_world_0_interrupt
+              20
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY
+              core_0_pif_pms_constrain_world_0_dma_copy
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG
+              core_0_pif_pms_constrain_world_0_cache_config
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD
+              core_0_pif_pms_constrain_world_0_ad
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO
+              core_0_pif_pms_constrain_world_0_dio
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER
+              core_0_pif_pms_constrain_world_0_world_controller
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_5
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+          0xEC
+          0x20
+          0xCF0FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART
+              core_0_pif_pms_constrain_world_1_uart
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1
+              core_0_pif_pms_constrain_world_1_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0
+              core_0_pif_pms_constrain_world_1_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO
+              core_0_pif_pms_constrain_world_1_gpio
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2
+              core_0_pif_pms_constrain_world_1_fe2
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE
+              core_0_pif_pms_constrain_world_1_fe
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER
+              core_0_pif_pms_constrain_world_1_timer
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC
+              core_0_pif_pms_constrain_world_1_rtc
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX
+              core_0_pif_pms_constrain_world_1_io_mux
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG
+              core_0_pif_pms_constrain_world_1_wdg
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC
+              core_0_pif_pms_constrain_world_1_misc
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C
+              core_0_pif_pms_constrain_world_1_i2c
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1
+              core_0_pif_pms_constrain_world_1_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_6
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+          0xF0
+          0x20
+          0xFCC30CF3
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT
+              core_0_pif_pms_constrain_world_1_bt
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0
+              core_0_pif_pms_constrain_world_1_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0
+              core_0_pif_pms_constrain_world_1_uhci0
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT
+              core_0_pif_pms_constrain_world_1_rmt
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC
+              core_0_pif_pms_constrain_world_1_ledc
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB
+              core_0_pif_pms_constrain_world_1_bb
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP
+              core_0_pif_pms_constrain_world_1_timergroup
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1
+              core_0_pif_pms_constrain_world_1_timergroup1
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER
+              core_0_pif_pms_constrain_world_1_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_7
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+          0xF4
+          0x20
+          0x3CC0CC33
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2
+              core_0_pif_pms_constrain_world_1_spi_2
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL
+              core_0_pif_pms_constrain_world_1_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN
+              core_0_pif_pms_constrain_world_1_can
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1
+              core_0_pif_pms_constrain_world_1_i2s1
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT
+              core_0_pif_pms_constrain_world_1_rwbt
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC
+              core_0_pif_pms_constrain_world_1_wifimac
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR
+              core_0_pif_pms_constrain_world_1_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_8
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+          0xF8
+          0x20
+          0xFFFFF3FC
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP
+              core_0_pif_pms_constrain_world_1_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI
+              core_0_pif_pms_constrain_world_1_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA
+              core_0_pif_pms_constrain_world_1_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC
+              core_0_pif_pms_constrain_world_1_apb_adc
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR
+              core_0_pif_pms_constrain_world_1_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE
+              core_0_pif_pms_constrain_world_1_usb_device
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM
+              core_0_pif_pms_constrain_world_1_system
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE
+              core_0_pif_pms_constrain_world_1_sensitive
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT
+              core_0_pif_pms_constrain_world_1_interrupt
+              20
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY
+              core_0_pif_pms_constrain_world_1_dma_copy
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG
+              core_0_pif_pms_constrain_world_1_cache_config
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD
+              core_0_pif_pms_constrain_world_1_ad
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO
+              core_0_pif_pms_constrain_world_1_dio
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER
+              core_0_pif_pms_constrain_world_1_world_controller
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_9
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+          0xFC
+          0x20
+          0x003FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0
+              core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+              0
+              11
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1
+              core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+              11
+              11
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_10
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+          0x100
+          0x20
+          0x00000FFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L
+              core_0_pif_pms_constrain_rtcfast_world_0_l
+              0
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H
+              core_0_pif_pms_constrain_rtcfast_world_0_h
+              3
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L
+              core_0_pif_pms_constrain_rtcfast_world_1_l
+              6
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H
+              core_0_pif_pms_constrain_rtcfast_world_1_h
+              9
+              3
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_0
+          SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+          0x104
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_LOCK
+              region_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_1
+          SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+          0x108
+          0x20
+          0x00003FFF
+          
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_0
+              region_pms_constrain_world_0_area_0
+              0
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_1
+              region_pms_constrain_world_0_area_1
+              2
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_2
+              region_pms_constrain_world_0_area_2
+              4
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_3
+              region_pms_constrain_world_0_area_3
+              6
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_4
+              region_pms_constrain_world_0_area_4
+              8
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_5
+              region_pms_constrain_world_0_area_5
+              10
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_6
+              region_pms_constrain_world_0_area_6
+              12
+              2
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_2
+          SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+          0x10C
+          0x20
+          0x00003FFF
+          
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_0
+              region_pms_constrain_world_1_area_0
+              0
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_1
+              region_pms_constrain_world_1_area_1
+              2
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_2
+              region_pms_constrain_world_1_area_2
+              4
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_3
+              region_pms_constrain_world_1_area_3
+              6
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_4
+              region_pms_constrain_world_1_area_4
+              8
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_5
+              region_pms_constrain_world_1_area_5
+              10
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_6
+              region_pms_constrain_world_1_area_6
+              12
+              2
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_3
+          SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+          0x110
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_0
+              region_pms_constrain_addr_0
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_4
+          SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+          0x114
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_1
+              region_pms_constrain_addr_1
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_5
+          SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+          0x118
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_2
+              region_pms_constrain_addr_2
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_6
+          SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+          0x11C
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_3
+              region_pms_constrain_addr_3
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_7
+          SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+          0x120
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_4
+              region_pms_constrain_addr_4
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_8
+          SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+          0x124
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_5
+              region_pms_constrain_addr_5
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_9
+          SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+          0x128
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_6
+              region_pms_constrain_addr_6
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_10
+          SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+          0x12C
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_7
+              region_pms_constrain_addr_7
+              0
+              30
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_0
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+          0x130
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_LOCK
+              core_0_pif_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_1
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+          0x134
+          0x20
+          0x00000003
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR
+              core_0_pif_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_EN
+              core_0_pif_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_2
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+          0x138
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR
+              core_0_pif_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0
+              core_0_pif_pms_monitor_violate_status_hport_0
+              1
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE
+              core_0_pif_pms_monitor_violate_status_hsize
+              2
+              3
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE
+              core_0_pif_pms_monitor_violate_status_hwrite
+              5
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD
+              core_0_pif_pms_monitor_violate_status_hworld
+              6
+              2
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_3
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+          0x13C
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR
+              core_0_pif_pms_monitor_violate_status_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_4
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+          0x140
+          0x20
+          0x00000003
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR
+              core_0_pif_pms_monitor_nonword_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN
+              core_0_pif_pms_monitor_nonword_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_5
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+          0x144
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR
+              core_0_pif_pms_monitor_nonword_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE
+              core_0_pif_pms_monitor_nonword_violate_status_hsize
+              1
+              2
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD
+              core_0_pif_pms_monitor_nonword_violate_status_hworld
+              3
+              2
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_6
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+          0x148
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR
+              core_0_pif_pms_monitor_nonword_violate_status_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_0
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+          0x14C
+          0x20
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_LOCK
+              backup_bus_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_1
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+          0x150
+          0x20
+          0xCF0FFFFF
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UART
+              backup_bus_pms_constrain_uart
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1
+              backup_bus_pms_constrain_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0
+              backup_bus_pms_constrain_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_GPIO
+              backup_bus_pms_constrain_gpio
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_FE2
+              backup_bus_pms_constrain_fe2
+              8
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_FE
+              backup_bus_pms_constrain_fe
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMER
+              backup_bus_pms_constrain_timer
+              12
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RTC
+              backup_bus_pms_constrain_rtc
+              14
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_IO_MUX
+              backup_bus_pms_constrain_io_mux
+              16
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_WDG
+              backup_bus_pms_constrain_wdg
+              18
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_MISC
+              backup_bus_pms_constrain_misc
+              24
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2C
+              backup_bus_pms_constrain_i2c
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UART1
+              backup_bus_pms_constrain_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_2
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+          0x154
+          0x20
+          0xFCC30CF3
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BT
+              backup_bus_pms_constrain_bt
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0
+              backup_bus_pms_constrain_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UHCI0
+              backup_bus_pms_constrain_uhci0
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RMT
+              backup_bus_pms_constrain_rmt
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_LEDC
+              backup_bus_pms_constrain_ledc
+              16
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BB
+              backup_bus_pms_constrain_bb
+              22
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP
+              backup_bus_pms_constrain_timergroup
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1
+              backup_bus_pms_constrain_timergroup1
+              28
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER
+              backup_bus_pms_constrain_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_3
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+          0x158
+          0x20
+          0x3CC0CC33
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_SPI_2
+              backup_bus_pms_constrain_spi_2
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL
+              backup_bus_pms_constrain_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CAN
+              backup_bus_pms_constrain_can
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2S1
+              backup_bus_pms_constrain_i2s1
+              14
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RWBT
+              backup_bus_pms_constrain_rwbt
+              22
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC
+              backup_bus_pms_constrain_wifimac
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_PWR
+              backup_bus_pms_constrain_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_4
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+          0x15C
+          0x20
+          0x0000F3FC
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP
+              backup_bus_pms_constrain_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI
+              backup_bus_pms_constrain_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA
+              backup_bus_pms_constrain_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_APB_ADC
+              backup_bus_pms_constrain_apb_adc
+              8
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BT_PWR
+              backup_bus_pms_constrain_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE
+              backup_bus_pms_constrain_usb_device
+              14
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_0
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+          0x160
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_LOCK
+              backup_bus_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_1
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+          0x164
+          0x20
+          0x00000003
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR
+              backup_bus_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_EN
+              backup_bus_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_2
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+          0x168
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR
+              backup_bus_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS
+              backup_bus_pms_monitor_violate_status_htrans
+              1
+              2
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE
+              backup_bus_pms_monitor_violate_status_hsize
+              3
+              3
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE
+              backup_bus_pms_monitor_violate_status_hwrite
+              6
+              1
+              read-only
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_3
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+          0x16C
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR
+              backup_bus_pms_monitor_violate_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          SENSITIVE_CLOCK_GATE_REG
+          0x170
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          SENSITIVE_DATE_REG
+          0xFFC
+          0x20
+          0x02010200
+          
+            
+              DATE
+              reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SHA
+      SHA (Secure Hash Algorithm) Accelerator
+      SHA
+      0x6003B000
+      
+        0x0
+        0xB0
+        registers
+      
+      
+        SHA
+        49
+      
+      
+        
+          MODE
+          Initial configuration register.
+          0x0
+          0x20
+          
+            
+              MODE
+              Sha mode.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          T_STRING
+          SHA 512/t configuration register 0.
+          0x4
+          0x20
+          
+            
+              T_STRING
+              Sha t_string (used if and only if mode == SHA_512/t).
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T_LENGTH
+          SHA 512/t configuration register 1.
+          0x8
+          0x20
+          
+            
+              T_LENGTH
+              Sha t_length (used if and only if mode == SHA_512/t).
+              0
+              6
+              read-write
+            
+          
+        
+        
+          DMA_BLOCK_NUM
+          DMA configuration register 0.
+          0xC
+          0x20
+          
+            
+              DMA_BLOCK_NUM
+              Dma-sha block number.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          START
+          Typical SHA configuration register 0.
+          0x10
+          0x20
+          
+            
+              START
+              Reserved.
+              1
+              31
+              read-only
+            
+          
+        
+        
+          CONTINUE
+          Typical SHA configuration register 1.
+          0x14
+          0x20
+          
+            
+              CONTINUE
+              Reserved.
+              1
+              31
+              read-only
+            
+          
+        
+        
+          BUSY
+          Busy register.
+          0x18
+          0x20
+          
+            
+              STATE
+              Sha busy state. 1'b0: idle. 1'b1: busy.
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DMA_START
+          DMA configuration register 1.
+          0x1C
+          0x20
+          
+            
+              DMA_START
+              Start dma-sha.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          DMA_CONTINUE
+          DMA configuration register 2.
+          0x20
+          0x20
+          
+            
+              DMA_CONTINUE
+              Continue dma-sha.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          CLEAR_IRQ
+          Interrupt clear register.
+          0x24
+          0x20
+          
+            
+              CLEAR_INTERRUPT
+              Clear sha interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          IRQ_ENA
+          Interrupt enable register.
+          0x28
+          0x20
+          
+            
+              INTERRUPT_ENA
+              Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Date register.
+          0x2C
+          0x20
+          0x20200616
+          
+            
+              DATE
+              Sha date information/ sha version information.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          64
+          0x1
+          H_MEM[%s]
+          Sha H memory which contains intermediate hash or finial hash.
+          0x40
+          0x8
+        
+        
+          64
+          0x1
+          M_MEM[%s]
+          Sha M memory which contains message.
+          0x80
+          0x8
+        
+      
+    
+    
+      SPI0
+      SPI (Serial Peripheral Interface) Controller
+      SPI0
+      0x60003000
+      
+        0x0
+        0x48
+        registers
+      
+      
+        
+          CTRL
+          SPI0 control register.
+          0x8
+          0x20
+          0x002C2000
+          
+            
+              FDUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller.
+              3
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable
+              7
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable
+              8
+              1
+              read-write
+            
+            
+              FASTRD_MODE
+              This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+              13
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+              14
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low
+              19
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              WP
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.
+              21
+              1
+              read-write
+            
+            
+              FREAD_DIO
+              In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FREAD_QIO
+              In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          CTRL1
+          SPI0 control1 register.
+          0xC
+          0x20
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+              0
+              2
+              read-write
+            
+            
+              RXFIFO_RST
+              SPI0 RX FIFO reset signal.
+              30
+              1
+              write-only
+            
+          
+        
+        
+          CTRL2
+          SPI0 control2 register.
+          0x10
+          0x20
+          0x00000021
+          
+            
+              CS_SETUP_TIME
+              (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
+              0
+              5
+              read-write
+            
+            
+              CS_HOLD_TIME
+              Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
+              5
+              5
+              read-write
+            
+            
+              CS_HOLD_DELAY
+              These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
+              25
+              6
+              read-write
+            
+            
+              SYNC_RESET
+              The FSM will be reset.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          CLOCK
+          SPI clock division control register.
+          0x14
+          0x20
+          0x00030103
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_mem_clkcnt_N.
+              0
+              8
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+              8
+              8
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+              16
+              8
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              Set this bit in 1-division mode.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI0 user register.
+          0x18
+          0x20
+          
+            
+              CS_HOLD
+              spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+              6
+              1
+              read-write
+            
+            
+              CS_SETUP
+              spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+              7
+              1
+              read-write
+            
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+              9
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              spi clock is disable in dummy phase when the bit is enable.
+              26
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI0 user1 register.
+          0x1C
+          0x20
+          0x5C000007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+              0
+              6
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1).
+              26
+              6
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI0 user2 register.
+          0x20
+          0x20
+          0x70000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command.
+              0
+              16
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1)
+              28
+              4
+              read-write
+            
+          
+        
+        
+          RD_STATUS
+          SPI0 read control register.
+          0x2C
+          0x20
+          
+            
+              WB_MODE
+              Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+              16
+              8
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI0 misc register
+          0x34
+          0x20
+          
+            
+              TRANS_END
+              The bit is used to indicate the  spi0_mst_st controlled transmitting is done.
+              3
+              1
+              read-write
+            
+            
+              TRANS_END_INT_ENA
+              The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.
+              4
+              1
+              read-write
+            
+            
+              CSPI_ST_TRANS_END
+              The bit is used to indicate the  spi0_slv_st controlled transmitting is done.
+              5
+              1
+              read-write
+            
+            
+              CSPI_ST_TRANS_END_INT_ENA
+              The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
+              6
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle
+              9
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_FCTRL
+          SPI0 bit mode control register.
+          0x3C
+          0x20
+          
+            
+              CACHE_REQ_EN
+              For SPI0, Cache access enable, 1: enable, 0:disable.
+              0
+              1
+              read-write
+            
+            
+              CACHE_USR_ADDR_4BYTE
+              For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+              1
+              1
+              read-write
+            
+            
+              CACHE_FLASH_USR_CMD
+              For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.
+              2
+              1
+              read-write
+            
+            
+              FDIN_DUAL
+              For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              3
+              1
+              read-write
+            
+            
+              FDOUT_DUAL
+              For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              4
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.
+              5
+              1
+              read-write
+            
+            
+              FDIN_QUAD
+              For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              6
+              1
+              read-write
+            
+            
+              FDOUT_QUAD
+              For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              7
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          FSM
+          SPI0 FSM status register
+          0x54
+          0x20
+          0x00000200
+          
+            
+              CSPI_ST
+              The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+              0
+              4
+              read-only
+            
+            
+              EM_ST
+              The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+              4
+              3
+              read-only
+            
+            
+              CSPI_LOCK_DELAY_TIME
+              The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+              7
+              5
+              read-write
+            
+          
+        
+        
+          TIMING_CALI
+          SPI0 timing calibration register
+          0xA8
+          0x20
+          0x00000001
+          
+            
+              TIMING_CLK_ENA
+              The bit is used to enable timing adjust clock for all reading operations.
+              0
+              1
+              read-write
+            
+            
+              TIMING_CALI
+              The bit is used to enable timing auto-calibration for all reading operations.
+              1
+              1
+              read-write
+            
+            
+              EXTRA_DUMMY_CYCLELEN
+              add extra dummy spi clock cycle length for spi clock calibration.
+              2
+              3
+              read-write
+            
+          
+        
+        
+          DIN_MODE
+          SPI0 input delay mode control register
+          0xAC
+          0x20
+          
+            
+              DIN0_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              0
+              2
+              read-write
+            
+            
+              DIN1_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              2
+              2
+              read-write
+            
+            
+              DIN2_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              4
+              2
+              read-write
+            
+            
+              DIN3_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DIN_NUM
+          SPI0 input delay number control register
+          0xB0
+          0x20
+          
+            
+              DIN0_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              0
+              2
+              read-write
+            
+            
+              DIN1_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              2
+              2
+              read-write
+            
+            
+              DIN2_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              4
+              2
+              read-write
+            
+            
+              DIN3_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DOUT_MODE
+          SPI0 output delay mode control register
+          0xB4
+          0x20
+          
+            
+              DOUT0_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              0
+              1
+              read-write
+            
+            
+              DOUT1_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              1
+              1
+              read-write
+            
+            
+              DOUT2_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              2
+              1
+              read-write
+            
+            
+              DOUT3_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          SPI0 clk_gate register
+          0xDC
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              Register clock gate enable signal. 1: Enable. 0: Disable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_CLK_SEL
+          SPI0 module clock select register
+          0xE0
+          0x20
+          
+            
+              SPI01_CLK_SEL
+              When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
+              0
+              2
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x3FC
+          0x20
+          0x02007130
+          
+            
+              DATE
+              SPI register version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI1
+      SPI (Serial Peripheral Interface) Controller
+      SPI1
+      0x60002000
+      
+        0x0
+        0xA8
+        registers
+      
+      
+        
+          CMD
+          SPI1 memory command register
+          0x0
+          0x20
+          
+            
+              SPI1_MST_ST
+              The current status of SPI1 master FSM.
+              0
+              4
+              read-only
+            
+            
+              MSPI_ST
+              The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+              4
+              4
+              read-only
+            
+            
+              FLASH_PE
+              In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
+              17
+              1
+              read-write
+            
+            
+              USR
+              User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              18
+              1
+              read-write
+            
+            
+              FLASH_HPM
+              Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.
+              19
+              1
+              read-write
+            
+            
+              FLASH_RES
+              This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              FLASH_DP
+              Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              21
+              1
+              read-write
+            
+            
+              FLASH_CE
+              Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              22
+              1
+              read-write
+            
+            
+              FLASH_BE
+              Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FLASH_SE
+              Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              24
+              1
+              read-write
+            
+            
+              FLASH_PP
+              Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
+              25
+              1
+              read-write
+            
+            
+              FLASH_WRSR
+              Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              26
+              1
+              read-write
+            
+            
+              FLASH_RDSR
+              Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              27
+              1
+              read-write
+            
+            
+              FLASH_RDID
+              Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              28
+              1
+              read-write
+            
+            
+              FLASH_WRDI
+              Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              29
+              1
+              read-write
+            
+            
+              FLASH_WREN
+              Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              30
+              1
+              read-write
+            
+            
+              FLASH_READ
+              Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          ADDR
+          SPI1 address register
+          0x4
+          0x20
+          
+            
+              USR_ADDR_VALUE
+              In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CTRL
+          SPI1 control register.
+          0x8
+          0x20
+          0x002CA000
+          
+            
+              FDUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller.
+              3
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable
+              7
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable
+              8
+              1
+              read-write
+            
+            
+              FCS_CRC_EN
+              For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.
+              10
+              1
+              read-write
+            
+            
+              TX_CRC_EN
+              For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+              11
+              1
+              read-write
+            
+            
+              FASTRD_MODE
+              This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+              13
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+              14
+              1
+              read-write
+            
+            
+              RESANDRES
+              The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
+              15
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low
+              19
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              WP
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.
+              21
+              1
+              read-write
+            
+            
+              WRSR_2B
+              two bytes data will be written to status register when it is set. 1: enable 0: disable.
+              22
+              1
+              read-write
+            
+            
+              FREAD_DIO
+              In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FREAD_QIO
+              In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          CTRL1
+          SPI1 control1 register.
+          0xC
+          0x20
+          0x00000FFC
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+              0
+              2
+              read-write
+            
+            
+              CS_HOLD_DLY_RES
+              After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
+              2
+              10
+              read-write
+            
+          
+        
+        
+          CTRL2
+          SPI1 control2 register.
+          0x10
+          0x20
+          
+            
+              SYNC_RESET
+              The FSM will be reset.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          CLOCK
+          SPI1 clock division control register.
+          0x14
+          0x20
+          0x00030103
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_mem_clkcnt_N.
+              0
+              8
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+              8
+              8
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+              16
+              8
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              reserved
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI1 user register.
+          0x18
+          0x20
+          0x80000000
+          
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+              9
+              1
+              read-write
+            
+            
+              FWRITE_DUAL
+              In the write operations read-data phase apply 2 signals
+              12
+              1
+              read-write
+            
+            
+              FWRITE_QUAD
+              In the write operations read-data phase apply 4 signals
+              13
+              1
+              read-write
+            
+            
+              FWRITE_DIO
+              In the write operations address phase and read-data phase apply 2 signals.
+              14
+              1
+              read-write
+            
+            
+              FWRITE_QIO
+              In the write operations address phase and read-data phase apply 4 signals.
+              15
+              1
+              read-write
+            
+            
+              USR_MISO_HIGHPART
+              read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+            
+              USR_MOSI_HIGHPART
+              write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+              25
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              SPI clock is disable in dummy phase when the bit is enable.
+              26
+              1
+              read-write
+            
+            
+              USR_MOSI
+              This bit enable the write-data phase of an operation.
+              27
+              1
+              read-write
+            
+            
+              USR_MISO
+              This bit enable the read-data phase of an operation.
+              28
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation.
+              29
+              1
+              read-write
+            
+            
+              USR_ADDR
+              This bit enable the address phase of an operation.
+              30
+              1
+              read-write
+            
+            
+              USR_COMMAND
+              This bit enable the command phase of an operation.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI1 user1 register.
+          0x1C
+          0x20
+          0x5C000007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+              0
+              6
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1).
+              26
+              6
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI1 user2 register.
+          0x20
+          0x20
+          0x70000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command.
+              0
+              16
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1)
+              28
+              4
+              read-write
+            
+          
+        
+        
+          MOSI_DLEN
+          SPI1 send data bit length control register.
+          0x24
+          0x20
+          
+            
+              USR_MOSI_DBITLEN
+              The length in bits of write-data. The register value shall be (bit_num-1).
+              0
+              10
+              read-write
+            
+          
+        
+        
+          MISO_DLEN
+          SPI1 receive data bit length control register.
+          0x28
+          0x20
+          
+            
+              USR_MISO_DBITLEN
+              The length in bits of  read-data. The register value shall be (bit_num-1).
+              0
+              10
+              read-write
+            
+          
+        
+        
+          RD_STATUS
+          SPI1 status register.
+          0x2C
+          0x20
+          
+            
+              STATUS
+              The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+              0
+              16
+              read-write
+            
+            
+              WB_MODE
+              Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+              16
+              8
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI1 misc register
+          0x34
+          0x20
+          0x00000002
+          
+            
+              CS0_DIS
+              SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
+              0
+              1
+              read-write
+            
+            
+              CS1_DIS
+              SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
+              1
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle
+              9
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          TX_CRC
+          SPI1 TX CRC data register.
+          0x38
+          0x20
+          0xFFFFFFFF
+          
+            
+              DATA
+              For SPI1, the value of crc32.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_FCTRL
+          SPI1 bit mode control register.
+          0x3C
+          0x20
+          
+            
+              CACHE_USR_ADDR_4BYTE
+              For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+              1
+              1
+              read-write
+            
+            
+              FDIN_DUAL
+              For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              3
+              1
+              read-write
+            
+            
+              FDOUT_DUAL
+              For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              4
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.
+              5
+              1
+              read-write
+            
+            
+              FDIN_QUAD
+              For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              6
+              1
+              read-write
+            
+            
+              FDOUT_QUAD
+              For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              7
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          W0
+          SPI1 memory data buffer0
+          0x58
+          0x20
+          
+            
+              BUF0
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W1
+          SPI1 memory data buffer1
+          0x5C
+          0x20
+          
+            
+              BUF1
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W2
+          SPI1 memory data buffer2
+          0x60
+          0x20
+          
+            
+              BUF2
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W3
+          SPI1 memory data buffer3
+          0x64
+          0x20
+          
+            
+              BUF3
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W4
+          SPI1 memory data buffer4
+          0x68
+          0x20
+          
+            
+              BUF4
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W5
+          SPI1 memory data buffer5
+          0x6C
+          0x20
+          
+            
+              BUF5
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W6
+          SPI1 memory data buffer6
+          0x70
+          0x20
+          
+            
+              BUF6
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W7
+          SPI1 memory data buffer7
+          0x74
+          0x20
+          
+            
+              BUF7
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W8
+          SPI1 memory data buffer8
+          0x78
+          0x20
+          
+            
+              BUF8
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W9
+          SPI1 memory data buffer9
+          0x7C
+          0x20
+          
+            
+              BUF9
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W10
+          SPI1 memory data buffer10
+          0x80
+          0x20
+          
+            
+              BUF10
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W11
+          SPI1 memory data buffer11
+          0x84
+          0x20
+          
+            
+              BUF11
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W12
+          SPI1 memory data buffer12
+          0x88
+          0x20
+          
+            
+              BUF12
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W13
+          SPI1 memory data buffer13
+          0x8C
+          0x20
+          
+            
+              BUF13
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W14
+          SPI1 memory data buffer14
+          0x90
+          0x20
+          
+            
+              BUF14
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W15
+          SPI1 memory data buffer15
+          0x94
+          0x20
+          
+            
+              BUF15
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_WAITI_CTRL
+          SPI1 wait idle control register
+          0x98
+          0x20
+          0x00000014
+          
+            
+              WAITI_DUMMY
+              The dummy phase enable when wait flash idle (RDSR)
+              1
+              1
+              read-write
+            
+            
+              WAITI_CMD
+              The command to wait flash idle(RDSR).
+              2
+              8
+              read-write
+            
+            
+              WAITI_DUMMY_CYCLELEN
+              The dummy cycle length when wait flash idle(RDSR).
+              10
+              6
+              read-write
+            
+          
+        
+        
+          FLASH_SUS_CTRL
+          SPI1 flash suspend control register
+          0x9C
+          0x20
+          0x08002000
+          
+            
+              FLASH_PER
+              program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              0
+              1
+              read-write
+            
+            
+              FLASH_PES
+              program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              1
+              1
+              read-write
+            
+            
+              FLASH_PER_WAIT_EN
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
+              2
+              1
+              read-write
+            
+            
+              FLASH_PES_WAIT_EN
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
+              3
+              1
+              read-write
+            
+            
+              PES_PER_EN
+              Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
+              4
+              1
+              read-write
+            
+            
+              FLASH_PES_EN
+              Set this bit to enable Auto-suspending function.
+              5
+              1
+              read-write
+            
+            
+              PESR_END_MSK
+              The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+              6
+              16
+              read-write
+            
+            
+              RD_SUS_2B
+              1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit
+              22
+              1
+              read-write
+            
+            
+              PER_END_EN
+              1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
+              23
+              1
+              read-write
+            
+            
+              PES_END_EN
+              1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
+              24
+              1
+              read-write
+            
+            
+              SUS_TIMEOUT_CNT
+              When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
+              25
+              7
+              read-write
+            
+          
+        
+        
+          FLASH_SUS_CMD
+          SPI1 flash suspend command register
+          0xA0
+          0x20
+          0x0005757A
+          
+            
+              FLASH_PER_COMMAND
+              Program/Erase resume command.
+              0
+              8
+              read-write
+            
+            
+              FLASH_PES_COMMAND
+              Program/Erase suspend command.
+              8
+              8
+              read-write
+            
+            
+              WAIT_PESR_COMMAND
+              Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          SUS_STATUS
+          SPI1 flash suspend status register
+          0xA4
+          0x20
+          
+            
+              FLASH_SUS
+              The status of flash suspend, only used in SPI1.
+              0
+              1
+              read-write
+            
+            
+              WAIT_PESR_CMD_2B
+              1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+              1
+              1
+              read-write
+            
+            
+              FLASH_HPM_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
+              2
+              1
+              read-write
+            
+            
+              FLASH_RES_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
+              3
+              1
+              read-write
+            
+            
+              FLASH_DP_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
+              4
+              1
+              read-write
+            
+            
+              FLASH_PER_DLY_128
+              Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
+              5
+              1
+              read-write
+            
+            
+              FLASH_PES_DLY_128
+              Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
+              6
+              1
+              read-write
+            
+            
+              SPI0_LOCK_EN
+              1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+              7
+              1
+              read-write
+            
+          
+        
+        
+          TIMING_CALI
+          SPI1 timing control register
+          0xA8
+          0x20
+          
+            
+              TIMING_CALI
+              The bit is used to enable timing auto-calibration for all reading operations.
+              1
+              1
+              read-write
+            
+            
+              EXTRA_DUMMY_CYCLELEN
+              add extra dummy spi clock cycle length for spi clock calibration.
+              2
+              3
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          SPI1 interrupt enable register
+          0xC0
+          0x20
+          
+            
+              PER_END_INT_ENA
+              The enable bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              PES_END_INT_ENA
+              The enable bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              WPE_END_INT_ENA
+              The enable bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              SLV_ST_END_INT_ENA
+              The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              MST_ST_END_INT_ENA
+              The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          SPI1 interrupt clear register
+          0xC4
+          0x20
+          
+            
+              PER_END_INT_CLR
+              The clear bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              PES_END_INT_CLR
+              The clear bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              WPE_END_INT_CLR
+              The clear bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              SLV_ST_END_INT_CLR
+              The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              MST_ST_END_INT_CLR
+              The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW
+          SPI1 interrupt raw register
+          0xC8
+          0x20
+          
+            
+              PER_END_INT_RAW
+              The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
+              0
+              1
+              read-only
+            
+            
+              PES_END_INT_RAW
+              The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
+              1
+              1
+              read-only
+            
+            
+              WPE_END_INT_RAW
+              The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+              2
+              1
+              read-only
+            
+            
+              SLV_ST_END_INT_RAW
+              The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
+              3
+              1
+              read-only
+            
+            
+              MST_ST_END_INT_RAW
+              The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
+              4
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          SPI1 interrupt status register
+          0xCC
+          0x20
+          
+            
+              PER_END_INT_ST
+              The status bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              PES_END_INT_ST
+              The status bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              WPE_END_INT_ST
+              The status bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              SLV_ST_END_INT_ST
+              The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              MST_ST_END_INT_ST
+              The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          SPI1 clk_gate register
+          0xDC
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              Register clock gate enable signal. 1: Enable. 0: Disable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x3FC
+          0x20
+          0x02007170
+          
+            
+              DATE
+              Version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI2
+      SPI (Serial Peripheral Interface) Controller
+      SPI2
+      0x60024000
+      
+        0x0
+        0x94
+        registers
+      
+      
+        SPI2
+        19
+      
+      
+        
+          CMD
+          Command control register
+          0x0
+          0x20
+          
+            
+              CONF_BITLEN
+              Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+              0
+              18
+              read-write
+            
+            
+              UPDATE
+              Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
+              23
+              1
+              read-write
+            
+            
+              USR
+              User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          ADDR
+          Address value register
+          0x4
+          0x20
+          
+            
+              USR_ADDR_VALUE
+              Address to slave. Can be configured in CONF state.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CTRL
+          SPI control register
+          0x8
+          0x20
+          0x003C0000
+          
+            
+              DUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+              5
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+              8
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+              9
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
+              14
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.
+              15
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
+              19
+              1
+              read-write
+            
+            
+              HOLD_POL
+              SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+              20
+              1
+              read-write
+            
+            
+              WP_POL
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.
+              21
+              1
+              read-write
+            
+            
+              RD_BIT_ORDER
+              In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
+              25
+              1
+              read-write
+            
+            
+              WR_BIT_ORDER
+              In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
+              26
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK
+          SPI clock control register
+          0xC
+          0x20
+          0x80003043
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
+              0
+              6
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
+              6
+              6
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+              12
+              6
+              read-write
+            
+            
+              CLKDIV_PRE
+              In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+              18
+              4
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI USER control register
+          0x10
+          0x20
+          0x800000C0
+          
+            
+              DOUTDIN
+              Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              QPI_MODE
+              Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              TSCK_I_EDGE
+              In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
+              5
+              1
+              read-write
+            
+            
+              CS_HOLD
+              spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              CS_SETUP
+              spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.
+              7
+              1
+              read-write
+            
+            
+              RSCK_I_EDGE
+              In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
+              8
+              1
+              read-write
+            
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
+              9
+              1
+              read-write
+            
+            
+              FWRITE_DUAL
+              In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
+              12
+              1
+              read-write
+            
+            
+              FWRITE_QUAD
+              In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
+              13
+              1
+              read-write
+            
+            
+              USR_CONF_NXT
+              1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
+              15
+              1
+              read-write
+            
+            
+              SIO
+              Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+              17
+              1
+              read-write
+            
+            
+              USR_MISO_HIGHPART
+              read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+              24
+              1
+              read-write
+            
+            
+              USR_MOSI_HIGHPART
+              write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.
+              25
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
+              26
+              1
+              read-write
+            
+            
+              USR_MOSI
+              This bit enable the write-data phase of an operation. Can be configured in CONF state.
+              27
+              1
+              read-write
+            
+            
+              USR_MISO
+              This bit enable the read-data phase of an operation. Can be configured in CONF state.
+              28
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation. Can be configured in CONF state.
+              29
+              1
+              read-write
+            
+            
+              USR_ADDR
+              This bit enable the address phase of an operation. Can be configured in CONF state.
+              30
+              1
+              read-write
+            
+            
+              USR_COMMAND
+              This bit enable the command phase of an operation. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI USER control register 1
+          0x14
+          0x20
+          0xB8410007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
+              0
+              8
+              read-write
+            
+            
+              MST_WFULL_ERR_END_EN
+              1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
+              16
+              1
+              read-write
+            
+            
+              CS_SETUP_TIME
+              (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
+              17
+              5
+              read-write
+            
+            
+              CS_HOLD_TIME
+              delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
+              22
+              5
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+              27
+              5
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI USER control register 2
+          0x18
+          0x20
+          0x78000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command. Can be configured in CONF state.
+              0
+              16
+              read-write
+            
+            
+              MST_REMPTY_ERR_END_EN
+              1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
+              27
+              1
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+              28
+              4
+              read-write
+            
+          
+        
+        
+          MS_DLEN
+          SPI data bit length control register
+          0x1C
+          0x20
+          
+            
+              MS_DATA_BITLEN
+              The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
+              0
+              18
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI misc register
+          0x20
+          0x20
+          0x0000003E
+          
+            
+              CS0_DIS
+              SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              CS1_DIS
+              SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
+              1
+              1
+              read-write
+            
+            
+              CS2_DIS
+              SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
+              2
+              1
+              read-write
+            
+            
+              CS3_DIS
+              SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              CS4_DIS
+              SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
+              4
+              1
+              read-write
+            
+            
+              CS5_DIS
+              SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
+              5
+              1
+              read-write
+            
+            
+              CK_DIS
+              1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              MASTER_CS_POL
+              In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+              7
+              6
+              read-write
+            
+            
+              SLAVE_CS_POL
+              spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.
+              23
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.
+              29
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set. Can be configured in CONF state.
+              30
+              1
+              read-write
+            
+            
+              QUAD_DIN_PIN_SWAP
+              1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DIN_MODE
+          SPI input delay mode configuration
+          0x24
+          0x20
+          
+            
+              DIN0_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              DIN1_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              2
+              2
+              read-write
+            
+            
+              DIN2_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              4
+              2
+              read-write
+            
+            
+              DIN3_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              6
+              2
+              read-write
+            
+            
+              TIMING_HCLK_ACTIVE
+              1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.
+              16
+              1
+              read-write
+            
+          
+        
+        
+          DIN_NUM
+          SPI input delay number configuration
+          0x28
+          0x20
+          
+            
+              DIN0_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              DIN1_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              2
+              2
+              read-write
+            
+            
+              DIN2_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              4
+              2
+              read-write
+            
+            
+              DIN3_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DOUT_MODE
+          SPI output delay mode configuration
+          0x2C
+          0x20
+          
+            
+              DOUT0_MODE
+              The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              DOUT1_MODE
+              The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              1
+              1
+              read-write
+            
+            
+              DOUT2_MODE
+              The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              2
+              1
+              read-write
+            
+            
+              DOUT3_MODE
+              The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+          
+        
+        
+          DMA_CONF
+          SPI DMA control register
+          0x30
+          0x20
+          
+            
+              DMA_SLV_SEG_TRANS_EN
+              Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+              18
+              1
+              read-write
+            
+            
+              SLV_RX_SEG_TRANS_CLR_EN
+              1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
+              19
+              1
+              read-write
+            
+            
+              SLV_TX_SEG_TRANS_CLR_EN
+              1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+              20
+              1
+              read-write
+            
+            
+              RX_EOF_EN
+              1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
+              21
+              1
+              read-write
+            
+            
+              DMA_RX_ENA
+              Set this bit to enable SPI DMA controlled receive data mode.
+              27
+              1
+              read-write
+            
+            
+              DMA_TX_ENA
+              Set this bit to enable SPI DMA controlled send data mode.
+              28
+              1
+              read-write
+            
+            
+              RX_AFIFO_RST
+              Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
+              29
+              1
+              write-only
+            
+            
+              BUF_AFIFO_RST
+              Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
+              30
+              1
+              write-only
+            
+            
+              DMA_AFIFO_RST
+              Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          DMA_INT_ENA
+          SPI DMA interrupt enable register
+          0x34
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_ENA
+              The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_ENA
+              The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              SLV_EX_QPI_INT_ENA
+              The enable bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              read-write
+            
+            
+              SLV_EN_QPI_INT_ENA
+              The enable bit for SPI slave En_QPI interrupt.
+              3
+              1
+              read-write
+            
+            
+              SLV_CMD7_INT_ENA
+              The enable bit for SPI slave CMD7 interrupt.
+              4
+              1
+              read-write
+            
+            
+              SLV_CMD8_INT_ENA
+              The enable bit for SPI slave CMD8 interrupt.
+              5
+              1
+              read-write
+            
+            
+              SLV_CMD9_INT_ENA
+              The enable bit for SPI slave CMD9 interrupt.
+              6
+              1
+              read-write
+            
+            
+              SLV_CMDA_INT_ENA
+              The enable bit for SPI slave CMDA interrupt.
+              7
+              1
+              read-write
+            
+            
+              SLV_RD_DMA_DONE_INT_ENA
+              The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              SLV_WR_DMA_DONE_INT_ENA
+              The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              SLV_RD_BUF_DONE_INT_ENA
+              The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              SLV_WR_BUF_DONE_INT_ENA
+              The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              TRANS_DONE_INT_ENA
+              The enable bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              read-write
+            
+            
+              DMA_SEG_TRANS_DONE_INT_ENA
+              The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              read-write
+            
+            
+              SEG_MAGIC_ERR_INT_ENA
+              The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              read-write
+            
+            
+              SLV_BUF_ADDR_ERR_INT_ENA
+              The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              read-write
+            
+            
+              SLV_CMD_ERR_INT_ENA
+              The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              read-write
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_ENA
+              The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              read-write
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_ENA
+              The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              read-write
+            
+            
+              APP2_INT_ENA
+              The enable bit for SPI_APP2_INT interrupt.
+              19
+              1
+              read-write
+            
+            
+              APP1_INT_ENA
+              The enable bit for SPI_APP1_INT interrupt.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          DMA_INT_CLR
+          SPI DMA interrupt clear register
+          0x38
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_CLR
+              The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_CLR
+              The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              SLV_EX_QPI_INT_CLR
+              The clear bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              write-only
+            
+            
+              SLV_EN_QPI_INT_CLR
+              The clear bit for SPI slave En_QPI interrupt.
+              3
+              1
+              write-only
+            
+            
+              SLV_CMD7_INT_CLR
+              The clear bit for SPI slave CMD7 interrupt.
+              4
+              1
+              write-only
+            
+            
+              SLV_CMD8_INT_CLR
+              The clear bit for SPI slave CMD8 interrupt.
+              5
+              1
+              write-only
+            
+            
+              SLV_CMD9_INT_CLR
+              The clear bit for SPI slave CMD9 interrupt.
+              6
+              1
+              write-only
+            
+            
+              SLV_CMDA_INT_CLR
+              The clear bit for SPI slave CMDA interrupt.
+              7
+              1
+              write-only
+            
+            
+              SLV_RD_DMA_DONE_INT_CLR
+              The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              SLV_WR_DMA_DONE_INT_CLR
+              The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              SLV_RD_BUF_DONE_INT_CLR
+              The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              SLV_WR_BUF_DONE_INT_CLR
+              The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              TRANS_DONE_INT_CLR
+              The clear bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              write-only
+            
+            
+              DMA_SEG_TRANS_DONE_INT_CLR
+              The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              write-only
+            
+            
+              SEG_MAGIC_ERR_INT_CLR
+              The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              write-only
+            
+            
+              SLV_BUF_ADDR_ERR_INT_CLR
+              The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              write-only
+            
+            
+              SLV_CMD_ERR_INT_CLR
+              The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              write-only
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_CLR
+              The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              write-only
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_CLR
+              The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              write-only
+            
+            
+              APP2_INT_CLR
+              The clear bit for SPI_APP2_INT interrupt.
+              19
+              1
+              write-only
+            
+            
+              APP1_INT_CLR
+              The clear bit for SPI_APP1_INT interrupt.
+              20
+              1
+              write-only
+            
+          
+        
+        
+          DMA_INT_RAW
+          SPI DMA interrupt raw register
+          0x3C
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_RAW
+              1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.
+              0
+              1
+              read-write
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_RAW
+              1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.
+              1
+              1
+              read-write
+            
+            
+              SLV_EX_QPI_INT_RAW
+              The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
+              2
+              1
+              read-write
+            
+            
+              SLV_EN_QPI_INT_RAW
+              The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
+              3
+              1
+              read-write
+            
+            
+              SLV_CMD7_INT_RAW
+              The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
+              4
+              1
+              read-write
+            
+            
+              SLV_CMD8_INT_RAW
+              The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
+              5
+              1
+              read-write
+            
+            
+              SLV_CMD9_INT_RAW
+              The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
+              6
+              1
+              read-write
+            
+            
+              SLV_CMDA_INT_RAW
+              The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
+              7
+              1
+              read-write
+            
+            
+              SLV_RD_DMA_DONE_INT_RAW
+              The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
+              8
+              1
+              read-write
+            
+            
+              SLV_WR_DMA_DONE_INT_RAW
+              The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
+              9
+              1
+              read-write
+            
+            
+              SLV_RD_BUF_DONE_INT_RAW
+              The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
+              10
+              1
+              read-write
+            
+            
+              SLV_WR_BUF_DONE_INT_RAW
+              The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
+              11
+              1
+              read-write
+            
+            
+              TRANS_DONE_INT_RAW
+              The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
+              12
+              1
+              read-write
+            
+            
+              DMA_SEG_TRANS_DONE_INT_RAW
+              The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.
+              13
+              1
+              read-write
+            
+            
+              SEG_MAGIC_ERR_INT_RAW
+              The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
+              14
+              1
+              read-write
+            
+            
+              SLV_BUF_ADDR_ERR_INT_RAW
+              The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
+              15
+              1
+              read-write
+            
+            
+              SLV_CMD_ERR_INT_RAW
+              The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
+              16
+              1
+              read-write
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_RAW
+              The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
+              17
+              1
+              read-write
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_RAW
+              The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+              18
+              1
+              read-write
+            
+            
+              APP2_INT_RAW
+              The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+              19
+              1
+              read-write
+            
+            
+              APP1_INT_RAW
+              The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          DMA_INT_ST
+          SPI DMA interrupt status register
+          0x40
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_ST
+              The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_ST
+              The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              SLV_EX_QPI_INT_ST
+              The status bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              read-only
+            
+            
+              SLV_EN_QPI_INT_ST
+              The status bit for SPI slave En_QPI interrupt.
+              3
+              1
+              read-only
+            
+            
+              SLV_CMD7_INT_ST
+              The status bit for SPI slave CMD7 interrupt.
+              4
+              1
+              read-only
+            
+            
+              SLV_CMD8_INT_ST
+              The status bit for SPI slave CMD8 interrupt.
+              5
+              1
+              read-only
+            
+            
+              SLV_CMD9_INT_ST
+              The status bit for SPI slave CMD9 interrupt.
+              6
+              1
+              read-only
+            
+            
+              SLV_CMDA_INT_ST
+              The status bit for SPI slave CMDA interrupt.
+              7
+              1
+              read-only
+            
+            
+              SLV_RD_DMA_DONE_INT_ST
+              The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              SLV_WR_DMA_DONE_INT_ST
+              The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              SLV_RD_BUF_DONE_INT_ST
+              The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              SLV_WR_BUF_DONE_INT_ST
+              The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              TRANS_DONE_INT_ST
+              The status bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              read-only
+            
+            
+              DMA_SEG_TRANS_DONE_INT_ST
+              The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              read-only
+            
+            
+              SEG_MAGIC_ERR_INT_ST
+              The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              read-only
+            
+            
+              SLV_BUF_ADDR_ERR_INT_ST
+              The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              read-only
+            
+            
+              SLV_CMD_ERR_INT_ST
+              The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              read-only
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_ST
+              The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              read-only
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_ST
+              The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              read-only
+            
+            
+              APP2_INT_ST
+              The status bit for SPI_APP2_INT interrupt.
+              19
+              1
+              read-only
+            
+            
+              APP1_INT_ST
+              The status bit for SPI_APP1_INT interrupt.
+              20
+              1
+              read-only
+            
+          
+        
+        
+          W0
+          SPI CPU-controlled buffer0
+          0x98
+          0x20
+          
+            
+              BUF0
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W1
+          SPI CPU-controlled buffer1
+          0x9C
+          0x20
+          
+            
+              BUF1
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W2
+          SPI CPU-controlled buffer2
+          0xA0
+          0x20
+          
+            
+              BUF2
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W3
+          SPI CPU-controlled buffer3
+          0xA4
+          0x20
+          
+            
+              BUF3
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W4
+          SPI CPU-controlled buffer4
+          0xA8
+          0x20
+          
+            
+              BUF4
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W5
+          SPI CPU-controlled buffer5
+          0xAC
+          0x20
+          
+            
+              BUF5
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W6
+          SPI CPU-controlled buffer6
+          0xB0
+          0x20
+          
+            
+              BUF6
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W7
+          SPI CPU-controlled buffer7
+          0xB4
+          0x20
+          
+            
+              BUF7
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W8
+          SPI CPU-controlled buffer8
+          0xB8
+          0x20
+          
+            
+              BUF8
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W9
+          SPI CPU-controlled buffer9
+          0xBC
+          0x20
+          
+            
+              BUF9
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W10
+          SPI CPU-controlled buffer10
+          0xC0
+          0x20
+          
+            
+              BUF10
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W11
+          SPI CPU-controlled buffer11
+          0xC4
+          0x20
+          
+            
+              BUF11
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W12
+          SPI CPU-controlled buffer12
+          0xC8
+          0x20
+          
+            
+              BUF12
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W13
+          SPI CPU-controlled buffer13
+          0xCC
+          0x20
+          
+            
+              BUF13
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W14
+          SPI CPU-controlled buffer14
+          0xD0
+          0x20
+          
+            
+              BUF14
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W15
+          SPI CPU-controlled buffer15
+          0xD4
+          0x20
+          
+            
+              BUF15
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SLAVE
+          SPI slave control register
+          0xE0
+          0x20
+          0x02800000
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              CLK_MODE_13
+              {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+              2
+              1
+              read-write
+            
+            
+              RSCK_DATA_OUT
+              It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge
+              3
+              1
+              read-write
+            
+            
+              SLV_RDDMA_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
+              8
+              1
+              read-write
+            
+            
+              SLV_WRDMA_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
+              9
+              1
+              read-write
+            
+            
+              SLV_RDBUF_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
+              10
+              1
+              read-write
+            
+            
+              SLV_WRBUF_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
+              11
+              1
+              read-write
+            
+            
+              DMA_SEG_MAGIC_VALUE
+              The magic value of BM table in master DMA seg-trans.
+              22
+              4
+              read-write
+            
+            
+              MODE
+              Set SPI work mode. 1: slave mode 0: master mode.
+              26
+              1
+              read-write
+            
+            
+              SOFT_RESET
+              Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
+              27
+              1
+              write-only
+            
+            
+              USR_CONF
+              1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
+              28
+              1
+              read-write
+            
+          
+        
+        
+          SLAVE1
+          SPI slave control register 1
+          0xE4
+          0x20
+          
+            
+              SLV_DATA_BITLEN
+              The transferred data bit length in SPI slave FD and HD mode.
+              0
+              18
+              read-write
+            
+            
+              SLV_LAST_COMMAND
+              In the slave mode it is the value of command.
+              18
+              8
+              read-write
+            
+            
+              SLV_LAST_ADDR
+              In the slave mode it is the value of address.
+              26
+              6
+              read-write
+            
+          
+        
+        
+          CLK_GATE
+          SPI module clock and register clock control
+          0xE8
+          0x20
+          
+            
+              CLK_EN
+              Set this bit to enable clk gate
+              0
+              1
+              read-write
+            
+            
+              MST_CLK_ACTIVE
+              Set this bit to power on the SPI module clock.
+              1
+              1
+              read-write
+            
+            
+              MST_CLK_SEL
+              This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control
+          0xF0
+          0x20
+          0x02007220
+          
+            
+              DATE
+              SPI register version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSTEM
+      System
+      SYSTEM
+      0x600C0000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          CPU_PERI_CLK_EN
+          cpu_peripheral clock gating register
+          0x0
+          0x20
+          
+            
+              CLK_EN_ASSIST_DEBUG
+              reg_clk_en_assist_debug
+              6
+              1
+              read-write
+            
+            
+              CLK_EN_DEDICATED_GPIO
+              reg_clk_en_dedicated_gpio
+              7
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PERI_RST_EN
+          cpu_peripheral reset register
+          0x4
+          0x20
+          0x000000C0
+          
+            
+              RST_EN_ASSIST_DEBUG
+              reg_rst_en_assist_debug
+              6
+              1
+              read-write
+            
+            
+              RST_EN_DEDICATED_GPIO
+              reg_rst_en_dedicated_gpio
+              7
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PER_CONF
+          cpu clock config register
+          0x8
+          0x20
+          0x0000000C
+          
+            
+              CPUPERIOD_SEL
+              reg_cpuperiod_sel
+              0
+              2
+              read-write
+            
+            
+              PLL_FREQ_SEL
+              reg_pll_freq_sel
+              2
+              1
+              read-write
+            
+            
+              CPU_WAIT_MODE_FORCE_ON
+              reg_cpu_wait_mode_force_on
+              3
+              1
+              read-write
+            
+            
+              CPU_WAITI_DELAY_NUM
+              reg_cpu_waiti_delay_num
+              4
+              4
+              read-write
+            
+          
+        
+        
+          MEM_PD_MASK
+          memory power down mask register
+          0xC
+          0x20
+          0x00000001
+          
+            
+              LSLP_MEM_PD_MASK
+              reg_lslp_mem_pd_mask
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_CLK_EN0
+          peripheral clock gating register
+          0x10
+          0x20
+          0xF9C1E06F
+          
+            
+              TIMERS_CLK_EN
+              reg_timers_clk_en
+              0
+              1
+              read-write
+            
+            
+              SPI01_CLK_EN
+              reg_spi01_clk_en
+              1
+              1
+              read-write
+            
+            
+              UART_CLK_EN
+              reg_uart_clk_en
+              2
+              1
+              read-write
+            
+            
+              WDG_CLK_EN
+              reg_wdg_clk_en
+              3
+              1
+              read-write
+            
+            
+              I2S0_CLK_EN
+              reg_i2s0_clk_en
+              4
+              1
+              read-write
+            
+            
+              UART1_CLK_EN
+              reg_uart1_clk_en
+              5
+              1
+              read-write
+            
+            
+              SPI2_CLK_EN
+              reg_spi2_clk_en
+              6
+              1
+              read-write
+            
+            
+              I2C_EXT0_CLK_EN
+              reg_ext0_clk_en
+              7
+              1
+              read-write
+            
+            
+              UHCI0_CLK_EN
+              reg_uhci0_clk_en
+              8
+              1
+              read-write
+            
+            
+              RMT_CLK_EN
+              reg_rmt_clk_en
+              9
+              1
+              read-write
+            
+            
+              PCNT_CLK_EN
+              reg_pcnt_clk_en
+              10
+              1
+              read-write
+            
+            
+              LEDC_CLK_EN
+              reg_ledc_clk_en
+              11
+              1
+              read-write
+            
+            
+              UHCI1_CLK_EN
+              reg_uhci1_clk_en
+              12
+              1
+              read-write
+            
+            
+              TIMERGROUP_CLK_EN
+              reg_timergroup_clk_en
+              13
+              1
+              read-write
+            
+            
+              EFUSE_CLK_EN
+              reg_efuse_clk_en
+              14
+              1
+              read-write
+            
+            
+              TIMERGROUP1_CLK_EN
+              reg_timergroup1_clk_en
+              15
+              1
+              read-write
+            
+            
+              SPI3_CLK_EN
+              reg_spi3_clk_en
+              16
+              1
+              read-write
+            
+            
+              PWM0_CLK_EN
+              reg_pwm0_clk_en
+              17
+              1
+              read-write
+            
+            
+              EXT1_CLK_EN
+              reg_ext1_clk_en
+              18
+              1
+              read-write
+            
+            
+              CAN_CLK_EN
+              reg_can_clk_en
+              19
+              1
+              read-write
+            
+            
+              PWM1_CLK_EN
+              reg_pwm1_clk_en
+              20
+              1
+              read-write
+            
+            
+              I2S1_CLK_EN
+              reg_i2s1_clk_en
+              21
+              1
+              read-write
+            
+            
+              SPI2_DMA_CLK_EN
+              reg_spi2_dma_clk_en
+              22
+              1
+              read-write
+            
+            
+              USB_DEVICE_CLK_EN
+              reg_usb_device_clk_en
+              23
+              1
+              read-write
+            
+            
+              UART_MEM_CLK_EN
+              reg_uart_mem_clk_en
+              24
+              1
+              read-write
+            
+            
+              PWM2_CLK_EN
+              reg_pwm2_clk_en
+              25
+              1
+              read-write
+            
+            
+              PWM3_CLK_EN
+              reg_pwm3_clk_en
+              26
+              1
+              read-write
+            
+            
+              SPI3_DMA_CLK_EN
+              reg_spi3_dma_clk_en
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_CLK_EN
+              reg_apb_saradc_clk_en
+              28
+              1
+              read-write
+            
+            
+              SYSTIMER_CLK_EN
+              reg_systimer_clk_en
+              29
+              1
+              read-write
+            
+            
+              ADC2_ARB_CLK_EN
+              reg_adc2_arb_clk_en
+              30
+              1
+              read-write
+            
+            
+              SPI4_CLK_EN
+              reg_spi4_clk_en
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_CLK_EN1
+          peripheral clock gating register
+          0x14
+          0x20
+          0x00000200
+          
+            
+              CRYPTO_AES_CLK_EN
+              reg_crypto_aes_clk_en
+              1
+              1
+              read-write
+            
+            
+              CRYPTO_SHA_CLK_EN
+              reg_crypto_sha_clk_en
+              2
+              1
+              read-write
+            
+            
+              CRYPTO_RSA_CLK_EN
+              reg_crypto_rsa_clk_en
+              3
+              1
+              read-write
+            
+            
+              CRYPTO_DS_CLK_EN
+              reg_crypto_ds_clk_en
+              4
+              1
+              read-write
+            
+            
+              CRYPTO_HMAC_CLK_EN
+              reg_crypto_hmac_clk_en
+              5
+              1
+              read-write
+            
+            
+              DMA_CLK_EN
+              reg_dma_clk_en
+              6
+              1
+              read-write
+            
+            
+              SDIO_HOST_CLK_EN
+              reg_sdio_host_clk_en
+              7
+              1
+              read-write
+            
+            
+              LCD_CAM_CLK_EN
+              reg_lcd_cam_clk_en
+              8
+              1
+              read-write
+            
+            
+              UART2_CLK_EN
+              reg_uart2_clk_en
+              9
+              1
+              read-write
+            
+            
+              TSENS_CLK_EN
+              reg_tsens_clk_en
+              10
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_RST_EN0
+          reserved
+          0x18
+          0x20
+          
+            
+              TIMERS_RST
+              reg_timers_rst
+              0
+              1
+              read-write
+            
+            
+              SPI01_RST
+              reg_spi01_rst
+              1
+              1
+              read-write
+            
+            
+              UART_RST
+              reg_uart_rst
+              2
+              1
+              read-write
+            
+            
+              WDG_RST
+              reg_wdg_rst
+              3
+              1
+              read-write
+            
+            
+              I2S0_RST
+              reg_i2s0_rst
+              4
+              1
+              read-write
+            
+            
+              UART1_RST
+              reg_uart1_rst
+              5
+              1
+              read-write
+            
+            
+              SPI2_RST
+              reg_spi2_rst
+              6
+              1
+              read-write
+            
+            
+              I2C_EXT0_RST
+              reg_ext0_rst
+              7
+              1
+              read-write
+            
+            
+              UHCI0_RST
+              reg_uhci0_rst
+              8
+              1
+              read-write
+            
+            
+              RMT_RST
+              reg_rmt_rst
+              9
+              1
+              read-write
+            
+            
+              PCNT_RST
+              reg_pcnt_rst
+              10
+              1
+              read-write
+            
+            
+              LEDC_RST
+              reg_ledc_rst
+              11
+              1
+              read-write
+            
+            
+              UHCI1_RST
+              reg_uhci1_rst
+              12
+              1
+              read-write
+            
+            
+              TIMERGROUP_RST
+              reg_timergroup_rst
+              13
+              1
+              read-write
+            
+            
+              EFUSE_RST
+              reg_efuse_rst
+              14
+              1
+              read-write
+            
+            
+              TIMERGROUP1_RST
+              reg_timergroup1_rst
+              15
+              1
+              read-write
+            
+            
+              SPI3_RST
+              reg_spi3_rst
+              16
+              1
+              read-write
+            
+            
+              PWM0_RST
+              reg_pwm0_rst
+              17
+              1
+              read-write
+            
+            
+              EXT1_RST
+              reg_ext1_rst
+              18
+              1
+              read-write
+            
+            
+              CAN_RST
+              reg_can_rst
+              19
+              1
+              read-write
+            
+            
+              PWM1_RST
+              reg_pwm1_rst
+              20
+              1
+              read-write
+            
+            
+              I2S1_RST
+              reg_i2s1_rst
+              21
+              1
+              read-write
+            
+            
+              SPI2_DMA_RST
+              reg_spi2_dma_rst
+              22
+              1
+              read-write
+            
+            
+              USB_DEVICE_RST
+              reg_usb_device_rst
+              23
+              1
+              read-write
+            
+            
+              UART_MEM_RST
+              reg_uart_mem_rst
+              24
+              1
+              read-write
+            
+            
+              PWM2_RST
+              reg_pwm2_rst
+              25
+              1
+              read-write
+            
+            
+              PWM3_RST
+              reg_pwm3_rst
+              26
+              1
+              read-write
+            
+            
+              SPI3_DMA_RST
+              reg_spi3_dma_rst
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_RST
+              reg_apb_saradc_rst
+              28
+              1
+              read-write
+            
+            
+              SYSTIMER_RST
+              reg_systimer_rst
+              29
+              1
+              read-write
+            
+            
+              ADC2_ARB_RST
+              reg_adc2_arb_rst
+              30
+              1
+              read-write
+            
+            
+              SPI4_RST
+              reg_spi4_rst
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_RST_EN1
+          peripheral reset register
+          0x1C
+          0x20
+          0x000001FE
+          
+            
+              CRYPTO_AES_RST
+              reg_crypto_aes_rst
+              1
+              1
+              read-write
+            
+            
+              CRYPTO_SHA_RST
+              reg_crypto_sha_rst
+              2
+              1
+              read-write
+            
+            
+              CRYPTO_RSA_RST
+              reg_crypto_rsa_rst
+              3
+              1
+              read-write
+            
+            
+              CRYPTO_DS_RST
+              reg_crypto_ds_rst
+              4
+              1
+              read-write
+            
+            
+              CRYPTO_HMAC_RST
+              reg_crypto_hmac_rst
+              5
+              1
+              read-write
+            
+            
+              DMA_RST
+              reg_dma_rst
+              6
+              1
+              read-write
+            
+            
+              SDIO_HOST_RST
+              reg_sdio_host_rst
+              7
+              1
+              read-write
+            
+            
+              LCD_CAM_RST
+              reg_lcd_cam_rst
+              8
+              1
+              read-write
+            
+            
+              UART2_RST
+              reg_uart2_rst
+              9
+              1
+              read-write
+            
+            
+              TSENS_RST
+              reg_tsens_rst
+              10
+              1
+              read-write
+            
+          
+        
+        
+          BT_LPCK_DIV_INT
+          clock config register
+          0x20
+          0x20
+          0x000000FF
+          
+            
+              BT_LPCK_DIV_NUM
+              reg_bt_lpck_div_num
+              0
+              12
+              read-write
+            
+          
+        
+        
+          BT_LPCK_DIV_FRAC
+          clock config register
+          0x24
+          0x20
+          0x02001001
+          
+            
+              BT_LPCK_DIV_B
+              reg_bt_lpck_div_b
+              0
+              12
+              read-write
+            
+            
+              BT_LPCK_DIV_A
+              reg_bt_lpck_div_a
+              12
+              12
+              read-write
+            
+            
+              LPCLK_SEL_RTC_SLOW
+              reg_lpclk_sel_rtc_slow
+              24
+              1
+              read-write
+            
+            
+              LPCLK_SEL_8M
+              reg_lpclk_sel_8m
+              25
+              1
+              read-write
+            
+            
+              LPCLK_SEL_XTAL
+              reg_lpclk_sel_xtal
+              26
+              1
+              read-write
+            
+            
+              LPCLK_SEL_XTAL32K
+              reg_lpclk_sel_xtal32k
+              27
+              1
+              read-write
+            
+            
+              LPCLK_RTC_EN
+              reg_lpclk_rtc_en
+              28
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_0
+          interrupt generate register
+          0x28
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_0
+              reg_cpu_intr_from_cpu_0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_1
+          interrupt generate register
+          0x2C
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_1
+              reg_cpu_intr_from_cpu_1
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_2
+          interrupt generate register
+          0x30
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_2
+              reg_cpu_intr_from_cpu_2
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_3
+          interrupt generate register
+          0x34
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_3
+              reg_cpu_intr_from_cpu_3
+              0
+              1
+              read-write
+            
+          
+        
+        
+          RSA_PD_CTRL
+          rsa memory power control register
+          0x38
+          0x20
+          0x00000001
+          
+            
+              RSA_MEM_PD
+              reg_rsa_mem_pd
+              0
+              1
+              read-write
+            
+            
+              RSA_MEM_FORCE_PU
+              reg_rsa_mem_force_pu
+              1
+              1
+              read-write
+            
+            
+              RSA_MEM_FORCE_PD
+              reg_rsa_mem_force_pd
+              2
+              1
+              read-write
+            
+          
+        
+        
+          EDMA_CTRL
+          edma clcok and reset register
+          0x3C
+          0x20
+          0x00000001
+          
+            
+              EDMA_CLK_ON
+              reg_edma_clk_on
+              0
+              1
+              read-write
+            
+            
+              EDMA_RESET
+              reg_edma_reset
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_CONTROL
+          cache control register
+          0x40
+          0x20
+          0x00000005
+          
+            
+              ICACHE_CLK_ON
+              reg_icache_clk_on
+              0
+              1
+              read-write
+            
+            
+              ICACHE_RESET
+              reg_icache_reset
+              1
+              1
+              read-write
+            
+            
+              DCACHE_CLK_ON
+              reg_dcache_clk_on
+              2
+              1
+              read-write
+            
+            
+              DCACHE_RESET
+              reg_dcache_reset
+              3
+              1
+              read-write
+            
+          
+        
+        
+          EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
+          SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+          0x44
+          0x20
+          
+            
+              ENABLE_SPI_MANUAL_ENCRYPT
+              reg_enable_spi_manual_encrypt
+              0
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_DB_ENCRYPT
+              reg_enable_download_db_encrypt
+              1
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_G0CB_DECRYPT
+              reg_enable_download_g0cb_decrypt
+              2
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_MANUAL_ENCRYPT
+              reg_enable_download_manual_encrypt
+              3
+              1
+              read-write
+            
+          
+        
+        
+          RTC_FASTMEM_CONFIG
+          fast memory config register
+          0x48
+          0x20
+          0x7FF00000
+          
+            
+              RTC_MEM_CRC_START
+              reg_rtc_mem_crc_start
+              8
+              1
+              read-write
+            
+            
+              RTC_MEM_CRC_ADDR
+              reg_rtc_mem_crc_addr
+              9
+              11
+              read-write
+            
+            
+              RTC_MEM_CRC_LEN
+              reg_rtc_mem_crc_len
+              20
+              11
+              read-write
+            
+            
+              RTC_MEM_CRC_FINISH
+              reg_rtc_mem_crc_finish
+              31
+              1
+              read-only
+            
+          
+        
+        
+          RTC_FASTMEM_CRC
+          reserved
+          0x4C
+          0x20
+          
+            
+              RTC_MEM_CRC_RES
+              reg_rtc_mem_crc_res
+              0
+              32
+              read-only
+            
+          
+        
+        
+          REDUNDANT_ECO_CTRL
+          eco register
+          0x50
+          0x20
+          
+            
+              REDUNDANT_ECO_DRIVE
+              reg_redundant_eco_drive
+              0
+              1
+              read-write
+            
+            
+              REDUNDANT_ECO_RESULT
+              reg_redundant_eco_result
+              1
+              1
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          clock gating register
+          0x54
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              reg_clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SYSCLK_CONF
+          system clock config register
+          0x58
+          0x20
+          0x00000001
+          
+            
+              PRE_DIV_CNT
+              reg_pre_div_cnt
+              0
+              10
+              read-write
+            
+            
+              SOC_CLK_SEL
+              reg_soc_clk_sel
+              10
+              2
+              read-write
+            
+            
+              CLK_XTAL_FREQ
+              reg_clk_xtal_freq
+              12
+              7
+              read-only
+            
+            
+              CLK_DIV_EN
+              reg_clk_div_en
+              19
+              1
+              read-only
+            
+          
+        
+        
+          MEM_PVT
+          mem pvt register
+          0x5C
+          0x20
+          0x00000003
+          
+            
+              MEM_PATH_LEN
+              reg_mem_path_len
+              0
+              4
+              read-write
+            
+            
+              MEM_ERR_CNT_CLR
+              reg_mem_err_cnt_clr
+              4
+              1
+              write-only
+            
+            
+              MONITOR_EN
+              reg_mem_pvt_monitor_en
+              5
+              1
+              read-write
+            
+            
+              MEM_TIMING_ERR_CNT
+              reg_mem_timing_err_cnt
+              6
+              16
+              read-only
+            
+            
+              MEM_VT_SEL
+              reg_mem_vt_sel
+              22
+              2
+              read-write
+            
+          
+        
+        
+          COMB_PVT_LVT_CONF
+          mem pvt register
+          0x60
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_LVT
+              reg_comb_path_len_lvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_LVT
+              reg_comb_err_cnt_clr_lvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_LVT
+              reg_comb_pvt_monitor_en_lvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_NVT_CONF
+          mem pvt register
+          0x64
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_NVT
+              reg_comb_path_len_nvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_NVT
+              reg_comb_err_cnt_clr_nvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_NVT
+              reg_comb_pvt_monitor_en_nvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_HVT_CONF
+          mem pvt register
+          0x68
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_HVT
+              reg_comb_path_len_hvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_HVT
+              reg_comb_err_cnt_clr_hvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_HVT
+              reg_comb_pvt_monitor_en_hvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE0
+          mem pvt register
+          0x6C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE0
+              reg_comb_timing_err_cnt_lvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE0
+          mem pvt register
+          0x70
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE0
+              reg_comb_timing_err_cnt_nvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE0
+          mem pvt register
+          0x74
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE0
+              reg_comb_timing_err_cnt_hvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE1
+          mem pvt register
+          0x78
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE1
+              reg_comb_timing_err_cnt_lvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE1
+          mem pvt register
+          0x7C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE1
+              reg_comb_timing_err_cnt_nvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE1
+          mem pvt register
+          0x80
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE1
+              reg_comb_timing_err_cnt_hvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE2
+          mem pvt register
+          0x84
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE2
+              reg_comb_timing_err_cnt_lvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE2
+          mem pvt register
+          0x88
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE2
+              reg_comb_timing_err_cnt_nvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE2
+          mem pvt register
+          0x8C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE2
+              reg_comb_timing_err_cnt_hvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE3
+          mem pvt register
+          0x90
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE3
+              reg_comb_timing_err_cnt_lvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE3
+          mem pvt register
+          0x94
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE3
+              reg_comb_timing_err_cnt_nvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE3
+          mem pvt register
+          0x98
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE3
+              reg_comb_timing_err_cnt_hvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          SYSTEM_REG_DATE
+          Version register
+          0xFFC
+          0x20
+          0x02007150
+          
+            
+              SYSTEM_REG_DATE
+              reg_system_reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSTIMER
+      System Timer
+      SYSTIMER
+      0x60023000
+      
+        0x0
+        0x78
+        registers
+      
+      
+        SYSTIMER_TARGET0
+        37
+      
+      
+        SYSTIMER_TARGET1
+        38
+      
+      
+        SYSTIMER_TARGET2
+        39
+      
+      
+        
+          CONF
+          SYSTIMER_CONF.
+          0x0
+          0x20
+          0x46000000
+          
+            
+              SYSTIMER_CLK_FO
+              systimer clock force on
+              0
+              1
+              read-write
+            
+            
+              TARGET2_WORK_EN
+              target2 work enable
+              22
+              1
+              read-write
+            
+            
+              TARGET1_WORK_EN
+              target1 work enable
+              23
+              1
+              read-write
+            
+            
+              TARGET0_WORK_EN
+              target0 work enable
+              24
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_CORE1_STALL_EN
+              If timer unit1 is stalled when core1 stalled
+              25
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_CORE0_STALL_EN
+              If timer unit1 is stalled when core0 stalled
+              26
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_CORE1_STALL_EN
+              If timer unit0 is stalled when core1 stalled
+              27
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_CORE0_STALL_EN
+              If timer unit0 is stalled when core0 stalled
+              28
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_WORK_EN
+              timer unit1 work enable
+              29
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_WORK_EN
+              timer unit0 work enable
+              30
+              1
+              read-write
+            
+            
+              CLK_EN
+              register file clk gating
+              31
+              1
+              read-write
+            
+          
+        
+        
+          UNIT0_OP
+          SYSTIMER_UNIT0_OP.
+          0x4
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_VALID
+              reg_timer_unit0_value_valid
+              29
+              1
+              read-only
+            
+            
+              TIMER_UNIT0_UPDATE
+              update timer_unit0
+              30
+              1
+              write-only
+            
+          
+        
+        
+          UNIT1_OP
+          SYSTIMER_UNIT1_OP.
+          0x8
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_VALID
+              timer value is sync and valid
+              29
+              1
+              read-only
+            
+            
+              TIMER_UNIT1_UPDATE
+              update timer unit1
+              30
+              1
+              write-only
+            
+          
+        
+        
+          UNIT0_LOAD_HI
+          SYSTIMER_UNIT0_LOAD_HI.
+          0xC
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD_HI
+              timer unit0 load high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          UNIT0_LOAD_LO
+          SYSTIMER_UNIT0_LOAD_LO.
+          0x10
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD_LO
+              timer unit0 load low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          UNIT1_LOAD_HI
+          SYSTIMER_UNIT1_LOAD_HI.
+          0x14
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD_HI
+              timer unit1 load high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          UNIT1_LOAD_LO
+          SYSTIMER_UNIT1_LOAD_LO.
+          0x18
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD_LO
+              timer unit1 load low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET0_HI
+          SYSTIMER_TARGET0_HI.
+          0x1C
+          0x20
+          
+            
+              TIMER_TARGET0_HI
+              timer taget0 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET0_LO
+          SYSTIMER_TARGET0_LO.
+          0x20
+          0x20
+          
+            
+              TIMER_TARGET0_LO
+              timer taget0 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET1_HI
+          SYSTIMER_TARGET1_HI.
+          0x24
+          0x20
+          
+            
+              TIMER_TARGET1_HI
+              timer taget1 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET1_LO
+          SYSTIMER_TARGET1_LO.
+          0x28
+          0x20
+          
+            
+              TIMER_TARGET1_LO
+              timer taget1 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET2_HI
+          SYSTIMER_TARGET2_HI.
+          0x2C
+          0x20
+          
+            
+              TIMER_TARGET2_HI
+              timer taget2 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET2_LO
+          SYSTIMER_TARGET2_LO.
+          0x30
+          0x20
+          
+            
+              TIMER_TARGET2_LO
+              timer taget2 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET0_CONF
+          SYSTIMER_TARGET0_CONF.
+          0x34
+          0x20
+          
+            
+              TARGET0_PERIOD
+              target0 period
+              0
+              26
+              read-write
+            
+            
+              TARGET0_PERIOD_MODE
+              Set target0 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET0_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TARGET1_CONF
+          SYSTIMER_TARGET1_CONF.
+          0x38
+          0x20
+          
+            
+              TARGET1_PERIOD
+              target1 period
+              0
+              26
+              read-write
+            
+            
+              TARGET1_PERIOD_MODE
+              Set target1 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET1_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TARGET2_CONF
+          SYSTIMER_TARGET2_CONF.
+          0x3C
+          0x20
+          
+            
+              TARGET2_PERIOD
+              target2 period
+              0
+              26
+              read-write
+            
+            
+              TARGET2_PERIOD_MODE
+              Set target2 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET2_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          UNIT0_VALUE_HI
+          SYSTIMER_UNIT0_VALUE_HI.
+          0x40
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_HI
+              timer read value high 32bit
+              0
+              20
+              read-only
+            
+          
+        
+        
+          UNIT0_VALUE_LO
+          SYSTIMER_UNIT0_VALUE_LO.
+          0x44
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_LO
+              timer read value low 32bit
+              0
+              32
+              read-only
+            
+          
+        
+        
+          UNIT1_VALUE_HI
+          SYSTIMER_UNIT1_VALUE_HI.
+          0x48
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_HI
+              timer read value high 32bit
+              0
+              20
+              read-only
+            
+          
+        
+        
+          UNIT1_VALUE_LO
+          SYSTIMER_UNIT1_VALUE_LO.
+          0x4C
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_LO
+              timer read value low 32bit
+              0
+              32
+              read-only
+            
+          
+        
+        
+          COMP0_LOAD
+          SYSTIMER_COMP0_LOAD.
+          0x50
+          0x20
+          
+            
+              TIMER_COMP0_LOAD
+              timer comp0 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          COMP1_LOAD
+          SYSTIMER_COMP1_LOAD.
+          0x54
+          0x20
+          
+            
+              TIMER_COMP1_LOAD
+              timer comp1 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          COMP2_LOAD
+          SYSTIMER_COMP2_LOAD.
+          0x58
+          0x20
+          
+            
+              TIMER_COMP2_LOAD
+              timer comp2 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          UNIT0_LOAD
+          SYSTIMER_UNIT0_LOAD.
+          0x5C
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD
+              timer unit0 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          UNIT1_LOAD
+          SYSTIMER_UNIT1_LOAD.
+          0x60
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD
+              timer unit1 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          SYSTIMER_INT_ENA.
+          0x64
+          0x20
+          
+            
+              TARGET0_INT_ENA
+              interupt0 enable
+              0
+              1
+              read-write
+            
+            
+              TARGET1_INT_ENA
+              interupt1 enable
+              1
+              1
+              read-write
+            
+            
+              TARGET2_INT_ENA
+              interupt2 enable
+              2
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          SYSTIMER_INT_RAW.
+          0x68
+          0x20
+          
+            
+              TARGET0_INT_RAW
+              interupt0 raw
+              0
+              1
+              read-only
+            
+            
+              TARGET1_INT_RAW
+              interupt1 raw
+              1
+              1
+              read-only
+            
+            
+              TARGET2_INT_RAW
+              interupt2 raw
+              2
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          SYSTIMER_INT_CLR.
+          0x6C
+          0x20
+          
+            
+              TARGET0_INT_CLR
+              interupt0 clear
+              0
+              1
+              write-only
+            
+            
+              TARGET1_INT_CLR
+              interupt1 clear
+              1
+              1
+              write-only
+            
+            
+              TARGET2_INT_CLR
+              interupt2 clear
+              2
+              1
+              write-only
+            
+          
+        
+        
+          INT_ST
+          SYSTIMER_INT_ST.
+          0x70
+          0x20
+          
+            
+              TARGET0_INT_ST
+              reg_target0_int_st
+              0
+              1
+              read-only
+            
+            
+              TARGET1_INT_ST
+              reg_target1_int_st
+              1
+              1
+              read-only
+            
+            
+              TARGET2_INT_ST
+              reg_target2_int_st
+              2
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          SYSTIMER_DATE.
+          0xFC
+          0x20
+          0x02006171
+          
+            
+              DATE
+              reg_date
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      TIMG0
+      Timer Group
+      TIMG
+      0x6001F000
+      
+        0x0
+        0x68
+        registers
+      
+      
+        TG0_T0_LEVEL
+        32
+      
+      
+        TG0_WDT_LEVEL
+        33
+      
+      
+        
+          T0CONFIG
+          TIMG_T0CONFIG_REG.
+          0x0
+          0x20
+          0x60002000
+          
+            
+              T0_USE_XTAL
+              reg_t0_use_xtal.
+              9
+              1
+              read-write
+            
+            
+              T0_ALARM_EN
+              reg_t0_alarm_en.
+              10
+              1
+              read-write
+            
+            
+              T0_DIVCNT_RST
+              reg_t0_divcnt_rst.
+              12
+              1
+              write-only
+            
+            
+              T0_DIVIDER
+              reg_t0_divider.
+              13
+              16
+              read-write
+            
+            
+              T0_AUTORELOAD
+              reg_t0_autoreload.
+              29
+              1
+              read-write
+            
+            
+              T0_INCREASE
+              reg_t0_increase.
+              30
+              1
+              read-write
+            
+            
+              T0_EN
+              reg_t0_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          T0LO
+          TIMG_T0LO_REG.
+          0x4
+          0x20
+          
+            
+              T0_LO
+              t0_lo
+              0
+              32
+              read-only
+            
+          
+        
+        
+          T0HI
+          TIMG_T0HI_REG.
+          0x8
+          0x20
+          
+            
+              T0_HI
+              t0_hi
+              0
+              22
+              read-only
+            
+          
+        
+        
+          T0UPDATE
+          TIMG_T0UPDATE_REG.
+          0xC
+          0x20
+          
+            
+              T0_UPDATE
+              t0_update
+              31
+              1
+              read-write
+            
+          
+        
+        
+          T0ALARMLO
+          TIMG_T0ALARMLO_REG.
+          0x10
+          0x20
+          
+            
+              T0_ALARM_LO
+              reg_t0_alarm_lo.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T0ALARMHI
+          TIMG_T0ALARMHI_REG.
+          0x14
+          0x20
+          
+            
+              T0_ALARM_HI
+              reg_t0_alarm_hi.
+              0
+              22
+              read-write
+            
+          
+        
+        
+          T0LOADLO
+          TIMG_T0LOADLO_REG.
+          0x18
+          0x20
+          
+            
+              T0_LOAD_LO
+              reg_t0_load_lo.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T0LOADHI
+          TIMG_T0LOADHI_REG.
+          0x1C
+          0x20
+          
+            
+              T0_LOAD_HI
+              reg_t0_load_hi.
+              0
+              22
+              read-write
+            
+          
+        
+        
+          T0LOAD
+          TIMG_T0LOAD_REG.
+          0x20
+          0x20
+          
+            
+              T0_LOAD
+              t0_load
+              0
+              32
+              write-only
+            
+          
+        
+        
+          WDTCONFIG0
+          TIMG_WDTCONFIG0_REG.
+          0x48
+          0x20
+          0x0004C000
+          
+            
+              WDT_APPCPU_RESET_EN
+              reg_wdt_appcpu_reset_en.
+              12
+              1
+              read-write
+            
+            
+              WDT_PROCPU_RESET_EN
+              reg_wdt_procpu_reset_en.
+              13
+              1
+              read-write
+            
+            
+              WDT_FLASHBOOT_MOD_EN
+              reg_wdt_flashboot_mod_en.
+              14
+              1
+              read-write
+            
+            
+              WDT_SYS_RESET_LENGTH
+              reg_wdt_sys_reset_length.
+              15
+              3
+              read-write
+            
+            
+              WDT_CPU_RESET_LENGTH
+              reg_wdt_cpu_reset_length.
+              18
+              3
+              read-write
+            
+            
+              WDT_USE_XTAL
+              reg_wdt_use_xtal.
+              21
+              1
+              read-write
+            
+            
+              WDT_CONF_UPDATE_EN
+              reg_wdt_conf_update_en.
+              22
+              1
+              write-only
+            
+            
+              WDT_STG3
+              reg_wdt_stg3.
+              23
+              2
+              read-write
+            
+            
+              WDT_STG2
+              reg_wdt_stg2.
+              25
+              2
+              read-write
+            
+            
+              WDT_STG1
+              reg_wdt_stg1.
+              27
+              2
+              read-write
+            
+            
+              WDT_STG0
+              reg_wdt_stg0.
+              29
+              2
+              read-write
+            
+            
+              WDT_EN
+              reg_wdt_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG1
+          TIMG_WDTCONFIG1_REG.
+          0x4C
+          0x20
+          0x00010000
+          
+            
+              WDT_DIVCNT_RST
+              reg_wdt_divcnt_rst.
+              0
+              1
+              write-only
+            
+            
+              WDT_CLK_PRESCALE
+              reg_wdt_clk_prescale.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          WDTCONFIG2
+          TIMG_WDTCONFIG2_REG.
+          0x50
+          0x20
+          0x018CBA80
+          
+            
+              WDT_STG0_HOLD
+              reg_wdt_stg0_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG3
+          TIMG_WDTCONFIG3_REG.
+          0x54
+          0x20
+          0x07FFFFFF
+          
+            
+              WDT_STG1_HOLD
+              reg_wdt_stg1_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG4
+          TIMG_WDTCONFIG4_REG.
+          0x58
+          0x20
+          0x000FFFFF
+          
+            
+              WDT_STG2_HOLD
+              reg_wdt_stg2_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG5
+          TIMG_WDTCONFIG5_REG.
+          0x5C
+          0x20
+          0x000FFFFF
+          
+            
+              WDT_STG3_HOLD
+              reg_wdt_stg3_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTFEED
+          TIMG_WDTFEED_REG.
+          0x60
+          0x20
+          
+            
+              WDT_FEED
+              wdt_feed
+              0
+              32
+              write-only
+            
+          
+        
+        
+          WDTWPROTECT
+          TIMG_WDTWPROTECT_REG.
+          0x64
+          0x20
+          0x50D83AA1
+          
+            
+              WDT_WKEY
+              reg_wdt_wkey.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          RTCCALICFG
+          TIMG_RTCCALICFG_REG.
+          0x68
+          0x20
+          0x00013000
+          
+            
+              RTC_CALI_START_CYCLING
+              reg_rtc_cali_start_cycling.
+              12
+              1
+              read-write
+            
+            
+              RTC_CALI_CLK_SEL
+              reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+              13
+              2
+              read-write
+            
+            
+              RTC_CALI_RDY
+              rtc_cali_rdy
+              15
+              1
+              read-only
+            
+            
+              RTC_CALI_MAX
+              reg_rtc_cali_max.
+              16
+              15
+              read-write
+            
+            
+              RTC_CALI_START
+              reg_rtc_cali_start.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          RTCCALICFG1
+          TIMG_RTCCALICFG1_REG.
+          0x6C
+          0x20
+          
+            
+              RTC_CALI_CYCLING_DATA_VLD
+              rtc_cali_cycling_data_vld
+              0
+              1
+              read-only
+            
+            
+              RTC_CALI_VALUE
+              rtc_cali_value
+              7
+              25
+              read-only
+            
+          
+        
+        
+          INT_ENA_TIMERS
+          INT_ENA_TIMG_REG
+          0x70
+          0x20
+          
+            
+              T0_INT_ENA
+              t0_int_ena
+              0
+              1
+              read-write
+            
+            
+              WDT_INT_ENA
+              wdt_int_ena
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW_TIMERS
+          INT_RAW_TIMG_REG
+          0x74
+          0x20
+          
+            
+              T0_INT_RAW
+              t0_int_raw
+              0
+              1
+              read-only
+            
+            
+              WDT_INT_RAW
+              wdt_int_raw
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_TIMERS
+          INT_ST_TIMG_REG
+          0x78
+          0x20
+          
+            
+              T0_INT_ST
+              t0_int_st
+              0
+              1
+              read-only
+            
+            
+              WDT_INT_ST
+              wdt_int_st
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR_TIMERS
+          INT_CLR_TIMG_REG
+          0x7C
+          0x20
+          
+            
+              T0_INT_CLR
+              t0_int_clr
+              0
+              1
+              write-only
+            
+            
+              WDT_INT_CLR
+              wdt_int_clr
+              1
+              1
+              write-only
+            
+          
+        
+        
+          RTCCALICFG2
+          TIMG_RTCCALICFG2_REG.
+          0x80
+          0x20
+          0xFFFFFF98
+          
+            
+              RTC_CALI_TIMEOUT
+              timeoutindicator
+              0
+              1
+              read-only
+            
+            
+              RTC_CALI_TIMEOUT_RST_CNT
+              reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+              3
+              4
+              read-write
+            
+            
+              RTC_CALI_TIMEOUT_THRES
+              reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+              7
+              25
+              read-write
+            
+          
+        
+        
+          NTIMG_DATE
+          TIMG_NTIMG_DATE_REG.
+          0xF8
+          0x20
+          0x02006191
+          
+            
+              NTIMGS_DATE
+              reg_ntimers_date.
+              0
+              28
+              read-write
+            
+          
+        
+        
+          REGCLK
+          TIMG_REGCLK_REG.
+          0xFC
+          0x20
+          0x60000000
+          
+            
+              WDT_CLK_IS_ACTIVE
+              reg_wdt_clk_is_active.
+              29
+              1
+              read-write
+            
+            
+              TIMER_CLK_IS_ACTIVE
+              reg_timer_clk_is_active.
+              30
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      TIMG1
+      Timer Group
+      0x60020000
+      
+        TG1_T0_LEVEL
+        34
+      
+      
+        TG1_WDT_LEVEL
+        35
+      
+    
+    
+      TWAI
+      Two-Wire Automotive Interface
+      TWAI
+      0x6002B000
+      
+        0x0
+        0x6C
+        registers
+      
+      
+        TWAI
+        25
+      
+      
+        
+          MODE
+          Mode Register
+          0x0
+          0x20
+          0x00000001
+          
+            
+              RESET_MODE
+              This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
+              0
+              1
+              read-write
+            
+            
+              LISTEN_ONLY_MODE
+              1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
+              1
+              1
+              read-write
+            
+            
+              SELF_TEST_MODE
+              1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
+              2
+              1
+              read-write
+            
+            
+              RX_FILTER_MODE
+              This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CMD
+          Command Register
+          0x4
+          0x20
+          
+            
+              TX_REQ
+              Set the bit to 1 to allow the driving nodes start transmission.
+              0
+              1
+              write-only
+            
+            
+              ABORT_TX
+              Set the bit to 1 to cancel a pending transmission request.
+              1
+              1
+              write-only
+            
+            
+              RELEASE_BUF
+              Set the bit to 1 to release the RX buffer.
+              2
+              1
+              write-only
+            
+            
+              CLR_OVERRUN
+              Set the bit to 1 to clear the data overrun status bit.
+              3
+              1
+              write-only
+            
+            
+              SELF_RX_REQ
+              Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
+              4
+              1
+              write-only
+            
+          
+        
+        
+          STATUS
+          Status register
+          0x8
+          0x20
+          
+            
+              RX_BUF_ST
+              1: The data in the RX buffer is not empty, with at least one received data packet.
+              0
+              1
+              read-only
+            
+            
+              OVERRUN_ST
+              1: The RX FIFO is full and data overrun has occurred.
+              1
+              1
+              read-only
+            
+            
+              TX_BUF_ST
+              1: The TX buffer is empty, the CPU may write a message into it.
+              2
+              1
+              read-only
+            
+            
+              TX_COMPLETE
+              1: The TWAI controller has successfully received a packet from the bus.
+              3
+              1
+              read-only
+            
+            
+              RX_ST
+              1: The TWAI Controller is receiving a message from the bus.
+              4
+              1
+              read-only
+            
+            
+              TX_ST
+              1: The TWAI Controller is transmitting a message to the bus.
+              5
+              1
+              read-only
+            
+            
+              ERR_ST
+              1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
+              6
+              1
+              read-only
+            
+            
+              BUS_OFF_ST
+              1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
+              7
+              1
+              read-only
+            
+            
+              MISS_ST
+              This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
+              8
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          Interrupt Register
+          0xC
+          0x20
+          
+            
+              RX_INT_ST
+              Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
+              0
+              1
+              read-only
+            
+            
+              TX_INT_ST
+              Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
+              1
+              1
+              read-only
+            
+            
+              ERR_WARN_INT_ST
+              Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
+              2
+              1
+              read-only
+            
+            
+              OVERRUN_INT_ST
+              Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
+              3
+              1
+              read-only
+            
+            
+              ERR_PASSIVE_INT_ST
+              Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
+              5
+              1
+              read-only
+            
+            
+              ARB_LOST_INT_ST
+              Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
+              6
+              1
+              read-only
+            
+            
+              BUS_ERR_INT_ST
+              Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
+              7
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          Interrupt Enable Register
+          0x10
+          0x20
+          
+            
+              RX_INT_ENA
+              Set this bit to 1 to enable receive interrupt.
+              0
+              1
+              read-write
+            
+            
+              TX_INT_ENA
+              Set this bit to 1 to enable transmit interrupt.
+              1
+              1
+              read-write
+            
+            
+              ERR_WARN_INT_ENA
+              Set this bit to 1 to enable error warning interrupt.
+              2
+              1
+              read-write
+            
+            
+              OVERRUN_INT_ENA
+              Set this bit to 1 to enable data overrun interrupt.
+              3
+              1
+              read-write
+            
+            
+              ERR_PASSIVE_INT_ENA
+              Set this bit to 1 to enable error passive interrupt.
+              5
+              1
+              read-write
+            
+            
+              ARB_LOST_INT_ENA
+              Set this bit to 1 to enable arbitration lost interrupt.
+              6
+              1
+              read-write
+            
+            
+              BUS_ERR_INT_ENA
+              Set this bit to 1 to enable error interrupt.
+              7
+              1
+              read-write
+            
+          
+        
+        
+          BUS_TIMING_0
+          Bus Timing Register 0
+          0x18
+          0x20
+          
+            
+              BAUD_PRESC
+              Baud Rate Prescaler, determines the frequency dividing ratio.
+              0
+              13
+            
+            
+              SYNC_JUMP_WIDTH
+              Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+              14
+              2
+            
+          
+        
+        
+          BUS_TIMING_1
+          Bus Timing Register 1
+          0x1C
+          0x20
+          
+            
+              TIME_SEG1
+              The width of PBS1.
+              0
+              4
+            
+            
+              TIME_SEG2
+              The width of PBS2.
+              4
+              3
+            
+            
+              TIME_SAMP
+              The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
+              7
+              1
+            
+          
+        
+        
+          ARB_LOST_CAP
+          Arbitration Lost Capture Register
+          0x2C
+          0x20
+          
+            
+              ARB_LOST_CAP
+              This register contains information about the bit position of lost arbitration.
+              0
+              5
+              read-only
+            
+          
+        
+        
+          ERR_CODE_CAP
+          Error Code Capture Register
+          0x30
+          0x20
+          
+            
+              ECC_SEGMENT
+              This register contains information about the location of errors, see Table 181 for details.
+              0
+              5
+              read-only
+            
+            
+              ECC_DIRECTION
+              This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
+              5
+              1
+              read-only
+            
+            
+              ECC_TYPE
+              This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
+              6
+              2
+              read-only
+            
+          
+        
+        
+          ERR_WARNING_LIMIT
+          Error Warning Limit Register
+          0x34
+          0x20
+          0x00000060
+          
+            
+              ERR_WARNING_LIMIT
+              Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
+              0
+              8
+            
+          
+        
+        
+          RX_ERR_CNT
+          Receive Error Counter Register
+          0x38
+          0x20
+          
+            
+              RX_ERR_CNT
+              The RX error counter register, reflects value changes under reception status.
+              0
+              8
+            
+          
+        
+        
+          TX_ERR_CNT
+          Transmit Error Counter Register
+          0x3C
+          0x20
+          
+            
+              TX_ERR_CNT
+              The TX error counter register, reflects value changes under transmission status.
+              0
+              8
+            
+          
+        
+        
+          DATA_0
+          Data register 0
+          0x40
+          0x20
+          
+            
+              TX_BYTE_0
+              In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_1
+          Data register 1
+          0x44
+          0x20
+          
+            
+              TX_BYTE_1
+              In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_2
+          Data register 2
+          0x48
+          0x20
+          
+            
+              TX_BYTE_2
+              In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_3
+          Data register 3
+          0x4C
+          0x20
+          
+            
+              TX_BYTE_3
+              In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_4
+          Data register 4
+          0x50
+          0x20
+          
+            
+              TX_BYTE_4
+              In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_5
+          Data register 5
+          0x54
+          0x20
+          
+            
+              TX_BYTE_5
+              In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_6
+          Data register 6
+          0x58
+          0x20
+          
+            
+              TX_BYTE_6
+              In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_7
+          Data register 7
+          0x5C
+          0x20
+          
+            
+              TX_BYTE_7
+              In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_8
+          Data register 8
+          0x60
+          0x20
+          
+            
+              TX_BYTE_8
+              Stored the 8th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_9
+          Data register 9
+          0x64
+          0x20
+          
+            
+              TX_BYTE_9
+              Stored the 9th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_10
+          Data register 10
+          0x68
+          0x20
+          
+            
+              TX_BYTE_10
+              Stored the 10th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_11
+          Data register 11
+          0x6C
+          0x20
+          
+            
+              TX_BYTE_11
+              Stored the 11th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_12
+          Data register 12
+          0x70
+          0x20
+          
+            
+              TX_BYTE_12
+              Stored the 12th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          RX_MESSAGE_CNT
+          Receive Message Counter Register
+          0x74
+          0x20
+          
+            
+              RX_MESSAGE_COUNTER
+              This register reflects the number of messages available within the RX FIFO.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          CLOCK_DIVIDER
+          Clock Divider register
+          0x7C
+          0x20
+          
+            
+              CD
+              These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
+              0
+              8
+              read-write
+            
+            
+              CLOCK_OFF
+              This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
+              8
+              1
+            
+          
+        
+      
+    
+    
+      UART0
+      UART (Universal Asynchronous Receiver-Transmitter) Controller
+      UART
+      0x60000000
+      
+        0x0
+        0x84
+        registers
+      
+      
+        UART0
+        21
+      
+      
+        
+          FIFO
+          FIFO data register
+          0x0
+          0x20
+          
+            
+              RXFIFO_RD_BYTE
+              UART 0 accesses FIFO via this register.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          Raw interrupt status
+          0x4
+          0x20
+          0x00000002
+          
+            
+              RXFIFO_FULL_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_EMPTY_INT_RAW
+              This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
+              1
+              1
+              read-only
+            
+            
+              PARITY_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a parity error in the data.
+              2
+              1
+              read-only
+            
+            
+              FRM_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a data frame error .
+              3
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
+              4
+              1
+              read-only
+            
+            
+              DSR_CHG_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
+              5
+              1
+              read-only
+            
+            
+              CTS_CHG_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
+              6
+              1
+              read-only
+            
+            
+              BRK_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
+              7
+              1
+              read-only
+            
+            
+              RXFIFO_TOUT_INT_RAW
+              This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
+              8
+              1
+              read-only
+            
+            
+              SW_XON_INT_RAW
+              This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
+              9
+              1
+              read-only
+            
+            
+              SW_XOFF_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
+              10
+              1
+              read-only
+            
+            
+              GLITCH_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
+              11
+              1
+              read-only
+            
+            
+              TX_BRK_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.
+              12
+              1
+              read-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.
+              13
+              1
+              read-only
+            
+            
+              TX_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
+              14
+              1
+              read-only
+            
+            
+              RS485_PARITY_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
+              15
+              1
+              read-only
+            
+            
+              RS485_FRM_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
+              16
+              1
+              read-only
+            
+            
+              RS485_CLASH_INT_RAW
+              This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
+              17
+              1
+              read-only
+            
+            
+              AT_CMD_CHAR_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
+              18
+              1
+              read-only
+            
+            
+              WAKEUP_INT_RAW
+              This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
+              19
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          Masked interrupt status
+          0x8
+          0x20
+          
+            
+              RXFIFO_FULL_INT_ST
+              This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_EMPTY_INT_ST
+              This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.
+              1
+              1
+              read-only
+            
+            
+              PARITY_ERR_INT_ST
+              This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+              2
+              1
+              read-only
+            
+            
+              FRM_ERR_INT_ST
+              This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+              3
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_ST
+              This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+              4
+              1
+              read-only
+            
+            
+              DSR_CHG_INT_ST
+              This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+              5
+              1
+              read-only
+            
+            
+              CTS_CHG_INT_ST
+              This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+              6
+              1
+              read-only
+            
+            
+              BRK_DET_INT_ST
+              This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+              7
+              1
+              read-only
+            
+            
+              RXFIFO_TOUT_INT_ST
+              This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+              8
+              1
+              read-only
+            
+            
+              SW_XON_INT_ST
+              This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+              9
+              1
+              read-only
+            
+            
+              SW_XOFF_INT_ST
+              This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+              10
+              1
+              read-only
+            
+            
+              GLITCH_DET_INT_ST
+              This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+              11
+              1
+              read-only
+            
+            
+              TX_BRK_DONE_INT_ST
+              This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+              12
+              1
+              read-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_ST
+              This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
+              13
+              1
+              read-only
+            
+            
+              TX_DONE_INT_ST
+              This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+              14
+              1
+              read-only
+            
+            
+              RS485_PARITY_ERR_INT_ST
+              This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
+              15
+              1
+              read-only
+            
+            
+              RS485_FRM_ERR_INT_ST
+              This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
+              16
+              1
+              read-only
+            
+            
+              RS485_CLASH_INT_ST
+              This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+              17
+              1
+              read-only
+            
+            
+              AT_CMD_CHAR_DET_INT_ST
+              This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
+              18
+              1
+              read-only
+            
+            
+              WAKEUP_INT_ST
+              This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+              19
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          Interrupt enable bits
+          0xC
+          0x20
+          
+            
+              RXFIFO_FULL_INT_ENA
+              This is the enable bit for rxfifo_full_int_st register.
+              0
+              1
+              read-write
+            
+            
+              TXFIFO_EMPTY_INT_ENA
+              This is the enable bit for txfifo_empty_int_st register.
+              1
+              1
+              read-write
+            
+            
+              PARITY_ERR_INT_ENA
+              This is the enable bit for parity_err_int_st register.
+              2
+              1
+              read-write
+            
+            
+              FRM_ERR_INT_ENA
+              This is the enable bit for frm_err_int_st register.
+              3
+              1
+              read-write
+            
+            
+              RXFIFO_OVF_INT_ENA
+              This is the enable bit for rxfifo_ovf_int_st register.
+              4
+              1
+              read-write
+            
+            
+              DSR_CHG_INT_ENA
+              This is the enable bit for dsr_chg_int_st register.
+              5
+              1
+              read-write
+            
+            
+              CTS_CHG_INT_ENA
+              This is the enable bit for cts_chg_int_st register.
+              6
+              1
+              read-write
+            
+            
+              BRK_DET_INT_ENA
+              This is the enable bit for brk_det_int_st register.
+              7
+              1
+              read-write
+            
+            
+              RXFIFO_TOUT_INT_ENA
+              This is the enable bit for rxfifo_tout_int_st register.
+              8
+              1
+              read-write
+            
+            
+              SW_XON_INT_ENA
+              This is the enable bit for sw_xon_int_st register.
+              9
+              1
+              read-write
+            
+            
+              SW_XOFF_INT_ENA
+              This is the enable bit for sw_xoff_int_st register.
+              10
+              1
+              read-write
+            
+            
+              GLITCH_DET_INT_ENA
+              This is the enable bit for glitch_det_int_st register.
+              11
+              1
+              read-write
+            
+            
+              TX_BRK_DONE_INT_ENA
+              This is the enable bit for tx_brk_done_int_st register.
+              12
+              1
+              read-write
+            
+            
+              TX_BRK_IDLE_DONE_INT_ENA
+              This is the enable bit for tx_brk_idle_done_int_st register.
+              13
+              1
+              read-write
+            
+            
+              TX_DONE_INT_ENA
+              This is the enable bit for tx_done_int_st register.
+              14
+              1
+              read-write
+            
+            
+              RS485_PARITY_ERR_INT_ENA
+              This is the enable bit for rs485_parity_err_int_st register.
+              15
+              1
+              read-write
+            
+            
+              RS485_FRM_ERR_INT_ENA
+              This is the enable bit for rs485_parity_err_int_st register.
+              16
+              1
+              read-write
+            
+            
+              RS485_CLASH_INT_ENA
+              This is the enable bit for rs485_clash_int_st register.
+              17
+              1
+              read-write
+            
+            
+              AT_CMD_CHAR_DET_INT_ENA
+              This is the enable bit for at_cmd_char_det_int_st register.
+              18
+              1
+              read-write
+            
+            
+              WAKEUP_INT_ENA
+              This is the enable bit for uart_wakeup_int_st register.
+              19
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          Interrupt clear bits
+          0x10
+          0x20
+          
+            
+              RXFIFO_FULL_INT_CLR
+              Set this bit to clear the rxfifo_full_int_raw interrupt.
+              0
+              1
+              write-only
+            
+            
+              TXFIFO_EMPTY_INT_CLR
+              Set this bit to clear txfifo_empty_int_raw interrupt.
+              1
+              1
+              write-only
+            
+            
+              PARITY_ERR_INT_CLR
+              Set this bit to clear parity_err_int_raw interrupt.
+              2
+              1
+              write-only
+            
+            
+              FRM_ERR_INT_CLR
+              Set this bit to clear frm_err_int_raw interrupt.
+              3
+              1
+              write-only
+            
+            
+              RXFIFO_OVF_INT_CLR
+              Set this bit to clear rxfifo_ovf_int_raw interrupt.
+              4
+              1
+              write-only
+            
+            
+              DSR_CHG_INT_CLR
+              Set this bit to clear the dsr_chg_int_raw interrupt.
+              5
+              1
+              write-only
+            
+            
+              CTS_CHG_INT_CLR
+              Set this bit to clear the cts_chg_int_raw interrupt.
+              6
+              1
+              write-only
+            
+            
+              BRK_DET_INT_CLR
+              Set this bit to clear the brk_det_int_raw interrupt.
+              7
+              1
+              write-only
+            
+            
+              RXFIFO_TOUT_INT_CLR
+              Set this bit to clear the rxfifo_tout_int_raw interrupt.
+              8
+              1
+              write-only
+            
+            
+              SW_XON_INT_CLR
+              Set this bit to clear the sw_xon_int_raw interrupt.
+              9
+              1
+              write-only
+            
+            
+              SW_XOFF_INT_CLR
+              Set this bit to clear the sw_xoff_int_raw interrupt.
+              10
+              1
+              write-only
+            
+            
+              GLITCH_DET_INT_CLR
+              Set this bit to clear the glitch_det_int_raw interrupt.
+              11
+              1
+              write-only
+            
+            
+              TX_BRK_DONE_INT_CLR
+              Set this bit to clear the tx_brk_done_int_raw interrupt..
+              12
+              1
+              write-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_CLR
+              Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+              13
+              1
+              write-only
+            
+            
+              TX_DONE_INT_CLR
+              Set this bit to clear the tx_done_int_raw interrupt.
+              14
+              1
+              write-only
+            
+            
+              RS485_PARITY_ERR_INT_CLR
+              Set this bit to clear the rs485_parity_err_int_raw interrupt.
+              15
+              1
+              write-only
+            
+            
+              RS485_FRM_ERR_INT_CLR
+              Set this bit to clear the rs485_frm_err_int_raw interrupt.
+              16
+              1
+              write-only
+            
+            
+              RS485_CLASH_INT_CLR
+              Set this bit to clear the rs485_clash_int_raw interrupt.
+              17
+              1
+              write-only
+            
+            
+              AT_CMD_CHAR_DET_INT_CLR
+              Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+              18
+              1
+              write-only
+            
+            
+              WAKEUP_INT_CLR
+              Set this bit to clear the uart_wakeup_int_raw interrupt.
+              19
+              1
+              write-only
+            
+          
+        
+        
+          CLKDIV
+          Clock divider configuration
+          0x14
+          0x20
+          0x000002B6
+          
+            
+              CLKDIV
+              The integral part of the frequency divider factor.
+              0
+              12
+              read-write
+            
+            
+              FRAG
+              The decimal part of the frequency divider factor.
+              20
+              4
+              read-write
+            
+          
+        
+        
+          RX_FILT
+          Rx Filter configuration
+          0x18
+          0x20
+          0x00000008
+          
+            
+              GLITCH_FILT
+              when input pulse width is lower than this value, the pulse is ignored.
+              0
+              8
+              read-write
+            
+            
+              GLITCH_FILT_EN
+              Set this bit to enable Rx signal filter.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          STATUS
+          UART status register
+          0x1C
+          0x20
+          0xE000C000
+          
+            
+              RXFIFO_CNT
+              Stores the byte number of valid data in Rx-FIFO.
+              0
+              10
+              read-only
+            
+            
+              DSRN
+              The register represent the level value of the internal uart dsr signal.
+              13
+              1
+              read-only
+            
+            
+              CTSN
+              This register represent the level value of the internal uart cts signal.
+              14
+              1
+              read-only
+            
+            
+              RXD
+              This register represent the  level value of the internal uart rxd signal.
+              15
+              1
+              read-only
+            
+            
+              TXFIFO_CNT
+              Stores the byte number of data in Tx-FIFO.
+              16
+              10
+              read-only
+            
+            
+              DTRN
+              This bit represents the level of the internal uart dtr signal.
+              29
+              1
+              read-only
+            
+            
+              RTSN
+              This bit represents the level of the internal uart rts signal.
+              30
+              1
+              read-only
+            
+            
+              TXD
+              This bit represents the  level of the internal uart txd signal.
+              31
+              1
+              read-only
+            
+          
+        
+        
+          CONF0
+          a
+          0x20
+          0x20
+          0x1000001C
+          
+            
+              PARITY
+              This register is used to configure the parity check mode.
+              0
+              1
+              read-write
+            
+            
+              PARITY_EN
+              Set this bit to enable uart parity check.
+              1
+              1
+              read-write
+            
+            
+              BIT_NUM
+              This register is used to set the length of data.
+              2
+              2
+              read-write
+            
+            
+              STOP_BIT_NUM
+              This register is used to set the length of  stop bit.
+              4
+              2
+              read-write
+            
+            
+              SW_RTS
+              This register is used to configure the software rts signal which is used in software flow control.
+              6
+              1
+              read-write
+            
+            
+              SW_DTR
+              This register is used to configure the software dtr signal which is used in software flow control.
+              7
+              1
+              read-write
+            
+            
+              TXD_BRK
+              Set this bit to enbale transmitter to  send NULL when the process of sending data is done.
+              8
+              1
+              read-write
+            
+            
+              IRDA_DPLX
+              Set this bit to enable IrDA loopback mode.
+              9
+              1
+              read-write
+            
+            
+              IRDA_TX_EN
+              This is the start enable bit for IrDA transmitter.
+              10
+              1
+              read-write
+            
+            
+              IRDA_WCTL
+              1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
+              11
+              1
+              read-write
+            
+            
+              IRDA_TX_INV
+              Set this bit to invert the level of  IrDA transmitter.
+              12
+              1
+              read-write
+            
+            
+              IRDA_RX_INV
+              Set this bit to invert the level of IrDA receiver.
+              13
+              1
+              read-write
+            
+            
+              LOOPBACK
+              Set this bit to enable uart loopback test mode.
+              14
+              1
+              read-write
+            
+            
+              TX_FLOW_EN
+              Set this bit to enable flow control function for transmitter.
+              15
+              1
+              read-write
+            
+            
+              IRDA_EN
+              Set this bit to enable IrDA protocol.
+              16
+              1
+              read-write
+            
+            
+              RXFIFO_RST
+              Set this bit to reset the uart receive-FIFO.
+              17
+              1
+              read-write
+            
+            
+              TXFIFO_RST
+              Set this bit to reset the uart transmit-FIFO.
+              18
+              1
+              read-write
+            
+            
+              RXD_INV
+              Set this bit to inverse the level value of uart rxd signal.
+              19
+              1
+              read-write
+            
+            
+              CTS_INV
+              Set this bit to inverse the level value of uart cts signal.
+              20
+              1
+              read-write
+            
+            
+              DSR_INV
+              Set this bit to inverse the level value of uart dsr signal.
+              21
+              1
+              read-write
+            
+            
+              TXD_INV
+              Set this bit to inverse the level value of uart txd signal.
+              22
+              1
+              read-write
+            
+            
+              RTS_INV
+              Set this bit to inverse the level value of uart rts signal.
+              23
+              1
+              read-write
+            
+            
+              DTR_INV
+              Set this bit to inverse the level value of uart dtr signal.
+              24
+              1
+              read-write
+            
+            
+              CLK_EN
+              1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+              25
+              1
+              read-write
+            
+            
+              ERR_WR_MASK
+              1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.
+              26
+              1
+              read-write
+            
+            
+              AUTOBAUD_EN
+              This is the enable bit for detecting baudrate.
+              27
+              1
+              read-write
+            
+            
+              MEM_CLK_EN
+              UART memory clock gate enable signal.
+              28
+              1
+              read-write
+            
+          
+        
+        
+          CONF1
+          Configuration register 1
+          0x24
+          0x20
+          0x0000C060
+          
+            
+              RXFIFO_FULL_THRHD
+              It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
+              0
+              9
+              read-write
+            
+            
+              TXFIFO_EMPTY_THRHD
+              It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
+              9
+              9
+              read-write
+            
+            
+              DIS_RX_DAT_OVF
+              Disable UART Rx data overflow detect.
+              18
+              1
+              read-write
+            
+            
+              RX_TOUT_FLOW_DIS
+              Set this bit to stop accumulating idle_cnt when hardware flow control works.
+              19
+              1
+              read-write
+            
+            
+              RX_FLOW_EN
+              This is the flow enable bit for UART receiver.
+              20
+              1
+              read-write
+            
+            
+              RX_TOUT_EN
+              This is the enble bit for uart receiver's timeout function.
+              21
+              1
+              read-write
+            
+          
+        
+        
+          LOWPULSE
+          Autobaud minimum low pulse duration register
+          0x28
+          0x20
+          0x00000FFF
+          
+            
+              MIN_CNT
+              This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          HIGHPULSE
+          Autobaud minimum high pulse duration register
+          0x2C
+          0x20
+          0x00000FFF
+          
+            
+              MIN_CNT
+              This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          RXD_CNT
+          Autobaud edge change count register
+          0x30
+          0x20
+          
+            
+              RXD_EDGE_CNT
+              This register stores the count of rxd edge change. It is used in baud rate-detect process.
+              0
+              10
+              read-only
+            
+          
+        
+        
+          FLOW_CONF
+          Software flow-control configuration
+          0x34
+          0x20
+          
+            
+              SW_FLOW_CON_EN
+              Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
+              0
+              1
+              read-write
+            
+            
+              XONOFF_DEL
+              Set this bit to remove flow control char from the received data.
+              1
+              1
+              read-write
+            
+            
+              FORCE_XON
+              Set this bit to enable the transmitter to go on sending data.
+              2
+              1
+              read-write
+            
+            
+              FORCE_XOFF
+              Set this bit to stop the  transmitter from sending data.
+              3
+              1
+              read-write
+            
+            
+              SEND_XON
+              Set this bit to send Xon char. It is cleared by hardware automatically.
+              4
+              1
+              read-write
+            
+            
+              SEND_XOFF
+              Set this bit to send Xoff char. It is cleared by hardware automatically.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          SLEEP_CONF
+          Sleep-mode configuration
+          0x38
+          0x20
+          0x000000F0
+          
+            
+              ACTIVE_THRESHOLD
+              The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
+              0
+              10
+              read-write
+            
+          
+        
+        
+          SWFC_CONF0
+          Software flow-control character configuration
+          0x3C
+          0x20
+          0x000026E0
+          
+            
+              XOFF_THRESHOLD
+              When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
+              0
+              9
+              read-write
+            
+            
+              XOFF_CHAR
+              This register stores the Xoff flow control char.
+              9
+              8
+              read-write
+            
+          
+        
+        
+          SWFC_CONF1
+          Software flow-control character configuration
+          0x40
+          0x20
+          0x00002200
+          
+            
+              XON_THRESHOLD
+              When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
+              0
+              9
+              read-write
+            
+            
+              XON_CHAR
+              This register stores the Xon flow control char.
+              9
+              8
+              read-write
+            
+          
+        
+        
+          TXBRK_CONF
+          Tx Break character configuration
+          0x44
+          0x20
+          0x0000000A
+          
+            
+              TX_BRK_NUM
+              This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          IDLE_CONF
+          Frame-end idle configuration
+          0x48
+          0x20
+          0x00040100
+          
+            
+              RX_IDLE_THRHD
+              It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
+              0
+              10
+              read-write
+            
+            
+              TX_IDLE_NUM
+              This register is used to configure the duration time between transfers.
+              10
+              10
+              read-write
+            
+          
+        
+        
+          RS485_CONF
+          RS485 mode configuration
+          0x4C
+          0x20
+          
+            
+              RS485_EN
+              Set this bit to choose the rs485 mode.
+              0
+              1
+              read-write
+            
+            
+              DL0_EN
+              Set this bit to delay the stop bit by 1 bit.
+              1
+              1
+              read-write
+            
+            
+              DL1_EN
+              Set this bit to delay the stop bit by 1 bit.
+              2
+              1
+              read-write
+            
+            
+              RS485TX_RX_EN
+              Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
+              3
+              1
+              read-write
+            
+            
+              RS485RXBY_TX_EN
+              1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+              4
+              1
+              read-write
+            
+            
+              RS485_RX_DLY_NUM
+              This register is used to delay the receiver's internal data signal.
+              5
+              1
+              read-write
+            
+            
+              RS485_TX_DLY_NUM
+              This register is used to delay the transmitter's internal data signal.
+              6
+              4
+              read-write
+            
+          
+        
+        
+          AT_CMD_PRECNT
+          Pre-sequence timing configuration
+          0x50
+          0x20
+          0x00000901
+          
+            
+              PRE_IDLE_NUM
+              This register is used to configure the idle duration time before the first at_cmd is received by receiver.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_POSTCNT
+          Post-sequence timing configuration
+          0x54
+          0x20
+          0x00000901
+          
+            
+              POST_IDLE_NUM
+              This register is used to configure the duration time between the last at_cmd and the next data.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_GAPTOUT
+          Timeout configuration
+          0x58
+          0x20
+          0x0000000B
+          
+            
+              RX_GAP_TOUT
+              This register is used to configure the duration time between the at_cmd chars.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_CHAR
+          AT escape sequence detection configuration
+          0x5C
+          0x20
+          0x0000032B
+          
+            
+              AT_CMD_CHAR
+              This register is used to configure the content of at_cmd char.
+              0
+              8
+              read-write
+            
+            
+              CHAR_NUM
+              This register is used to configure the num of continuous at_cmd chars received by receiver.
+              8
+              8
+              read-write
+            
+          
+        
+        
+          MEM_CONF
+          UART threshold and allocation configuration
+          0x60
+          0x20
+          0x000A0012
+          
+            
+              RX_SIZE
+              This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
+              1
+              3
+              read-write
+            
+            
+              TX_SIZE
+              This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
+              4
+              3
+              read-write
+            
+            
+              RX_FLOW_THRHD
+              This register is used to configure the maximum amount of data that can be received  when hardware flow control works.
+              7
+              9
+              read-write
+            
+            
+              RX_TOUT_THRHD
+              This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
+              16
+              10
+              read-write
+            
+            
+              MEM_FORCE_PD
+              Set this bit to force power down UART memory.
+              26
+              1
+              read-write
+            
+            
+              MEM_FORCE_PU
+              Set this bit to force power up UART memory.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          MEM_TX_STATUS
+          Tx-FIFO write and read offset address.
+          0x64
+          0x20
+          
+            
+              APB_TX_WADDR
+              This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
+              0
+              10
+              read-only
+            
+            
+              TX_RADDR
+              This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
+              11
+              10
+              read-only
+            
+          
+        
+        
+          MEM_RX_STATUS
+          Rx-FIFO write and read offset address.
+          0x68
+          0x20
+          0x00080100
+          
+            
+              APB_RX_RADDR
+              This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+              0
+              10
+              read-only
+            
+            
+              RX_WADDR
+              This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+              11
+              10
+              read-only
+            
+          
+        
+        
+          FSM_STATUS
+          UART transmit and receive status.
+          0x6C
+          0x20
+          
+            
+              ST_URX_OUT
+              This is the status register of receiver.
+              0
+              4
+              read-only
+            
+            
+              ST_UTX_OUT
+              This is the status register of transmitter.
+              4
+              4
+              read-only
+            
+          
+        
+        
+          POSPULSE
+          Autobaud high pulse register
+          0x70
+          0x20
+          0x00000FFF
+          
+            
+              POSEDGE_MIN_CNT
+              This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          NEGPULSE
+          Autobaud low pulse register
+          0x74
+          0x20
+          0x00000FFF
+          
+            
+              NEGEDGE_MIN_CNT
+              This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          CLK_CONF
+          UART core clock configuration
+          0x78
+          0x20
+          0x03701000
+          
+            
+              SCLK_DIV_B
+              The  denominator of the frequency divider factor.
+              0
+              6
+              read-write
+            
+            
+              SCLK_DIV_A
+              The numerator of the frequency divider factor.
+              6
+              6
+              read-write
+            
+            
+              SCLK_DIV_NUM
+              The integral part of the frequency divider factor.
+              12
+              8
+              read-write
+            
+            
+              SCLK_SEL
+              UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+              20
+              2
+              read-write
+            
+            
+              SCLK_EN
+              Set this bit to enable UART Tx/Rx clock.
+              22
+              1
+              read-write
+            
+            
+              RST_CORE
+              Write 1 then write 0 to this bit, reset UART Tx/Rx.
+              23
+              1
+              read-write
+            
+            
+              TX_SCLK_EN
+              Set this bit to enable UART Tx clock.
+              24
+              1
+              read-write
+            
+            
+              RX_SCLK_EN
+              Set this bit to enable UART Rx clock.
+              25
+              1
+              read-write
+            
+            
+              TX_RST_CORE
+              Write 1 then write 0 to this bit, reset UART Tx.
+              26
+              1
+              read-write
+            
+            
+              RX_RST_CORE
+              Write 1 then write 0 to this bit, reset UART Rx.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          UART Version register
+          0x7C
+          0x20
+          0x02008270
+          
+            
+              DATE
+              This is the version register.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ID
+          UART ID register
+          0x80
+          0x20
+          0x40000500
+          
+            
+              ID
+              This register is used to configure the uart_id.
+              0
+              30
+              read-write
+            
+            
+              HIGH_SPEED
+              This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
+              30
+              1
+              read-write
+            
+            
+              REG_UPDATE
+              Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
+              31
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      UART1
+      UART (Universal Asynchronous Receiver-Transmitter) Controller
+      0x60010000
+      
+        UART1
+        22
+      
+    
+    
+      UHCI0
+      Universal Host Controller Interface
+      UHCI
+      0x60014000
+      
+        0x0
+        0x84
+        registers
+      
+      
+        UHCI0
+        15
+      
+      
+        
+          CONF0
+          a
+          0x0
+          0x20
+          0x000006E0
+          
+            
+              TX_RST
+              Write 1, then write 0 to this bit to reset decode state machine.
+              0
+              1
+              read-write
+            
+            
+              RX_RST
+              Write 1, then write 0 to this bit to reset encode state machine.
+              1
+              1
+              read-write
+            
+            
+              UART0_CE
+              Set this bit to link up HCI and UART0.
+              2
+              1
+              read-write
+            
+            
+              UART1_CE
+              Set this bit to link up HCI and UART1.
+              3
+              1
+              read-write
+            
+            
+              SEPER_EN
+              Set this bit to separate the data frame using a special char.
+              5
+              1
+              read-write
+            
+            
+              HEAD_EN
+              Set this bit to encode the data packet with a formatting header.
+              6
+              1
+              read-write
+            
+            
+              CRC_REC_EN
+              Set this bit to enable UHCI to receive the 16 bit CRC.
+              7
+              1
+              read-write
+            
+            
+              UART_IDLE_EOF_EN
+              If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
+              8
+              1
+              read-write
+            
+            
+              LEN_EOF_EN
+              If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
+              9
+              1
+              read-write
+            
+            
+              ENCODE_CRC_EN
+              Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
+              10
+              1
+              read-write
+            
+            
+              CLK_EN
+              1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
+              11
+              1
+              read-write
+            
+            
+              UART_RX_BRK_EOF_EN
+              If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          a
+          0x4
+          0x20
+          
+            
+              RX_START_INT_RAW
+              a
+              0
+              1
+              read-only
+            
+            
+              TX_START_INT_RAW
+              a
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_RAW
+              a
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_RAW
+              a
+              3
+              1
+              read-only
+            
+            
+              SEND_S_REG_Q_INT_RAW
+              a
+              4
+              1
+              read-only
+            
+            
+              SEND_A_REG_Q_INT_RAW
+              a
+              5
+              1
+              read-only
+            
+            
+              OUT_EOF_INT_RAW
+              This is the interrupt raw bit. Triggered when there are some errors in EOF in the
+              6
+              1
+              read-only
+            
+            
+              APP_CTRL0_INT_RAW
+              Soft control int raw bit.
+              7
+              1
+              read-write
+            
+            
+              APP_CTRL1_INT_RAW
+              Soft control int raw bit.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          INT_ST
+          a
+          0x8
+          0x20
+          
+            
+              RX_START_INT_ST
+              a
+              0
+              1
+              read-only
+            
+            
+              TX_START_INT_ST
+              a
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_ST
+              a
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_ST
+              a
+              3
+              1
+              read-only
+            
+            
+              SEND_S_REG_Q_INT_ST
+              a
+              4
+              1
+              read-only
+            
+            
+              SEND_A_REG_Q_INT_ST
+              a
+              5
+              1
+              read-only
+            
+            
+              OUTLINK_EOF_ERR_INT_ST
+              a
+              6
+              1
+              read-only
+            
+            
+              APP_CTRL0_INT_ST
+              a
+              7
+              1
+              read-only
+            
+            
+              APP_CTRL1_INT_ST
+              a
+              8
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          a
+          0xC
+          0x20
+          
+            
+              RX_START_INT_ENA
+              a
+              0
+              1
+              read-write
+            
+            
+              TX_START_INT_ENA
+              a
+              1
+              1
+              read-write
+            
+            
+              RX_HUNG_INT_ENA
+              a
+              2
+              1
+              read-write
+            
+            
+              TX_HUNG_INT_ENA
+              a
+              3
+              1
+              read-write
+            
+            
+              SEND_S_REG_Q_INT_ENA
+              a
+              4
+              1
+              read-write
+            
+            
+              SEND_A_REG_Q_INT_ENA
+              a
+              5
+              1
+              read-write
+            
+            
+              OUTLINK_EOF_ERR_INT_ENA
+              a
+              6
+              1
+              read-write
+            
+            
+              APP_CTRL0_INT_ENA
+              a
+              7
+              1
+              read-write
+            
+            
+              APP_CTRL1_INT_ENA
+              a
+              8
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          a
+          0x10
+          0x20
+          
+            
+              RX_START_INT_CLR
+              a
+              0
+              1
+              write-only
+            
+            
+              TX_START_INT_CLR
+              a
+              1
+              1
+              write-only
+            
+            
+              RX_HUNG_INT_CLR
+              a
+              2
+              1
+              write-only
+            
+            
+              TX_HUNG_INT_CLR
+              a
+              3
+              1
+              write-only
+            
+            
+              SEND_S_REG_Q_INT_CLR
+              a
+              4
+              1
+              write-only
+            
+            
+              SEND_A_REG_Q_INT_CLR
+              a
+              5
+              1
+              write-only
+            
+            
+              OUTLINK_EOF_ERR_INT_CLR
+              a
+              6
+              1
+              write-only
+            
+            
+              APP_CTRL0_INT_CLR
+              a
+              7
+              1
+              write-only
+            
+            
+              APP_CTRL1_INT_CLR
+              a
+              8
+              1
+              write-only
+            
+          
+        
+        
+          CONF1
+          a
+          0x14
+          0x20
+          0x00000033
+          
+            
+              CHECK_SUM_EN
+              a
+              0
+              1
+              read-write
+            
+            
+              CHECK_SEQ_EN
+              a
+              1
+              1
+              read-write
+            
+            
+              CRC_DISABLE
+              a
+              2
+              1
+              read-write
+            
+            
+              SAVE_HEAD
+              a
+              3
+              1
+              read-write
+            
+            
+              TX_CHECK_SUM_RE
+              a
+              4
+              1
+              read-write
+            
+            
+              TX_ACK_NUM_RE
+              a
+              5
+              1
+              read-write
+            
+            
+              WAIT_SW_START
+              a
+              7
+              1
+              read-write
+            
+            
+              SW_START
+              a
+              8
+              1
+              read-write
+            
+          
+        
+        
+          STATE0
+          a
+          0x18
+          0x20
+          
+            
+              RX_ERR_CAUSE
+              a
+              0
+              3
+              read-only
+            
+            
+              DECODE_STATE
+              a
+              3
+              3
+              read-only
+            
+          
+        
+        
+          STATE1
+          a
+          0x1C
+          0x20
+          
+            
+              ENCODE_STATE
+              a
+              0
+              3
+              read-only
+            
+          
+        
+        
+          ESCAPE_CONF
+          a
+          0x20
+          0x20
+          0x00000033
+          
+            
+              TX_C0_ESC_EN
+              a
+              0
+              1
+              read-write
+            
+            
+              TX_DB_ESC_EN
+              a
+              1
+              1
+              read-write
+            
+            
+              TX_11_ESC_EN
+              a
+              2
+              1
+              read-write
+            
+            
+              TX_13_ESC_EN
+              a
+              3
+              1
+              read-write
+            
+            
+              RX_C0_ESC_EN
+              a
+              4
+              1
+              read-write
+            
+            
+              RX_DB_ESC_EN
+              a
+              5
+              1
+              read-write
+            
+            
+              RX_11_ESC_EN
+              a
+              6
+              1
+              read-write
+            
+            
+              RX_13_ESC_EN
+              a
+              7
+              1
+              read-write
+            
+          
+        
+        
+          HUNG_CONF
+          a
+          0x24
+          0x20
+          0x00810810
+          
+            
+              TXFIFO_TIMEOUT
+              a
+              0
+              8
+              read-write
+            
+            
+              TXFIFO_TIMEOUT_SHIFT
+              a
+              8
+              3
+              read-write
+            
+            
+              TXFIFO_TIMEOUT_ENA
+              a
+              11
+              1
+              read-write
+            
+            
+              RXFIFO_TIMEOUT
+              a
+              12
+              8
+              read-write
+            
+            
+              RXFIFO_TIMEOUT_SHIFT
+              a
+              20
+              3
+              read-write
+            
+            
+              RXFIFO_TIMEOUT_ENA
+              a
+              23
+              1
+              read-write
+            
+          
+        
+        
+          ACK_NUM
+          a
+          0x28
+          0x20
+          0x00000008
+          
+            
+              ACK_NUM
+              a
+              0
+              3
+              read-write
+            
+            
+              LOAD
+              a
+              3
+              1
+              write-only
+            
+          
+        
+        
+          RX_HEAD
+          a
+          0x2C
+          0x20
+          
+            
+              RX_HEAD
+              a
+              0
+              32
+              read-only
+            
+          
+        
+        
+          QUICK_SENT
+          a
+          0x30
+          0x20
+          
+            
+              SINGLE_SEND_NUM
+              a
+              0
+              3
+              read-write
+            
+            
+              SINGLE_SEND_EN
+              a
+              3
+              1
+              read-write
+            
+            
+              ALWAYS_SEND_NUM
+              a
+              4
+              3
+              read-write
+            
+            
+              ALWAYS_SEND_EN
+              a
+              7
+              1
+              read-write
+            
+          
+        
+        
+          REG_Q0_WORD0
+          a
+          0x34
+          0x20
+          
+            
+              SEND_Q0_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q0_WORD1
+          a
+          0x38
+          0x20
+          
+            
+              SEND_Q0_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q1_WORD0
+          a
+          0x3C
+          0x20
+          
+            
+              SEND_Q1_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q1_WORD1
+          a
+          0x40
+          0x20
+          
+            
+              SEND_Q1_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q2_WORD0
+          a
+          0x44
+          0x20
+          
+            
+              SEND_Q2_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q2_WORD1
+          a
+          0x48
+          0x20
+          
+            
+              SEND_Q2_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q3_WORD0
+          a
+          0x4C
+          0x20
+          
+            
+              SEND_Q3_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q3_WORD1
+          a
+          0x50
+          0x20
+          
+            
+              SEND_Q3_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q4_WORD0
+          a
+          0x54
+          0x20
+          
+            
+              SEND_Q4_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q4_WORD1
+          a
+          0x58
+          0x20
+          
+            
+              SEND_Q4_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q5_WORD0
+          a
+          0x5C
+          0x20
+          
+            
+              SEND_Q5_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q5_WORD1
+          a
+          0x60
+          0x20
+          
+            
+              SEND_Q5_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q6_WORD0
+          a
+          0x64
+          0x20
+          
+            
+              SEND_Q6_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q6_WORD1
+          a
+          0x68
+          0x20
+          
+            
+              SEND_Q6_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ESC_CONF0
+          a
+          0x6C
+          0x20
+          0x00DCDBC0
+          
+            
+              SEPER_CHAR
+              a
+              0
+              8
+              read-write
+            
+            
+              SEPER_ESC_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              SEPER_ESC_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF1
+          a
+          0x70
+          0x20
+          0x00DDDBDB
+          
+            
+              ESC_SEQ0
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ0_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ0_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF2
+          a
+          0x74
+          0x20
+          0x00DEDB11
+          
+            
+              ESC_SEQ1
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ1_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ1_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF3
+          a
+          0x78
+          0x20
+          0x00DFDB13
+          
+            
+              ESC_SEQ2
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ2_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ2_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          PKT_THRES
+          a
+          0x7C
+          0x20
+          0x00000080
+          
+            
+              PKT_THRS
+              a
+              0
+              13
+              read-write
+            
+          
+        
+        
+          DATE
+          a
+          0x80
+          0x20
+          0x02007170
+          
+            
+              DATE
+              a
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      UHCI1
+      Universal Host Controller Interface
+      0x6000C000
+    
+    
+      USB_DEVICE
+      Full-speed USB Serial/JTAG Controller
+      USB_DEVICE
+      0x60043000
+      
+        0x0
+        0x50
+        registers
+      
+      
+        USB_SERIAL_JTAG
+        26
+      
+      
+        
+          EP1
+          USB_DEVICE_EP1_REG.
+          0x0
+          0x20
+          
+            
+              RDWR_BYTE
+              Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          EP1_CONF
+          USB_DEVICE_EP1_CONF_REG.
+          0x4
+          0x20
+          0x00000002
+          
+            
+              WR_DONE
+              Set this bit to indicate writing byte data to UART Tx FIFO is done.
+              0
+              1
+              write-only
+            
+            
+              SERIAL_IN_EP_DATA_FREE
+              1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_EP_DATA_AVAIL
+              1'b1: Indicate there is data in UART Rx FIFO.
+              2
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          USB_DEVICE_INT_RAW_REG.
+          0x8
+          0x20
+          0x00000008
+          
+            
+              JTAG_IN_FLUSH_INT_RAW
+              The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
+              0
+              1
+              read-only
+            
+            
+              SOF_INT_RAW
+              The raw interrupt bit turns to high level when SOF frame is received.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_RAW
+              The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
+              2
+              1
+              read-only
+            
+            
+              SERIAL_IN_EMPTY_INT_RAW
+              The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+              3
+              1
+              read-only
+            
+            
+              PID_ERR_INT_RAW
+              The raw interrupt bit turns to high level when pid error is detected.
+              4
+              1
+              read-only
+            
+            
+              CRC5_ERR_INT_RAW
+              The raw interrupt bit turns to high level when CRC5 error is detected.
+              5
+              1
+              read-only
+            
+            
+              CRC16_ERR_INT_RAW
+              The raw interrupt bit turns to high level when CRC16 error is detected.
+              6
+              1
+              read-only
+            
+            
+              STUFF_ERR_INT_RAW
+              The raw interrupt bit turns to high level when stuff error is detected.
+              7
+              1
+              read-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_RAW
+              The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
+              8
+              1
+              read-only
+            
+            
+              USB_BUS_RESET_INT_RAW
+              The raw interrupt bit turns to high level when usb bus reset is detected.
+              9
+              1
+              read-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_RAW
+              The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
+              10
+              1
+              read-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_RAW
+              The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
+              11
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          USB_DEVICE_INT_ST_REG.
+          0xC
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              SOF_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              SERIAL_IN_EMPTY_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              PID_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              CRC5_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              CRC16_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              STUFF_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              USB_BUS_RESET_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          USB_DEVICE_INT_ENA_REG.
+          0x10
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              SOF_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              SERIAL_IN_EMPTY_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              PID_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              CRC5_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              CRC16_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              STUFF_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              USB_BUS_RESET_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          USB_DEVICE_INT_CLR_REG.
+          0x14
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_CLR
+              Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              SOF_INT_CLR
+              Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_CLR
+              Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              SERIAL_IN_EMPTY_INT_CLR
+              Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              PID_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              CRC5_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              CRC16_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              STUFF_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_CLR
+              Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              USB_BUS_RESET_INT_CLR
+              Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_CLR
+              Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_CLR
+              Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              write-only
+            
+          
+        
+        
+          CONF0
+          USB_DEVICE_CONF0_REG.
+          0x18
+          0x20
+          0x00004200
+          
+            
+              PHY_SEL
+              Select internal/external PHY
+              0
+              1
+              read-write
+            
+            
+              EXCHG_PINS_OVERRIDE
+              Enable software control USB D+ D- exchange
+              1
+              1
+              read-write
+            
+            
+              EXCHG_PINS
+              USB D+ D- exchange
+              2
+              1
+              read-write
+            
+            
+              VREFH
+              Control single-end input high threshold,1.76V to 2V, step 80mV
+              3
+              2
+              read-write
+            
+            
+              VREFL
+              Control single-end input low threshold,0.8V to 1.04V, step 80mV
+              5
+              2
+              read-write
+            
+            
+              VREF_OVERRIDE
+              Enable software control input  threshold
+              7
+              1
+              read-write
+            
+            
+              PAD_PULL_OVERRIDE
+              Enable software control USB D+ D- pullup pulldown
+              8
+              1
+              read-write
+            
+            
+              DP_PULLUP
+              Control USB D+ pull up.
+              9
+              1
+              read-write
+            
+            
+              DP_PULLDOWN
+              Control USB D+ pull down.
+              10
+              1
+              read-write
+            
+            
+              DM_PULLUP
+              Control USB D- pull up.
+              11
+              1
+              read-write
+            
+            
+              DM_PULLDOWN
+              Control USB D- pull down.
+              12
+              1
+              read-write
+            
+            
+              PULLUP_VALUE
+              Control pull up value.
+              13
+              1
+              read-write
+            
+            
+              USB_PAD_ENABLE
+              Enable USB pad function.
+              14
+              1
+              read-write
+            
+          
+        
+        
+          TEST
+          USB_DEVICE_TEST_REG.
+          0x1C
+          0x20
+          
+            
+              ENABLE
+              Enable test of the USB pad
+              0
+              1
+              read-write
+            
+            
+              USB_OE
+              USB pad oen in test
+              1
+              1
+              read-write
+            
+            
+              TX_DP
+              USB D+ tx value in test
+              2
+              1
+              read-write
+            
+            
+              TX_DM
+              USB D- tx value in test
+              3
+              1
+              read-write
+            
+          
+        
+        
+          JFIFO_ST
+          USB_DEVICE_JFIFO_ST_REG.
+          0x20
+          0x20
+          0x00000044
+          
+            
+              IN_FIFO_CNT
+              JTAT in fifo counter.
+              0
+              2
+              read-only
+            
+            
+              IN_FIFO_EMPTY
+              1: JTAG in fifo is empty.
+              2
+              1
+              read-only
+            
+            
+              IN_FIFO_FULL
+              1: JTAG in fifo is full.
+              3
+              1
+              read-only
+            
+            
+              OUT_FIFO_CNT
+              JTAT out fifo counter.
+              4
+              2
+              read-only
+            
+            
+              OUT_FIFO_EMPTY
+              1: JTAG out fifo is empty.
+              6
+              1
+              read-only
+            
+            
+              OUT_FIFO_FULL
+              1: JTAG out fifo is full.
+              7
+              1
+              read-only
+            
+            
+              IN_FIFO_RESET
+              Write 1 to reset JTAG in fifo.
+              8
+              1
+              read-write
+            
+            
+              OUT_FIFO_RESET
+              Write 1 to reset JTAG out fifo.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          FRAM_NUM
+          USB_DEVICE_FRAM_NUM_REG.
+          0x24
+          0x20
+          
+            
+              SOF_FRAME_INDEX
+              Frame index of received SOF frame.
+              0
+              11
+              read-only
+            
+          
+        
+        
+          IN_EP0_ST
+          USB_DEVICE_IN_EP0_ST_REG.
+          0x28
+          0x20
+          0x00000001
+          
+            
+              IN_EP0_STATE
+              State of IN Endpoint 0.
+              0
+              2
+              read-only
+            
+            
+              IN_EP0_WR_ADDR
+              Write data address of IN endpoint 0.
+              2
+              7
+              read-only
+            
+            
+              IN_EP0_RD_ADDR
+              Read data address of IN endpoint 0.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP1_ST
+          USB_DEVICE_IN_EP1_ST_REG.
+          0x2C
+          0x20
+          0x00000001
+          
+            
+              IN_EP1_STATE
+              State of IN Endpoint 1.
+              0
+              2
+              read-only
+            
+            
+              IN_EP1_WR_ADDR
+              Write data address of IN endpoint 1.
+              2
+              7
+              read-only
+            
+            
+              IN_EP1_RD_ADDR
+              Read data address of IN endpoint 1.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP2_ST
+          USB_DEVICE_IN_EP2_ST_REG.
+          0x30
+          0x20
+          0x00000001
+          
+            
+              IN_EP2_STATE
+              State of IN Endpoint 2.
+              0
+              2
+              read-only
+            
+            
+              IN_EP2_WR_ADDR
+              Write data address of IN endpoint 2.
+              2
+              7
+              read-only
+            
+            
+              IN_EP2_RD_ADDR
+              Read data address of IN endpoint 2.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP3_ST
+          USB_DEVICE_IN_EP3_ST_REG.
+          0x34
+          0x20
+          0x00000001
+          
+            
+              IN_EP3_STATE
+              State of IN Endpoint 3.
+              0
+              2
+              read-only
+            
+            
+              IN_EP3_WR_ADDR
+              Write data address of IN endpoint 3.
+              2
+              7
+              read-only
+            
+            
+              IN_EP3_RD_ADDR
+              Read data address of IN endpoint 3.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP0_ST
+          USB_DEVICE_OUT_EP0_ST_REG.
+          0x38
+          0x20
+          
+            
+              OUT_EP0_STATE
+              State of OUT Endpoint 0.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP0_WR_ADDR
+              Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP0_RD_ADDR
+              Read data address of OUT endpoint 0.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP1_ST
+          USB_DEVICE_OUT_EP1_ST_REG.
+          0x3C
+          0x20
+          
+            
+              OUT_EP1_STATE
+              State of OUT Endpoint 1.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP1_WR_ADDR
+              Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP1_RD_ADDR
+              Read data address of OUT endpoint 1.
+              9
+              7
+              read-only
+            
+            
+              OUT_EP1_REC_DATA_CNT
+              Data count in OUT endpoint 1 when one packet is received.
+              16
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP2_ST
+          USB_DEVICE_OUT_EP2_ST_REG.
+          0x40
+          0x20
+          
+            
+              OUT_EP2_STATE
+              State of OUT Endpoint 2.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP2_WR_ADDR
+              Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP2_RD_ADDR
+              Read data address of OUT endpoint 2.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          MISC_CONF
+          USB_DEVICE_MISC_CONF_REG.
+          0x44
+          0x20
+          
+            
+              CLK_EN
+              1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          MEM_CONF
+          USB_DEVICE_MEM_CONF_REG.
+          0x48
+          0x20
+          0x00000002
+          
+            
+              USB_MEM_PD
+              1: power down usb memory.
+              0
+              1
+              read-write
+            
+            
+              USB_MEM_CLK_EN
+              1: Force clock on for usb memory.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          USB_DEVICE_DATE_REG.
+          0x80
+          0x20
+          0x02007300
+          
+            
+              DATE
+              register version.
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      XTS_AES
+      XTS-AES-128 Flash Encryption
+      XTS_AES
+      0x600CC000
+      
+        0x0
+        0x30
+        registers
+      
+      
+        
+          16
+          0x1
+          PLAIN_MEM[%s]
+          The memory that stores plaintext
+          0x0
+          0x8
+        
+        
+          LINESIZE
+          XTS-AES line-size register
+          0x40
+          0x20
+          
+            
+              LINESIZE
+              This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DESTINATION
+          XTS-AES destination register
+          0x44
+          0x20
+          
+            
+              DESTINATION
+              This bit stores the destination. 0: flash(default). 1: reserved.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PHYSICAL_ADDRESS
+          XTS-AES physical address register
+          0x48
+          0x20
+          
+            
+              PHYSICAL_ADDRESS
+              Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          TRIGGER
+          XTS-AES trigger register
+          0x4C
+          0x20
+          
+            
+              TRIGGER
+              Set this bit to start manual encryption calculation
+              0
+              1
+              write-only
+            
+          
+        
+        
+          RELEASE
+          XTS-AES release register
+          0x50
+          0x20
+          
+            
+              RELEASE
+              Set this bit to release the manual encrypted result, after that the result will be visible to spi
+              0
+              1
+              write-only
+            
+          
+        
+        
+          DESTROY
+          XTS-AES destroy register
+          0x54
+          0x20
+          
+            
+              DESTROY
+              Set this bit to destroy XTS-AES result.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          STATE
+          XTS-AES status register
+          0x58
+          0x20
+          
+            
+              STATE
+              Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
+              0
+              2
+              read-only
+            
+          
+        
+        
+          DATE
+          XTS-AES version control register
+          0x5C
+          0x20
+          0x20200623
+          
+            
+              DATE
+              Those bits stores the version information of XTS-AES.
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+  
+
\ No newline at end of file
diff --git a/src/esp32c3.zig b/src/esp32c3.zig
new file mode 100644
index 0000000..77bed3f
--- /dev/null
+++ b/src/esp32c3.zig
@@ -0,0 +1,37956 @@
+// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz
+// commit: 62e33d0e2175e4c1621e1dbf9f6ac3ec18f6ba38
+//
+// vendor: ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
+// device: ESP32-C3
+// cpu: RV32IMC
+
+pub const registers = struct {
+    /// AES (Advanced Encryption Standard) Accelerator
+    pub const AES = struct {
+        pub const base_address = 0x6003a000;
+
+        /// address: 0x6003a000
+        /// Key material key_0 configure register
+        pub const KEY_0 = @intToPtr(*volatile u32, base_address + 0x0);
+
+        /// address: 0x6003a004
+        /// Key material key_1 configure register
+        pub const KEY_1 = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x6003a008
+        /// Key material key_2 configure register
+        pub const KEY_2 = @intToPtr(*volatile u32, base_address + 0x8);
+
+        /// address: 0x6003a00c
+        /// Key material key_3 configure register
+        pub const KEY_3 = @intToPtr(*volatile u32, base_address + 0xc);
+
+        /// address: 0x6003a010
+        /// Key material key_4 configure register
+        pub const KEY_4 = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x6003a014
+        /// Key material key_5 configure register
+        pub const KEY_5 = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x6003a018
+        /// Key material key_6 configure register
+        pub const KEY_6 = @intToPtr(*volatile u32, base_address + 0x18);
+
+        /// address: 0x6003a01c
+        /// Key material key_7 configure register
+        pub const KEY_7 = @intToPtr(*volatile u32, base_address + 0x1c);
+
+        /// address: 0x6003a020
+        /// source text material text_in_0 configure register
+        pub const TEXT_IN_0 = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x6003a024
+        /// source text material text_in_1 configure register
+        pub const TEXT_IN_1 = @intToPtr(*volatile u32, base_address + 0x24);
+
+        /// address: 0x6003a028
+        /// source text material text_in_2 configure register
+        pub const TEXT_IN_2 = @intToPtr(*volatile u32, base_address + 0x28);
+
+        /// address: 0x6003a02c
+        /// source text material text_in_3 configure register
+        pub const TEXT_IN_3 = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x6003a030
+        /// result text material text_out_0 configure register
+        pub const TEXT_OUT_0 = @intToPtr(*volatile u32, base_address + 0x30);
+
+        /// address: 0x6003a034
+        /// result text material text_out_1 configure register
+        pub const TEXT_OUT_1 = @intToPtr(*volatile u32, base_address + 0x34);
+
+        /// address: 0x6003a038
+        /// result text material text_out_2 configure register
+        pub const TEXT_OUT_2 = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x6003a03c
+        /// result text material text_out_3 configure register
+        pub const TEXT_OUT_3 = @intToPtr(*volatile u32, base_address + 0x3c);
+
+        /// address: 0x6003a040
+        /// AES Mode register
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x40);
+
+        /// address: 0x6003a044
+        /// AES Endian configure register
+        pub const ENDIAN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44);
+
+        /// address: 0x6003a048
+        /// AES trigger register
+        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48);
+
+        /// address: 0x6003a04c
+        /// AES state register
+        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x4c);
+
+        /// address: 0x6003a050
+        /// The memory that stores initialization vector
+        pub const IV_MEM = @intToPtr(*volatile [16]u8, base_address + 0x50);
+
+        /// address: 0x6003a060
+        /// The memory that stores GCM hash subkey
+        pub const H_MEM = @intToPtr(*volatile [16]u8, base_address + 0x60);
+
+        /// address: 0x6003a070
+        /// The memory that stores J0
+        pub const J0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x70);
+
+        /// address: 0x6003a080
+        /// The memory that stores T0
+        pub const T0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x80);
+
+        /// address: 0x6003a090
+        /// DMA-AES working mode register
+        pub const DMA_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x90);
+
+        /// address: 0x6003a094
+        /// AES cipher block mode register
+        pub const BLOCK_MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x94);
+
+        /// address: 0x6003a098
+        /// AES block number register
+        pub const BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0x98);
+
+        /// address: 0x6003a09c
+        /// Standard incrementing function configure register
+        pub const INC_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x9c);
+
+        /// address: 0x6003a0a0
+        /// Additional Authential Data block number register
+        pub const AAD_BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0xa0);
+
+        /// address: 0x6003a0a4
+        /// AES remainder bit number register
+        pub const REMAINDER_BIT_NUM = @intToPtr(*volatile MmioInt(32, u7), base_address + 0xa4);
+
+        /// address: 0x6003a0a8
+        /// AES continue register
+        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa8);
+
+        /// address: 0x6003a0ac
+        /// AES Interrupt clear register
+        pub const INT_CLEAR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xac);
+
+        /// address: 0x6003a0b0
+        /// AES Interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb0);
+
+        /// address: 0x6003a0b4
+        /// AES version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xb4);
+
+        /// address: 0x6003a0b8
+        /// AES-DMA exit config
+        pub const DMA_EXIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb8);
+    };
+
+    /// Advanced Peripheral Bus Controller
+    pub const APB_CTRL = struct {
+        pub const base_address = 0x60026000;
+
+        /// address: 0x60026000
+        /// APB_CTRL_SYSCLK_CONF_REG
+        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_pre_div_cnt
+            PRE_DIV_CNT: u10,
+            /// reg_clk_320m_en
+            CLK_320M_EN: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            /// reg_rst_tick_cnt
+            RST_TICK_CNT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60026004
+        /// APB_CTRL_TICK_CONF_REG
+        pub const TICK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_xtal_tick_num
+            XTAL_TICK_NUM: u8,
+            /// reg_ck8m_tick_num
+            CK8M_TICK_NUM: u8,
+            /// reg_tick_enable
+            TICK_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60026008
+        /// APB_CTRL_CLK_OUT_EN_REG
+        pub const CLK_OUT_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_clk20_oen
+            CLK20_OEN: u1,
+            /// reg_clk22_oen
+            CLK22_OEN: u1,
+            /// reg_clk44_oen
+            CLK44_OEN: u1,
+            /// reg_clk_bb_oen
+            CLK_BB_OEN: u1,
+            /// reg_clk80_oen
+            CLK80_OEN: u1,
+            /// reg_clk160_oen
+            CLK160_OEN: u1,
+            /// reg_clk_320m_oen
+            CLK_320M_OEN: u1,
+            /// reg_clk_adc_inf_oen
+            CLK_ADC_INF_OEN: u1,
+            /// reg_clk_dac_cpu_oen
+            CLK_DAC_CPU_OEN: u1,
+            /// reg_clk40x_bb_oen
+            CLK40X_BB_OEN: u1,
+            /// reg_clk_xtal_oen
+            CLK_XTAL_OEN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002600c
+        /// APB_CTRL_WIFI_BB_CFG_REG
+        pub const WIFI_BB_CFG = @intToPtr(*volatile u32, base_address + 0xc);
+
+        /// address: 0x60026010
+        /// APB_CTRL_WIFI_BB_CFG_2_REG
+        pub const WIFI_BB_CFG_2 = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x60026014
+        /// APB_CTRL_WIFI_CLK_EN_REG
+        pub const WIFI_CLK_EN = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x60026018
+        /// APB_CTRL_WIFI_RST_EN_REG
+        pub const WIFI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wifi_rst
+            WIFI_RST: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002601c
+        /// APB_CTRL_HOST_INF_SEL_REG
+        pub const HOST_INF_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_io_swap
+            PERI_IO_SWAP: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60026020
+        /// APB_CTRL_EXT_MEM_PMS_LOCK_REG
+        pub const EXT_MEM_PMS_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
+
+        /// address: 0x60026028
+        /// APB_CTRL_FLASH_ACE0_ATTR_REG
+        pub const FLASH_ACE0_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x28);
+
+        /// address: 0x6002602c
+        /// APB_CTRL_FLASH_ACE1_ATTR_REG
+        pub const FLASH_ACE1_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x2c);
+
+        /// address: 0x60026030
+        /// APB_CTRL_FLASH_ACE2_ATTR_REG
+        pub const FLASH_ACE2_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x30);
+
+        /// address: 0x60026034
+        /// APB_CTRL_FLASH_ACE3_ATTR_REG
+        pub const FLASH_ACE3_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x34);
+
+        /// address: 0x60026038
+        /// APB_CTRL_FLASH_ACE0_ADDR_REG
+        pub const FLASH_ACE0_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace0_addr_s
+            S: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6002603c
+        /// APB_CTRL_FLASH_ACE1_ADDR_REG
+        pub const FLASH_ACE1_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace1_addr_s
+            S: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x60026040
+        /// APB_CTRL_FLASH_ACE2_ADDR_REG
+        pub const FLASH_ACE2_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace2_addr_s
+            S: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x60026044
+        /// APB_CTRL_FLASH_ACE3_ADDR_REG
+        pub const FLASH_ACE3_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace3_addr_s
+            S: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60026048
+        /// APB_CTRL_FLASH_ACE0_SIZE_REG
+        pub const FLASH_ACE0_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x48);
+
+        /// address: 0x6002604c
+        /// APB_CTRL_FLASH_ACE1_SIZE_REG
+        pub const FLASH_ACE1_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x4c);
+
+        /// address: 0x60026050
+        /// APB_CTRL_FLASH_ACE2_SIZE_REG
+        pub const FLASH_ACE2_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50);
+
+        /// address: 0x60026054
+        /// APB_CTRL_FLASH_ACE3_SIZE_REG
+        pub const FLASH_ACE3_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x54);
+
+        /// address: 0x60026088
+        /// APB_CTRL_SPI_MEM_PMS_CTRL_REG
+        pub const SPI_MEM_PMS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_spi_mem_reject_int
+            SPI_MEM_REJECT_INT: u1,
+            /// reg_spi_mem_reject_clr
+            SPI_MEM_REJECT_CLR: u1,
+            /// reg_spi_mem_reject_cde
+            SPI_MEM_REJECT_CDE: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6002608c
+        /// APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+        pub const SPI_MEM_REJECT_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x60026090
+        /// APB_CTRL_SDIO_CTRL_REG
+        pub const SDIO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sdio_win_access_en
+            SDIO_WIN_ACCESS_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60026094
+        /// APB_CTRL_REDCY_SIG0_REG
+        pub const REDCY_SIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redcy_sig0
+            REDCY_SIG0: u31,
+            /// reg_redcy_andor
+            REDCY_ANDOR: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x60026098
+        /// APB_CTRL_REDCY_SIG1_REG
+        pub const REDCY_SIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redcy_sig1
+            REDCY_SIG1: u31,
+            /// reg_redcy_nandor
+            REDCY_NANDOR: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6002609c
+        /// APB_CTRL_FRONT_END_MEM_PD_REG
+        pub const FRONT_END_MEM_PD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_agc_mem_force_pu
+            AGC_MEM_FORCE_PU: u1,
+            /// reg_agc_mem_force_pd
+            AGC_MEM_FORCE_PD: u1,
+            /// reg_pbus_mem_force_pu
+            PBUS_MEM_FORCE_PU: u1,
+            /// reg_pbus_mem_force_pd
+            PBUS_MEM_FORCE_PD: u1,
+            /// reg_dc_mem_force_pu
+            DC_MEM_FORCE_PU: u1,
+            /// reg_dc_mem_force_pd
+            DC_MEM_FORCE_PD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600260a0
+        /// APB_CTRL_RETENTION_CTRL_REG
+        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_retention_link_addr
+            RETENTION_LINK_ADDR: u27,
+            /// reg_nobypass_cpu_iso_rst
+            NOBYPASS_CPU_ISO_RST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600260a4
+        /// APB_CTRL_CLKGATE_FORCE_ON_REG
+        pub const CLKGATE_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_clkgate_force_on
+            ROM_CLKGATE_FORCE_ON: u2,
+            /// reg_sram_clkgate_force_on
+            SRAM_CLKGATE_FORCE_ON: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600260a8
+        /// APB_CTRL_MEM_POWER_DOWN_REG
+        pub const MEM_POWER_DOWN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_power_down
+            ROM_POWER_DOWN: u2,
+            /// reg_sram_power_down
+            SRAM_POWER_DOWN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600260ac
+        /// APB_CTRL_MEM_POWER_UP_REG
+        pub const MEM_POWER_UP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_power_up
+            ROM_POWER_UP: u2,
+            /// reg_sram_power_up
+            SRAM_POWER_UP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600260b0
+        /// APB_CTRL_RND_DATA_REG
+        pub const RND_DATA = @intToPtr(*volatile u32, base_address + 0xb0);
+
+        /// address: 0x600260b4
+        /// APB_CTRL_PERI_BACKUP_CONFIG_REG
+        pub const PERI_BACKUP_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_peri_backup_flow_err
+            PERI_BACKUP_FLOW_ERR: u2,
+            reserved1: u1,
+            /// reg_peri_backup_burst_limit
+            PERI_BACKUP_BURST_LIMIT: u5,
+            /// reg_peri_backup_tout_thres
+            PERI_BACKUP_TOUT_THRES: u10,
+            /// reg_peri_backup_size
+            PERI_BACKUP_SIZE: u10,
+            /// reg_peri_backup_start
+            PERI_BACKUP_START: u1,
+            /// reg_peri_backup_to_mem
+            PERI_BACKUP_TO_MEM: u1,
+            /// reg_peri_backup_ena
+            PERI_BACKUP_ENA: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600260b8
+        /// APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+        pub const PERI_BACKUP_APB_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_backup_apb_start_addr
+            BACKUP_APB_START_ADDR: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600260bc
+        /// APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+        pub const PERI_BACKUP_MEM_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_backup_mem_start_addr
+            BACKUP_MEM_START_ADDR: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600260c0
+        /// APB_CTRL_PERI_BACKUP_INT_RAW_REG
+        pub const PERI_BACKUP_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_raw
+            PERI_BACKUP_DONE_INT_RAW: u1,
+            /// reg_peri_backup_err_int_raw
+            PERI_BACKUP_ERR_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600260c4
+        /// APB_CTRL_PERI_BACKUP_INT_ST_REG
+        pub const PERI_BACKUP_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_st
+            PERI_BACKUP_DONE_INT_ST: u1,
+            /// reg_peri_backup_err_int_st
+            PERI_BACKUP_ERR_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600260c8
+        /// APB_CTRL_PERI_BACKUP_INT_ENA_REG
+        pub const PERI_BACKUP_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_ena
+            PERI_BACKUP_DONE_INT_ENA: u1,
+            /// reg_peri_backup_err_int_ena
+            PERI_BACKUP_ERR_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600260d0
+        /// APB_CTRL_PERI_BACKUP_INT_CLR_REG
+        pub const PERI_BACKUP_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_clr
+            PERI_BACKUP_DONE_INT_CLR: u1,
+            /// reg_peri_backup_err_int_clr
+            PERI_BACKUP_ERR_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600263fc
+        /// APB_CTRL_DATE_REG
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x3fc);
+    };
+
+    /// Successive Approximation Register Analog to Digital Converter
+    pub const APB_SARADC = struct {
+        pub const base_address = 0x60040000;
+
+        /// address: 0x60040000
+        /// digital saradc configure register
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// select software enable saradc sample
+            SARADC_START_FORCE: u1,
+            /// software enable saradc sample
+            SARADC_START: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// SAR clock gated
+            SARADC_SAR_CLK_GATED: u1,
+            /// SAR clock divider
+            SARADC_SAR_CLK_DIV: u8,
+            /// 0 ~ 15 means length 1 ~ 16
+            SARADC_SAR_PATT_LEN: u3,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// clear the pointer of pattern table for DIG ADC1 CTRL
+            SARADC_SAR_PATT_P_CLEAR: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// force option to xpd sar blocks
+            SARADC_XPD_SAR_FORCE: u2,
+            reserved12: u1,
+            /// wait arbit signal stable after sar_done
+            SARADC_WAIT_ARB_CYCLE: u2,
+        }), base_address + 0x0);
+
+        /// address: 0x60040004
+        /// digital saradc configure register
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable max meas num
+            SARADC_MEAS_NUM_LIMIT: u1,
+            /// max conversion number
+            SARADC_MAX_MEAS_NUM: u8,
+            /// 1: data to DIG ADC1 CTRL is inverted, otherwise not
+            SARADC_SAR1_INV: u1,
+            /// 1: data to DIG ADC2 CTRL is inverted, otherwise not
+            SARADC_SAR2_INV: u1,
+            reserved0: u1,
+            /// to set saradc timer target
+            SARADC_TIMER_TARGET: u12,
+            /// to enable saradc timer trigger
+            SARADC_TIMER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60040008
+        /// digital saradc configure register
+        pub const FILTER_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// Factor of saradc filter1
+            APB_SARADC_FILTER_FACTOR1: u3,
+            /// Factor of saradc filter0
+            APB_SARADC_FILTER_FACTOR0: u3,
+        }), base_address + 0x8);
+
+        /// address: 0x6004000c
+        /// digital saradc configure register
+        pub const FSM_WAIT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc_xpd_wait
+            SARADC_XPD_WAIT: u8,
+            /// saradc_rstb_wait
+            SARADC_RSTB_WAIT: u8,
+            /// saradc_standby_wait
+            SARADC_STANDBY_WAIT: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60040010
+        /// digital saradc configure register
+        pub const SAR1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc1 status about data and channel
+            SARADC_SAR1_STATUS: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60040014
+        /// digital saradc configure register
+        pub const SAR2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc2 status about data and channel
+            SARADC_SAR2_STATUS: u32,
+        }), base_address + 0x14);
+
+        /// address: 0x60040018
+        /// digital saradc configure register
+        pub const SAR_PATT_TAB1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// item 0 ~ 3 for pattern table 1 (each item one byte)
+            SARADC_SAR_PATT_TAB1: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6004001c
+        /// digital saradc configure register
+        pub const SAR_PATT_TAB2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Item 4 ~ 7 for pattern table 1 (each item one byte)
+            SARADC_SAR_PATT_TAB2: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60040020
+        /// digital saradc configure register
+        pub const ONETIME_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// configure onetime atten
+            SARADC_ONETIME_ATTEN: u2,
+            /// configure onetime channel
+            SARADC_ONETIME_CHANNEL: u4,
+            /// trigger adc onetime sample
+            SARADC_ONETIME_START: u1,
+            /// enable adc2 onetime sample
+            SARADC2_ONETIME_SAMPLE: u1,
+            /// enable adc1 onetime sample
+            SARADC1_ONETIME_SAMPLE: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60040024
+        /// digital saradc configure register
+        pub const ARB_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// adc2 arbiter force to enableapb controller
+            ADC_ARB_APB_FORCE: u1,
+            /// adc2 arbiter force to enable rtc controller
+            ADC_ARB_RTC_FORCE: u1,
+            /// adc2 arbiter force to enable wifi controller
+            ADC_ARB_WIFI_FORCE: u1,
+            /// adc2 arbiter force grant
+            ADC_ARB_GRANT_FORCE: u1,
+            /// Set adc2 arbiterapb priority
+            ADC_ARB_APB_PRIORITY: u2,
+            /// Set adc2 arbiter rtc priority
+            ADC_ARB_RTC_PRIORITY: u2,
+            /// Set adc2 arbiter wifi priority
+            ADC_ARB_WIFI_PRIORITY: u2,
+            /// adc2 arbiter uses fixed priority
+            ADC_ARB_FIX_PRIORITY: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60040028
+        /// digital saradc configure register
+        pub const FILTER_CTRL0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// configure filter1 to adc channel
+            APB_SARADC_FILTER_CHANNEL1: u4,
+            /// configure filter0 to adc channel
+            APB_SARADC_FILTER_CHANNEL0: u4,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// enable apb_adc1_filter
+            APB_SARADC_FILTER_RESET: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6004002c
+        /// digital saradc configure register
+        pub const SAR1DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc1 data
+            APB_SARADC1_DATA: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60040030
+        /// digital saradc configure register
+        pub const SAR2DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc2 data
+            APB_SARADC2_DATA: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60040034
+        /// digital saradc configure register
+        pub const THRES0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure thres0 to adc channel
+            APB_SARADC_THRES0_CHANNEL: u4,
+            reserved0: u1,
+            /// saradc thres0 monitor thres
+            APB_SARADC_THRES0_HIGH: u13,
+            /// saradc thres0 monitor thres
+            APB_SARADC_THRES0_LOW: u13,
+            padding0: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60040038
+        /// digital saradc configure register
+        pub const THRES1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure thres1 to adc channel
+            APB_SARADC_THRES1_CHANNEL: u4,
+            reserved0: u1,
+            /// saradc thres1 monitor thres
+            APB_SARADC_THRES1_HIGH: u13,
+            /// saradc thres1 monitor thres
+            APB_SARADC_THRES1_LOW: u13,
+            padding0: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6004003c
+        /// digital saradc configure register
+        pub const THRES_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// enable thres to all channel
+            APB_SARADC_THRES_ALL_EN: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// enable thres1
+            APB_SARADC_THRES1_EN: u1,
+            /// enable thres0
+            APB_SARADC_THRES0_EN: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60040040
+        /// digital saradc int register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt enable
+            APB_SARADC_THRES1_LOW_INT_ENA: u1,
+            /// saradc thres0 low interrupt enable
+            APB_SARADC_THRES0_LOW_INT_ENA: u1,
+            /// saradc thres1 high interrupt enable
+            APB_SARADC_THRES1_HIGH_INT_ENA: u1,
+            /// saradc thres0 high interrupt enable
+            APB_SARADC_THRES0_HIGH_INT_ENA: u1,
+            /// saradc2 done interrupt enable
+            APB_SARADC2_DONE_INT_ENA: u1,
+            /// saradc1 done interrupt enable
+            APB_SARADC1_DONE_INT_ENA: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60040044
+        /// digital saradc int register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt raw
+            APB_SARADC_THRES1_LOW_INT_RAW: u1,
+            /// saradc thres0 low interrupt raw
+            APB_SARADC_THRES0_LOW_INT_RAW: u1,
+            /// saradc thres1 high interrupt raw
+            APB_SARADC_THRES1_HIGH_INT_RAW: u1,
+            /// saradc thres0 high interrupt raw
+            APB_SARADC_THRES0_HIGH_INT_RAW: u1,
+            /// saradc2 done interrupt raw
+            APB_SARADC2_DONE_INT_RAW: u1,
+            /// saradc1 done interrupt raw
+            APB_SARADC1_DONE_INT_RAW: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60040048
+        /// digital saradc int register
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt state
+            APB_SARADC_THRES1_LOW_INT_ST: u1,
+            /// saradc thres0 low interrupt state
+            APB_SARADC_THRES0_LOW_INT_ST: u1,
+            /// saradc thres1 high interrupt state
+            APB_SARADC_THRES1_HIGH_INT_ST: u1,
+            /// saradc thres0 high interrupt state
+            APB_SARADC_THRES0_HIGH_INT_ST: u1,
+            /// saradc2 done interrupt state
+            APB_SARADC2_DONE_INT_ST: u1,
+            /// saradc1 done interrupt state
+            APB_SARADC1_DONE_INT_ST: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6004004c
+        /// digital saradc int register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt clear
+            APB_SARADC_THRES1_LOW_INT_CLR: u1,
+            /// saradc thres0 low interrupt clear
+            APB_SARADC_THRES0_LOW_INT_CLR: u1,
+            /// saradc thres1 high interrupt clear
+            APB_SARADC_THRES1_HIGH_INT_CLR: u1,
+            /// saradc thres0 high interrupt clear
+            APB_SARADC_THRES0_HIGH_INT_CLR: u1,
+            /// saradc2 done interrupt clear
+            APB_SARADC2_DONE_INT_CLR: u1,
+            /// saradc1 done interrupt clear
+            APB_SARADC1_DONE_INT_CLR: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60040050
+        /// digital saradc configure register
+        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the dma_in_suc_eof gen when sample cnt = spi_eof_num
+            APB_ADC_EOF_NUM: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// reset_apb_adc_state
+            APB_ADC_RESET_FSM: u1,
+            /// enable apb_adc use spi_dma
+            APB_ADC_TRANS: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60040054
+        /// digital saradc configure register
+        pub const CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S clock divider value
+            CLKM_DIV_NUM: u8,
+            /// Fractional clock divider numerator value
+            CLKM_DIV_B: u6,
+            /// Fractional clock divider denominator value
+            CLKM_DIV_A: u6,
+            /// reg clk en
+            CLK_EN: u1,
+            /// Set this bit to enable clk_apll
+            CLK_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60040058
+        /// digital tsens configure register
+        pub const APB_TSENS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// temperature sensor data out
+            TSENS_OUT: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// invert temperature sensor data
+            TSENS_IN_INV: u1,
+            /// temperature sensor clock divider
+            TSENS_CLK_DIV: u8,
+            /// temperature sensor power up
+            TSENS_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6004005c
+        /// digital tsens configure register
+        pub const TSENS_CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the time that power up tsens need wait
+            TSENS_XPD_WAIT: u12,
+            /// force power up tsens
+            TSENS_XPD_FORCE: u2,
+            /// inv tsens clk
+            TSENS_CLK_INV: u1,
+            /// tsens clk select
+            TSENS_CLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60040060
+        /// digital saradc configure register
+        pub const CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc cali factor
+            APB_SARADC_CALI_CFG: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600403fc
+        /// version
+        pub const CTRL_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// version
+            DATE: u32,
+        }), base_address + 0x3fc);
+    };
+
+    /// Debug Assist
+    pub const ASSIST_DEBUG = struct {
+        pub const base_address = 0x600ce000;
+
+        /// address: 0x600ce000
+        /// ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+        pub const C0RE_0_MONTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_ena
+            CORE_0_AREA_DRAM0_0_RD_ENA: u1,
+            /// reg_core_0_area_dram0_0_wr_ena
+            CORE_0_AREA_DRAM0_0_WR_ENA: u1,
+            /// reg_core_0_area_dram0_1_rd_ena
+            CORE_0_AREA_DRAM0_1_RD_ENA: u1,
+            /// reg_core_0_area_dram0_1_wr_ena
+            CORE_0_AREA_DRAM0_1_WR_ENA: u1,
+            /// reg_core_0_area_pif_0_rd_ena
+            CORE_0_AREA_PIF_0_RD_ENA: u1,
+            /// reg_core_0_area_pif_0_wr_ena
+            CORE_0_AREA_PIF_0_WR_ENA: u1,
+            /// reg_core_0_area_pif_1_rd_ena
+            CORE_0_AREA_PIF_1_RD_ENA: u1,
+            /// reg_core_0_area_pif_1_wr_ena
+            CORE_0_AREA_PIF_1_WR_ENA: u1,
+            /// reg_core_0_sp_spill_min_ena
+            CORE_0_SP_SPILL_MIN_ENA: u1,
+            /// reg_core_0_sp_spill_max_ena
+            CORE_0_SP_SPILL_MAX_ENA: u1,
+            /// reg_core_0_iram0_exception_monitor_ena
+            CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
+            /// reg_core_0_dram0_exception_monitor_ena
+            CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600ce004
+        /// ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+        pub const CORE_0_INTR_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_raw
+            CORE_0_AREA_DRAM0_0_RD_RAW: u1,
+            /// reg_core_0_area_dram0_0_wr_raw
+            CORE_0_AREA_DRAM0_0_WR_RAW: u1,
+            /// reg_core_0_area_dram0_1_rd_raw
+            CORE_0_AREA_DRAM0_1_RD_RAW: u1,
+            /// reg_core_0_area_dram0_1_wr_raw
+            CORE_0_AREA_DRAM0_1_WR_RAW: u1,
+            /// reg_core_0_area_pif_0_rd_raw
+            CORE_0_AREA_PIF_0_RD_RAW: u1,
+            /// reg_core_0_area_pif_0_wr_raw
+            CORE_0_AREA_PIF_0_WR_RAW: u1,
+            /// reg_core_0_area_pif_1_rd_raw
+            CORE_0_AREA_PIF_1_RD_RAW: u1,
+            /// reg_core_0_area_pif_1_wr_raw
+            CORE_0_AREA_PIF_1_WR_RAW: u1,
+            /// reg_core_0_sp_spill_min_raw
+            CORE_0_SP_SPILL_MIN_RAW: u1,
+            /// reg_core_0_sp_spill_max_raw
+            CORE_0_SP_SPILL_MAX_RAW: u1,
+            /// reg_core_0_iram0_exception_monitor_raw
+            CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
+            /// reg_core_0_dram0_exception_monitor_raw
+            CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600ce008
+        /// ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+        pub const CORE_0_INTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_intr_ena
+            CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_0_wr_intr_ena
+            CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_1_rd_intr_ena
+            CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_1_wr_intr_ena
+            CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
+            /// reg_core_0_area_pif_0_rd_intr_ena
+            CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
+            /// reg_core_0_area_pif_0_wr_intr_ena
+            CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
+            /// reg_core_0_area_pif_1_rd_intr_ena
+            CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
+            /// reg_core_0_area_pif_1_wr_intr_ena
+            CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
+            /// reg_core_0_sp_spill_min_intr_ena
+            CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
+            /// reg_core_0_sp_spill_max_intr_ena
+            CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
+            /// reg_core_0_iram0_exception_monitor_ena
+            CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
+            /// reg_core_0_dram0_exception_monitor_ena
+            CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600ce00c
+        /// ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+        pub const CORE_0_INTR_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_clr
+            CORE_0_AREA_DRAM0_0_RD_CLR: u1,
+            /// reg_core_0_area_dram0_0_wr_clr
+            CORE_0_AREA_DRAM0_0_WR_CLR: u1,
+            /// reg_core_0_area_dram0_1_rd_clr
+            CORE_0_AREA_DRAM0_1_RD_CLR: u1,
+            /// reg_core_0_area_dram0_1_wr_clr
+            CORE_0_AREA_DRAM0_1_WR_CLR: u1,
+            /// reg_core_0_area_pif_0_rd_clr
+            CORE_0_AREA_PIF_0_RD_CLR: u1,
+            /// reg_core_0_area_pif_0_wr_clr
+            CORE_0_AREA_PIF_0_WR_CLR: u1,
+            /// reg_core_0_area_pif_1_rd_clr
+            CORE_0_AREA_PIF_1_RD_CLR: u1,
+            /// reg_core_0_area_pif_1_wr_clr
+            CORE_0_AREA_PIF_1_WR_CLR: u1,
+            /// reg_core_0_sp_spill_min_clr
+            CORE_0_SP_SPILL_MIN_CLR: u1,
+            /// reg_core_0_sp_spill_max_clr
+            CORE_0_SP_SPILL_MAX_CLR: u1,
+            /// reg_core_0_iram0_exception_monitor_clr
+            CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
+            /// reg_core_0_dram0_exception_monitor_clr
+            CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600ce010
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+        pub const CORE_0_AREA_DRAM0_0_MIN = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x600ce014
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+        pub const CORE_0_AREA_DRAM0_0_MAX = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x600ce018
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+        pub const CORE_0_AREA_DRAM0_1_MIN = @intToPtr(*volatile u32, base_address + 0x18);
+
+        /// address: 0x600ce01c
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+        pub const CORE_0_AREA_DRAM0_1_MAX = @intToPtr(*volatile u32, base_address + 0x1c);
+
+        /// address: 0x600ce020
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+        pub const CORE_0_AREA_PIF_0_MIN = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x600ce024
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+        pub const CORE_0_AREA_PIF_0_MAX = @intToPtr(*volatile u32, base_address + 0x24);
+
+        /// address: 0x600ce028
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+        pub const CORE_0_AREA_PIF_1_MIN = @intToPtr(*volatile u32, base_address + 0x28);
+
+        /// address: 0x600ce02c
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+        pub const CORE_0_AREA_PIF_1_MAX = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x600ce030
+        /// ASSIST_DEBUG_CORE_0_AREA_PC_REG
+        pub const CORE_0_AREA_PC = @intToPtr(*volatile u32, base_address + 0x30);
+
+        /// address: 0x600ce034
+        /// ASSIST_DEBUG_CORE_0_AREA_SP_REG
+        pub const CORE_0_AREA_SP = @intToPtr(*volatile u32, base_address + 0x34);
+
+        /// address: 0x600ce038
+        /// ASSIST_DEBUG_CORE_0_SP_MIN_REG
+        pub const CORE_0_SP_MIN = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x600ce03c
+        /// ASSIST_DEBUG_CORE_0_SP_MAX_REG
+        pub const CORE_0_SP_MAX = @intToPtr(*volatile u32, base_address + 0x3c);
+
+        /// address: 0x600ce040
+        /// ASSIST_DEBUG_CORE_0_SP_PC_REG
+        pub const CORE_0_SP_PC = @intToPtr(*volatile u32, base_address + 0x40);
+
+        /// address: 0x600ce044
+        /// ASSIST_DEBUG_CORE_0_RCD_EN_REG
+        pub const CORE_0_RCD_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_rcd_recorden
+            CORE_0_RCD_RECORDEN: u1,
+            /// reg_core_0_rcd_pdebugen
+            CORE_0_RCD_PDEBUGEN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600ce048
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+        pub const CORE_0_RCD_PDEBUGPC = @intToPtr(*volatile u32, base_address + 0x48);
+
+        /// address: 0x600ce04c
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+        pub const CORE_0_RCD_PDEBUGSP = @intToPtr(*volatile u32, base_address + 0x4c);
+
+        /// address: 0x600ce050
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_iram0_recording_addr_0
+            CORE_0_IRAM0_RECORDING_ADDR_0: u24,
+            /// reg_core_0_iram0_recording_wr_0
+            CORE_0_IRAM0_RECORDING_WR_0: u1,
+            /// reg_core_0_iram0_recording_loadstore_0
+            CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600ce054
+        /// ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_iram0_recording_addr_1
+            CORE_0_IRAM0_RECORDING_ADDR_1: u24,
+            /// reg_core_0_iram0_recording_wr_1
+            CORE_0_IRAM0_RECORDING_WR_1: u1,
+            /// reg_core_0_iram0_recording_loadstore_1
+            CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600ce058
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_addr_0
+            CORE_0_DRAM0_RECORDING_ADDR_0: u24,
+            /// reg_core_0_dram0_recording_wr_0
+            CORE_0_DRAM0_RECORDING_WR_0: u1,
+            /// reg_core_0_dram0_recording_byteen_0
+            CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600ce05c
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_pc_0
+            CORE_0_DRAM0_RECORDING_PC_0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x600ce060
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_addr_1
+            CORE_0_DRAM0_RECORDING_ADDR_1: u24,
+            /// reg_core_0_dram0_recording_wr_1
+            CORE_0_DRAM0_RECORDING_WR_1: u1,
+            /// reg_core_0_dram0_recording_byteen_1
+            CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600ce064
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_pc_1
+            CORE_0_DRAM0_RECORDING_PC_1: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x600ce068
+        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_x_iram0_dram0_limit_cycle_0
+            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600ce06c
+        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_x_iram0_dram0_limit_cycle_1
+            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600ce070
+        /// ASSIST_DEBUG_LOG_SETTING
+        pub const LOG_SETTING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_ena
+            LOG_ENA: u3,
+            /// reg_log_mode
+            LOG_MODE: u4,
+            /// reg_log_mem_loop_enable
+            LOG_MEM_LOOP_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600ce074
+        /// ASSIST_DEBUG_LOG_DATA_0_REG
+        pub const LOG_DATA_0 = @intToPtr(*volatile u32, base_address + 0x74);
+
+        /// address: 0x600ce078
+        /// ASSIST_DEBUG_LOG_DATA_MASK_REG
+        pub const LOG_DATA_MASK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_data_size
+            LOG_DATA_SIZE: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600ce07c
+        /// ASSIST_DEBUG_LOG_MIN_REG
+        pub const LOG_MIN = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x600ce080
+        /// ASSIST_DEBUG_LOG_MAX_REG
+        pub const LOG_MAX = @intToPtr(*volatile u32, base_address + 0x80);
+
+        /// address: 0x600ce084
+        /// ASSIST_DEBUG_LOG_MEM_START_REG
+        pub const LOG_MEM_START = @intToPtr(*volatile u32, base_address + 0x84);
+
+        /// address: 0x600ce088
+        /// ASSIST_DEBUG_LOG_MEM_END_REG
+        pub const LOG_MEM_END = @intToPtr(*volatile u32, base_address + 0x88);
+
+        /// address: 0x600ce08c
+        /// ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+        pub const LOG_MEM_WRITING_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x600ce090
+        /// ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+        pub const LOG_MEM_FULL_FLAG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_mem_full_flag
+            LOG_MEM_FULL_FLAG: u1,
+            /// reg_clr_log_mem_full_flag
+            CLR_LOG_MEM_FULL_FLAG: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600ce094
+        /// ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+        pub const C0RE_0_LASTPC_BEFORE_EXCEPTION = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_lastpc_before_exc
+            CORE_0_LASTPC_BEFORE_EXC: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x600ce098
+        /// ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+        pub const C0RE_0_DEBUG_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_debug_mode
+            CORE_0_DEBUG_MODE: u1,
+            /// reg_core_0_debug_module_active
+            CORE_0_DEBUG_MODULE_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600ce1fc
+        /// ASSIST_DEBUG_DATE_REG
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_assist_debug_date
+            ASSIST_DEBUG_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1fc);
+    };
+
+    /// DMA (Direct Memory Access) Controller
+    pub const DMA = struct {
+        pub const base_address = 0x6003f000;
+
+        /// address: 0x6003f000
+        /// DMA_INT_RAW_CH0_REG.
+        pub const INT_RAW_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 0.
+            IN_DONE_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 0. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 0.
+            IN_SUC_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 0.
+            OUT_DONE_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 0.
+            OUT_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 0.
+            IN_DSCR_ERR_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 0.
+            OUT_DSCR_ERR_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 0.
+            IN_DSCR_EMPTY_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 0.
+            OUT_TOTAL_EOF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+            /// overflow.
+            INFIFO_OVF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+            /// underflow.
+            INFIFO_UDF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+            /// overflow.
+            OUTFIFO_OVF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+            /// underflow.
+            OUTFIFO_UDF_CH0_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6003f004
+        /// DMA_INT_ST_CH0_REG.
+        pub const INT_ST_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6003f008
+        /// DMA_INT_ENA_CH0_REG.
+        pub const INT_ENA_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6003f00c
+        /// DMA_INT_CLR_CH0_REG.
+        pub const INT_CLR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6003f010
+        /// DMA_INT_RAW_CH1_REG.
+        pub const INT_RAW_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 1.
+            IN_DONE_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 1. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 1.
+            IN_SUC_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 1.
+            OUT_DONE_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 1.
+            OUT_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 1.
+            IN_DSCR_ERR_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 1.
+            OUT_DSCR_ERR_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 1.
+            IN_DSCR_EMPTY_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 1.
+            OUT_TOTAL_EOF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
+            /// overflow.
+            INFIFO_OVF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
+            /// underflow.
+            INFIFO_UDF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
+            /// overflow.
+            OUTFIFO_OVF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
+            /// underflow.
+            OUTFIFO_UDF_CH1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6003f014
+        /// DMA_INT_ST_CH1_REG.
+        pub const INT_ST_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6003f018
+        /// DMA_INT_ENA_CH1_REG.
+        pub const INT_ENA_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6003f01c
+        /// DMA_INT_CLR_CH1_REG.
+        pub const INT_CLR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6003f020
+        /// DMA_INT_RAW_CH2_REG.
+        pub const INT_RAW_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 2.
+            IN_DONE_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 2. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 2.
+            IN_SUC_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 2.
+            OUT_DONE_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 2.
+            OUT_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 2.
+            IN_DSCR_ERR_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 2.
+            OUT_DSCR_ERR_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 2.
+            IN_DSCR_EMPTY_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 2.
+            OUT_TOTAL_EOF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
+            /// overflow.
+            INFIFO_OVF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
+            /// underflow.
+            INFIFO_UDF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
+            /// overflow.
+            OUTFIFO_OVF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
+            /// underflow.
+            OUTFIFO_UDF_CH2_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6003f024
+        /// DMA_INT_ST_CH2_REG.
+        pub const INT_ST_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6003f028
+        /// DMA_INT_ENA_CH2_REG.
+        pub const INT_ENA_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6003f02c
+        /// DMA_INT_CLR_CH2_REG.
+        pub const INT_CLR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x6003f040
+        /// DMA_AHB_TEST_REG.
+        pub const AHB_TEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved
+            AHB_TESTMODE: u3,
+            reserved0: u1,
+            /// reserved
+            AHB_TESTADDR: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6003f044
+        /// DMA_MISC_CONF_REG.
+        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit, then clear this bit to reset the internal ahb FSM.
+            AHBM_RST_INTER: u1,
+            reserved0: u1,
+            /// Set this bit to disable priority arbitration function.
+            ARB_PRI_DIS: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6003f048
+        /// DMA_DATE_REG.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x48);
+
+        /// address: 0x6003f070
+        /// DMA_IN_CONF0_CH0_REG.
+        pub const IN_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH0: u1,
+            /// reserved
+            IN_LOOP_TEST_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH0: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6003f074
+        /// DMA_IN_CONF1_CH0_REG.
+        pub const IN_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6003f078
+        /// DMA_INFIFO_STATUS_CH0_REG.
+        pub const INFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 0.
+            INFIFO_FULL_CH0: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 0.
+            INFIFO_EMPTY_CH0: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+            INFIFO_CNT_CH0: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH0: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6003f07c
+        /// DMA_IN_POP_CH0_REG.
+        pub const IN_POP_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH0: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6003f080
+        /// DMA_IN_LINK_CH0_REG.
+        pub const IN_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH0: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH0: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH0: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH0: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH0: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x6003f084
+        /// DMA_IN_STATE_CH0_REG.
+        pub const IN_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH0: u18,
+            /// reserved
+            IN_DSCR_STATE_CH0: u2,
+            /// reserved
+            IN_STATE_CH0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x6003f088
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x88);
+
+        /// address: 0x6003f08c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x6003f090
+        /// DMA_IN_DSCR_CH0_REG.
+        pub const IN_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH0: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x6003f094
+        /// DMA_IN_DSCR_BF0_CH0_REG.
+        pub const IN_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH0: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x6003f098
+        /// DMA_IN_DSCR_BF1_CH0_REG.
+        pub const IN_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH0: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6003f09c
+        /// DMA_IN_PRI_CH0_REG.
+        pub const IN_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 0. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x6003f0a0
+        /// DMA_IN_PERI_SEL_CH0_REG.
+        pub const IN_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH0: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x6003f0d0
+        /// DMA_OUT_CONF0_CH0_REG.
+        pub const OUT_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH0: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH0: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH0: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x6003f0d4
+        /// DMA_OUT_CONF1_CH0_REG.
+        pub const OUT_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x6003f0d8
+        /// DMA_OUTFIFO_STATUS_CH0_REG.
+        pub const OUTFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 0.
+            OUTFIFO_FULL_CH0: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 0.
+            OUTFIFO_EMPTY_CH0: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+            OUTFIFO_CNT_CH0: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x6003f0dc
+        /// DMA_OUT_PUSH_CH0_REG.
+        pub const OUT_PUSH_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH0: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x6003f0e0
+        /// DMA_OUT_LINK_CH0_REG.
+        pub const OUT_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH0: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH0: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH0: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH0: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x6003f0e4
+        /// DMA_OUT_STATE_CH0_REG.
+        pub const OUT_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH0: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH0: u2,
+            /// reserved
+            OUT_STATE_CH0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x6003f0e8
+        /// DMA_OUT_EOF_DES_ADDR_CH0_REG.
+        pub const OUT_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xe8);
+
+        /// address: 0x6003f0ec
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xec);
+
+        /// address: 0x6003f0f0
+        /// DMA_OUT_DSCR_CH0_REG.
+        pub const OUT_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH0: u32,
+        }), base_address + 0xf0);
+
+        /// address: 0x6003f0f4
+        /// DMA_OUT_DSCR_BF0_CH0_REG.
+        pub const OUT_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH0: u32,
+        }), base_address + 0xf4);
+
+        /// address: 0x6003f0f8
+        /// DMA_OUT_DSCR_BF1_CH0_REG.
+        pub const OUT_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH0: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x6003f0fc
+        /// DMA_OUT_PRI_CH0_REG.
+        pub const OUT_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 0. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x6003f100
+        /// DMA_OUT_PERI_SEL_CH0_REG.
+        pub const OUT_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH0: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x6003f130
+        /// DMA_IN_CONF0_CH1_REG.
+        pub const IN_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH1: u1,
+            /// reserved
+            IN_LOOP_TEST_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH1: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x6003f134
+        /// DMA_IN_CONF1_CH1_REG.
+        pub const IN_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x6003f138
+        /// DMA_INFIFO_STATUS_CH1_REG.
+        pub const INFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 1.
+            INFIFO_FULL_CH1: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 1.
+            INFIFO_EMPTY_CH1: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+            INFIFO_CNT_CH1: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH1: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x6003f13c
+        /// DMA_IN_POP_CH1_REG.
+        pub const IN_POP_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH1: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x13c);
+
+        /// address: 0x6003f140
+        /// DMA_IN_LINK_CH1_REG.
+        pub const IN_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH1: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH1: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH1: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH1: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH1: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x6003f144
+        /// DMA_IN_STATE_CH1_REG.
+        pub const IN_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH1: u18,
+            /// reserved
+            IN_DSCR_STATE_CH1: u2,
+            /// reserved
+            IN_STATE_CH1: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x6003f148
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x148);
+
+        /// address: 0x6003f14c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x14c);
+
+        /// address: 0x6003f150
+        /// DMA_IN_DSCR_CH1_REG.
+        pub const IN_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH1: u32,
+        }), base_address + 0x150);
+
+        /// address: 0x6003f154
+        /// DMA_IN_DSCR_BF0_CH1_REG.
+        pub const IN_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH1: u32,
+        }), base_address + 0x154);
+
+        /// address: 0x6003f158
+        /// DMA_IN_DSCR_BF1_CH1_REG.
+        pub const IN_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH1: u32,
+        }), base_address + 0x158);
+
+        /// address: 0x6003f15c
+        /// DMA_IN_PRI_CH1_REG.
+        pub const IN_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 1. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x6003f160
+        /// DMA_IN_PERI_SEL_CH1_REG.
+        pub const IN_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 1. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH1: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x6003f190
+        /// DMA_OUT_CONF0_CH1_REG.
+        pub const OUT_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH1: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH1: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH1: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x6003f194
+        /// DMA_OUT_CONF1_CH1_REG.
+        pub const OUT_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x194);
+
+        /// address: 0x6003f198
+        /// DMA_OUTFIFO_STATUS_CH1_REG.
+        pub const OUTFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 1.
+            OUTFIFO_FULL_CH1: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 1.
+            OUTFIFO_EMPTY_CH1: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+            OUTFIFO_CNT_CH1: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x198);
+
+        /// address: 0x6003f19c
+        /// DMA_OUT_PUSH_CH1_REG.
+        pub const OUT_PUSH_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH1: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x19c);
+
+        /// address: 0x6003f1a0
+        /// DMA_OUT_LINK_CH1_REG.
+        pub const OUT_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH1: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH1: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH1: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH1: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1a0);
+
+        /// address: 0x6003f1a4
+        /// DMA_OUT_STATE_CH1_REG.
+        pub const OUT_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH1: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH1: u2,
+            /// reserved
+            OUT_STATE_CH1: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x1a4);
+
+        /// address: 0x6003f1a8
+        /// DMA_OUT_EOF_DES_ADDR_CH1_REG.
+        pub const OUT_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1a8);
+
+        /// address: 0x6003f1ac
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1ac);
+
+        /// address: 0x6003f1b0
+        /// DMA_OUT_DSCR_CH1_REG.
+        pub const OUT_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH1: u32,
+        }), base_address + 0x1b0);
+
+        /// address: 0x6003f1b4
+        /// DMA_OUT_DSCR_BF0_CH1_REG.
+        pub const OUT_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH1: u32,
+        }), base_address + 0x1b4);
+
+        /// address: 0x6003f1b8
+        /// DMA_OUT_DSCR_BF1_CH1_REG.
+        pub const OUT_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH1: u32,
+        }), base_address + 0x1b8);
+
+        /// address: 0x6003f1bc
+        /// DMA_OUT_PRI_CH1_REG.
+        pub const OUT_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 1. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1bc);
+
+        /// address: 0x6003f1c0
+        /// DMA_OUT_PERI_SEL_CH1_REG.
+        pub const OUT_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 1. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH1: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x6003f1f0
+        /// DMA_IN_CONF0_CH2_REG.
+        pub const IN_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH2: u1,
+            /// reserved
+            IN_LOOP_TEST_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH2: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x6003f1f4
+        /// DMA_IN_CONF1_CH2_REG.
+        pub const IN_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x6003f1f8
+        /// DMA_INFIFO_STATUS_CH2_REG.
+        pub const INFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 2.
+            INFIFO_FULL_CH2: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 2.
+            INFIFO_EMPTY_CH2: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+            INFIFO_CNT_CH2: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH2: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1f8);
+
+        /// address: 0x6003f1fc
+        /// DMA_IN_POP_CH2_REG.
+        pub const IN_POP_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH2: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1fc);
+
+        /// address: 0x6003f200
+        /// DMA_IN_LINK_CH2_REG.
+        pub const IN_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH2: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH2: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH2: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH2: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH2: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x200);
+
+        /// address: 0x6003f204
+        /// DMA_IN_STATE_CH2_REG.
+        pub const IN_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH2: u18,
+            /// reserved
+            IN_DSCR_STATE_CH2: u2,
+            /// reserved
+            IN_STATE_CH2: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x204);
+
+        /// address: 0x6003f208
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x208);
+
+        /// address: 0x6003f20c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x20c);
+
+        /// address: 0x6003f210
+        /// DMA_IN_DSCR_CH2_REG.
+        pub const IN_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH2: u32,
+        }), base_address + 0x210);
+
+        /// address: 0x6003f214
+        /// DMA_IN_DSCR_BF0_CH2_REG.
+        pub const IN_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH2: u32,
+        }), base_address + 0x214);
+
+        /// address: 0x6003f218
+        /// DMA_IN_DSCR_BF1_CH2_REG.
+        pub const IN_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH2: u32,
+        }), base_address + 0x218);
+
+        /// address: 0x6003f21c
+        /// DMA_IN_PRI_CH2_REG.
+        pub const IN_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 2. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH2: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x21c);
+
+        /// address: 0x6003f220
+        /// DMA_IN_PERI_SEL_CH2_REG.
+        pub const IN_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 2. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH2: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x220);
+
+        /// address: 0x6003f250
+        /// DMA_OUT_CONF0_CH2_REG.
+        pub const OUT_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH2: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH2: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH2: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x250);
+
+        /// address: 0x6003f254
+        /// DMA_OUT_CONF1_CH2_REG.
+        pub const OUT_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x254);
+
+        /// address: 0x6003f258
+        /// DMA_OUTFIFO_STATUS_CH2_REG.
+        pub const OUTFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 2.
+            OUTFIFO_FULL_CH2: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 2.
+            OUTFIFO_EMPTY_CH2: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+            OUTFIFO_CNT_CH2: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x258);
+
+        /// address: 0x6003f25c
+        /// DMA_OUT_PUSH_CH2_REG.
+        pub const OUT_PUSH_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH2: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x25c);
+
+        /// address: 0x6003f260
+        /// DMA_OUT_LINK_CH2_REG.
+        pub const OUT_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH2: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH2: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH2: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH2: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x260);
+
+        /// address: 0x6003f264
+        /// DMA_OUT_STATE_CH2_REG.
+        pub const OUT_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH2: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH2: u2,
+            /// reserved
+            OUT_STATE_CH2: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x264);
+
+        /// address: 0x6003f268
+        /// DMA_OUT_EOF_DES_ADDR_CH2_REG.
+        pub const OUT_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x268);
+
+        /// address: 0x6003f26c
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x26c);
+
+        /// address: 0x6003f270
+        /// DMA_OUT_DSCR_CH2_REG.
+        pub const OUT_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH2: u32,
+        }), base_address + 0x270);
+
+        /// address: 0x6003f274
+        /// DMA_OUT_DSCR_BF0_CH2_REG.
+        pub const OUT_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH2: u32,
+        }), base_address + 0x274);
+
+        /// address: 0x6003f278
+        /// DMA_OUT_DSCR_BF1_CH2_REG.
+        pub const OUT_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH2: u32,
+        }), base_address + 0x278);
+
+        /// address: 0x6003f27c
+        /// DMA_OUT_PRI_CH2_REG.
+        pub const OUT_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 2. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH2: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x27c);
+
+        /// address: 0x6003f280
+        /// DMA_OUT_PERI_SEL_CH2_REG.
+        pub const OUT_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 2. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH2: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x280);
+    };
+
+    /// Digital Signature
+    pub const DS = struct {
+        pub const base_address = 0x6003d000;
+
+        /// address: 0x6003d000
+        /// memory that stores Y
+        pub const Y_MEM = @intToPtr(*volatile [512]u8, base_address + 0x0);
+
+        /// address: 0x6003d200
+        /// memory that stores M
+        pub const M_MEM = @intToPtr(*volatile [512]u8, base_address + 0x200);
+
+        /// address: 0x6003d400
+        /// memory that stores Rb
+        pub const RB_MEM = @intToPtr(*volatile [512]u8, base_address + 0x400);
+
+        /// address: 0x6003d600
+        /// memory that stores BOX
+        pub const BOX_MEM = @intToPtr(*volatile [48]u8, base_address + 0x600);
+
+        /// address: 0x6003d800
+        /// memory that stores X
+        pub const X_MEM = @intToPtr(*volatile [512]u8, base_address + 0x800);
+
+        /// address: 0x6003da00
+        /// memory that stores Z
+        pub const Z_MEM = @intToPtr(*volatile [512]u8, base_address + 0xa00);
+
+        /// address: 0x6003de00
+        /// DS start control register
+        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe00);
+
+        /// address: 0x6003de04
+        /// DS continue control register
+        pub const SET_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe04);
+
+        /// address: 0x6003de08
+        /// DS finish control register
+        pub const SET_FINISH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe08);
+
+        /// address: 0x6003de0c
+        /// DS query busy register
+        pub const QUERY_BUSY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe0c);
+
+        /// address: 0x6003de10
+        /// DS query key-wrong counter register
+        pub const QUERY_KEY_WRONG = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xe10);
+
+        /// address: 0x6003de14
+        /// DS query check result register
+        pub const QUERY_CHECK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+            MD_ERROR: u1,
+            /// padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+            PADDING_BAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xe14);
+
+        /// address: 0x6003de20
+        /// DS version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xe20);
+    };
+
+    /// eFuse Controller
+    pub const EFUSE = struct {
+        pub const base_address = 0x60008800;
+
+        /// address: 0x60008800
+        /// Register 0 that stores data to be programmed.
+        pub const PGM_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 0th 32-bit data to be programmed.
+            PGM_DATA_0: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60008804
+        /// Register 1 that stores data to be programmed.
+        pub const PGM_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 1st 32-bit data to be programmed.
+            PGM_DATA_1: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60008808
+        /// Register 2 that stores data to be programmed.
+        pub const PGM_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 2nd 32-bit data to be programmed.
+            PGM_DATA_2: u32,
+        }), base_address + 0x8);
+
+        /// address: 0x6000880c
+        /// Register 3 that stores data to be programmed.
+        pub const PGM_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 3rd 32-bit data to be programmed.
+            PGM_DATA_3: u32,
+        }), base_address + 0xc);
+
+        /// address: 0x60008810
+        /// Register 4 that stores data to be programmed.
+        pub const PGM_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 4th 32-bit data to be programmed.
+            PGM_DATA_4: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60008814
+        /// Register 5 that stores data to be programmed.
+        pub const PGM_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 5th 32-bit data to be programmed.
+            PGM_DATA_5: u32,
+        }), base_address + 0x14);
+
+        /// address: 0x60008818
+        /// Register 6 that stores data to be programmed.
+        pub const PGM_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 6th 32-bit data to be programmed.
+            PGM_DATA_6: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6000881c
+        /// Register 7 that stores data to be programmed.
+        pub const PGM_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 7th 32-bit data to be programmed.
+            PGM_DATA_7: u32,
+        }), base_address + 0x1c);
+
+        /// address: 0x60008820
+        /// Register 0 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 0th 32-bit RS code to be programmed.
+            PGM_RS_DATA_0: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60008824
+        /// Register 1 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 1st 32-bit RS code to be programmed.
+            PGM_RS_DATA_1: u32,
+        }), base_address + 0x24);
+
+        /// address: 0x60008828
+        /// Register 2 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 2nd 32-bit RS code to be programmed.
+            PGM_RS_DATA_2: u32,
+        }), base_address + 0x28);
+
+        /// address: 0x6000882c
+        /// BLOCK0 data register 0.
+        pub const RD_WR_DIS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Disable programming of individual eFuses.
+            WR_DIS: u32,
+        }), base_address + 0x2c);
+
+        /// address: 0x60008830
+        /// BLOCK0 data register 1.
+        pub const RD_REPEAT_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to disable reading from BlOCK4-10.
+            RD_DIS: u7,
+            /// Set this bit to disable boot from RTC RAM.
+            DIS_RTC_RAM_BOOT: u1,
+            /// Set this bit to disable Icache.
+            DIS_ICACHE: u1,
+            /// Set this bit to disable function of usb switch to jtag in module of usb device.
+            DIS_USB_JTAG: u1,
+            /// Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3,
+            /// 6, 7).
+            DIS_DOWNLOAD_ICACHE: u1,
+            /// Set this bit to disable usb device.
+            DIS_USB_DEVICE: u1,
+            /// Set this bit to disable the function that forces chip into download mode.
+            DIS_FORCE_DOWNLOAD: u1,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED6: u1,
+            /// Set this bit to disable CAN function.
+            DIS_CAN: u1,
+            /// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+            /// strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+            JTAG_SEL_ENABLE: u1,
+            /// Set these bits to disable JTAG in the soft way (odd number 1 means disable ).
+            /// JTAG can be enabled in HMAC module.
+            SOFT_DIS_JTAG: u3,
+            /// Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+            DIS_PAD_JTAG: u1,
+            /// Set this bit to disable flash encryption when in download boot modes.
+            DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
+            /// Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV,
+            /// stored in eFuse.
+            USB_DREFH: u2,
+            /// Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+            /// stored in eFuse.
+            USB_DREFL: u2,
+            /// Set this bit to exchange USB D+ and D- pins.
+            USB_EXCHG_PINS: u1,
+            /// Set this bit to vdd spi pin function as gpio.
+            VDD_SPI_AS_GPIO: u1,
+            /// Enable btlc gpio.
+            BTLC_GPIO_ENABLE: u2,
+            /// Set this bit to enable power glitch function.
+            POWERGLITCH_EN: u1,
+            /// Sample delay configuration of power glitch.
+            POWER_GLITCH_DSENSE: u2,
+        }), base_address + 0x30);
+
+        /// address: 0x60008834
+        /// BLOCK0 data register 2.
+        pub const RD_REPEAT_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED2: u16,
+            /// Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000.
+            /// 1: 80000. 2: 160000. 3:320000.
+            WDT_DELAY_SEL: u2,
+            /// Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+            /// number of 1: disable.
+            SPI_BOOT_CRYPT_CNT: u3,
+            /// Set this bit to enable revoking first secure boot key.
+            SECURE_BOOT_KEY_REVOKE0: u1,
+            /// Set this bit to enable revoking second secure boot key.
+            SECURE_BOOT_KEY_REVOKE1: u1,
+            /// Set this bit to enable revoking third secure boot key.
+            SECURE_BOOT_KEY_REVOKE2: u1,
+            /// Purpose of Key0.
+            KEY_PURPOSE_0: u4,
+            /// Purpose of Key1.
+            KEY_PURPOSE_1: u4,
+        }), base_address + 0x34);
+
+        /// address: 0x60008838
+        /// BLOCK0 data register 3.
+        pub const RD_REPEAT_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Purpose of Key2.
+            KEY_PURPOSE_2: u4,
+            /// Purpose of Key3.
+            KEY_PURPOSE_3: u4,
+            /// Purpose of Key4.
+            KEY_PURPOSE_4: u4,
+            /// Purpose of Key5.
+            KEY_PURPOSE_5: u4,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED3: u4,
+            /// Set this bit to enable secure boot.
+            SECURE_BOOT_EN: u1,
+            /// Set this bit to enable revoking aggressive secure boot.
+            SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED0: u6,
+            /// Configures flash waiting time after power-up, in unit of ms. If the value is
+            /// less than 15, the waiting time is the configurable value; Otherwise, the waiting
+            /// time is twice the configurable value.
+            FLASH_TPUW: u4,
+        }), base_address + 0x38);
+
+        /// address: 0x6000883c
+        /// BLOCK0 data register 4.
+        pub const RD_REPEAT_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+            DIS_DOWNLOAD_MODE: u1,
+            /// Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+            DIS_LEGACY_SPI_BOOT: u1,
+            /// Selectes the default UART print channel. 0: UART0. 1: UART1.
+            UART_PRINT_CHANNEL: u1,
+            /// Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+            /// use 16to17 byte mode.
+            FLASH_ECC_MODE: u1,
+            /// Set this bit to disable UART download mode through USB.
+            DIS_USB_DOWNLOAD_MODE: u1,
+            /// Set this bit to enable secure UART download mode.
+            ENABLE_SECURITY_DOWNLOAD: u1,
+            /// Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when
+            /// GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+            UART_PRINT_CONTROL: u2,
+            /// GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+            PIN_POWER_SELECTION: u1,
+            /// Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+            FLASH_TYPE: u1,
+            /// Set Flash page size.
+            FLASH_PAGE_SIZE: u2,
+            /// Set 1 to enable ECC for flash boot.
+            FLASH_ECC_EN: u1,
+            /// Set this bit to force ROM code to send a resume command during SPI boot.
+            FORCE_SEND_RESUME: u1,
+            /// Secure version (used by ESP-IDF anti-rollback feature).
+            SECURE_VERSION: u16,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED1: u2,
+        }), base_address + 0x3c);
+
+        /// address: 0x60008840
+        /// BLOCK0 data register 5.
+        pub const RD_REPEAT_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED4: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60008844
+        /// BLOCK1 data register 0.
+        pub const RD_MAC_SPI_SYS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the low 32 bits of MAC address.
+            MAC_0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60008848
+        /// BLOCK1 data register 1.
+        pub const RD_MAC_SPI_SYS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the high 16 bits of MAC address.
+            MAC_1: u16,
+            /// Stores the zeroth part of SPI_PAD_CONF.
+            SPI_PAD_CONF_0: u16,
+        }), base_address + 0x48);
+
+        /// address: 0x6000884c
+        /// BLOCK1 data register 2.
+        pub const RD_MAC_SPI_SYS_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first part of SPI_PAD_CONF.
+            SPI_PAD_CONF_1: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60008850
+        /// BLOCK1 data register 3.
+        pub const RD_MAC_SPI_SYS_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second part of SPI_PAD_CONF.
+            SPI_PAD_CONF_2: u18,
+            /// Stores the fist 14 bits of the zeroth part of system data.
+            SYS_DATA_PART0_0: u14,
+        }), base_address + 0x50);
+
+        /// address: 0x60008854
+        /// BLOCK1 data register 4.
+        pub const RD_MAC_SPI_SYS_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fist 32 bits of the zeroth part of system data.
+            SYS_DATA_PART0_1: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60008858
+        /// BLOCK1 data register 5.
+        pub const RD_MAC_SPI_SYS_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of the zeroth part of system data.
+            SYS_DATA_PART0_2: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000885c
+        /// Register 0 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of the first part of system data.
+            SYS_DATA_PART1_0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60008860
+        /// Register 1 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of the first part of system data.
+            SYS_DATA_PART1_1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60008864
+        /// Register 2 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of the first part of system data.
+            SYS_DATA_PART1_2: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60008868
+        /// Register 3 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of the first part of system data.
+            SYS_DATA_PART1_3: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000886c
+        /// Register 4 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of the first part of system data.
+            SYS_DATA_PART1_4: u32,
+        }), base_address + 0x6c);
+
+        /// address: 0x60008870
+        /// Register 5 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of the first part of system data.
+            SYS_DATA_PART1_5: u32,
+        }), base_address + 0x70);
+
+        /// address: 0x60008874
+        /// Register 6 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of the first part of system data.
+            SYS_DATA_PART1_6: u32,
+        }), base_address + 0x74);
+
+        /// address: 0x60008878
+        /// Register 7 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of the first part of system data.
+            SYS_DATA_PART1_7: u32,
+        }), base_address + 0x78);
+
+        /// address: 0x6000887c
+        /// Register 0 of BLOCK3 (user).
+        pub const RD_USR_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of BLOCK3 (user).
+            USR_DATA0: u32,
+        }), base_address + 0x7c);
+
+        /// address: 0x60008880
+        /// Register 1 of BLOCK3 (user).
+        pub const RD_USR_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of BLOCK3 (user).
+            USR_DATA1: u32,
+        }), base_address + 0x80);
+
+        /// address: 0x60008884
+        /// Register 2 of BLOCK3 (user).
+        pub const RD_USR_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of BLOCK3 (user).
+            USR_DATA2: u32,
+        }), base_address + 0x84);
+
+        /// address: 0x60008888
+        /// Register 3 of BLOCK3 (user).
+        pub const RD_USR_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of BLOCK3 (user).
+            USR_DATA3: u32,
+        }), base_address + 0x88);
+
+        /// address: 0x6000888c
+        /// Register 4 of BLOCK3 (user).
+        pub const RD_USR_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of BLOCK3 (user).
+            USR_DATA4: u32,
+        }), base_address + 0x8c);
+
+        /// address: 0x60008890
+        /// Register 5 of BLOCK3 (user).
+        pub const RD_USR_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of BLOCK3 (user).
+            USR_DATA5: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x60008894
+        /// Register 6 of BLOCK3 (user).
+        pub const RD_USR_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of BLOCK3 (user).
+            USR_DATA6: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60008898
+        /// Register 7 of BLOCK3 (user).
+        pub const RD_USR_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of BLOCK3 (user).
+            USR_DATA7: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6000889c
+        /// Register 0 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY0.
+            KEY0_DATA0: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600088a0
+        /// Register 1 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY0.
+            KEY0_DATA1: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600088a4
+        /// Register 2 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY0.
+            KEY0_DATA2: u32,
+        }), base_address + 0xa4);
+
+        /// address: 0x600088a8
+        /// Register 3 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY0.
+            KEY0_DATA3: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600088ac
+        /// Register 4 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY0.
+            KEY0_DATA4: u32,
+        }), base_address + 0xac);
+
+        /// address: 0x600088b0
+        /// Register 5 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY0.
+            KEY0_DATA5: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600088b4
+        /// Register 6 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY0.
+            KEY0_DATA6: u32,
+        }), base_address + 0xb4);
+
+        /// address: 0x600088b8
+        /// Register 7 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY0.
+            KEY0_DATA7: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600088bc
+        /// Register 0 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY1.
+            KEY1_DATA0: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600088c0
+        /// Register 1 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY1.
+            KEY1_DATA1: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600088c4
+        /// Register 2 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY1.
+            KEY1_DATA2: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600088c8
+        /// Register 3 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY1.
+            KEY1_DATA3: u32,
+        }), base_address + 0xc8);
+
+        /// address: 0x600088cc
+        /// Register 4 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY1.
+            KEY1_DATA4: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600088d0
+        /// Register 5 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY1.
+            KEY1_DATA5: u32,
+        }), base_address + 0xd0);
+
+        /// address: 0x600088d4
+        /// Register 6 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY1.
+            KEY1_DATA6: u32,
+        }), base_address + 0xd4);
+
+        /// address: 0x600088d8
+        /// Register 7 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY1.
+            KEY1_DATA7: u32,
+        }), base_address + 0xd8);
+
+        /// address: 0x600088dc
+        /// Register 0 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY2.
+            KEY2_DATA0: u32,
+        }), base_address + 0xdc);
+
+        /// address: 0x600088e0
+        /// Register 1 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY2.
+            KEY2_DATA1: u32,
+        }), base_address + 0xe0);
+
+        /// address: 0x600088e4
+        /// Register 2 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY2.
+            KEY2_DATA2: u32,
+        }), base_address + 0xe4);
+
+        /// address: 0x600088e8
+        /// Register 3 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY2.
+            KEY2_DATA3: u32,
+        }), base_address + 0xe8);
+
+        /// address: 0x600088ec
+        /// Register 4 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY2.
+            KEY2_DATA4: u32,
+        }), base_address + 0xec);
+
+        /// address: 0x600088f0
+        /// Register 5 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY2.
+            KEY2_DATA5: u32,
+        }), base_address + 0xf0);
+
+        /// address: 0x600088f4
+        /// Register 6 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY2.
+            KEY2_DATA6: u32,
+        }), base_address + 0xf4);
+
+        /// address: 0x600088f8
+        /// Register 7 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY2.
+            KEY2_DATA7: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x600088fc
+        /// Register 0 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY3.
+            KEY3_DATA0: u32,
+        }), base_address + 0xfc);
+
+        /// address: 0x60008900
+        /// Register 1 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY3.
+            KEY3_DATA1: u32,
+        }), base_address + 0x100);
+
+        /// address: 0x60008904
+        /// Register 2 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY3.
+            KEY3_DATA2: u32,
+        }), base_address + 0x104);
+
+        /// address: 0x60008908
+        /// Register 3 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY3.
+            KEY3_DATA3: u32,
+        }), base_address + 0x108);
+
+        /// address: 0x6000890c
+        /// Register 4 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY3.
+            KEY3_DATA4: u32,
+        }), base_address + 0x10c);
+
+        /// address: 0x60008910
+        /// Register 5 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY3.
+            KEY3_DATA5: u32,
+        }), base_address + 0x110);
+
+        /// address: 0x60008914
+        /// Register 6 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY3.
+            KEY3_DATA6: u32,
+        }), base_address + 0x114);
+
+        /// address: 0x60008918
+        /// Register 7 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY3.
+            KEY3_DATA7: u32,
+        }), base_address + 0x118);
+
+        /// address: 0x6000891c
+        /// Register 0 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY4.
+            KEY4_DATA0: u32,
+        }), base_address + 0x11c);
+
+        /// address: 0x60008920
+        /// Register 1 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY4.
+            KEY4_DATA1: u32,
+        }), base_address + 0x120);
+
+        /// address: 0x60008924
+        /// Register 2 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY4.
+            KEY4_DATA2: u32,
+        }), base_address + 0x124);
+
+        /// address: 0x60008928
+        /// Register 3 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY4.
+            KEY4_DATA3: u32,
+        }), base_address + 0x128);
+
+        /// address: 0x6000892c
+        /// Register 4 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY4.
+            KEY4_DATA4: u32,
+        }), base_address + 0x12c);
+
+        /// address: 0x60008930
+        /// Register 5 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY4.
+            KEY4_DATA5: u32,
+        }), base_address + 0x130);
+
+        /// address: 0x60008934
+        /// Register 6 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY4.
+            KEY4_DATA6: u32,
+        }), base_address + 0x134);
+
+        /// address: 0x60008938
+        /// Register 7 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY4.
+            KEY4_DATA7: u32,
+        }), base_address + 0x138);
+
+        /// address: 0x6000893c
+        /// Register 0 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY5.
+            KEY5_DATA0: u32,
+        }), base_address + 0x13c);
+
+        /// address: 0x60008940
+        /// Register 1 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY5.
+            KEY5_DATA1: u32,
+        }), base_address + 0x140);
+
+        /// address: 0x60008944
+        /// Register 2 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY5.
+            KEY5_DATA2: u32,
+        }), base_address + 0x144);
+
+        /// address: 0x60008948
+        /// Register 3 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY5.
+            KEY5_DATA3: u32,
+        }), base_address + 0x148);
+
+        /// address: 0x6000894c
+        /// Register 4 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY5.
+            KEY5_DATA4: u32,
+        }), base_address + 0x14c);
+
+        /// address: 0x60008950
+        /// Register 5 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY5.
+            KEY5_DATA5: u32,
+        }), base_address + 0x150);
+
+        /// address: 0x60008954
+        /// Register 6 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY5.
+            KEY5_DATA6: u32,
+        }), base_address + 0x154);
+
+        /// address: 0x60008958
+        /// Register 7 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY5.
+            KEY5_DATA7: u32,
+        }), base_address + 0x158);
+
+        /// address: 0x6000895c
+        /// Register 0 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 0th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_0: u32,
+        }), base_address + 0x15c);
+
+        /// address: 0x60008960
+        /// Register 1 of BLOCK9 (KEY5).
+        pub const RD_SYS_PART2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 1st 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_1: u32,
+        }), base_address + 0x160);
+
+        /// address: 0x60008964
+        /// Register 2 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 2nd 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_2: u32,
+        }), base_address + 0x164);
+
+        /// address: 0x60008968
+        /// Register 3 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 3rd 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_3: u32,
+        }), base_address + 0x168);
+
+        /// address: 0x6000896c
+        /// Register 4 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 4th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_4: u32,
+        }), base_address + 0x16c);
+
+        /// address: 0x60008970
+        /// Register 5 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 5th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_5: u32,
+        }), base_address + 0x170);
+
+        /// address: 0x60008974
+        /// Register 6 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 6th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_6: u32,
+        }), base_address + 0x174);
+
+        /// address: 0x60008978
+        /// Register 7 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 7th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_7: u32,
+        }), base_address + 0x178);
+
+        /// address: 0x6000897c
+        /// Programming error record register 0 of BLOCK0.
+        pub const RD_REPEAT_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If any bit in RD_DIS is 1, then it indicates a programming error.
+            RD_DIS_ERR: u7,
+            /// If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+            DIS_RTC_RAM_BOOT_ERR: u1,
+            /// If DIS_ICACHE is 1, then it indicates a programming error.
+            DIS_ICACHE_ERR: u1,
+            /// If DIS_USB_JTAG is 1, then it indicates a programming error.
+            DIS_USB_JTAG_ERR: u1,
+            /// If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_ICACHE_ERR: u1,
+            /// If DIS_USB_DEVICE is 1, then it indicates a programming error.
+            DIS_USB_DEVICE_ERR: u1,
+            /// If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+            DIS_FORCE_DOWNLOAD_ERR: u1,
+            /// Reserved.
+            RPT4_RESERVED6_ERR: u1,
+            /// If DIS_CAN is 1, then it indicates a programming error.
+            DIS_CAN_ERR: u1,
+            /// If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+            JTAG_SEL_ENABLE_ERR: u1,
+            /// If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+            SOFT_DIS_JTAG_ERR: u3,
+            /// If DIS_PAD_JTAG is 1, then it indicates a programming error.
+            DIS_PAD_JTAG_ERR: u1,
+            /// If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
+            /// If any bit in USB_DREFH is 1, then it indicates a programming error.
+            USB_DREFH_ERR: u2,
+            /// If any bit in USB_DREFL is 1, then it indicates a programming error.
+            USB_DREFL_ERR: u2,
+            /// If USB_EXCHG_PINS is 1, then it indicates a programming error.
+            USB_EXCHG_PINS_ERR: u1,
+            /// If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+            VDD_SPI_AS_GPIO_ERR: u1,
+            /// If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+            BTLC_GPIO_ENABLE_ERR: u2,
+            /// If POWERGLITCH_EN is 1, then it indicates a programming error.
+            POWERGLITCH_EN_ERR: u1,
+            /// If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+            POWER_GLITCH_DSENSE_ERR: u2,
+        }), base_address + 0x17c);
+
+        /// address: 0x60008980
+        /// Programming error record register 1 of BLOCK0.
+        pub const RD_REPEAT_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RPT4_RESERVED2_ERR: u16,
+            /// If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+            WDT_DELAY_SEL_ERR: u2,
+            /// If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+            SPI_BOOT_CRYPT_CNT_ERR: u3,
+            /// If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE0_ERR: u1,
+            /// If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE1_ERR: u1,
+            /// If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE2_ERR: u1,
+            /// If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+            KEY_PURPOSE_0_ERR: u4,
+            /// If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+            KEY_PURPOSE_1_ERR: u4,
+        }), base_address + 0x180);
+
+        /// address: 0x60008984
+        /// Programming error record register 2 of BLOCK0.
+        pub const RD_REPEAT_ERR2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+            KEY_PURPOSE_2_ERR: u4,
+            /// If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+            KEY_PURPOSE_3_ERR: u4,
+            /// If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+            KEY_PURPOSE_4_ERR: u4,
+            /// If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+            KEY_PURPOSE_5_ERR: u4,
+            /// Reserved.
+            RPT4_RESERVED3_ERR: u4,
+            /// If SECURE_BOOT_EN is 1, then it indicates a programming error.
+            SECURE_BOOT_EN_ERR: u1,
+            /// If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+            SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
+            /// Reserved.
+            RPT4_RESERVED0_ERR: u6,
+            /// If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+            FLASH_TPUW_ERR: u4,
+        }), base_address + 0x184);
+
+        /// address: 0x60008988
+        /// Programming error record register 3 of BLOCK0.
+        pub const RD_REPEAT_ERR3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_MODE_ERR: u1,
+            /// If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+            DIS_LEGACY_SPI_BOOT_ERR: u1,
+            /// If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+            UART_PRINT_CHANNEL_ERR: u1,
+            /// If FLASH_ECC_MODE is 1, then it indicates a programming error.
+            FLASH_ECC_MODE_ERR: u1,
+            /// If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+            DIS_USB_DOWNLOAD_MODE_ERR: u1,
+            /// If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+            ENABLE_SECURITY_DOWNLOAD_ERR: u1,
+            /// If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+            UART_PRINT_CONTROL_ERR: u2,
+            /// If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+            PIN_POWER_SELECTION_ERR: u1,
+            /// If FLASH_TYPE is 1, then it indicates a programming error.
+            FLASH_TYPE_ERR: u1,
+            /// If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+            FLASH_PAGE_SIZE_ERR: u2,
+            /// If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+            FLASH_ECC_EN_ERR: u1,
+            /// If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+            FORCE_SEND_RESUME_ERR: u1,
+            /// If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+            SECURE_VERSION_ERR: u16,
+            /// Reserved.
+            RPT4_RESERVED1_ERR: u2,
+        }), base_address + 0x188);
+
+        /// address: 0x60008990
+        /// Programming error record register 4 of BLOCK0.
+        pub const RD_REPEAT_ERR4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RPT4_RESERVED4_ERR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x600089c0
+        /// Programming error record register 0 of BLOCK1-10.
+        pub const RD_RS_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of this signal means the number of error bytes.
+            MAC_SPI_8M_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            MAC_SPI_8M_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            SYS_PART1_NUM: u3,
+            /// 0: Means no failure and that the data of system part1 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            SYS_PART1_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            USR_DATA_ERR_NUM: u3,
+            /// 0: Means no failure and that the user data is reliable 1: Means that programming
+            /// user data failed and the number of error bytes is over 6.
+            USR_DATA_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY0_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key0 is reliable 1: Means that
+            /// programming key0 failed and the number of error bytes is over 6.
+            KEY0_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY1_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key1 is reliable 1: Means that
+            /// programming key1 failed and the number of error bytes is over 6.
+            KEY1_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY2_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key2 is reliable 1: Means that
+            /// programming key2 failed and the number of error bytes is over 6.
+            KEY2_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY3_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key3 is reliable 1: Means that
+            /// programming key3 failed and the number of error bytes is over 6.
+            KEY3_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY4_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key4 is reliable 1: Means that
+            /// programming key4 failed and the number of error bytes is over 6.
+            KEY4_FAIL: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x600089c4
+        /// Programming error record register 1 of BLOCK1-10.
+        pub const RD_RS_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of this signal means the number of error bytes.
+            KEY5_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of KEY5 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            KEY5_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            SYS_PART2_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of system part2 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            SYS_PART2_FAIL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c4);
+
+        /// address: 0x600089c8
+        /// eFuse clcok configuration register.
+        pub const CLK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to force eFuse SRAM into power-saving mode.
+            EFUSE_MEM_FORCE_PD: u1,
+            /// Set this bit and force to activate clock signal of eFuse SRAM.
+            MEM_CLK_FORCE_ON: u1,
+            /// Set this bit to force eFuse SRAM into working mode.
+            EFUSE_MEM_FORCE_PU: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// Set this bit and force to enable clock signal of eFuse memory.
+            EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x1c8);
+
+        /// address: 0x600089cc
+        /// eFuse operation mode configuraiton register;
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 0x5A5A: Operate programming command 0x5AA5: Operate read command.
+            OP_CODE: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1cc);
+
+        /// address: 0x600089d0
+        /// eFuse status register.
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Indicates the state of the eFuse state machine.
+            STATE: u4,
+            /// The value of OTP_LOAD_SW.
+            OTP_LOAD_SW: u1,
+            /// The value of OTP_VDDQ_C_SYNC2.
+            OTP_VDDQ_C_SYNC2: u1,
+            /// The value of OTP_STROBE_SW.
+            OTP_STROBE_SW: u1,
+            /// The value of OTP_CSB_SW.
+            OTP_CSB_SW: u1,
+            /// The value of OTP_PGENB_SW.
+            OTP_PGENB_SW: u1,
+            /// The value of OTP_VDDQ_IS_SW.
+            OTP_VDDQ_IS_SW: u1,
+            /// Indicates the number of error bits during programming BLOCK0.
+            REPEAT_ERR_CNT: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1d0);
+
+        /// address: 0x600089d4
+        /// eFuse command register.
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to send read command.
+            READ_CMD: u1,
+            /// Set this bit to send programming command.
+            PGM_CMD: u1,
+            /// The serial number of the block to be programmed. Value 0-10 corresponds to block
+            /// number 0-10, respectively.
+            BLK_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x1d4);
+
+        /// address: 0x600089d8
+        /// eFuse raw interrupt register.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw bit signal for read_done interrupt.
+            READ_DONE_INT_RAW: u1,
+            /// The raw bit signal for pgm_done interrupt.
+            PGM_DONE_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1d8);
+
+        /// address: 0x600089dc
+        /// eFuse interrupt status register.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status signal for read_done interrupt.
+            READ_DONE_INT_ST: u1,
+            /// The status signal for pgm_done interrupt.
+            PGM_DONE_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1dc);
+
+        /// address: 0x600089e0
+        /// eFuse interrupt enable register.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable signal for read_done interrupt.
+            READ_DONE_INT_ENA: u1,
+            /// The enable signal for pgm_done interrupt.
+            PGM_DONE_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1e0);
+
+        /// address: 0x600089e4
+        /// eFuse interrupt clear register.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear signal for read_done interrupt.
+            READ_DONE_INT_CLR: u1,
+            /// The clear signal for pgm_done interrupt.
+            PGM_DONE_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1e4);
+
+        /// address: 0x600089e8
+        /// Controls the eFuse programming voltage.
+        pub const DAC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Controls the division factor of the rising clock of the programming voltage.
+            DAC_CLK_DIV: u8,
+            /// Don't care.
+            DAC_CLK_PAD_SEL: u1,
+            /// Controls the rising period of the programming voltage.
+            DAC_NUM: u8,
+            /// Reduces the power supply of the programming voltage.
+            OE_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1e8);
+
+        /// address: 0x600089ec
+        /// Configures read timing parameters.
+        pub const RD_TIM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            /// Configures the initial read time of eFuse.
+            READ_INIT_NUM: u8,
+        }), base_address + 0x1ec);
+
+        /// address: 0x600089f0
+        /// Configurarion register 1 of eFuse programming timing parameters.
+        pub const WR_TIM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// Configures the power up time for VDDQ.
+            PWR_ON_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x600089f4
+        /// Configurarion register 2 of eFuse programming timing parameters.
+        pub const WR_TIM_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Configures the power outage time for VDDQ.
+            PWR_OFF_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x600089fc
+        /// eFuse version register.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x1fc);
+    };
+
+    /// External Memory
+    pub const EXTMEM = struct {
+        pub const base_address = 0x600c4000;
+
+        /// address: 0x600c4000
+        /// This description will be updated in the near future.
+        pub const ICACHE_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to activate the data cache. 0: disable, 1: enable
+            ICACHE_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600c4004
+        /// This description will be updated in the near future.
+        pub const ICACHE_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable core0 ibus, 0: enable, 1: disable
+            ICACHE_SHUT_IBUS: u1,
+            /// The bit is used to disable core1 ibus, 0: enable, 1: disable
+            ICACHE_SHUT_DBUS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600c4008
+        /// This description will be updated in the near future.
+        pub const ICACHE_TAG_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to close clock gating of icache tag memory. 1: close gating, 0:
+            /// open clock gating.
+            ICACHE_TAG_MEM_FORCE_ON: u1,
+            /// The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power
+            /// down
+            ICACHE_TAG_MEM_FORCE_PD: u1,
+            /// The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
+            ICACHE_TAG_MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600c400c
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable the first section of prelock function.
+            ICACHE_PRELOCK_SCT0_EN: u1,
+            /// The bit is used to enable the second section of prelock function.
+            ICACHE_PRELOCK_SCT1_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600c4010
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x600c4014
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x600c4018
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT_SIZE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to configure the second length of data locking, which is
+            /// combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+            ICACHE_PRELOCK_SCT1_SIZE: u16,
+            /// The bits are used to configure the first length of data locking, which is
+            /// combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+            ICACHE_PRELOCK_SCT0_SIZE: u16,
+        }), base_address + 0x18);
+
+        /// address: 0x600c401c
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable lock operation. It will be cleared by hardware after
+            /// lock operation done.
+            ICACHE_LOCK_ENA: u1,
+            /// The bit is used to enable unlock operation. It will be cleared by hardware after
+            /// unlock operation done.
+            ICACHE_UNLOCK_ENA: u1,
+            /// The bit is used to indicate unlock/lock operation is finished.
+            ICACHE_LOCK_DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c4020
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_ADDR = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x600c4024
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24);
+
+        /// address: 0x600c4028
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable invalidate operation. It will be cleared by hardware
+            /// after invalidate operation done.
+            ICACHE_INVALIDATE_ENA: u1,
+            /// The bit is used to indicate invalidate operation is finished.
+            ICACHE_SYNC_DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x600c402c
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_ADDR = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x600c4030
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_SIZE = @intToPtr(*volatile MmioInt(32, u23), base_address + 0x30);
+
+        /// address: 0x600c4034
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable preload operation. It will be cleared by hardware
+            /// after preload operation done.
+            ICACHE_PRELOAD_ENA: u1,
+            /// The bit is used to indicate preload operation is finished.
+            ICACHE_PRELOAD_DONE: u1,
+            /// The bit is used to configure the direction of preload operation. 1: descending,
+            /// 0: ascending.
+            ICACHE_PRELOAD_ORDER: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x600c4038
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_ADDR = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x600c403c
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c);
+
+        /// address: 0x600c4040
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to enable the first section for autoload operation.
+            ICACHE_AUTOLOAD_SCT0_ENA: u1,
+            /// The bits are used to enable the second section for autoload operation.
+            ICACHE_AUTOLOAD_SCT1_ENA: u1,
+            /// The bit is used to enable and disable autoload operation. It is combined with
+            /// icache_autoload_done. 1: enable, 0: disable.
+            ICACHE_AUTOLOAD_ENA: u1,
+            /// The bit is used to indicate autoload operation is finished.
+            ICACHE_AUTOLOAD_DONE: u1,
+            /// The bits are used to configure the direction of autoload. 1: descending, 0:
+            /// ascending.
+            ICACHE_AUTOLOAD_ORDER: u1,
+            /// The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
+            /// 1: cache hit, 2: both cache miss and hit.
+            ICACHE_AUTOLOAD_RQST: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c4044
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x44);
+
+        /// address: 0x600c4048
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT0_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x48);
+
+        /// address: 0x600c404c
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x4c);
+
+        /// address: 0x600c4050
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT1_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x50);
+
+        /// address: 0x600c4054
+        /// This description will be updated in the near future.
+        pub const IBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x54);
+
+        /// address: 0x600c4058
+        /// This description will be updated in the near future.
+        pub const IBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x58);
+
+        /// address: 0x600c405c
+        /// This description will be updated in the near future.
+        pub const DBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x5c);
+
+        /// address: 0x600c4060
+        /// This description will be updated in the near future.
+        pub const DBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x60);
+
+        /// address: 0x600c4064
+        /// This description will be updated in the near future.
+        pub const CACHE_ACS_CNT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear ibus counter.
+            IBUS_ACS_CNT_CLR: u1,
+            /// The bit is used to clear dbus counter.
+            DBUS_ACS_CNT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c4068
+        /// This description will be updated in the near future.
+        pub const IBUS_ACS_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x68);
+
+        /// address: 0x600c406c
+        /// This description will be updated in the near future.
+        pub const IBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x6c);
+
+        /// address: 0x600c4070
+        /// This description will be updated in the near future.
+        pub const DBUS_ACS_FLASH_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x70);
+
+        /// address: 0x600c4074
+        /// This description will be updated in the near future.
+        pub const DBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x74);
+
+        /// address: 0x600c4078
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to enable interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_INT_ENA: u1,
+            reserved3: u1,
+            /// The bit is used to enable interrupt by ibus counter overflow.
+            IBUS_CNT_OVF_INT_ENA: u1,
+            /// The bit is used to enable interrupt by dbus counter overflow.
+            DBUS_CNT_OVF_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c407c
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to clear interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_INT_CLR: u1,
+            reserved3: u1,
+            /// The bit is used to clear interrupt by ibus counter overflow.
+            IBUS_CNT_OVF_INT_CLR: u1,
+            /// The bit is used to clear interrupt by dbus counter overflow.
+            DBUS_CNT_OVF_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c4080
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_ST: u1,
+            /// The bit is used to indicate interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_ST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to indicate interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_ST: u1,
+            reserved3: u1,
+            /// The bit is used to indicate interrupt by ibus access flash/spiram counter
+            /// overflow.
+            IBUS_ACS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by ibus access flash/spiram miss counter
+            /// overflow.
+            IBUS_ACS_MISS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by dbus access flash/spiram counter
+            /// overflow.
+            DBUS_ACS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by dbus access flash miss counter
+            /// overflow.
+            DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c4084
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable interrupt by cpu access icache while the corresponding
+            /// ibus is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by authentication fail.
+            CORE0_IBUS_REJECT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by cpu access icache while the corresponding
+            /// dbus is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by authentication fail.
+            CORE0_DBUS_REJECT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_IC_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c4088
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear interrupt by cpu access icache while the corresponding
+            /// ibus is disabled or icache is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by authentication fail.
+            CORE0_IBUS_REJECT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by cpu access icache while the corresponding
+            /// dbus is disabled or icache is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by authentication fail.
+            CORE0_DBUS_REJECT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_IC_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c408c
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate interrupt by cpu access icache while the core0_ibus
+            /// is disabled or icache is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by authentication fail.
+            CORE0_IBUS_REJECT_ST: u1,
+            /// The bit is used to indicate interrupt by cpu access icache while the core0_dbus
+            /// is disabled or icache is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by authentication fail.
+            CORE0_DBUS_REJECT_ST: u1,
+            /// The bit is used to indicate interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_ICACHE_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c4090
+        /// This description will be updated in the near future.
+        pub const CORE0_DBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the attribute of CPU access dbus when
+            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4:
+            /// write-able.
+            CORE0_DBUS_ATTR: u3,
+            /// The bit is used to indicate the world of CPU access dbus when authentication
+            /// fail. 0: WORLD0, 1: WORLD1
+            CORE0_DBUS_WORLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c4094
+        /// This description will be updated in the near future.
+        pub const CORE0_DBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the virtual address of CPU access dbus when
+            /// authentication fail.
+            CORE0_DBUS_VADDR: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x600c4098
+        /// This description will be updated in the near future.
+        pub const CORE0_IBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the attribute of CPU access ibus when
+            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+            CORE0_IBUS_ATTR: u3,
+            /// The bit is used to indicate the world of CPU access ibus when authentication
+            /// fail. 0: WORLD0, 1: WORLD1
+            CORE0_IBUS_WORLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c409c
+        /// This description will be updated in the near future.
+        pub const CORE0_IBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the virtual address of CPU access ibus when
+            /// authentication fail.
+            CORE0_IBUS_VADDR: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600c40a0
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_FAULT_CONTENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the content of mmu entry which cause mmu fault..
+            CACHE_MMU_FAULT_CONTENT: u10,
+            /// The right-most 3 bits are used to indicate the operations which cause mmu fault
+            /// occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
+            /// evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
+            /// 7: external dma rx. The most significant bit is used to indicate this operation
+            /// occurs in which one icache.
+            CACHE_MMU_FAULT_CODE: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600c40a4
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_FAULT_VADDR = @intToPtr(*volatile u32, base_address + 0xa4);
+
+        /// address: 0x600c40a8
+        /// This description will be updated in the near future.
+        pub const CACHE_WRAP_AROUND_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable wrap around mode when read data from flash.
+            CACHE_FLASH_WRAP_AROUND: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600c40ac
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable clock gating to save power when access mmu memory, 0:
+            /// enable, 1: disable
+            CACHE_MMU_MEM_FORCE_ON: u1,
+            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+            CACHE_MMU_MEM_FORCE_PD: u1,
+            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+            CACHE_MMU_MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600c40b0
+        /// This description will be updated in the near future.
+        pub const CACHE_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate whether icache main fsm is in idle state or not. 1:
+            /// in idle state, 0: not in idle state
+            ICACHE_STATE: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600c40b4
+        /// This description will be updated in the near future.
+        pub const CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RECORD_DISABLE_DB_ENCRYPT: u1,
+            /// Reserved.
+            RECORD_DISABLE_G0CB_DECRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600c40b8
+        /// This description will be updated in the near future.
+        pub const CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
+            /// open clock gating.
+            CLK_FORCE_ON_MANUAL_CRYPT: u1,
+            /// The bit is used to close clock gating of automatic crypt clock. 1: close gating,
+            /// 0: open clock gating.
+            CLK_FORCE_ON_AUTO_CRYPT: u1,
+            /// The bit is used to close clock gating of external memory encrypt and decrypt
+            /// clock. 1: close gating, 0: open clock gating.
+            CLK_FORCE_ON_CRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600c40bc
+        /// This description will be updated in the near future.
+        pub const CACHE_PRELOAD_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_ST: u1,
+            /// The bit is used to enable the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_ENA: u1,
+            /// The bit is used to clear the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600c40c0
+        /// This description will be updated in the near future.
+        pub const CACHE_SYNC_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate the interrupt by icache sync done.
+            ICACHE_SYNC_INT_ST: u1,
+            /// The bit is used to enable the interrupt by icache sync done.
+            ICACHE_SYNC_INT_ENA: u1,
+            /// The bit is used to clear the interrupt by icache sync done.
+            ICACHE_SYNC_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600c40c4
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_OWNER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xc4);
+
+        /// address: 0x600c40c8
+        /// This description will be updated in the near future.
+        pub const CACHE_CONF_MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable checking mmu entry fault by preload operation.
+            CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
+            /// The bit is used to disable checking mmu entry fault by sync operation.
+            CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
+            /// The bit is used to enable cache trace function.
+            CACHE_TRACE_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600c40cc
+        /// This description will be updated in the near future.
+        pub const ICACHE_FREEZE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable icache freeze mode
+            ENA: u1,
+            /// The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert
+            /// hit if CPU miss
+            MODE: u1,
+            /// The bit is used to indicate icache freeze success
+            DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600c40d0
+        /// This description will be updated in the near future.
+        pub const ICACHE_ATOMIC_OPERATE_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xd0);
+
+        /// address: 0x600c40d4
+        /// This description will be updated in the near future.
+        pub const CACHE_REQUEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable request recording which could cause performance issue
+            BYPASS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600c40d8
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            IBUS_PMS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600c40dc
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            IBUS_PMS_BOUNDARY0: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600c40e0
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary1
+            IBUS_PMS_BOUNDARY1: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600c40e4
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary2
+            IBUS_PMS_BOUNDARY2: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x600c40e8
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure attribute of the ibus permission control section1,
+            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
+            /// in world1
+            IBUS_PMS_SCT1_ATTR: u4,
+            /// The bit is used to configure attribute of the ibus permission control section2,
+            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
+            /// in world1
+            IBUS_PMS_SCT2_ATTR: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xe8);
+
+        /// address: 0x600c40ec
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            DBUS_PMS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xec);
+
+        /// address: 0x600c40f0
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary0
+            DBUS_PMS_BOUNDARY0: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x600c40f4
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary1
+            DBUS_PMS_BOUNDARY1: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600c40f8
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary2
+            DBUS_PMS_BOUNDARY2: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c40fc
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure attribute of the dbus permission control section1,
+            /// bit0: load in world0, bit2: load in world1
+            DBUS_PMS_SCT1_ATTR: u2,
+            /// The bit is used to configure attribute of the dbus permission control section2,
+            /// bit0: load in world0, bit2: load in world1
+            DBUS_PMS_SCT2_ATTR: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c4100
+        /// This description will be updated in the near future.
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clock gate enable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c43fc
+        /// This description will be updated in the near future.
+        pub const REG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// version information
+            DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x3fc);
+    };
+
+    /// General Purpose Input/Output
+    pub const GPIO = struct {
+        pub const base_address = 0x60004000;
+
+        /// address: 0x60004000
+        /// GPIO bit select register
+        pub const BT_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO bit select register
+            BT_SEL: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60004004
+        /// GPIO output register
+        pub const OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO output register for GPIO0-25
+            DATA_ORIG: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60004008
+        /// GPIO output set register
+        pub const OUT_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x8);
+
+        /// address: 0x6000400c
+        /// GPIO output clear register
+        pub const OUT_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0xc);
+
+        /// address: 0x6000401c
+        /// GPIO sdio select register
+        pub const SDIO_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO sdio select register
+            SDIO_SEL: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60004020
+        /// GPIO output enable register
+        pub const ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO output enable register for GPIO0-25
+            DATA: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60004024
+        /// GPIO output enable set register
+        pub const ENABLE_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x24);
+
+        /// address: 0x60004028
+        /// GPIO output enable clear register
+        pub const ENABLE_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x28);
+
+        /// address: 0x60004038
+        /// pad strapping register
+        pub const STRAP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pad strapping register
+            STRAPPING: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000403c
+        /// GPIO input register
+        pub const IN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO input register for GPIO0-25
+            DATA_NEXT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60004044
+        /// GPIO interrupt status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO interrupt status register for GPIO0-25
+            INTERRUPT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60004048
+        /// GPIO interrupt status set register
+        pub const STATUS_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x48);
+
+        /// address: 0x6000404c
+        /// GPIO interrupt status clear register
+        pub const STATUS_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x4c);
+
+        /// address: 0x6000405c
+        /// GPIO PRO_CPU interrupt status register
+        pub const PCPU_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO PRO_CPU interrupt status register for GPIO0-25
+            PROCPU_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60004060
+        /// GPIO PRO_CPU(not shielded) interrupt status register
+        pub const PCPU_NMI_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+            PROCPU_NMI_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60004064
+        /// GPIO CPUSDIO interrupt status register
+        pub const CPUSDIO_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO CPUSDIO interrupt status register for GPIO0-25
+            SDIO_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60004074
+        /// GPIO pin configuration register
+        pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60004078
+        /// GPIO pin configuration register
+        pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000407c
+        /// GPIO pin configuration register
+        pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60004080
+        /// GPIO pin configuration register
+        pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60004084
+        /// GPIO pin configuration register
+        pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x60004088
+        /// GPIO pin configuration register
+        pub const PIN5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6000408c
+        /// GPIO pin configuration register
+        pub const PIN6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x60004090
+        /// GPIO pin configuration register
+        pub const PIN7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60004094
+        /// GPIO pin configuration register
+        pub const PIN8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x60004098
+        /// GPIO pin configuration register
+        pub const PIN9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6000409c
+        /// GPIO pin configuration register
+        pub const PIN10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600040a0
+        /// GPIO pin configuration register
+        pub const PIN11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600040a4
+        /// GPIO pin configuration register
+        pub const PIN12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600040a8
+        /// GPIO pin configuration register
+        pub const PIN13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600040ac
+        /// GPIO pin configuration register
+        pub const PIN14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600040b0
+        /// GPIO pin configuration register
+        pub const PIN15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600040b4
+        /// GPIO pin configuration register
+        pub const PIN16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600040b8
+        /// GPIO pin configuration register
+        pub const PIN17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600040bc
+        /// GPIO pin configuration register
+        pub const PIN18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600040c0
+        /// GPIO pin configuration register
+        pub const PIN19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600040c4
+        /// GPIO pin configuration register
+        pub const PIN20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600040c8
+        /// GPIO pin configuration register
+        pub const PIN21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600040cc
+        /// GPIO pin configuration register
+        pub const PIN22 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600040d0
+        /// GPIO pin configuration register
+        pub const PIN23 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600040d4
+        /// GPIO pin configuration register
+        pub const PIN24 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600040d8
+        /// GPIO pin configuration register
+        pub const PIN25 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x6000414c
+        /// GPIO interrupt source register
+        pub const STATUS_NEXT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO interrupt source register for GPIO0-25
+            STATUS_INTERRUPT_NEXT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x60004154
+        /// GPIO input function configuration register
+        pub const FUNC0_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x154);
+
+        /// address: 0x60004158
+        /// GPIO input function configuration register
+        pub const FUNC1_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x6000415c
+        /// GPIO input function configuration register
+        pub const FUNC2_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x60004160
+        /// GPIO input function configuration register
+        pub const FUNC3_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x60004164
+        /// GPIO input function configuration register
+        pub const FUNC4_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x60004168
+        /// GPIO input function configuration register
+        pub const FUNC5_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x6000416c
+        /// GPIO input function configuration register
+        pub const FUNC6_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x16c);
+
+        /// address: 0x60004170
+        /// GPIO input function configuration register
+        pub const FUNC7_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x60004174
+        /// GPIO input function configuration register
+        pub const FUNC8_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x174);
+
+        /// address: 0x60004178
+        /// GPIO input function configuration register
+        pub const FUNC9_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x178);
+
+        /// address: 0x6000417c
+        /// GPIO input function configuration register
+        pub const FUNC10_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x17c);
+
+        /// address: 0x60004180
+        /// GPIO input function configuration register
+        pub const FUNC11_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x180);
+
+        /// address: 0x60004184
+        /// GPIO input function configuration register
+        pub const FUNC12_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x184);
+
+        /// address: 0x60004188
+        /// GPIO input function configuration register
+        pub const FUNC13_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x188);
+
+        /// address: 0x6000418c
+        /// GPIO input function configuration register
+        pub const FUNC14_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x18c);
+
+        /// address: 0x60004190
+        /// GPIO input function configuration register
+        pub const FUNC15_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x60004194
+        /// GPIO input function configuration register
+        pub const FUNC16_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x194);
+
+        /// address: 0x60004198
+        /// GPIO input function configuration register
+        pub const FUNC17_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x198);
+
+        /// address: 0x6000419c
+        /// GPIO input function configuration register
+        pub const FUNC18_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x19c);
+
+        /// address: 0x600041a0
+        /// GPIO input function configuration register
+        pub const FUNC19_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a0);
+
+        /// address: 0x600041a4
+        /// GPIO input function configuration register
+        pub const FUNC20_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a4);
+
+        /// address: 0x600041a8
+        /// GPIO input function configuration register
+        pub const FUNC21_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a8);
+
+        /// address: 0x600041ac
+        /// GPIO input function configuration register
+        pub const FUNC22_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1ac);
+
+        /// address: 0x600041b0
+        /// GPIO input function configuration register
+        pub const FUNC23_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b0);
+
+        /// address: 0x600041b4
+        /// GPIO input function configuration register
+        pub const FUNC24_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b4);
+
+        /// address: 0x600041b8
+        /// GPIO input function configuration register
+        pub const FUNC25_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b8);
+
+        /// address: 0x600041bc
+        /// GPIO input function configuration register
+        pub const FUNC26_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1bc);
+
+        /// address: 0x600041c0
+        /// GPIO input function configuration register
+        pub const FUNC27_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x600041c4
+        /// GPIO input function configuration register
+        pub const FUNC28_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c4);
+
+        /// address: 0x600041c8
+        /// GPIO input function configuration register
+        pub const FUNC29_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c8);
+
+        /// address: 0x600041cc
+        /// GPIO input function configuration register
+        pub const FUNC30_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1cc);
+
+        /// address: 0x600041d0
+        /// GPIO input function configuration register
+        pub const FUNC31_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d0);
+
+        /// address: 0x600041d4
+        /// GPIO input function configuration register
+        pub const FUNC32_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d4);
+
+        /// address: 0x600041d8
+        /// GPIO input function configuration register
+        pub const FUNC33_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d8);
+
+        /// address: 0x600041dc
+        /// GPIO input function configuration register
+        pub const FUNC34_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1dc);
+
+        /// address: 0x600041e0
+        /// GPIO input function configuration register
+        pub const FUNC35_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e0);
+
+        /// address: 0x600041e4
+        /// GPIO input function configuration register
+        pub const FUNC36_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e4);
+
+        /// address: 0x600041e8
+        /// GPIO input function configuration register
+        pub const FUNC37_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e8);
+
+        /// address: 0x600041ec
+        /// GPIO input function configuration register
+        pub const FUNC38_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1ec);
+
+        /// address: 0x600041f0
+        /// GPIO input function configuration register
+        pub const FUNC39_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x600041f4
+        /// GPIO input function configuration register
+        pub const FUNC40_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x600041f8
+        /// GPIO input function configuration register
+        pub const FUNC41_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f8);
+
+        /// address: 0x600041fc
+        /// GPIO input function configuration register
+        pub const FUNC42_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1fc);
+
+        /// address: 0x60004200
+        /// GPIO input function configuration register
+        pub const FUNC43_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x200);
+
+        /// address: 0x60004204
+        /// GPIO input function configuration register
+        pub const FUNC44_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x204);
+
+        /// address: 0x60004208
+        /// GPIO input function configuration register
+        pub const FUNC45_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x208);
+
+        /// address: 0x6000420c
+        /// GPIO input function configuration register
+        pub const FUNC46_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x20c);
+
+        /// address: 0x60004210
+        /// GPIO input function configuration register
+        pub const FUNC47_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x210);
+
+        /// address: 0x60004214
+        /// GPIO input function configuration register
+        pub const FUNC48_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x214);
+
+        /// address: 0x60004218
+        /// GPIO input function configuration register
+        pub const FUNC49_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x218);
+
+        /// address: 0x6000421c
+        /// GPIO input function configuration register
+        pub const FUNC50_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x21c);
+
+        /// address: 0x60004220
+        /// GPIO input function configuration register
+        pub const FUNC51_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x220);
+
+        /// address: 0x60004224
+        /// GPIO input function configuration register
+        pub const FUNC52_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x224);
+
+        /// address: 0x60004228
+        /// GPIO input function configuration register
+        pub const FUNC53_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x228);
+
+        /// address: 0x6000422c
+        /// GPIO input function configuration register
+        pub const FUNC54_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x22c);
+
+        /// address: 0x60004230
+        /// GPIO input function configuration register
+        pub const FUNC55_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x230);
+
+        /// address: 0x60004234
+        /// GPIO input function configuration register
+        pub const FUNC56_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x234);
+
+        /// address: 0x60004238
+        /// GPIO input function configuration register
+        pub const FUNC57_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x238);
+
+        /// address: 0x6000423c
+        /// GPIO input function configuration register
+        pub const FUNC58_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x23c);
+
+        /// address: 0x60004240
+        /// GPIO input function configuration register
+        pub const FUNC59_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x240);
+
+        /// address: 0x60004244
+        /// GPIO input function configuration register
+        pub const FUNC60_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x244);
+
+        /// address: 0x60004248
+        /// GPIO input function configuration register
+        pub const FUNC61_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x248);
+
+        /// address: 0x6000424c
+        /// GPIO input function configuration register
+        pub const FUNC62_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x24c);
+
+        /// address: 0x60004250
+        /// GPIO input function configuration register
+        pub const FUNC63_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x250);
+
+        /// address: 0x60004254
+        /// GPIO input function configuration register
+        pub const FUNC64_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x254);
+
+        /// address: 0x60004258
+        /// GPIO input function configuration register
+        pub const FUNC65_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x258);
+
+        /// address: 0x6000425c
+        /// GPIO input function configuration register
+        pub const FUNC66_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x25c);
+
+        /// address: 0x60004260
+        /// GPIO input function configuration register
+        pub const FUNC67_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x260);
+
+        /// address: 0x60004264
+        /// GPIO input function configuration register
+        pub const FUNC68_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x264);
+
+        /// address: 0x60004268
+        /// GPIO input function configuration register
+        pub const FUNC69_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x268);
+
+        /// address: 0x6000426c
+        /// GPIO input function configuration register
+        pub const FUNC70_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x26c);
+
+        /// address: 0x60004270
+        /// GPIO input function configuration register
+        pub const FUNC71_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x270);
+
+        /// address: 0x60004274
+        /// GPIO input function configuration register
+        pub const FUNC72_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x274);
+
+        /// address: 0x60004278
+        /// GPIO input function configuration register
+        pub const FUNC73_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x278);
+
+        /// address: 0x6000427c
+        /// GPIO input function configuration register
+        pub const FUNC74_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x27c);
+
+        /// address: 0x60004280
+        /// GPIO input function configuration register
+        pub const FUNC75_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x280);
+
+        /// address: 0x60004284
+        /// GPIO input function configuration register
+        pub const FUNC76_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x284);
+
+        /// address: 0x60004288
+        /// GPIO input function configuration register
+        pub const FUNC77_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x288);
+
+        /// address: 0x6000428c
+        /// GPIO input function configuration register
+        pub const FUNC78_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x28c);
+
+        /// address: 0x60004290
+        /// GPIO input function configuration register
+        pub const FUNC79_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x290);
+
+        /// address: 0x60004294
+        /// GPIO input function configuration register
+        pub const FUNC80_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x294);
+
+        /// address: 0x60004298
+        /// GPIO input function configuration register
+        pub const FUNC81_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x298);
+
+        /// address: 0x6000429c
+        /// GPIO input function configuration register
+        pub const FUNC82_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x29c);
+
+        /// address: 0x600042a0
+        /// GPIO input function configuration register
+        pub const FUNC83_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a0);
+
+        /// address: 0x600042a4
+        /// GPIO input function configuration register
+        pub const FUNC84_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a4);
+
+        /// address: 0x600042a8
+        /// GPIO input function configuration register
+        pub const FUNC85_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a8);
+
+        /// address: 0x600042ac
+        /// GPIO input function configuration register
+        pub const FUNC86_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2ac);
+
+        /// address: 0x600042b0
+        /// GPIO input function configuration register
+        pub const FUNC87_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b0);
+
+        /// address: 0x600042b4
+        /// GPIO input function configuration register
+        pub const FUNC88_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b4);
+
+        /// address: 0x600042b8
+        /// GPIO input function configuration register
+        pub const FUNC89_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b8);
+
+        /// address: 0x600042bc
+        /// GPIO input function configuration register
+        pub const FUNC90_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2bc);
+
+        /// address: 0x600042c0
+        /// GPIO input function configuration register
+        pub const FUNC91_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c0);
+
+        /// address: 0x600042c4
+        /// GPIO input function configuration register
+        pub const FUNC92_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c4);
+
+        /// address: 0x600042c8
+        /// GPIO input function configuration register
+        pub const FUNC93_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c8);
+
+        /// address: 0x600042cc
+        /// GPIO input function configuration register
+        pub const FUNC94_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2cc);
+
+        /// address: 0x600042d0
+        /// GPIO input function configuration register
+        pub const FUNC95_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d0);
+
+        /// address: 0x600042d4
+        /// GPIO input function configuration register
+        pub const FUNC96_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d4);
+
+        /// address: 0x600042d8
+        /// GPIO input function configuration register
+        pub const FUNC97_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d8);
+
+        /// address: 0x600042dc
+        /// GPIO input function configuration register
+        pub const FUNC98_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2dc);
+
+        /// address: 0x600042e0
+        /// GPIO input function configuration register
+        pub const FUNC99_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e0);
+
+        /// address: 0x600042e4
+        /// GPIO input function configuration register
+        pub const FUNC100_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e4);
+
+        /// address: 0x600042e8
+        /// GPIO input function configuration register
+        pub const FUNC101_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e8);
+
+        /// address: 0x600042ec
+        /// GPIO input function configuration register
+        pub const FUNC102_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2ec);
+
+        /// address: 0x600042f0
+        /// GPIO input function configuration register
+        pub const FUNC103_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f0);
+
+        /// address: 0x600042f4
+        /// GPIO input function configuration register
+        pub const FUNC104_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f4);
+
+        /// address: 0x600042f8
+        /// GPIO input function configuration register
+        pub const FUNC105_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f8);
+
+        /// address: 0x600042fc
+        /// GPIO input function configuration register
+        pub const FUNC106_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2fc);
+
+        /// address: 0x60004300
+        /// GPIO input function configuration register
+        pub const FUNC107_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x300);
+
+        /// address: 0x60004304
+        /// GPIO input function configuration register
+        pub const FUNC108_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x304);
+
+        /// address: 0x60004308
+        /// GPIO input function configuration register
+        pub const FUNC109_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x308);
+
+        /// address: 0x6000430c
+        /// GPIO input function configuration register
+        pub const FUNC110_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x30c);
+
+        /// address: 0x60004310
+        /// GPIO input function configuration register
+        pub const FUNC111_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x310);
+
+        /// address: 0x60004314
+        /// GPIO input function configuration register
+        pub const FUNC112_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x314);
+
+        /// address: 0x60004318
+        /// GPIO input function configuration register
+        pub const FUNC113_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x318);
+
+        /// address: 0x6000431c
+        /// GPIO input function configuration register
+        pub const FUNC114_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x31c);
+
+        /// address: 0x60004320
+        /// GPIO input function configuration register
+        pub const FUNC115_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x320);
+
+        /// address: 0x60004324
+        /// GPIO input function configuration register
+        pub const FUNC116_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x324);
+
+        /// address: 0x60004328
+        /// GPIO input function configuration register
+        pub const FUNC117_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x328);
+
+        /// address: 0x6000432c
+        /// GPIO input function configuration register
+        pub const FUNC118_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x32c);
+
+        /// address: 0x60004330
+        /// GPIO input function configuration register
+        pub const FUNC119_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x330);
+
+        /// address: 0x60004334
+        /// GPIO input function configuration register
+        pub const FUNC120_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x334);
+
+        /// address: 0x60004338
+        /// GPIO input function configuration register
+        pub const FUNC121_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x338);
+
+        /// address: 0x6000433c
+        /// GPIO input function configuration register
+        pub const FUNC122_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x33c);
+
+        /// address: 0x60004340
+        /// GPIO input function configuration register
+        pub const FUNC123_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x340);
+
+        /// address: 0x60004344
+        /// GPIO input function configuration register
+        pub const FUNC124_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x344);
+
+        /// address: 0x60004348
+        /// GPIO input function configuration register
+        pub const FUNC125_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x348);
+
+        /// address: 0x6000434c
+        /// GPIO input function configuration register
+        pub const FUNC126_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x34c);
+
+        /// address: 0x60004350
+        /// GPIO input function configuration register
+        pub const FUNC127_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x350);
+
+        /// address: 0x60004554
+        /// GPIO output function select register
+        pub const FUNC0_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x554);
+
+        /// address: 0x60004558
+        /// GPIO output function select register
+        pub const FUNC1_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x558);
+
+        /// address: 0x6000455c
+        /// GPIO output function select register
+        pub const FUNC2_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x55c);
+
+        /// address: 0x60004560
+        /// GPIO output function select register
+        pub const FUNC3_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x560);
+
+        /// address: 0x60004564
+        /// GPIO output function select register
+        pub const FUNC4_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x564);
+
+        /// address: 0x60004568
+        /// GPIO output function select register
+        pub const FUNC5_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x568);
+
+        /// address: 0x6000456c
+        /// GPIO output function select register
+        pub const FUNC6_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x56c);
+
+        /// address: 0x60004570
+        /// GPIO output function select register
+        pub const FUNC7_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x570);
+
+        /// address: 0x60004574
+        /// GPIO output function select register
+        pub const FUNC8_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x574);
+
+        /// address: 0x60004578
+        /// GPIO output function select register
+        pub const FUNC9_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x578);
+
+        /// address: 0x6000457c
+        /// GPIO output function select register
+        pub const FUNC10_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x57c);
+
+        /// address: 0x60004580
+        /// GPIO output function select register
+        pub const FUNC11_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x580);
+
+        /// address: 0x60004584
+        /// GPIO output function select register
+        pub const FUNC12_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x584);
+
+        /// address: 0x60004588
+        /// GPIO output function select register
+        pub const FUNC13_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x588);
+
+        /// address: 0x6000458c
+        /// GPIO output function select register
+        pub const FUNC14_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x58c);
+
+        /// address: 0x60004590
+        /// GPIO output function select register
+        pub const FUNC15_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x590);
+
+        /// address: 0x60004594
+        /// GPIO output function select register
+        pub const FUNC16_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x594);
+
+        /// address: 0x60004598
+        /// GPIO output function select register
+        pub const FUNC17_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x598);
+
+        /// address: 0x6000459c
+        /// GPIO output function select register
+        pub const FUNC18_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x59c);
+
+        /// address: 0x600045a0
+        /// GPIO output function select register
+        pub const FUNC19_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a0);
+
+        /// address: 0x600045a4
+        /// GPIO output function select register
+        pub const FUNC20_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a4);
+
+        /// address: 0x600045a8
+        /// GPIO output function select register
+        pub const FUNC21_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a8);
+
+        /// address: 0x600045ac
+        /// GPIO output function select register
+        pub const FUNC22_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5ac);
+
+        /// address: 0x600045b0
+        /// GPIO output function select register
+        pub const FUNC23_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b0);
+
+        /// address: 0x600045b4
+        /// GPIO output function select register
+        pub const FUNC24_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b4);
+
+        /// address: 0x600045b8
+        /// GPIO output function select register
+        pub const FUNC25_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b8);
+
+        /// address: 0x6000462c
+        /// GPIO clock gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this bit to enable GPIO clock gate
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x62c);
+
+        /// address: 0x600046fc
+        /// GPIO version register
+        pub const REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x6fc);
+    };
+
+    /// Sigma-Delta Modulation
+    pub const GPIOSD = struct {
+        pub const base_address = 0x60004f00;
+
+        /// address: 0x60004f00
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60004f04
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60004f08
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x60004f0c
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60004f20
+        /// Clock Gating Configure Register
+        pub const SIGMADELTA_CG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// Clock enable bit of configuration registers for sigma delta modulation.
+            CLK_EN: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60004f24
+        /// MISC Register
+        pub const SIGMADELTA_MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            /// Clock enable bit of sigma delta modulation.
+            FUNCTION_CLK_EN: u1,
+            /// Reserved.
+            SPI_SWAP: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60004f28
+        /// Version Control Register
+        pub const SIGMADELTA_VERSION = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Version control register.
+            GPIO_SD_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x28);
+    };
+
+    /// HMAC (Hash-based Message Authentication Code) Accelerator
+    pub const HMAC = struct {
+        pub const base_address = 0x6003e000;
+
+        /// address: 0x6003e040
+        /// Process control register 0.
+        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
+
+        /// address: 0x6003e044
+        /// Configure purpose.
+        pub const SET_PARA_PURPOSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set hmac parameter purpose.
+            PURPOSE_SET: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6003e048
+        /// Configure key.
+        pub const SET_PARA_KEY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set hmac parameter key.
+            KEY_SET: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6003e04c
+        /// Finish initial configuration.
+        pub const SET_PARA_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Finish hmac configuration.
+            SET_PARA_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x6003e050
+        /// Process control register 1.
+        pub const SET_MESSAGE_ONE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Call SHA to calculate one message block.
+            SET_TEXT_ONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6003e054
+        /// Process control register 2.
+        pub const SET_MESSAGE_ING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Continue typical hmac.
+            SET_TEXT_ING: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6003e058
+        /// Process control register 3.
+        pub const SET_MESSAGE_END = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Start hardware padding.
+            SET_TEXT_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6003e05c
+        /// Process control register 4.
+        pub const SET_RESULT_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
+            /// After read result from upstream, then let hmac back to idle.
+            SET_RESULT_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6003e060
+        /// Invalidate register 0.
+        pub const SET_INVALIDATE_JTAG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x60);
+
+        /// address: 0x6003e064
+        /// Invalidate register 1.
+        pub const SET_INVALIDATE_DS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x64);
+
+        /// address: 0x6003e068
+        /// Error register.
+        pub const QUERY_ERROR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Hmac configuration state. 0: key are agree with purpose. 1: error
+            QUREY_CHECK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6003e06c
+        /// Busy register.
+        pub const QUERY_BUSY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Hmac state. 1'b0: idle. 1'b1: busy
+            BUSY_STATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6003e080
+        /// Message block memory.
+        pub const WR_MESSAGE_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
+
+        /// address: 0x6003e0c0
+        /// Result from upstream.
+        pub const RD_RESULT_MEM = @intToPtr(*volatile [32]u8, base_address + 0xc0);
+
+        /// address: 0x6003e0f0
+        /// Process control register 5.
+        pub const SET_MESSAGE_PAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Start software padding.
+            SET_TEXT_PAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x6003e0f4
+        /// Process control register 6.
+        pub const ONE_BLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Don't have to do padding.
+            SET_ONE_BLOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x6003e0f8
+        /// Jtag register 0.
+        pub const SOFT_JTAG_CTRL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xf8);
+
+        /// address: 0x6003e0fc
+        /// Jtag register 1.
+        pub const WR_JTAG = @intToPtr(*volatile u32, base_address + 0xfc);
+    };
+
+    /// I2C (Inter-Integrated Circuit) Controller
+    pub const I2C0 = struct {
+        pub const base_address = 0x60013000;
+
+        /// address: 0x60013000
+        /// I2C_SCL_LOW_PERIOD_REG
+        pub const SCL_LOW_PERIOD = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x0);
+
+        /// address: 0x60013004
+        /// I2C_CTR_REG
+        pub const CTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_force_out
+            SDA_FORCE_OUT: u1,
+            /// reg_scl_force_out
+            SCL_FORCE_OUT: u1,
+            /// reg_sample_scl_level
+            SAMPLE_SCL_LEVEL: u1,
+            /// reg_rx_full_ack_level
+            RX_FULL_ACK_LEVEL: u1,
+            /// reg_ms_mode
+            MS_MODE: u1,
+            /// reg_trans_start
+            TRANS_START: u1,
+            /// reg_tx_lsb_first
+            TX_LSB_FIRST: u1,
+            /// reg_rx_lsb_first
+            RX_LSB_FIRST: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            /// reg_arbitration_en
+            ARBITRATION_EN: u1,
+            /// reg_fsm_rst
+            FSM_RST: u1,
+            /// reg_conf_upgate
+            CONF_UPGATE: u1,
+            /// reg_slv_tx_auto_start_en
+            SLV_TX_AUTO_START_EN: u1,
+            /// reg_addr_10bit_rw_check_en
+            ADDR_10BIT_RW_CHECK_EN: u1,
+            /// reg_addr_broadcasting_en
+            ADDR_BROADCASTING_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60013008
+        /// I2C_SR_REG
+        pub const SR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_resp_rec
+            RESP_REC: u1,
+            /// reg_slave_rw
+            SLAVE_RW: u1,
+            reserved0: u1,
+            /// reg_arb_lost
+            ARB_LOST: u1,
+            /// reg_bus_busy
+            BUS_BUSY: u1,
+            /// reg_slave_addressed
+            SLAVE_ADDRESSED: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_rxfifo_cnt
+            RXFIFO_CNT: u6,
+            /// reg_stretch_cause
+            STRETCH_CAUSE: u2,
+            reserved3: u1,
+            reserved4: u1,
+            /// reg_txfifo_cnt
+            TXFIFO_CNT: u6,
+            /// reg_scl_main_state_last
+            SCL_MAIN_STATE_LAST: u3,
+            reserved5: u1,
+            /// reg_scl_state_last
+            SCL_STATE_LAST: u3,
+            padding0: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001300c
+        /// I2C_TO_REG
+        pub const TO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_time_out_value
+            TIME_OUT_VALUE: u5,
+            /// reg_time_out_en
+            TIME_OUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60013010
+        /// I2C_SLAVE_ADDR_REG
+        pub const SLAVE_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_slave_addr
+            SLAVE_ADDR: u15,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// reg_addr_10bit_en
+            ADDR_10BIT_EN: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60013014
+        /// I2C_FIFO_ST_REG
+        pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_raddr
+            RXFIFO_RADDR: u5,
+            /// reg_rxfifo_waddr
+            RXFIFO_WADDR: u5,
+            /// reg_txfifo_raddr
+            TXFIFO_RADDR: u5,
+            /// reg_txfifo_waddr
+            TXFIFO_WADDR: u5,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_slave_rw_point
+            SLAVE_RW_POINT: u8,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60013018
+        /// I2C_FIFO_CONF_REG
+        pub const FIFO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_thrhd
+            RXFIFO_WM_THRHD: u5,
+            /// reg_txfifo_wm_thrhd
+            TXFIFO_WM_THRHD: u5,
+            /// reg_nonfifo_en
+            NONFIFO_EN: u1,
+            /// reg_fifo_addr_cfg_en
+            FIFO_ADDR_CFG_EN: u1,
+            /// reg_rx_fifo_rst
+            RX_FIFO_RST: u1,
+            /// reg_tx_fifo_rst
+            TX_FIFO_RST: u1,
+            /// reg_fifo_prt_en
+            FIFO_PRT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001301c
+        /// I2C_FIFO_DATA_REG
+        pub const DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_fifo_rdata
+            FIFO_RDATA: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60013020
+        /// I2C_INT_RAW_REG
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_raw
+            RXFIFO_WM_INT_RAW: u1,
+            /// reg_txfifo_wm_int_raw
+            TXFIFO_WM_INT_RAW: u1,
+            /// reg_rxfifo_ovf_int_raw
+            RXFIFO_OVF_INT_RAW: u1,
+            /// reg_end_detect_int_raw
+            END_DETECT_INT_RAW: u1,
+            /// reg_byte_trans_done_int_raw
+            BYTE_TRANS_DONE_INT_RAW: u1,
+            /// reg_arbitration_lost_int_raw
+            ARBITRATION_LOST_INT_RAW: u1,
+            /// reg_mst_txfifo_udf_int_raw
+            MST_TXFIFO_UDF_INT_RAW: u1,
+            /// reg_trans_complete_int_raw
+            TRANS_COMPLETE_INT_RAW: u1,
+            /// reg_time_out_int_raw
+            TIME_OUT_INT_RAW: u1,
+            /// reg_trans_start_int_raw
+            TRANS_START_INT_RAW: u1,
+            /// reg_nack_int_raw
+            NACK_INT_RAW: u1,
+            /// reg_txfifo_ovf_int_raw
+            TXFIFO_OVF_INT_RAW: u1,
+            /// reg_rxfifo_udf_int_raw
+            RXFIFO_UDF_INT_RAW: u1,
+            /// reg_scl_st_to_int_raw
+            SCL_ST_TO_INT_RAW: u1,
+            /// reg_scl_main_st_to_int_raw
+            SCL_MAIN_ST_TO_INT_RAW: u1,
+            /// reg_det_start_int_raw
+            DET_START_INT_RAW: u1,
+            /// reg_slave_stretch_int_raw
+            SLAVE_STRETCH_INT_RAW: u1,
+            /// reg_general_call_int_raw
+            GENERAL_CALL_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60013024
+        /// I2C_INT_CLR_REG
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_clr
+            RXFIFO_WM_INT_CLR: u1,
+            /// reg_txfifo_wm_int_clr
+            TXFIFO_WM_INT_CLR: u1,
+            /// reg_rxfifo_ovf_int_clr
+            RXFIFO_OVF_INT_CLR: u1,
+            /// reg_end_detect_int_clr
+            END_DETECT_INT_CLR: u1,
+            /// reg_byte_trans_done_int_clr
+            BYTE_TRANS_DONE_INT_CLR: u1,
+            /// reg_arbitration_lost_int_clr
+            ARBITRATION_LOST_INT_CLR: u1,
+            /// reg_mst_txfifo_udf_int_clr
+            MST_TXFIFO_UDF_INT_CLR: u1,
+            /// reg_trans_complete_int_clr
+            TRANS_COMPLETE_INT_CLR: u1,
+            /// reg_time_out_int_clr
+            TIME_OUT_INT_CLR: u1,
+            /// reg_trans_start_int_clr
+            TRANS_START_INT_CLR: u1,
+            /// reg_nack_int_clr
+            NACK_INT_CLR: u1,
+            /// reg_txfifo_ovf_int_clr
+            TXFIFO_OVF_INT_CLR: u1,
+            /// reg_rxfifo_udf_int_clr
+            RXFIFO_UDF_INT_CLR: u1,
+            /// reg_scl_st_to_int_clr
+            SCL_ST_TO_INT_CLR: u1,
+            /// reg_scl_main_st_to_int_clr
+            SCL_MAIN_ST_TO_INT_CLR: u1,
+            /// reg_det_start_int_clr
+            DET_START_INT_CLR: u1,
+            /// reg_slave_stretch_int_clr
+            SLAVE_STRETCH_INT_CLR: u1,
+            /// reg_general_call_int_clr
+            GENERAL_CALL_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60013028
+        /// I2C_INT_ENA_REG
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_ena
+            RXFIFO_WM_INT_ENA: u1,
+            /// reg_txfifo_wm_int_ena
+            TXFIFO_WM_INT_ENA: u1,
+            /// reg_rxfifo_ovf_int_ena
+            RXFIFO_OVF_INT_ENA: u1,
+            /// reg_end_detect_int_ena
+            END_DETECT_INT_ENA: u1,
+            /// reg_byte_trans_done_int_ena
+            BYTE_TRANS_DONE_INT_ENA: u1,
+            /// reg_arbitration_lost_int_ena
+            ARBITRATION_LOST_INT_ENA: u1,
+            /// reg_mst_txfifo_udf_int_ena
+            MST_TXFIFO_UDF_INT_ENA: u1,
+            /// reg_trans_complete_int_ena
+            TRANS_COMPLETE_INT_ENA: u1,
+            /// reg_time_out_int_ena
+            TIME_OUT_INT_ENA: u1,
+            /// reg_trans_start_int_ena
+            TRANS_START_INT_ENA: u1,
+            /// reg_nack_int_ena
+            NACK_INT_ENA: u1,
+            /// reg_txfifo_ovf_int_ena
+            TXFIFO_OVF_INT_ENA: u1,
+            /// reg_rxfifo_udf_int_ena
+            RXFIFO_UDF_INT_ENA: u1,
+            /// reg_scl_st_to_int_ena
+            SCL_ST_TO_INT_ENA: u1,
+            /// reg_scl_main_st_to_int_ena
+            SCL_MAIN_ST_TO_INT_ENA: u1,
+            /// reg_det_start_int_ena
+            DET_START_INT_ENA: u1,
+            /// reg_slave_stretch_int_ena
+            SLAVE_STRETCH_INT_ENA: u1,
+            /// reg_general_call_int_ena
+            GENERAL_CALL_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001302c
+        /// I2C_INT_STATUS_REG
+        pub const INT_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_st
+            RXFIFO_WM_INT_ST: u1,
+            /// reg_txfifo_wm_int_st
+            TXFIFO_WM_INT_ST: u1,
+            /// reg_rxfifo_ovf_int_st
+            RXFIFO_OVF_INT_ST: u1,
+            /// reg_end_detect_int_st
+            END_DETECT_INT_ST: u1,
+            /// reg_byte_trans_done_int_st
+            BYTE_TRANS_DONE_INT_ST: u1,
+            /// reg_arbitration_lost_int_st
+            ARBITRATION_LOST_INT_ST: u1,
+            /// reg_mst_txfifo_udf_int_st
+            MST_TXFIFO_UDF_INT_ST: u1,
+            /// reg_trans_complete_int_st
+            TRANS_COMPLETE_INT_ST: u1,
+            /// reg_time_out_int_st
+            TIME_OUT_INT_ST: u1,
+            /// reg_trans_start_int_st
+            TRANS_START_INT_ST: u1,
+            /// reg_nack_int_st
+            NACK_INT_ST: u1,
+            /// reg_txfifo_ovf_int_st
+            TXFIFO_OVF_INT_ST: u1,
+            /// reg_rxfifo_udf_int_st
+            RXFIFO_UDF_INT_ST: u1,
+            /// reg_scl_st_to_int_st
+            SCL_ST_TO_INT_ST: u1,
+            /// reg_scl_main_st_to_int_st
+            SCL_MAIN_ST_TO_INT_ST: u1,
+            /// reg_det_start_int_st
+            DET_START_INT_ST: u1,
+            /// reg_slave_stretch_int_st
+            SLAVE_STRETCH_INT_ST: u1,
+            /// reg_general_call_int_st
+            GENERAL_CALL_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60013030
+        /// I2C_SDA_HOLD_REG
+        pub const SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60013034
+        /// I2C_SDA_SAMPLE_REG
+        pub const SDA_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_sample_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60013038
+        /// I2C_SCL_HIGH_PERIOD_REG
+        pub const SCL_HIGH_PERIOD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_high_period
+            SCL_HIGH_PERIOD: u9,
+            /// reg_scl_wait_high_period
+            SCL_WAIT_HIGH_PERIOD: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x60013040
+        /// I2C_SCL_START_HOLD_REG
+        pub const SCL_START_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_start_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60013044
+        /// I2C_SCL_RSTART_SETUP_REG
+        pub const SCL_RSTART_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_rstart_setup_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60013048
+        /// I2C_SCL_STOP_HOLD_REG
+        pub const SCL_STOP_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_stop_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001304c
+        /// I2C_SCL_STOP_SETUP_REG
+        pub const SCL_STOP_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_stop_setup_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60013050
+        /// I2C_FILTER_CFG_REG
+        pub const FILTER_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_filter_thres
+            SCL_FILTER_THRES: u4,
+            /// reg_sda_filter_thres
+            SDA_FILTER_THRES: u4,
+            /// reg_scl_filter_en
+            SCL_FILTER_EN: u1,
+            /// reg_sda_filter_en
+            SDA_FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60013054
+        /// I2C_CLK_CONF_REG
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sclk_div_num
+            SCLK_DIV_NUM: u8,
+            /// reg_sclk_div_a
+            SCLK_DIV_A: u6,
+            /// reg_sclk_div_b
+            SCLK_DIV_B: u6,
+            /// reg_sclk_sel
+            SCLK_SEL: u1,
+            /// reg_sclk_active
+            SCLK_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60013058
+        /// I2C_COMD%s_REG
+        pub const COMD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001305c
+        /// I2C_COMD%s_REG
+        pub const COMD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60013060
+        /// I2C_COMD%s_REG
+        pub const COMD2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60013064
+        /// I2C_COMD%s_REG
+        pub const COMD3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60013068
+        /// I2C_COMD%s_REG
+        pub const COMD4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001306c
+        /// I2C_COMD%s_REG
+        pub const COMD5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60013070
+        /// I2C_COMD%s_REG
+        pub const COMD6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60013074
+        /// I2C_COMD%s_REG
+        pub const COMD7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60013078
+        /// I2C_SCL_ST_TIME_OUT_REG
+        pub const SCL_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_st_to_regno more than 23
+            SCL_ST_TO_I2C: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001307c
+        /// I2C_SCL_MAIN_ST_TIME_OUT_REG
+        pub const SCL_MAIN_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_main_st_to_regno more than 23
+            SCL_MAIN_ST_TO_I2C: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60013080
+        /// I2C_SCL_SP_CONF_REG
+        pub const SCL_SP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_rst_slv_en
+            SCL_RST_SLV_EN: u1,
+            /// reg_scl_rst_slv_num
+            SCL_RST_SLV_NUM: u5,
+            /// reg_scl_pd_en
+            SCL_PD_EN: u1,
+            /// reg_sda_pd_en
+            SDA_PD_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60013084
+        /// I2C_SCL_STRETCH_CONF_REG
+        pub const SCL_STRETCH_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_stretch_protect_num
+            STRETCH_PROTECT_NUM: u10,
+            /// reg_slave_scl_stretch_en
+            SLAVE_SCL_STRETCH_EN: u1,
+            /// reg_slave_scl_stretch_clr
+            SLAVE_SCL_STRETCH_CLR: u1,
+            /// reg_slave_byte_ack_ctl_en
+            SLAVE_BYTE_ACK_CTL_EN: u1,
+            /// reg_slave_byte_ack_lvl
+            SLAVE_BYTE_ACK_LVL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600130f8
+        /// I2C_DATE_REG
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0xf8);
+
+        /// address: 0x60013100
+        /// I2C_TXFIFO_START_ADDR_REG
+        pub const TXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x100);
+
+        /// address: 0x60013180
+        /// I2C_RXFIFO_START_ADDR_REG
+        pub const RXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x180);
+    };
+
+    /// I2S (Inter-IC Sound) Controller
+    pub const I2S = struct {
+        pub const base_address = 0x6002d000;
+
+        /// address: 0x6002d00c
+        /// I2S interrupt raw register, valid in level.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6002d010
+        /// I2S interrupt status register.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The masked interrupt status bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6002d014
+        /// I2S interrupt enable register.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6002d018
+        /// I2S interrupt clear register.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the i2s_rx_done_int interrupt
+            RX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the i2s_tx_done_int interrupt
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_CLR: u1,
+            /// Set this bit to clear the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6002d020
+        /// I2S RX configure register
+        pub const RX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to reset receiver
+            RX_RESET: u1,
+            /// Set this bit to reset Rx AFIFO
+            RX_FIFO_RESET: u1,
+            /// Set this bit to start receiving data
+            RX_START: u1,
+            /// Set this bit to enable slave receiver mode
+            RX_SLAVE_MOD: u1,
+            reserved0: u1,
+            /// Set this bit to enable receiver in mono mode
+            RX_MONO: u1,
+            reserved1: u1,
+            /// I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr
+            /// value.
+            RX_BIG_ENDIAN: u1,
+            /// Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain.
+            /// This bit will be cleared by hardware after update register done.
+            RX_UPDATE: u1,
+            /// 1: The first channel data value is valid in I2S RX mono mode. 0: The second
+            /// channel data value is valid in I2S RX mono mode.
+            RX_MONO_FST_VLD: u1,
+            /// I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
+            /// &
+            RX_PCM_CONF: u2,
+            /// Set this bit to bypass Compress/Decompress module for received data.
+            RX_PCM_BYPASS: u1,
+            /// 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
+            /// 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+            RX_STOP_MODE: u2,
+            /// 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+            RX_LEFT_ALIGN: u1,
+            /// 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+            RX_24_FILL_EN: u1,
+            /// 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+            /// 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+            RX_WS_IDLE_POL: u1,
+            /// I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
+            /// MSB is received first.
+            RX_BIT_ORDER: u1,
+            /// 1: Enable I2S TDM Rx mode . 0: Disable.
+            RX_TDM_EN: u1,
+            /// 1: Enable I2S PDM Rx mode . 0: Disable.
+            RX_PDM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6002d024
+        /// I2S TX configure register
+        pub const TX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to reset transmitter
+            TX_RESET: u1,
+            /// Set this bit to reset Tx AFIFO
+            TX_FIFO_RESET: u1,
+            /// Set this bit to start transmitting data
+            TX_START: u1,
+            /// Set this bit to enable slave transmitter mode
+            TX_SLAVE_MOD: u1,
+            reserved0: u1,
+            /// Set this bit to enable transmitter in mono mode
+            TX_MONO: u1,
+            /// 1: The value of Left channel data is equal to the value of right channel data in
+            /// I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+            /// reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+            TX_CHAN_EQUAL: u1,
+            /// I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
+            /// value.
+            TX_BIG_ENDIAN: u1,
+            /// Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain.
+            /// This bit will be cleared by hardware after update register done.
+            TX_UPDATE: u1,
+            /// 1: The first channel data value is valid in I2S TX mono mode. 0: The second
+            /// channel data value is valid in I2S TX mono mode.
+            TX_MONO_FST_VLD: u1,
+            /// I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
+            /// &
+            TX_PCM_CONF: u2,
+            /// Set this bit to bypass Compress/Decompress module for transmitted data.
+            TX_PCM_BYPASS: u1,
+            /// Set this bit to stop disable output BCK signal and WS signal when tx FIFO is
+            /// emtpy
+            TX_STOP_EN: u1,
+            reserved1: u1,
+            /// 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+            TX_LEFT_ALIGN: u1,
+            /// 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+            TX_24_FILL_EN: u1,
+            /// 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
+            /// 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+            TX_WS_IDLE_POL: u1,
+            /// I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
+            /// is sent first.
+            TX_BIT_ORDER: u1,
+            /// 1: Enable I2S TDM Tx mode . 0: Disable.
+            TX_TDM_EN: u1,
+            /// 1: Enable I2S PDM Tx mode . 0: Disable.
+            TX_PDM_EN: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// I2S transmitter channel mode configuration bits.
+            TX_CHAN_MOD: u3,
+            /// Enable signal loop back mode with transmitter module and receiver module sharing
+            /// the same WS and BCK signals.
+            SIG_LOOPBACK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6002d028
+        /// I2S RX configure register 1
+        pub const RX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+            RX_TDM_WS_WIDTH: u7,
+            /// Bit clock configuration bits in receiver mode.
+            RX_BCK_DIV_NUM: u6,
+            /// Set the bits to configure the valid data bit length of I2S receiver channel. 7:
+            /// all the valid channel data is in 8-bit-mode. 15: all the valid channel data is
+            /// in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
+            /// valid channel data is in 32-bit-mode.
+            RX_BITS_MOD: u5,
+            /// I2S Rx half sample bits -1.
+            RX_HALF_SAMPLE_BITS: u6,
+            /// The Rx bit number for each channel minus 1in TDM mode.
+            RX_TDM_CHAN_BITS: u5,
+            /// Set this bit to enable receiver in Phillips standard mode
+            RX_MSB_SHIFT: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6002d02c
+        /// I2S TX configure register 1
+        pub const TX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+            TX_TDM_WS_WIDTH: u7,
+            /// Bit clock configuration bits in transmitter mode.
+            TX_BCK_DIV_NUM: u6,
+            /// Set the bits to configure the valid data bit length of I2S transmitter channel.
+            /// 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data
+            /// is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
+            /// valid channel data is in 32-bit-mode.
+            TX_BITS_MOD: u5,
+            /// I2S Tx half sample bits -1.
+            TX_HALF_SAMPLE_BITS: u6,
+            /// The Tx bit number for each channel minus 1in TDM mode.
+            TX_TDM_CHAN_BITS: u5,
+            /// Set this bit to enable transmitter in Phillips standard mode
+            TX_MSB_SHIFT: u1,
+            /// 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
+            /// to generate pos/neg edge in master mode.
+            TX_BCK_NO_DLY: u1,
+            padding0: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x6002d030
+        /// I2S RX clock configure register
+        pub const RX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S clock divider value
+            RX_CLKM_DIV_NUM: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// I2S Rx module clock enable signal.
+            RX_CLK_ACTIVE: u1,
+            /// Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3:
+            /// I2S_MCLK_in.
+            RX_CLK_SEL: u2,
+            /// 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
+            /// I2S_MCLK_OUT.
+            MCLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6002d034
+        /// I2S TX clock configure register
+        pub const TX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
+            /// be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
+            /// a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+            /// (n+1)-div] + y * (n+1)-div.
+            TX_CLKM_DIV_NUM: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// I2S Tx module clock enable signal.
+            TX_CLK_ACTIVE: u1,
+            /// Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+            /// I2S_MCLK_in.
+            TX_CLK_SEL: u2,
+            /// Set this bit to enable clk gate
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x6002d038
+        /// I2S RX module clock divider configure register
+        pub const RX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+            /// I2S_RX_CLKM_DIV_Z is (a-b).
+            RX_CLKM_DIV_Z: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
+            /// of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+            RX_CLKM_DIV_Y: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
+            /// value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+            RX_CLKM_DIV_X: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+            /// I2S_RX_CLKM_DIV_YN1 is 1.
+            RX_CLKM_DIV_YN1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002d03c
+        /// I2S TX module clock divider configure register
+        pub const TX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+            /// I2S_TX_CLKM_DIV_Z is (a-b).
+            TX_CLKM_DIV_Z: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
+            /// of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+            TX_CLKM_DIV_Y: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
+            /// value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+            TX_CLKM_DIV_X: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+            /// I2S_TX_CLKM_DIV_YN1 is 1.
+            TX_CLKM_DIV_YN1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x6002d040
+        /// I2S TX PCM2PDM configuration register
+        pub const TX_PCM2PDM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// I2S TX PDM bypass hp filter or not. The option has been removed.
+            TX_PDM_HP_BYPASS: u1,
+            /// I2S TX PDM OSR2 value
+            TX_PDM_SINC_OSR2: u4,
+            /// I2S TX PDM prescale for sigmadelta
+            TX_PDM_PRESCALE: u8,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_HP_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_LP_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_SINC_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_SIGMADELTA_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta dither2 value
+            TX_PDM_SIGMADELTA_DITHER2: u1,
+            /// I2S TX PDM sigmadelta dither value
+            TX_PDM_SIGMADELTA_DITHER: u1,
+            /// I2S TX PDM dac mode enable
+            TX_PDM_DAC_2OUT_EN: u1,
+            /// I2S TX PDM dac 2channel enable
+            TX_PDM_DAC_MODE_EN: u1,
+            /// I2S TX PDM Converter enable
+            PCM2PDM_CONV_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6002d044
+        /// I2S TX PCM2PDM configuration register
+        pub const TX_PCM2PDM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// I2S TX PDM Fp
+            TX_PDM_FP: u10,
+            /// I2S TX PDM Fs
+            TX_PDM_FS: u10,
+            /// The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+            /// I2S_TX_IIR_HP_MULT12_5[2:0])
+            TX_IIR_HP_MULT12_5: u3,
+            /// The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+            /// I2S_TX_IIR_HP_MULT12_0[2:0])
+            TX_IIR_HP_MULT12_0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6002d050
+        /// I2S TX TDM mode control register
+        pub const RX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN0_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN1_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN2_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN3_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN4_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN5_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN6_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN7_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0
+            /// in this channel.
+            RX_TDM_CHAN8_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0
+            /// in this channel.
+            RX_TDM_CHAN9_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN10_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN11_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN12_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN13_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN14_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN15_EN: u1,
+            /// The total channel number of I2S TX TDM mode.
+            RX_TDM_TOT_CHAN_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6002d054
+        /// I2S TX TDM mode control register
+        pub const TX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN0_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN1_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN2_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN3_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN4_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN5_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN6_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN7_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN8_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN9_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN10_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN11_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN12_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN13_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN14_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN15_EN: u1,
+            /// The total channel number of I2S TX TDM mode.
+            TX_TDM_TOT_CHAN_NUM: u4,
+            /// When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels,
+            /// and only the data of the enabled channels is sent, then this bit should be set.
+            /// Clear it when all the data stored in DMA TX buffer is for enabled channels.
+            TX_TDM_SKIP_MSK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6002d058
+        /// I2S RX timing control register
+        pub const RX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_SD_IN_DM: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_WS_OUT_DM: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_BCK_OUT_DM: u2,
+            reserved16: u1,
+            reserved17: u1,
+            /// The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_WS_IN_DM: u2,
+            reserved18: u1,
+            reserved19: u1,
+            /// The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_BCK_IN_DM: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002d05c
+        /// I2S TX timing control register
+        pub const TX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_SD_OUT_DM: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_SD1_OUT_DM: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_WS_OUT_DM: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_BCK_OUT_DM: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_WS_IN_DM: u2,
+            reserved16: u1,
+            reserved17: u1,
+            /// The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_BCK_IN_DM: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6002d060
+        /// I2S HUNG configure register.
+        pub const LC_HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+            /// when fifo hung counter is equal to this value
+            LC_FIFO_TIMEOUT: u8,
+            /// The bits are used to scale tick counter threshold. The tick counter is reset
+            /// when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+            LC_FIFO_TIMEOUT_SHIFT: u3,
+            /// The enable bit for FIFO timeout
+            LC_FIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x6002d064
+        /// I2S RX data number control register.
+        pub const RXEOF_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) *
+            /// (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the
+            /// configured DMA RX channel.
+            RX_EOF_NUM: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x6002d068
+        /// I2S signal data register
+        pub const CONF_SIGLE_DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The configured constant channel data to be sent out.
+            SINGLE_DATA: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6002d06c
+        /// I2S TX status register
+        pub const STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: i2s_tx is idle state. 0: i2s_tx is working.
+            TX_IDLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6002d080
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x80);
+    };
+
+    /// Interrupt Core
+    pub const INTERRUPT_CORE0 = struct {
+        pub const base_address = 0x600c2000;
+
+        /// address: 0x600c2000
+        /// mac intr map register
+        pub const MAC_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x0);
+
+        /// address: 0x600c2004
+        /// mac nmi_intr map register
+        pub const MAC_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4);
+
+        /// address: 0x600c2008
+        /// pwr intr map register
+        pub const PWR_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8);
+
+        /// address: 0x600c200c
+        /// bb intr map register
+        pub const BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc);
+
+        /// address: 0x600c2010
+        /// bt intr map register
+        pub const BT_MAC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x10);
+
+        /// address: 0x600c2014
+        /// bb_bt intr map register
+        pub const BT_BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14);
+
+        /// address: 0x600c2018
+        /// bb_bt_nmi intr map register
+        pub const BT_BB_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x18);
+
+        /// address: 0x600c201c
+        /// rwbt intr map register
+        pub const RWBT_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c);
+
+        /// address: 0x600c2020
+        /// rwble intr map register
+        pub const RWBLE_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x20);
+
+        /// address: 0x600c2024
+        /// rwbt_nmi intr map register
+        pub const RWBT_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24);
+
+        /// address: 0x600c2028
+        /// rwble_nmi intr map register
+        pub const RWBLE_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x28);
+
+        /// address: 0x600c202c
+        /// i2c intr map register
+        pub const I2C_MST_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
+
+        /// address: 0x600c2030
+        /// slc0 intr map register
+        pub const SLC0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x30);
+
+        /// address: 0x600c2034
+        /// slc1 intr map register
+        pub const SLC1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x34);
+
+        /// address: 0x600c2038
+        /// apb_ctrl intr map register
+        pub const APB_CTRL_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x38);
+
+        /// address: 0x600c203c
+        /// uchi0 intr map register
+        pub const UHCI0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x3c);
+
+        /// address: 0x600c2040
+        /// gpio intr map register
+        pub const GPIO_INTERRUPT_PRO_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x40);
+
+        /// address: 0x600c2044
+        /// gpio_pro intr map register
+        pub const GPIO_INTERRUPT_PRO_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x44);
+
+        /// address: 0x600c2048
+        /// gpio_pro_nmi intr map register
+        pub const SPI_INTR_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x48);
+
+        /// address: 0x600c204c
+        /// spi1 intr map register
+        pub const SPI_INTR_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4c);
+
+        /// address: 0x600c2050
+        /// spi2 intr map register
+        pub const I2S1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x50);
+
+        /// address: 0x600c2054
+        /// i2s1 intr map register
+        pub const UART_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x54);
+
+        /// address: 0x600c2058
+        /// uart1 intr map register
+        pub const UART1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x58);
+
+        /// address: 0x600c205c
+        /// ledc intr map register
+        pub const LEDC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x5c);
+
+        /// address: 0x600c2060
+        /// efuse intr map register
+        pub const EFUSE_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x60);
+
+        /// address: 0x600c2064
+        /// can intr map register
+        pub const CAN_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x64);
+
+        /// address: 0x600c2068
+        /// usb intr map register
+        pub const USB_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x68);
+
+        /// address: 0x600c206c
+        /// rtc intr map register
+        pub const RTC_CORE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x6c);
+
+        /// address: 0x600c2070
+        /// rmt intr map register
+        pub const RMT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x70);
+
+        /// address: 0x600c2074
+        /// i2c intr map register
+        pub const I2C_EXT0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x74);
+
+        /// address: 0x600c2078
+        /// timer1 intr map register
+        pub const TIMER_INT1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x78);
+
+        /// address: 0x600c207c
+        /// timer2 intr map register
+        pub const TIMER_INT2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x7c);
+
+        /// address: 0x600c2080
+        /// tg to intr map register
+        pub const TG_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x80);
+
+        /// address: 0x600c2084
+        /// tg wdt intr map register
+        pub const TG_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x84);
+
+        /// address: 0x600c2088
+        /// tg1 to intr map register
+        pub const TG1_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x88);
+
+        /// address: 0x600c208c
+        /// tg1 wdt intr map register
+        pub const TG1_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8c);
+
+        /// address: 0x600c2090
+        /// cache ia intr map register
+        pub const CACHE_IA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x90);
+
+        /// address: 0x600c2094
+        /// systimer intr map register
+        pub const SYSTIMER_TARGET0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x94);
+
+        /// address: 0x600c2098
+        /// systimer target1 intr map register
+        pub const SYSTIMER_TARGET1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x98);
+
+        /// address: 0x600c209c
+        /// systimer target2 intr map register
+        pub const SYSTIMER_TARGET2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x9c);
+
+        /// address: 0x600c20a0
+        /// spi mem reject intr map register
+        pub const SPI_MEM_REJECT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa0);
+
+        /// address: 0x600c20a4
+        /// icache perload intr map register
+        pub const ICACHE_PRELOAD_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa4);
+
+        /// address: 0x600c20a8
+        /// icache sync intr map register
+        pub const ICACHE_SYNC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa8);
+
+        /// address: 0x600c20ac
+        /// adc intr map register
+        pub const APB_ADC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xac);
+
+        /// address: 0x600c20b0
+        /// dma ch0 intr map register
+        pub const DMA_CH0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb0);
+
+        /// address: 0x600c20b4
+        /// dma ch1 intr map register
+        pub const DMA_CH1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb4);
+
+        /// address: 0x600c20b8
+        /// dma ch2 intr map register
+        pub const DMA_CH2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb8);
+
+        /// address: 0x600c20bc
+        /// rsa intr map register
+        pub const RSA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xbc);
+
+        /// address: 0x600c20c0
+        /// aes intr map register
+        pub const AES_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc0);
+
+        /// address: 0x600c20c4
+        /// sha intr map register
+        pub const SHA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc4);
+
+        /// address: 0x600c20c8
+        /// cpu from cpu 0 intr map register
+        pub const CPU_INTR_FROM_CPU_0_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc8);
+
+        /// address: 0x600c20cc
+        /// cpu from cpu 0 intr map register
+        pub const CPU_INTR_FROM_CPU_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xcc);
+
+        /// address: 0x600c20d0
+        /// cpu from cpu 1 intr map register
+        pub const CPU_INTR_FROM_CPU_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd0);
+
+        /// address: 0x600c20d4
+        /// cpu from cpu 3 intr map register
+        pub const CPU_INTR_FROM_CPU_3_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
+
+        /// address: 0x600c20d8
+        /// assist debug intr map register
+        pub const ASSIST_DEBUG_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd8);
+
+        /// address: 0x600c20dc
+        /// dma pms violatile intr map register
+        pub const DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xdc);
+
+        /// address: 0x600c20e0
+        /// iram0 pms violatile intr map register
+        pub const CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe0);
+
+        /// address: 0x600c20e4
+        /// mac intr map register
+        pub const CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe4);
+
+        /// address: 0x600c20e8
+        /// mac intr map register
+        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe8);
+
+        /// address: 0x600c20ec
+        /// mac intr map register
+        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
+
+        /// address: 0x600c20f0
+        /// mac intr map register
+        pub const BACKUP_PMS_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf0);
+
+        /// address: 0x600c20f4
+        /// mac intr map register
+        pub const CACHE_CORE0_ACS_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf4);
+
+        /// address: 0x600c20f8
+        /// mac intr map register
+        pub const INTR_STATUS_REG_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_intr_status_0
+            INTR_STATUS_0: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c20fc
+        /// mac intr map register
+        pub const INTR_STATUS_REG_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_intr_status_1
+            INTR_STATUS_1: u32,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c2100
+        /// mac intr map register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_reg_clk_en
+            REG_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c2104
+        /// mac intr map register
+        pub const CPU_INT_ENABLE = @intToPtr(*volatile u32, base_address + 0x104);
+
+        /// address: 0x600c2108
+        /// mac intr map register
+        pub const CPU_INT_TYPE = @intToPtr(*volatile u32, base_address + 0x108);
+
+        /// address: 0x600c210c
+        /// mac intr map register
+        pub const CPU_INT_CLEAR = @intToPtr(*volatile u32, base_address + 0x10c);
+
+        /// address: 0x600c2110
+        /// mac intr map register
+        pub const CPU_INT_EIP_STATUS = @intToPtr(*volatile u32, base_address + 0x110);
+
+        /// address: 0x600c2114
+        /// mac intr map register
+        pub const CPU_INT_PRI_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_0_map
+            CPU_PRI_0_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x114);
+
+        /// address: 0x600c2118
+        /// mac intr map register
+        pub const CPU_INT_PRI_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_1_map
+            CPU_PRI_1_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x118);
+
+        /// address: 0x600c211c
+        /// mac intr map register
+        pub const CPU_INT_PRI_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_2_map
+            CPU_PRI_2_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x11c);
+
+        /// address: 0x600c2120
+        /// mac intr map register
+        pub const CPU_INT_PRI_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_3_map
+            CPU_PRI_3_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x120);
+
+        /// address: 0x600c2124
+        /// mac intr map register
+        pub const CPU_INT_PRI_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_4_map
+            CPU_PRI_4_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600c2128
+        /// mac intr map register
+        pub const CPU_INT_PRI_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_5_map
+            CPU_PRI_5_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x128);
+
+        /// address: 0x600c212c
+        /// mac intr map register
+        pub const CPU_INT_PRI_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_6_map
+            CPU_PRI_6_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x12c);
+
+        /// address: 0x600c2130
+        /// mac intr map register
+        pub const CPU_INT_PRI_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_7_map
+            CPU_PRI_7_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x600c2134
+        /// mac intr map register
+        pub const CPU_INT_PRI_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_8_map
+            CPU_PRI_8_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x600c2138
+        /// mac intr map register
+        pub const CPU_INT_PRI_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_9_map
+            CPU_PRI_9_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x600c213c
+        /// mac intr map register
+        pub const CPU_INT_PRI_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_10_map
+            CPU_PRI_10_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x13c);
+
+        /// address: 0x600c2140
+        /// mac intr map register
+        pub const CPU_INT_PRI_11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_11_map
+            CPU_PRI_11_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x600c2144
+        /// mac intr map register
+        pub const CPU_INT_PRI_12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_12_map
+            CPU_PRI_12_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x600c2148
+        /// mac intr map register
+        pub const CPU_INT_PRI_13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_13_map
+            CPU_PRI_13_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x148);
+
+        /// address: 0x600c214c
+        /// mac intr map register
+        pub const CPU_INT_PRI_14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_14_map
+            CPU_PRI_14_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x600c2150
+        /// mac intr map register
+        pub const CPU_INT_PRI_15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_15_map
+            CPU_PRI_15_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x150);
+
+        /// address: 0x600c2154
+        /// mac intr map register
+        pub const CPU_INT_PRI_16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_16_map
+            CPU_PRI_16_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x154);
+
+        /// address: 0x600c2158
+        /// mac intr map register
+        pub const CPU_INT_PRI_17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_17_map
+            CPU_PRI_17_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x600c215c
+        /// mac intr map register
+        pub const CPU_INT_PRI_18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_18_map
+            CPU_PRI_18_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x600c2160
+        /// mac intr map register
+        pub const CPU_INT_PRI_19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_19_map
+            CPU_PRI_19_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x600c2164
+        /// mac intr map register
+        pub const CPU_INT_PRI_20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_20_map
+            CPU_PRI_20_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x600c2168
+        /// mac intr map register
+        pub const CPU_INT_PRI_21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_21_map
+            CPU_PRI_21_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x600c216c
+        /// mac intr map register
+        pub const CPU_INT_PRI_22 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_22_map
+            CPU_PRI_22_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x16c);
+
+        /// address: 0x600c2170
+        /// mac intr map register
+        pub const CPU_INT_PRI_23 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_23_map
+            CPU_PRI_23_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x600c2174
+        /// mac intr map register
+        pub const CPU_INT_PRI_24 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_24_map
+            CPU_PRI_24_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x174);
+
+        /// address: 0x600c2178
+        /// mac intr map register
+        pub const CPU_INT_PRI_25 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_25_map
+            CPU_PRI_25_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x178);
+
+        /// address: 0x600c217c
+        /// mac intr map register
+        pub const CPU_INT_PRI_26 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_26_map
+            CPU_PRI_26_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x17c);
+
+        /// address: 0x600c2180
+        /// mac intr map register
+        pub const CPU_INT_PRI_27 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_27_map
+            CPU_PRI_27_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x180);
+
+        /// address: 0x600c2184
+        /// mac intr map register
+        pub const CPU_INT_PRI_28 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_28_map
+            CPU_PRI_28_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x184);
+
+        /// address: 0x600c2188
+        /// mac intr map register
+        pub const CPU_INT_PRI_29 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_29_map
+            CPU_PRI_29_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x188);
+
+        /// address: 0x600c218c
+        /// mac intr map register
+        pub const CPU_INT_PRI_30 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_30_map
+            CPU_PRI_30_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x18c);
+
+        /// address: 0x600c2190
+        /// mac intr map register
+        pub const CPU_INT_PRI_31 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_31_map
+            CPU_PRI_31_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x600c2194
+        /// mac intr map register
+        pub const CPU_INT_THRESH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x194);
+
+        /// address: 0x600c27fc
+        /// mac intr map register
+        pub const INTERRUPT_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x7fc);
+    };
+
+    /// Input/Output Multiplexer
+    pub const IO_MUX = struct {
+        pub const base_address = 0x60009000;
+
+        /// address: 0x60009000
+        /// Clock Output Configuration Register
+        pub const PIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
+            /// CLK_OUT_out1 can be found in peripheral output signals.
+            CLK_OUT1: u4,
+            /// If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
+            /// CLK_OUT_out2 can be found in peripheral output signals.
+            CLK_OUT2: u4,
+            /// If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
+            /// CLK_OUT_out3 can be found in peripheral output signals.
+            CLK_OUT3: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60009004
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60009008
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000900c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60009010
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60009014
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60009018
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000901c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60009020
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60009024
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60009028
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000902c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60009030
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60009034
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60009038
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000903c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60009040
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60009044
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60009048
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000904c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60009050
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60009054
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60009058
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600090fc
+        /// IO MUX Version Control Register
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Version control register
+            REG_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// LED Control PWM (Pulse Width Modulation)
+    pub const LEDC = struct {
+        pub const base_address = 0x60019000;
+
+        /// address: 0x60019000
+        /// LEDC_LSCH0_CONF0.
+        pub const LSCH0_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch0.
+            TIMER_SEL_LSCH0: u2,
+            /// reg_sig_out_en_lsch0.
+            SIG_OUT_EN_LSCH0: u1,
+            /// reg_idle_lv_lsch0.
+            IDLE_LV_LSCH0: u1,
+            /// reg_para_up_lsch0.
+            PARA_UP_LSCH0: u1,
+            /// reg_ovf_num_lsch0.
+            OVF_NUM_LSCH0: u10,
+            /// reg_ovf_cnt_en_lsch0.
+            OVF_CNT_EN_LSCH0: u1,
+            /// reg_ovf_cnt_reset_lsch0.
+            OVF_CNT_RESET_LSCH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60019004
+        /// LEDC_LSCH0_HPOINT.
+        pub const LSCH0_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch0.
+            HPOINT_LSCH0: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60019008
+        /// LEDC_LSCH0_DUTY.
+        pub const LSCH0_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch0.
+            DUTY_LSCH0: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001900c
+        /// LEDC_LSCH0_CONF1.
+        pub const LSCH0_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch0.
+            DUTY_SCALE_LSCH0: u10,
+            /// reg_duty_cycle_lsch0.
+            DUTY_CYCLE_LSCH0: u10,
+            /// reg_duty_num_lsch0.
+            DUTY_NUM_LSCH0: u10,
+            /// reg_duty_inc_lsch0.
+            DUTY_INC_LSCH0: u1,
+            /// reg_duty_start_lsch0.
+            DUTY_START_LSCH0: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60019010
+        /// LEDC_LSCH0_DUTY_R.
+        pub const LSCH0_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch0_r.
+            DUTY_LSCH0_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60019014
+        /// LEDC_LSCH1_CONF0.
+        pub const LSCH1_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch1.
+            TIMER_SEL_LSCH1: u2,
+            /// reg_sig_out_en_lsch1.
+            SIG_OUT_EN_LSCH1: u1,
+            /// reg_idle_lv_lsch1.
+            IDLE_LV_LSCH1: u1,
+            /// reg_para_up_lsch1.
+            PARA_UP_LSCH1: u1,
+            /// reg_ovf_num_lsch1.
+            OVF_NUM_LSCH1: u10,
+            /// reg_ovf_cnt_en_lsch1.
+            OVF_CNT_EN_LSCH1: u1,
+            /// reg_ovf_cnt_reset_lsch1.
+            OVF_CNT_RESET_LSCH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60019018
+        /// LEDC_LSCH1_HPOINT.
+        pub const LSCH1_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch1.
+            HPOINT_LSCH1: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001901c
+        /// LEDC_LSCH1_DUTY.
+        pub const LSCH1_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch1.
+            DUTY_LSCH1: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60019020
+        /// LEDC_LSCH1_CONF1.
+        pub const LSCH1_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch1.
+            DUTY_SCALE_LSCH1: u10,
+            /// reg_duty_cycle_lsch1.
+            DUTY_CYCLE_LSCH1: u10,
+            /// reg_duty_num_lsch1.
+            DUTY_NUM_LSCH1: u10,
+            /// reg_duty_inc_lsch1.
+            DUTY_INC_LSCH1: u1,
+            /// reg_duty_start_lsch1.
+            DUTY_START_LSCH1: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60019024
+        /// LEDC_LSCH1_DUTY_R.
+        pub const LSCH1_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch1_r.
+            DUTY_LSCH1_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60019028
+        /// LEDC_LSCH2_CONF0.
+        pub const LSCH2_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch2.
+            TIMER_SEL_LSCH2: u2,
+            /// reg_sig_out_en_lsch2.
+            SIG_OUT_EN_LSCH2: u1,
+            /// reg_idle_lv_lsch2.
+            IDLE_LV_LSCH2: u1,
+            /// reg_para_up_lsch2.
+            PARA_UP_LSCH2: u1,
+            /// reg_ovf_num_lsch2.
+            OVF_NUM_LSCH2: u10,
+            /// reg_ovf_cnt_en_lsch2.
+            OVF_CNT_EN_LSCH2: u1,
+            /// reg_ovf_cnt_reset_lsch2.
+            OVF_CNT_RESET_LSCH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001902c
+        /// LEDC_LSCH2_HPOINT.
+        pub const LSCH2_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch2.
+            HPOINT_LSCH2: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60019030
+        /// LEDC_LSCH2_DUTY.
+        pub const LSCH2_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch2.
+            DUTY_LSCH2: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60019034
+        /// LEDC_LSCH2_CONF1.
+        pub const LSCH2_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch2.
+            DUTY_SCALE_LSCH2: u10,
+            /// reg_duty_cycle_lsch2.
+            DUTY_CYCLE_LSCH2: u10,
+            /// reg_duty_num_lsch2.
+            DUTY_NUM_LSCH2: u10,
+            /// reg_duty_inc_lsch2.
+            DUTY_INC_LSCH2: u1,
+            /// reg_duty_start_lsch2.
+            DUTY_START_LSCH2: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60019038
+        /// LEDC_LSCH2_DUTY_R.
+        pub const LSCH2_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch2_r.
+            DUTY_LSCH2_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001903c
+        /// LEDC_LSCH3_CONF0.
+        pub const LSCH3_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch3.
+            TIMER_SEL_LSCH3: u2,
+            /// reg_sig_out_en_lsch3.
+            SIG_OUT_EN_LSCH3: u1,
+            /// reg_idle_lv_lsch3.
+            IDLE_LV_LSCH3: u1,
+            /// reg_para_up_lsch3.
+            PARA_UP_LSCH3: u1,
+            /// reg_ovf_num_lsch3.
+            OVF_NUM_LSCH3: u10,
+            /// reg_ovf_cnt_en_lsch3.
+            OVF_CNT_EN_LSCH3: u1,
+            /// reg_ovf_cnt_reset_lsch3.
+            OVF_CNT_RESET_LSCH3: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60019040
+        /// LEDC_LSCH3_HPOINT.
+        pub const LSCH3_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch3.
+            HPOINT_LSCH3: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60019044
+        /// LEDC_LSCH3_DUTY.
+        pub const LSCH3_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch3.
+            DUTY_LSCH3: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60019048
+        /// LEDC_LSCH3_CONF1.
+        pub const LSCH3_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch3.
+            DUTY_SCALE_LSCH3: u10,
+            /// reg_duty_cycle_lsch3.
+            DUTY_CYCLE_LSCH3: u10,
+            /// reg_duty_num_lsch3.
+            DUTY_NUM_LSCH3: u10,
+            /// reg_duty_inc_lsch3.
+            DUTY_INC_LSCH3: u1,
+            /// reg_duty_start_lsch3.
+            DUTY_START_LSCH3: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001904c
+        /// LEDC_LSCH3_DUTY_R.
+        pub const LSCH3_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch3_r.
+            DUTY_LSCH3_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60019050
+        /// LEDC_LSCH4_CONF0.
+        pub const LSCH4_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch4.
+            TIMER_SEL_LSCH4: u2,
+            /// reg_sig_out_en_lsch4.
+            SIG_OUT_EN_LSCH4: u1,
+            /// reg_idle_lv_lsch4.
+            IDLE_LV_LSCH4: u1,
+            /// reg_para_up_lsch4.
+            PARA_UP_LSCH4: u1,
+            /// reg_ovf_num_lsch4.
+            OVF_NUM_LSCH4: u10,
+            /// reg_ovf_cnt_en_lsch4.
+            OVF_CNT_EN_LSCH4: u1,
+            /// reg_ovf_cnt_reset_lsch4.
+            OVF_CNT_RESET_LSCH4: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60019054
+        /// LEDC_LSCH4_HPOINT.
+        pub const LSCH4_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch4.
+            HPOINT_LSCH4: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60019058
+        /// LEDC_LSCH4_DUTY.
+        pub const LSCH4_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch4.
+            DUTY_LSCH4: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001905c
+        /// LEDC_LSCH4_CONF1.
+        pub const LSCH4_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch4.
+            DUTY_SCALE_LSCH4: u10,
+            /// reg_duty_cycle_lsch4.
+            DUTY_CYCLE_LSCH4: u10,
+            /// reg_duty_num_lsch4.
+            DUTY_NUM_LSCH4: u10,
+            /// reg_duty_inc_lsch4.
+            DUTY_INC_LSCH4: u1,
+            /// reg_duty_start_lsch4.
+            DUTY_START_LSCH4: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60019060
+        /// LEDC_LSCH4_DUTY_R.
+        pub const LSCH4_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch4_r.
+            DUTY_LSCH4_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60019064
+        /// LEDC_LSCH5_CONF0.
+        pub const LSCH5_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch5.
+            TIMER_SEL_LSCH5: u2,
+            /// reg_sig_out_en_lsch5.
+            SIG_OUT_EN_LSCH5: u1,
+            /// reg_idle_lv_lsch5.
+            IDLE_LV_LSCH5: u1,
+            /// reg_para_up_lsch5.
+            PARA_UP_LSCH5: u1,
+            /// reg_ovf_num_lsch5.
+            OVF_NUM_LSCH5: u10,
+            /// reg_ovf_cnt_en_lsch5.
+            OVF_CNT_EN_LSCH5: u1,
+            /// reg_ovf_cnt_reset_lsch5.
+            OVF_CNT_RESET_LSCH5: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60019068
+        /// LEDC_LSCH5_HPOINT.
+        pub const LSCH5_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch5.
+            HPOINT_LSCH5: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001906c
+        /// LEDC_LSCH5_DUTY.
+        pub const LSCH5_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch5.
+            DUTY_LSCH5: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60019070
+        /// LEDC_LSCH5_CONF1.
+        pub const LSCH5_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch5.
+            DUTY_SCALE_LSCH5: u10,
+            /// reg_duty_cycle_lsch5.
+            DUTY_CYCLE_LSCH5: u10,
+            /// reg_duty_num_lsch5.
+            DUTY_NUM_LSCH5: u10,
+            /// reg_duty_inc_lsch5.
+            DUTY_INC_LSCH5: u1,
+            /// reg_duty_start_lsch5.
+            DUTY_START_LSCH5: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60019074
+        /// LEDC_LSCH5_DUTY_R.
+        pub const LSCH5_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch5_r.
+            DUTY_LSCH5_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600190a0
+        /// LEDC_LSTIMER0_CONF.
+        pub const LSTIMER0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_duty_res.
+            LSTIMER0_DUTY_RES: u4,
+            /// reg_clk_div_lstimer0.
+            CLK_DIV_LSTIMER0: u18,
+            /// reg_lstimer0_pause.
+            LSTIMER0_PAUSE: u1,
+            /// reg_lstimer0_rst.
+            LSTIMER0_RST: u1,
+            /// reg_tick_sel_lstimer0.
+            TICK_SEL_LSTIMER0: u1,
+            /// reg_lstimer0_para_up.
+            LSTIMER0_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600190a4
+        /// LEDC_LSTIMER0_VALUE.
+        pub const LSTIMER0_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_cnt.
+            LSTIMER0_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600190a8
+        /// LEDC_LSTIMER1_CONF.
+        pub const LSTIMER1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer1_duty_res.
+            LSTIMER1_DUTY_RES: u4,
+            /// reg_clk_div_lstimer1.
+            CLK_DIV_LSTIMER1: u18,
+            /// reg_lstimer1_pause.
+            LSTIMER1_PAUSE: u1,
+            /// reg_lstimer1_rst.
+            LSTIMER1_RST: u1,
+            /// reg_tick_sel_lstimer1.
+            TICK_SEL_LSTIMER1: u1,
+            /// reg_lstimer1_para_up.
+            LSTIMER1_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600190ac
+        /// LEDC_LSTIMER1_VALUE.
+        pub const LSTIMER1_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer1_cnt.
+            LSTIMER1_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600190b0
+        /// LEDC_LSTIMER2_CONF.
+        pub const LSTIMER2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer2_duty_res.
+            LSTIMER2_DUTY_RES: u4,
+            /// reg_clk_div_lstimer2.
+            CLK_DIV_LSTIMER2: u18,
+            /// reg_lstimer2_pause.
+            LSTIMER2_PAUSE: u1,
+            /// reg_lstimer2_rst.
+            LSTIMER2_RST: u1,
+            /// reg_tick_sel_lstimer2.
+            TICK_SEL_LSTIMER2: u1,
+            /// reg_lstimer2_para_up.
+            LSTIMER2_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600190b4
+        /// LEDC_LSTIMER2_VALUE.
+        pub const LSTIMER2_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer2_cnt.
+            LSTIMER2_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600190b8
+        /// LEDC_LSTIMER3_CONF.
+        pub const LSTIMER3_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer3_duty_res.
+            LSTIMER3_DUTY_RES: u4,
+            /// reg_clk_div_lstimer3.
+            CLK_DIV_LSTIMER3: u18,
+            /// reg_lstimer3_pause.
+            LSTIMER3_PAUSE: u1,
+            /// reg_lstimer3_rst.
+            LSTIMER3_RST: u1,
+            /// reg_tick_sel_lstimer3.
+            TICK_SEL_LSTIMER3: u1,
+            /// reg_lstimer3_para_up.
+            LSTIMER3_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600190bc
+        /// LEDC_LSTIMER3_VALUE.
+        pub const LSTIMER3_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer3_cnt.
+            LSTIMER3_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600190c0
+        /// LEDC_INT_RAW.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_raw.
+            LSTIMER0_OVF_INT_RAW: u1,
+            /// reg_lstimer1_ovf_int_raw.
+            LSTIMER1_OVF_INT_RAW: u1,
+            /// reg_lstimer2_ovf_int_raw.
+            LSTIMER2_OVF_INT_RAW: u1,
+            /// reg_lstimer3_ovf_int_raw.
+            LSTIMER3_OVF_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch0_int_raw.
+            DUTY_CHNG_END_LSCH0_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch1_int_raw.
+            DUTY_CHNG_END_LSCH1_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch2_int_raw.
+            DUTY_CHNG_END_LSCH2_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch3_int_raw.
+            DUTY_CHNG_END_LSCH3_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch4_int_raw.
+            DUTY_CHNG_END_LSCH4_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch5_int_raw.
+            DUTY_CHNG_END_LSCH5_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch0_int_raw.
+            OVF_CNT_LSCH0_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch1_int_raw.
+            OVF_CNT_LSCH1_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch2_int_raw.
+            OVF_CNT_LSCH2_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch3_int_raw.
+            OVF_CNT_LSCH3_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch4_int_raw.
+            OVF_CNT_LSCH4_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch5_int_raw.
+            OVF_CNT_LSCH5_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600190c4
+        /// LEDC_INT_ST.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_st.
+            LSTIMER0_OVF_INT_ST: u1,
+            /// reg_lstimer1_ovf_int_st.
+            LSTIMER1_OVF_INT_ST: u1,
+            /// reg_lstimer2_ovf_int_st.
+            LSTIMER2_OVF_INT_ST: u1,
+            /// reg_lstimer3_ovf_int_st.
+            LSTIMER3_OVF_INT_ST: u1,
+            /// reg_duty_chng_end_lsch0_int_st.
+            DUTY_CHNG_END_LSCH0_INT_ST: u1,
+            /// reg_duty_chng_end_lsch1_int_st.
+            DUTY_CHNG_END_LSCH1_INT_ST: u1,
+            /// reg_duty_chng_end_lsch2_int_st.
+            DUTY_CHNG_END_LSCH2_INT_ST: u1,
+            /// reg_duty_chng_end_lsch3_int_st.
+            DUTY_CHNG_END_LSCH3_INT_ST: u1,
+            /// reg_duty_chng_end_lsch4_int_st.
+            DUTY_CHNG_END_LSCH4_INT_ST: u1,
+            /// reg_duty_chng_end_lsch5_int_st.
+            DUTY_CHNG_END_LSCH5_INT_ST: u1,
+            /// reg_ovf_cnt_lsch0_int_st.
+            OVF_CNT_LSCH0_INT_ST: u1,
+            /// reg_ovf_cnt_lsch1_int_st.
+            OVF_CNT_LSCH1_INT_ST: u1,
+            /// reg_ovf_cnt_lsch2_int_st.
+            OVF_CNT_LSCH2_INT_ST: u1,
+            /// reg_ovf_cnt_lsch3_int_st.
+            OVF_CNT_LSCH3_INT_ST: u1,
+            /// reg_ovf_cnt_lsch4_int_st.
+            OVF_CNT_LSCH4_INT_ST: u1,
+            /// reg_ovf_cnt_lsch5_int_st.
+            OVF_CNT_LSCH5_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600190c8
+        /// LEDC_INT_ENA.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_ena.
+            LSTIMER0_OVF_INT_ENA: u1,
+            /// reg_lstimer1_ovf_int_ena.
+            LSTIMER1_OVF_INT_ENA: u1,
+            /// reg_lstimer2_ovf_int_ena.
+            LSTIMER2_OVF_INT_ENA: u1,
+            /// reg_lstimer3_ovf_int_ena.
+            LSTIMER3_OVF_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch0_int_ena.
+            DUTY_CHNG_END_LSCH0_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch1_int_ena.
+            DUTY_CHNG_END_LSCH1_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch2_int_ena.
+            DUTY_CHNG_END_LSCH2_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch3_int_ena.
+            DUTY_CHNG_END_LSCH3_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch4_int_ena.
+            DUTY_CHNG_END_LSCH4_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch5_int_ena.
+            DUTY_CHNG_END_LSCH5_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch0_int_ena.
+            OVF_CNT_LSCH0_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch1_int_ena.
+            OVF_CNT_LSCH1_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch2_int_ena.
+            OVF_CNT_LSCH2_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch3_int_ena.
+            OVF_CNT_LSCH3_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch4_int_ena.
+            OVF_CNT_LSCH4_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch5_int_ena.
+            OVF_CNT_LSCH5_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600190cc
+        /// LEDC_INT_CLR.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_clr.
+            LSTIMER0_OVF_INT_CLR: u1,
+            /// reg_lstimer1_ovf_int_clr.
+            LSTIMER1_OVF_INT_CLR: u1,
+            /// reg_lstimer2_ovf_int_clr.
+            LSTIMER2_OVF_INT_CLR: u1,
+            /// reg_lstimer3_ovf_int_clr.
+            LSTIMER3_OVF_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch0_int_clr.
+            DUTY_CHNG_END_LSCH0_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch1_int_clr.
+            DUTY_CHNG_END_LSCH1_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch2_int_clr.
+            DUTY_CHNG_END_LSCH2_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch3_int_clr.
+            DUTY_CHNG_END_LSCH3_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch4_int_clr.
+            DUTY_CHNG_END_LSCH4_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch5_int_clr.
+            DUTY_CHNG_END_LSCH5_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch0_int_clr.
+            OVF_CNT_LSCH0_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch1_int_clr.
+            OVF_CNT_LSCH1_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch2_int_clr.
+            OVF_CNT_LSCH2_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch3_int_clr.
+            OVF_CNT_LSCH3_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch4_int_clr.
+            OVF_CNT_LSCH4_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch5_int_clr.
+            OVF_CNT_LSCH5_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600190d0
+        /// LEDC_CONF.
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_apb_clk_sel.
+            APB_CLK_SEL: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600190fc
+        /// LEDC_DATE.
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ledc_date.
+            LEDC_DATE: u32,
+        }), base_address + 0xfc);
+    };
+
+    /// Remote Control Peripheral
+    pub const RMT = struct {
+        pub const base_address = 0x60016000;
+
+        /// address: 0x60016000
+        /// RMT_CH0DATA_REG.
+        pub const CH0DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60016004
+        /// RMT_CH1DATA_REG.
+        pub const CH1DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60016008
+        /// RMT_CH2DATA_REG.
+        pub const CH2DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x8);
+
+        /// address: 0x6001600c
+        /// RMT_CH3DATA_REG.
+        pub const CH3DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0xc);
+
+        /// address: 0x60016010
+        /// RMT_CH%sCONF%s_REG.
+        pub const CH0_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_tx_start_ch0.
+            TX_START: u1,
+            /// reg_mem_rd_rst_ch0.
+            MEM_RD_RST: u1,
+            /// reg_apb_mem_rst_ch0.
+            APB_MEM_RST: u1,
+            /// reg_tx_conti_mode_ch0.
+            TX_CONTI_MODE: u1,
+            /// reg_mem_tx_wrap_en_ch0.
+            MEM_TX_WRAP_EN: u1,
+            /// reg_idle_out_lv_ch0.
+            IDLE_OUT_LV: u1,
+            /// reg_idle_out_en_ch0.
+            IDLE_OUT_EN: u1,
+            /// reg_tx_stop_ch0.
+            TX_STOP: u1,
+            /// reg_div_cnt_ch0.
+            DIV_CNT: u8,
+            /// reg_mem_size_ch0.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            /// reg_carrier_eff_en_ch0.
+            CARRIER_EFF_EN: u1,
+            /// reg_carrier_en_ch0.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch0.
+            CARRIER_OUT_LV: u1,
+            /// reg_afifo_rst_ch0.
+            AFIFO_RST: u1,
+            /// reg_reg_conf_update_ch0.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60016014
+        /// RMT_CH%sCONF%s_REG.
+        pub const CH1_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_tx_start_ch0.
+            TX_START: u1,
+            /// reg_mem_rd_rst_ch0.
+            MEM_RD_RST: u1,
+            /// reg_apb_mem_rst_ch0.
+            APB_MEM_RST: u1,
+            /// reg_tx_conti_mode_ch0.
+            TX_CONTI_MODE: u1,
+            /// reg_mem_tx_wrap_en_ch0.
+            MEM_TX_WRAP_EN: u1,
+            /// reg_idle_out_lv_ch0.
+            IDLE_OUT_LV: u1,
+            /// reg_idle_out_en_ch0.
+            IDLE_OUT_EN: u1,
+            /// reg_tx_stop_ch0.
+            TX_STOP: u1,
+            /// reg_div_cnt_ch0.
+            DIV_CNT: u8,
+            /// reg_mem_size_ch0.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            /// reg_carrier_eff_en_ch0.
+            CARRIER_EFF_EN: u1,
+            /// reg_carrier_en_ch0.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch0.
+            CARRIER_OUT_LV: u1,
+            /// reg_afifo_rst_ch0.
+            AFIFO_RST: u1,
+            /// reg_reg_conf_update_ch0.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60016018
+        /// RMT_CH2CONF0_REG.
+        pub const CH2_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_div_cnt_ch2.
+            DIV_CNT: u8,
+            /// reg_idle_thres_ch2.
+            IDLE_THRES: u15,
+            /// reg_mem_size_ch2.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_carrier_en_ch2.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch2.
+            CARRIER_OUT_LV: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x60016020
+        /// RMT_CH2CONF0_REG.
+        pub const CH3_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_div_cnt_ch2.
+            DIV_CNT: u8,
+            /// reg_idle_thres_ch2.
+            IDLE_THRES: u15,
+            /// reg_mem_size_ch2.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_carrier_en_ch2.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch2.
+            CARRIER_OUT_LV: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6001601c
+        /// RMT_CH2CONF1_REG.
+        pub const CH2CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rx_en_ch2.
+            RX_EN: u1,
+            /// reg_mem_wr_rst_ch2.
+            MEM_WR_RST: u1,
+            /// reg_apb_mem_rst_ch2.
+            APB_MEM_RST: u1,
+            /// reg_mem_owner_ch2.
+            MEM_OWNER: u1,
+            /// reg_rx_filter_en_ch2.
+            RX_FILTER_EN: u1,
+            /// reg_rx_filter_thres_ch2.
+            RX_FILTER_THRES: u8,
+            /// reg_mem_rx_wrap_en_ch2.
+            MEM_RX_WRAP_EN: u1,
+            /// reg_afifo_rst_ch2.
+            AFIFO_RST: u1,
+            /// reg_conf_update_ch2.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60016024
+        /// RMT_CH3CONF1_REG.
+        pub const CH3CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rx_en_ch3.
+            RX_EN: u1,
+            /// reg_mem_wr_rst_ch3.
+            MEM_WR_RST: u1,
+            /// reg_apb_mem_rst_ch3.
+            APB_MEM_RST: u1,
+            /// reg_mem_owner_ch3.
+            MEM_OWNER: u1,
+            /// reg_rx_filter_en_ch3.
+            RX_FILTER_EN: u1,
+            /// reg_rx_filter_thres_ch3.
+            RX_FILTER_THRES: u8,
+            /// reg_mem_rx_wrap_en_ch3.
+            MEM_RX_WRAP_EN: u1,
+            /// reg_afifo_rst_ch3.
+            AFIFO_RST: u1,
+            /// reg_conf_update_ch3.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60016028
+        /// RMT_CH0STATUS_REG.
+        pub const CH0STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_raddr_ex_ch0.
+            MEM_RADDR_EX: u9,
+            /// reg_state_ch0.
+            STATE: u3,
+            /// reg_apb_mem_waddr_ch0.
+            APB_MEM_WADDR: u9,
+            /// reg_apb_mem_rd_err_ch0.
+            APB_MEM_RD_ERR: u1,
+            /// reg_mem_empty_ch0.
+            MEM_EMPTY: u1,
+            /// reg_apb_mem_wr_err_ch0.
+            APB_MEM_WR_ERR: u1,
+            /// reg_apb_mem_raddr_ch0.
+            APB_MEM_RADDR: u8,
+        }), base_address + 0x28);
+
+        /// address: 0x6001602c
+        /// RMT_CH1STATUS_REG.
+        pub const CH1STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_raddr_ex_ch1.
+            MEM_RADDR_EX: u9,
+            /// reg_state_ch1.
+            STATE: u3,
+            /// reg_apb_mem_waddr_ch1.
+            APB_MEM_WADDR: u9,
+            /// reg_apb_mem_rd_err_ch1.
+            APB_MEM_RD_ERR: u1,
+            /// reg_mem_empty_ch1.
+            MEM_EMPTY: u1,
+            /// reg_apb_mem_wr_err_ch1.
+            APB_MEM_WR_ERR: u1,
+            /// reg_apb_mem_raddr_ch1.
+            APB_MEM_RADDR: u8,
+        }), base_address + 0x2c);
+
+        /// address: 0x60016030
+        /// RMT_CH2STATUS_REG.
+        pub const CH2STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_waddr_ex_ch2.
+            MEM_WADDR_EX: u9,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_apb_mem_raddr_ch2.
+            APB_MEM_RADDR: u9,
+            reserved3: u1,
+            /// reg_state_ch2.
+            STATE: u3,
+            /// reg_mem_owner_err_ch2.
+            MEM_OWNER_ERR: u1,
+            /// reg_mem_full_ch2.
+            MEM_FULL: u1,
+            /// reg_apb_mem_rd_err_ch2.
+            APB_MEM_RD_ERR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60016034
+        /// RMT_CH3STATUS_REG.
+        pub const CH3STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_waddr_ex_ch3.
+            MEM_WADDR_EX: u9,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_apb_mem_raddr_ch3.
+            APB_MEM_RADDR: u9,
+            reserved3: u1,
+            /// reg_state_ch3.
+            STATE: u3,
+            /// reg_mem_owner_err_ch3.
+            MEM_OWNER_ERR: u1,
+            /// reg_mem_full_ch3.
+            MEM_FULL: u1,
+            /// reg_apb_mem_rd_err_ch3.
+            APB_MEM_RD_ERR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60016038
+        /// RMT_INT_RAW_REG.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_RAW: u1,
+            CH1_TX_END_INT_RAW: u1,
+            CH2_RX_END_INT_RAW: u1,
+            CH3_RX_END_INT_RAW: u1,
+            CH0_TX_ERR_INT_RAW: u1,
+            CH1_TX_ERR_INT_RAW: u1,
+            CH2_RX_ERR_INT_RAW: u1,
+            CH3_RX_ERR_INT_RAW: u1,
+            CH0_TX_THR_EVENT_INT_RAW: u1,
+            CH1_TX_THR_EVENT_INT_RAW: u1,
+            /// reg_ch2_rx_thr_event_int_raw.
+            CH2_RX_THR_EVENT_INT_RAW: u1,
+            /// reg_ch3_rx_thr_event_int_raw.
+            CH3_RX_THR_EVENT_INT_RAW: u1,
+            CH0_TX_LOOP_INT_RAW: u1,
+            CH1_TX_LOOP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001603c
+        /// RMT_INT_ST_REG.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_ST: u1,
+            CH1_TX_END_INT_ST: u1,
+            CH2_RX_END_INT_ST: u1,
+            CH3_RX_END_INT_ST: u1,
+            CH0_TX_ERR_INT_ST: u1,
+            CH1_TX_ERR_INT_ST: u1,
+            CH2_RX_ERR_INT_ST: u1,
+            CH3_RX_ERR_INT_ST: u1,
+            CH0_TX_THR_EVENT_INT_ST: u1,
+            CH1_TX_THR_EVENT_INT_ST: u1,
+            /// reg_ch2_rx_thr_event_int_st.
+            CH2_RX_THR_EVENT_INT_ST: u1,
+            /// reg_ch3_rx_thr_event_int_st.
+            CH3_RX_THR_EVENT_INT_ST: u1,
+            CH0_TX_LOOP_INT_ST: u1,
+            CH1_TX_LOOP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60016040
+        /// RMT_INT_ENA_REG.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_ENA: u1,
+            CH1_TX_END_INT_ENA: u1,
+            CH2_RX_END_INT_ENA: u1,
+            CH3_RX_END_INT_ENA: u1,
+            CH0_TX_ERR_INT_ENA: u1,
+            CH1_TX_ERR_INT_ENA: u1,
+            CH2_RX_ERR_INT_ENA: u1,
+            CH3_RX_ERR_INT_ENA: u1,
+            CH0_TX_THR_EVENT_INT_ENA: u1,
+            CH1_TX_THR_EVENT_INT_ENA: u1,
+            /// reg_ch2_rx_thr_event_int_ena.
+            CH2_RX_THR_EVENT_INT_ENA: u1,
+            /// reg_ch3_rx_thr_event_int_ena.
+            CH3_RX_THR_EVENT_INT_ENA: u1,
+            CH0_TX_LOOP_INT_ENA: u1,
+            CH1_TX_LOOP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60016044
+        /// RMT_INT_CLR_REG.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_CLR: u1,
+            CH1_TX_END_INT_CLR: u1,
+            CH2_RX_END_INT_CLR: u1,
+            CH3_RX_END_INT_CLR: u1,
+            CH0_TX_ERR_INT_CLR: u1,
+            CH1_TX_ERR_INT_CLR: u1,
+            CH2_RX_ERR_INT_CLR: u1,
+            CH3_RX_ERR_INT_CLR: u1,
+            CH0_TX_THR_EVENT_INT_CLR: u1,
+            CH1_TX_THR_EVENT_INT_CLR: u1,
+            /// reg_ch2_rx_thr_event_int_clr.
+            CH2_RX_THR_EVENT_INT_CLR: u1,
+            /// reg_ch3_rx_thr_event_int_clr.
+            CH3_RX_THR_EVENT_INT_CLR: u1,
+            CH0_TX_LOOP_INT_CLR: u1,
+            CH1_TX_LOOP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60016048
+        /// RMT_CH0CARRIER_DUTY_REG.
+        pub const CH0CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_ch0.
+            CARRIER_LOW: u16,
+            /// reg_carrier_high_ch0.
+            CARRIER_HIGH: u16,
+        }), base_address + 0x48);
+
+        /// address: 0x6001604c
+        /// RMT_CH1CARRIER_DUTY_REG.
+        pub const CH1CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_ch1.
+            CARRIER_LOW: u16,
+            /// reg_carrier_high_ch1.
+            CARRIER_HIGH: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x60016050
+        /// RMT_CH2_RX_CARRIER_RM_REG.
+        pub const CH2_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_thres_ch2.
+            CARRIER_LOW_THRES: u16,
+            /// reg_carrier_high_thres_ch2.
+            CARRIER_HIGH_THRES: u16,
+        }), base_address + 0x50);
+
+        /// address: 0x60016054
+        /// RMT_CH3_RX_CARRIER_RM_REG.
+        pub const CH3_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_thres_ch3.
+            CARRIER_LOW_THRES: u16,
+            /// reg_carrier_high_thres_ch3.
+            CARRIER_HIGH_THRES: u16,
+        }), base_address + 0x54);
+
+        /// address: 0x60016058
+        /// RMT_CH%s_TX_LIM_REG.
+        pub const CH0_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_lim_ch0.
+            TX_LIM: u9,
+            /// reg_rmt_tx_loop_num_ch0.
+            TX_LOOP_NUM: u10,
+            /// reg_rmt_tx_loop_cnt_en_ch0.
+            TX_LOOP_CNT_EN: u1,
+            /// reg_loop_count_reset_ch0.
+            LOOP_COUNT_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001605c
+        /// RMT_CH%s_TX_LIM_REG.
+        pub const CH1_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_lim_ch0.
+            TX_LIM: u9,
+            /// reg_rmt_tx_loop_num_ch0.
+            TX_LOOP_NUM: u10,
+            /// reg_rmt_tx_loop_cnt_en_ch0.
+            TX_LOOP_CNT_EN: u1,
+            /// reg_loop_count_reset_ch0.
+            LOOP_COUNT_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60016060
+        /// RMT_CH2_RX_LIM_REG.
+        pub const CH2_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_rx_lim_ch2.
+            RX_LIM: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60016064
+        /// RMT_CH2_RX_LIM_REG.
+        pub const CH3_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_rx_lim_ch2.
+            RX_LIM: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60016068
+        /// RMT_SYS_CONF_REG.
+        pub const SYS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_apb_fifo_mask.
+            APB_FIFO_MASK: u1,
+            /// reg_mem_clk_force_on.
+            MEM_CLK_FORCE_ON: u1,
+            /// reg_rmt_mem_force_pd.
+            MEM_FORCE_PD: u1,
+            /// reg_rmt_mem_force_pu.
+            MEM_FORCE_PU: u1,
+            /// reg_rmt_sclk_div_num.
+            SCLK_DIV_NUM: u8,
+            /// reg_rmt_sclk_div_a.
+            SCLK_DIV_A: u6,
+            /// reg_rmt_sclk_div_b.
+            SCLK_DIV_B: u6,
+            /// reg_rmt_sclk_sel.
+            SCLK_SEL: u2,
+            /// reg_rmt_sclk_active.
+            SCLK_ACTIVE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001606c
+        /// RMT_TX_SIM_REG.
+        pub const TX_SIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_sim_ch0.
+            TX_SIM_CH0: u1,
+            /// reg_rmt_tx_sim_ch1.
+            TX_SIM_CH1: u1,
+            /// reg_rmt_tx_sim_en.
+            TX_SIM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60016070
+        /// RMT_REF_CNT_RST_REG.
+        pub const REF_CNT_RST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ref_cnt_rst_ch0.
+            CH0: u1,
+            /// reg_ref_cnt_rst_ch1.
+            CH1: u1,
+            /// reg_ref_cnt_rst_ch2.
+            CH2: u1,
+            /// reg_ref_cnt_rst_ch3.
+            CH3: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600160cc
+        /// RMT_DATE_REG.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xcc);
+    };
+
+    /// Hardware random number generator
+    pub const RNG = struct {
+        pub const base_address = 0x60026000;
+
+        /// address: 0x600260b0
+        /// Random number data
+        pub const DATA = @intToPtr(*volatile u32, base_address + 0xb0);
+    };
+
+    /// RSA (Rivest Shamir Adleman) Accelerator
+    pub const RSA = struct {
+        pub const base_address = 0x6003c000;
+
+        /// address: 0x6003c000
+        /// The memory that stores M
+        pub const M_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
+
+        /// address: 0x6003c200
+        /// The memory that stores Z
+        pub const Z_MEM = @intToPtr(*volatile [16]u8, base_address + 0x200);
+
+        /// address: 0x6003c400
+        /// The memory that stores Y
+        pub const Y_MEM = @intToPtr(*volatile [16]u8, base_address + 0x400);
+
+        /// address: 0x6003c600
+        /// The memory that stores X
+        pub const X_MEM = @intToPtr(*volatile [16]u8, base_address + 0x600);
+
+        /// address: 0x6003c800
+        /// RSA M_prime register
+        pub const M_PRIME = @intToPtr(*volatile u32, base_address + 0x800);
+
+        /// address: 0x6003c804
+        /// RSA mode register
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x804);
+
+        /// address: 0x6003c808
+        /// RSA query clean register
+        pub const QUERY_CLEAN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x808);
+
+        /// address: 0x6003c80c
+        /// RSA modular exponentiation trigger register.
+        pub const SET_START_MODEXP = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x80c);
+
+        /// address: 0x6003c810
+        /// RSA modular multiplication trigger register.
+        pub const SET_START_MODMULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x810);
+
+        /// address: 0x6003c814
+        /// RSA normal multiplication trigger register.
+        pub const SET_START_MULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x814);
+
+        /// address: 0x6003c818
+        /// RSA query idle register
+        pub const QUERY_IDLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x818);
+
+        /// address: 0x6003c81c
+        /// RSA interrupt clear register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this bit to clear RSA interrupt.
+            CLEAR_INTERRUPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x81c);
+
+        /// address: 0x6003c820
+        /// RSA constant time option register
+        pub const CONSTANT_TIME = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x820);
+
+        /// address: 0x6003c824
+        /// RSA search option
+        pub const SEARCH_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x824);
+
+        /// address: 0x6003c828
+        /// RSA search position configure register
+        pub const SEARCH_POS = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x828);
+
+        /// address: 0x6003c82c
+        /// RSA interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x82c);
+
+        /// address: 0x6003c830
+        /// RSA version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x830);
+    };
+
+    /// Real-Time Clock Control
+    pub const RTC_CNTL = struct {
+        pub const base_address = 0x60008000;
+
+        /// address: 0x60008000
+        /// rtc configure register
+        pub const OPTIONS0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall
+            /// APP CPU
+            SW_STALL_APPCPU_C0: u2,
+            /// {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall
+            /// PRO CPU
+            SW_STALL_PROCPU_C0: u2,
+            /// APP CPU SW reset
+            SW_APPCPU_RST: u1,
+            /// PRO CPU SW reset
+            SW_PROCPU_RST: u1,
+            /// BB_I2C force power down
+            BB_I2C_FORCE_PD: u1,
+            /// BB_I2C force power up
+            BB_I2C_FORCE_PU: u1,
+            /// BB_PLL _I2C force power down
+            BBPLL_I2C_FORCE_PD: u1,
+            /// BB_PLL_I2C force power up
+            BBPLL_I2C_FORCE_PU: u1,
+            /// BB_PLL force power down
+            BBPLL_FORCE_PD: u1,
+            /// BB_PLL force power up
+            BBPLL_FORCE_PU: u1,
+            /// crystall force power down
+            XTL_FORCE_PD: u1,
+            /// crystall force power up
+            XTL_FORCE_PU: u1,
+            /// wait bias_sleep and current source wakeup
+            XTL_EN_WAIT: u4,
+            reserved0: u1,
+            reserved1: u1,
+            /// analog configure
+            XTL_EXT_CTR_SEL: u3,
+            /// analog configure
+            XTL_FORCE_ISO: u1,
+            /// analog configure
+            PLL_FORCE_ISO: u1,
+            /// analog configure
+            ANALOG_FORCE_ISO: u1,
+            /// analog configure
+            XTL_FORCE_NOISO: u1,
+            /// analog configure
+            PLL_FORCE_NOISO: u1,
+            /// analog configure
+            ANALOG_FORCE_NOISO: u1,
+            /// digital wrap force reset in deep sleep
+            DG_WRAP_FORCE_RST: u1,
+            /// digital core force no reset in deep sleep
+            DG_WRAP_FORCE_NORST: u1,
+            /// SW system reset
+            SW_SYS_RST: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60008004
+        /// rtc configure register
+        pub const SLP_TIMER0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure the sleep time
+            SLP_VAL_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60008008
+        /// rtc configure register
+        pub const SLP_TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC sleep timer high 16 bits
+            SLP_VAL_HI: u16,
+            /// timer alarm enable bit
+            RTC_MAIN_TIMER_ALARM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000800c
+        /// rtc configure register
+        pub const TIME_UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// Enable to record system stall time
+            TIMER_SYS_STALL: u1,
+            /// Enable to record 40M XTAL OFF time
+            TIMER_XTL_OFF: u1,
+            /// enable to record system reset time
+            TIMER_SYS_RST: u1,
+            reserved27: u1,
+            /// Set 1: to update register with RTC timer
+            RTC_TIME_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60008010
+        /// rtc configure register
+        pub const TIME_LOW0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer low 32 bits
+            RTC_TIMER_VALUE0_LOW: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60008014
+        /// rtc configure register
+        pub const TIME_HIGH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer high 16 bits
+            RTC_TIMER_VALUE0_HIGH: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60008018
+        /// rtc configure register
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc software interrupt to main cpu
+            RTC_SW_CPU_INT: u1,
+            /// clear rtc sleep reject cause
+            RTC_SLP_REJECT_CAUSE_CLR: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// 1: APB to RTC using bridge
+            APB2RTC_BRIDGE_SEL: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            /// SDIO active indication
+            SDIO_ACTIVE_IND: u1,
+            /// leep wakeup bit
+            SLP_WAKEUP: u1,
+            /// leep reject bit
+            SLP_REJECT: u1,
+            /// sleep enable bit
+            SLEEP_EN: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000801c
+        /// rtc configure register
+        pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// CPU stall enable bit
+            CPU_STALL_EN: u1,
+            /// CPU stall wait cycles in fast_clk_rtc
+            CPU_STALL_WAIT: u5,
+            /// CK8M wait cycles in slow_clk_rtc
+            CK8M_WAIT: u8,
+            /// XTAL wait cycles in slow_clk_rtc
+            XTL_BUF_WAIT: u10,
+            /// PLL wait cycles in slow_clk_rtc
+            PLL_BUF_WAIT: u8,
+        }), base_address + 0x1c);
+
+        /// address: 0x60008020
+        /// rtc configure register
+        pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            /// minimal cycles in slow_clk_rtc for CK8M in power down state
+            MIN_TIME_CK8M_OFF: u8,
+        }), base_address + 0x20);
+
+        /// address: 0x60008024
+        /// rtc configure register
+        pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wifi power domain wakeup time
+            WIFI_WAIT_TIMER: u9,
+            /// wifi power domain power on time
+            WIFI_POWERUP_TIMER: u7,
+            /// bt power domain wakeup time
+            BT_WAIT_TIMER: u9,
+            /// bt power domain power on time
+            BT_POWERUP_TIMER: u7,
+        }), base_address + 0x24);
+
+        /// address: 0x60008028
+        /// rtc configure register
+        pub const TIMER4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cpu top power domain wakeup time
+            CPU_TOP_WAIT_TIMER: u9,
+            /// cpu top power domain power on time
+            CPU_TOP_POWERUP_TIMER: u7,
+            /// digital wrap power domain wakeup time
+            DG_WRAP_WAIT_TIMER: u9,
+            /// digital wrap power domain power on time
+            DG_WRAP_POWERUP_TIMER: u7,
+        }), base_address + 0x28);
+
+        /// address: 0x6000802c
+        /// rtc configure register
+        pub const TIMER5 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// minimal sleep cycles in slow_clk_rtc
+            MIN_SLP_VAL: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60008030
+        /// rtc configure register
+        pub const TIMER6 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// digital peri power domain wakeup time
+            DG_PERI_WAIT_TIMER: u9,
+            /// digital peri power domain power on time
+            DG_PERI_POWERUP_TIMER: u7,
+        }), base_address + 0x30);
+
+        /// address: 0x60008034
+        /// rtc configure register
+        pub const ANA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// force no bypass i2c power on reset
+            RESET_POR_FORCE_PD: u1,
+            /// force bypass i2c power on reset
+            RESET_POR_FORCE_PU: u1,
+            /// enable glitch reset
+            GLITCH_RST_EN: u1,
+            reserved18: u1,
+            /// PLLA force power up
+            SAR_I2C_PU: u1,
+            /// PLLA force power down
+            PLLA_FORCE_PD: u1,
+            /// PLLA force power up
+            PLLA_FORCE_PU: u1,
+            /// start BBPLL calibration during sleep
+            BBPLL_CAL_SLP_START: u1,
+            /// 1: PVTMON power up
+            PVTMON_PU: u1,
+            /// 1: TXRF_I2C power up
+            TXRF_I2C_PU: u1,
+            /// 1: RFRX_PBUS power up
+            RFRX_PBUS_PU: u1,
+            reserved19: u1,
+            /// 1: CKGEN_I2C power up
+            CKGEN_I2C_PU: u1,
+            /// power up pll i2c
+            PLL_I2C_PU: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60008038
+        /// rtc configure register
+        pub const RESET_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reset cause of PRO CPU
+            RESET_CAUSE_PROCPU: u6,
+            /// reset cause of APP CPU
+            RESET_CAUSE_APPCPU: u6,
+            /// APP CPU state vector sel
+            STAT_VECTOR_SEL_APPCPU: u1,
+            /// PRO CPU state vector sel
+            STAT_VECTOR_SEL_PROCPU: u1,
+            /// PRO CPU reset_flag
+            ALL_RESET_FLAG_PROCPU: u1,
+            /// APP CPU reset flag
+            ALL_RESET_FLAG_APPCPU: u1,
+            /// clear PRO CPU reset_flag
+            ALL_RESET_FLAG_CLR_PROCPU: u1,
+            /// clear APP CPU reset flag
+            ALL_RESET_FLAG_CLR_APPCPU: u1,
+            /// APPCPU OcdHaltOnReset
+            OCD_HALT_ON_RESET_APPCPU: u1,
+            /// PROCPU OcdHaltOnReset
+            OCD_HALT_ON_RESET_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_APPCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_CLR_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_CLR_APPCPU: u1,
+            /// configure dreset configure
+            RTC_DRESET_MASK_APPCPU: u1,
+            /// configure dreset configure
+            RTC_DRESET_MASK_PROCPU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000803c
+        /// rtc configure register
+        pub const WAKEUP_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// wakeup enable bitmap
+            RTC_WAKEUP_ENA: u17,
+        }), base_address + 0x3c);
+
+        /// address: 0x60008040
+        /// rtc configure register
+        pub const INT_ENA_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable sleep wakeup interrupt
+            SLP_WAKEUP_INT_ENA: u1,
+            /// enable sleep reject interrupt
+            SLP_REJECT_INT_ENA: u1,
+            reserved0: u1,
+            /// enable RTC WDT interrupt
+            RTC_WDT_INT_ENA: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// enable brown out interrupt
+            RTC_BROWN_OUT_INT_ENA: u1,
+            /// enable RTC main timer interrupt
+            RTC_MAIN_TIMER_INT_ENA: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable super watch dog interrupt
+            RTC_SWD_INT_ENA: u1,
+            /// enable xtal32k_dead interrupt
+            RTC_XTAL32K_DEAD_INT_ENA: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// enbale gitch det interrupt
+            RTC_GLITCH_DET_INT_ENA: u1,
+            /// enbale bbpll cal end interrupt
+            RTC_BBPLL_CAL_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60008044
+        /// rtc configure register
+        pub const INT_RAW_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup interrupt raw
+            SLP_WAKEUP_INT_RAW: u1,
+            /// sleep reject interrupt raw
+            SLP_REJECT_INT_RAW: u1,
+            reserved0: u1,
+            /// RTC WDT interrupt raw
+            RTC_WDT_INT_RAW: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// brown out interrupt raw
+            RTC_BROWN_OUT_INT_RAW: u1,
+            /// RTC main timer interrupt raw
+            RTC_MAIN_TIMER_INT_RAW: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// super watch dog interrupt raw
+            RTC_SWD_INT_RAW: u1,
+            /// xtal32k dead detection interrupt raw
+            RTC_XTAL32K_DEAD_INT_RAW: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// glitch_det_interrupt_raw
+            RTC_GLITCH_DET_INT_RAW: u1,
+            /// bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60008048
+        /// rtc configure register
+        pub const INT_ST_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup interrupt state
+            SLP_WAKEUP_INT_ST: u1,
+            /// sleep reject interrupt state
+            SLP_REJECT_INT_ST: u1,
+            reserved0: u1,
+            /// RTC WDT interrupt state
+            RTC_WDT_INT_ST: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// brown out interrupt state
+            RTC_BROWN_OUT_INT_ST: u1,
+            /// RTC main timer interrupt state
+            RTC_MAIN_TIMER_INT_ST: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// super watch dog interrupt state
+            RTC_SWD_INT_ST: u1,
+            /// xtal32k dead detection interrupt state
+            RTC_XTAL32K_DEAD_INT_ST: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// glitch_det_interrupt state
+            RTC_GLITCH_DET_INT_ST: u1,
+            /// bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000804c
+        /// rtc configure register
+        pub const INT_CLR_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Clear sleep wakeup interrupt state
+            SLP_WAKEUP_INT_CLR: u1,
+            /// Clear sleep reject interrupt state
+            SLP_REJECT_INT_CLR: u1,
+            reserved0: u1,
+            /// Clear RTC WDT interrupt state
+            RTC_WDT_INT_CLR: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Clear brown out interrupt state
+            RTC_BROWN_OUT_INT_CLR: u1,
+            /// Clear RTC main timer interrupt state
+            RTC_MAIN_TIMER_INT_CLR: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// Clear super watch dog interrupt state
+            RTC_SWD_INT_CLR: u1,
+            /// Clear RTC WDT interrupt state
+            RTC_XTAL32K_DEAD_INT_CLR: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Clear glitch det interrupt state
+            RTC_GLITCH_DET_INT_CLR: u1,
+            /// clear bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60008050
+        /// rtc configure register
+        pub const STORE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH0: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60008054
+        /// rtc configure register
+        pub const STORE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH1: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60008058
+        /// rtc configure register
+        pub const STORE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH2: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000805c
+        /// rtc configure register
+        pub const STORE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH3: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60008060
+        /// rtc configure register
+        pub const EXT_XTL_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// xtal 32k watch dog enable
+            XTAL32K_WDT_EN: u1,
+            /// xtal 32k watch dog clock force on
+            XTAL32K_WDT_CLK_FO: u1,
+            /// xtal 32k watch dog sw reset
+            XTAL32K_WDT_RESET: u1,
+            /// xtal 32k external xtal clock force on
+            XTAL32K_EXT_CLK_FO: u1,
+            /// xtal 32k switch to back up clock when xtal is dead
+            XTAL32K_AUTO_BACKUP: u1,
+            /// xtal 32k restart xtal when xtal is dead
+            XTAL32K_AUTO_RESTART: u1,
+            /// xtal 32k switch back xtal when xtal is restarted
+            XTAL32K_AUTO_RETURN: u1,
+            /// Xtal 32k xpd control by sw or fsm
+            XTAL32K_XPD_FORCE: u1,
+            /// apply an internal clock to help xtal 32k to start
+            ENCKINIT_XTAL_32K: u1,
+            /// 0: single-end buffer 1: differential buffer
+            DBUF_XTAL_32K: u1,
+            /// xtal_32k gm control
+            DGM_XTAL_32K: u3,
+            /// DRES_XTAL_32K
+            DRES_XTAL_32K: u3,
+            /// XPD_XTAL_32K
+            XPD_XTAL_32K: u1,
+            /// DAC_XTAL_32K
+            DAC_XTAL_32K: u3,
+            /// state of 32k_wdt
+            RTC_WDT_STATE: u3,
+            /// XTAL_32K sel. 0: external XTAL_32K
+            RTC_XTAL32K_GPIO_SEL: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// 0: power down XTAL at high level
+            XTL_EXT_CTR_LV: u1,
+            /// enable gpio configure xtal power on
+            XTL_EXT_CTR_EN: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60008064
+        /// rtc configure register
+        pub const EXT_WAKEUP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// enable filter for gpio wakeup event
+            GPIO_WAKEUP_FILTER: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60008068
+        /// rtc configure register
+        pub const SLP_REJECT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// sleep reject enable
+            RTC_SLEEP_REJECT_ENA: u18,
+            /// enable reject for light sleep
+            LIGHT_SLP_REJECT_EN: u1,
+            /// enable reject for deep sleep
+            DEEP_SLP_REJECT_EN: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6000806c
+        /// rtc configure register
+        pub const CPU_PERIOD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// CPU sel option
+            RTC_CPUSEL_CONF: u1,
+            /// CPU clk sel option
+            RTC_CPUPERIOD_SEL: u2,
+        }), base_address + 0x6c);
+
+        /// address: 0x60008070
+        /// rtc configure register
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// efuse_clk_force_gating
+            EFUSE_CLK_FORCE_GATING: u1,
+            /// efuse_clk_force_nogating
+            EFUSE_CLK_FORCE_NOGATING: u1,
+            /// used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+            CK8M_DIV_SEL_VLD: u1,
+            /// CK8M_D256_OUT divider. 00: div128
+            CK8M_DIV: u2,
+            /// disable CK8M and CK8M_D256_OUT
+            ENB_CK8M: u1,
+            /// 1: CK8M_D256_OUT is actually CK8M
+            ENB_CK8M_DIV: u1,
+            /// enable CK_XTAL_32K for digital core (no relationship with RTC core)
+            DIG_XTAL32K_EN: u1,
+            /// enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+            DIG_CLK8M_D256_EN: u1,
+            /// enable CK8M for digital core (no relationship with RTC core)
+            DIG_CLK8M_EN: u1,
+            reserved1: u1,
+            /// divider = reg_ck8m_div_sel + 1
+            CK8M_DIV_SEL: u3,
+            /// XTAL force no gating during sleep
+            XTAL_FORCE_NOGATING: u1,
+            /// CK8M force no gating during sleep
+            CK8M_FORCE_NOGATING: u1,
+            /// CK8M_DFREQ
+            CK8M_DFREQ: u8,
+            /// CK8M force power down
+            CK8M_FORCE_PD: u1,
+            /// CK8M force power up
+            CK8M_FORCE_PU: u1,
+            /// force enable xtal clk gating
+            XTAL_GLOBAL_FORCE_GATING: u1,
+            /// force bypass xtal clk gating
+            XTAL_GLOBAL_FORCE_NOGATING: u1,
+            /// fast_clk_rtc sel. 0: XTAL div 4
+            FAST_CLK_RTC_SEL: u1,
+            /// slelect rtc slow clk
+            ANA_CLK_RTC_SEL: u2,
+        }), base_address + 0x70);
+
+        /// address: 0x60008074
+        /// rtc configure register
+        pub const SLOW_CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            /// used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+            RTC_ANA_CLK_DIV_VLD: u1,
+            /// the clk divider num of RTC_CLK
+            RTC_ANA_CLK_DIV: u8,
+            /// flag rtc_slow_clk_next_edge
+            RTC_SLOW_CLK_NEXT_EDGE: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60008078
+        /// rtc configure register
+        pub const SDIO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer count to apply reg_sdio_dcap after sdio power on
+            SDIO_TIMER_TARGET: u8,
+            reserved0: u1,
+            /// Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+            SDIO_DTHDRV: u2,
+            /// ability to prevent LDO from overshoot
+            SDIO_DCAP: u2,
+            /// add resistor from ldo output to ground. 0: no res
+            SDIO_INITI: u2,
+            /// 0 to set init[1:0]=0
+            SDIO_EN_INITI: u1,
+            /// tune current limit threshold when tieh = 0. About 800mA/(8+d)
+            SDIO_DCURLIM: u3,
+            /// select current limit mode
+            SDIO_MODECURLIM: u1,
+            /// enable current limit
+            SDIO_ENCURLIM: u1,
+            /// power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+            SDIO_REG_PD_EN: u1,
+            /// 1: use SW option to control SDIO_REG
+            SDIO_FORCE: u1,
+            /// SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+            SDIO_TIEH: u1,
+            /// read only register for REG1P8_READY
+            _1P8_READY: u1,
+            /// SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+            DREFL_SDIO: u2,
+            /// SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+            DREFM_SDIO: u2,
+            /// SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+            DREFH_SDIO: u2,
+            XPD_SDIO: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000807c
+        /// rtc configure register
+        pub const BIAS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            DG_VDD_DRV_B_SLP: u8,
+            DG_VDD_DRV_B_SLP_EN: u1,
+            reserved0: u1,
+            /// bias buf when rtc in normal work state
+            BIAS_BUF_IDLE: u1,
+            /// bias buf when rtc in wakeup state
+            BIAS_BUF_WAKE: u1,
+            /// bias buf when rtc in sleep state
+            BIAS_BUF_DEEP_SLP: u1,
+            /// bias buf when rtc in monitor state
+            BIAS_BUF_MONITOR: u1,
+            /// xpd cur when rtc in sleep_state
+            PD_CUR_DEEP_SLP: u1,
+            /// xpd cur when rtc in monitor state
+            PD_CUR_MONITOR: u1,
+            /// bias_sleep when rtc in sleep_state
+            BIAS_SLEEP_DEEP_SLP: u1,
+            /// bias_sleep when rtc in monitor state
+            BIAS_SLEEP_MONITOR: u1,
+            /// DBG_ATTEN when rtc in sleep state
+            DBG_ATTEN_DEEP_SLP: u4,
+            /// DBG_ATTEN when rtc in monitor state
+            DBG_ATTEN_MONITOR: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60008080
+        /// rtc configure register
+        pub const RTC_CNTL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// software enable digital regulator cali
+            DIG_REG_CAL_EN: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// SCK_DCAP
+            SCK_DCAP: u8,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            /// RTC_DBOOST force power down
+            DBOOST_FORCE_PD: u1,
+            /// RTC_DBOOST force power up
+            DBOOST_FORCE_PU: u1,
+            /// RTC_REG force power down (for RTC_REG power down means decrease the voltage to
+            /// 0.8v or lower )
+            REGULATOR_FORCE_PD: u1,
+            /// RTC_REG force power up
+            REGULATOR_FORCE_PU: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60008084
+        /// rtc configure register
+        pub const PWC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            /// rtc pad force hold
+            RTC_PAD_FORCE_HOLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x60008088
+        /// rtc configure register
+        pub const DIG_PWC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// vdd_spi drv's software value
+            VDD_SPI_PWR_DRV: u2,
+            /// vdd_spi drv use software value
+            VDD_SPI_PWR_FORCE: u1,
+            /// memories in digital core force PD in sleep
+            LSLP_MEM_FORCE_PD: u1,
+            /// memories in digital core force PU in sleep
+            LSLP_MEM_FORCE_PU: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// bt force power down
+            BT_FORCE_PD: u1,
+            /// bt force power up
+            BT_FORCE_PU: u1,
+            /// digital peri force power down
+            DG_PERI_FORCE_PD: u1,
+            /// digital peri force power up
+            DG_PERI_FORCE_PU: u1,
+            /// fastmemory retention mode in sleep
+            RTC_FASTMEM_FORCE_LPD: u1,
+            /// fastmemory donlt entry retention mode in sleep
+            RTC_FASTMEM_FORCE_LPU: u1,
+            /// wifi force power down
+            WIFI_FORCE_PD: u1,
+            /// wifi force power up
+            WIFI_FORCE_PU: u1,
+            /// digital core force power down
+            DG_WRAP_FORCE_PD: u1,
+            /// digital core force power up
+            DG_WRAP_FORCE_PU: u1,
+            /// cpu core force power down
+            CPU_TOP_FORCE_PD: u1,
+            /// cpu force power up
+            CPU_TOP_FORCE_PU: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable power down bt in sleep
+            BT_PD_EN: u1,
+            /// enable power down digital peri in sleep
+            DG_PERI_PD_EN: u1,
+            /// enable power down cpu in sleep
+            CPU_TOP_PD_EN: u1,
+            /// enable power down wifi in sleep
+            WIFI_PD_EN: u1,
+            /// enable power down digital wrap in sleep
+            DG_WRAP_PD_EN: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6000808c
+        /// rtc configure register
+        pub const DIG_ISO = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// DIG_ISO force off
+            FORCE_OFF: u1,
+            /// DIG_ISO force on
+            FORCE_ON: u1,
+            /// read only register to indicate digital pad auto-hold status
+            DG_PAD_AUTOHOLD: u1,
+            /// wtite only register to clear digital pad auto-hold
+            CLR_DG_PAD_AUTOHOLD: u1,
+            /// digital pad enable auto-hold
+            DG_PAD_AUTOHOLD_EN: u1,
+            /// digital pad force no ISO
+            DG_PAD_FORCE_NOISO: u1,
+            /// digital pad force ISO
+            DG_PAD_FORCE_ISO: u1,
+            /// digital pad force un-hold
+            DG_PAD_FORCE_UNHOLD: u1,
+            /// digital pad force hold
+            DG_PAD_FORCE_HOLD: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// bt force ISO
+            BT_FORCE_ISO: u1,
+            /// bt force no ISO
+            BT_FORCE_NOISO: u1,
+            /// Digital peri force ISO
+            DG_PERI_FORCE_ISO: u1,
+            /// digital peri force no ISO
+            DG_PERI_FORCE_NOISO: u1,
+            /// cpu force ISO
+            CPU_TOP_FORCE_ISO: u1,
+            /// cpu force no ISO
+            CPU_TOP_FORCE_NOISO: u1,
+            /// wifi force ISO
+            WIFI_FORCE_ISO: u1,
+            /// wifi force no ISO
+            WIFI_FORCE_NOISO: u1,
+            /// digital core force ISO
+            DG_WRAP_FORCE_ISO: u1,
+            /// digital core force no ISO
+            DG_WRAP_FORCE_NOISO: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x60008090
+        /// rtc configure register
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// chip reset siginal pulse width
+            WDT_CHIP_RESET_WIDTH: u8,
+            /// wdt reset whole chip enable
+            WDT_CHIP_RESET_EN: u1,
+            /// pause WDT in sleep
+            WDT_PAUSE_IN_SLP: u1,
+            /// enable WDT reset APP CPU
+            WDT_APPCPU_RESET_EN: u1,
+            /// enable WDT reset PRO CPU
+            WDT_PROCPU_RESET_EN: u1,
+            /// enable WDT in flash boot
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// system reset counter length
+            WDT_SYS_RESET_LENGTH: u3,
+            /// CPU reset counter length
+            WDT_CPU_RESET_LENGTH: u3,
+            /// 1: interrupt stage en
+            WDT_STG3: u3,
+            /// 1: interrupt stage en
+            WDT_STG2: u3,
+            /// 1: interrupt stage en
+            WDT_STG1: u3,
+            /// 1: interrupt stage en
+            WDT_STG0: u3,
+            /// enable rtc wdt
+            WDT_EN: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60008094
+        /// rtc configure register
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage0
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60008098
+        /// rtc configure register
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage1
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6000809c
+        /// rtc configure register
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage2
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600080a0
+        /// rtc configure register
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage3
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600080a4
+        /// rtc configure register
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// sw feed rtc wdt
+            RTC_WDT_FEED: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600080a8
+        /// rtc configure register
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the key of rtc wdt
+            WDT_WKEY: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600080ac
+        /// rtc configure register
+        pub const SWD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// swd reset flag
+            SWD_RESET_FLAG: u1,
+            /// swd interrupt for feeding
+            SWD_FEED_INT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// Bypass swd rst
+            SWD_BYPASS_RST: u1,
+            /// adjust signal width send to swd
+            SWD_SIGNAL_WIDTH: u10,
+            /// reset swd reset flag
+            SWD_RST_FLAG_CLR: u1,
+            /// Sw feed swd
+            SWD_FEED: u1,
+            /// disabel SWD
+            SWD_DISABLE: u1,
+            /// automatically feed swd when int comes
+            SWD_AUTO_FEED_EN: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600080b0
+        /// rtc configure register
+        pub const SWD_WPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the key of super wdt
+            SWD_WKEY: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600080b4
+        /// rtc configure register
+        pub const SW_CPU_STALL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// {reg_sw_stall_appcpu_c1[5:0]
+            SW_STALL_APPCPU_C1: u6,
+            /// stall cpu by software
+            SW_STALL_PROCPU_C1: u6,
+        }), base_address + 0xb4);
+
+        /// address: 0x600080b8
+        /// rtc configure register
+        pub const STORE4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH4: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600080bc
+        /// rtc configure register
+        pub const STORE5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH5: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600080c0
+        /// rtc configure register
+        pub const STORE6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH6: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600080c4
+        /// rtc configure register
+        pub const STORE7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH7: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600080c8
+        /// rtc configure register
+        pub const LOW_POWER_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rom0 power down
+            XPD_ROM0: u1,
+            reserved0: u1,
+            /// External DCDC power down
+            XPD_DIG_DCDC: u1,
+            /// rtc peripheral iso
+            RTC_PERI_ISO: u1,
+            /// rtc peripheral power down
+            XPD_RTC_PERI: u1,
+            /// wifi iso
+            WIFI_ISO: u1,
+            /// wifi wrap power down
+            XPD_WIFI: u1,
+            /// digital wrap iso
+            DIG_ISO: u1,
+            /// digital wrap power down
+            XPD_DIG: u1,
+            /// touch should start to work
+            RTC_TOUCH_STATE_START: u1,
+            /// touch is about to working. Switch rtc main state
+            RTC_TOUCH_STATE_SWITCH: u1,
+            /// touch is in sleep state
+            RTC_TOUCH_STATE_SLP: u1,
+            /// touch is done
+            RTC_TOUCH_STATE_DONE: u1,
+            /// ulp/cocpu should start to work
+            RTC_COCPU_STATE_START: u1,
+            /// ulp/cocpu is about to working. Switch rtc main state
+            RTC_COCPU_STATE_SWITCH: u1,
+            /// ulp/cocpu is in sleep state
+            RTC_COCPU_STATE_SLP: u1,
+            /// ulp/cocpu is done
+            RTC_COCPU_STATE_DONE: u1,
+            /// no use any more
+            RTC_MAIN_STATE_XTAL_ISO: u1,
+            /// rtc main state machine is in states that pll should be running
+            RTC_MAIN_STATE_PLL_ON: u1,
+            /// rtc is ready to receive wake up trigger from wake up source
+            RTC_RDY_FOR_WAKEUP: u1,
+            /// rtc main state machine has been waited for some cycles
+            RTC_MAIN_STATE_WAIT_END: u1,
+            /// rtc main state machine is in the states of wakeup process
+            RTC_IN_WAKEUP_STATE: u1,
+            /// rtc main state machine is in the states of low power
+            RTC_IN_LOW_POWER_STATE: u1,
+            /// rtc main state machine is in wait 8m state
+            RTC_MAIN_STATE_IN_WAIT_8M: u1,
+            /// rtc main state machine is in wait pll state
+            RTC_MAIN_STATE_IN_WAIT_PLL: u1,
+            /// rtc main state machine is in wait xtal state
+            RTC_MAIN_STATE_IN_WAIT_XTL: u1,
+            /// rtc main state machine is in sleep state
+            RTC_MAIN_STATE_IN_SLP: u1,
+            /// rtc main state machine is in idle state
+            RTC_MAIN_STATE_IN_IDLE: u1,
+            /// rtc main state machine status
+            RTC_MAIN_STATE: u4,
+        }), base_address + 0xc8);
+
+        /// address: 0x600080cc
+        /// rtc configure register
+        pub const DIAG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            RTC_LOW_POWER_DIAG1: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600080d0
+        /// rtc configure register
+        pub const PAD_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold configure of rtc gpio0
+            RTC_GPIO_PIN0_HOLD: u1,
+            /// the hold configure of rtc gpio1
+            RTC_GPIO_PIN1_HOLD: u1,
+            /// the hold configure of rtc gpio2
+            RTC_GPIO_PIN2_HOLD: u1,
+            /// the hold configure of rtc gpio3
+            RTC_GPIO_PIN3_HOLD: u1,
+            /// the hold configure of rtc gpio4
+            RTC_GPIO_PIN4_HOLD: u1,
+            /// the hold configure of rtc gpio5
+            RTC_GPIO_PIN5_HOLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600080d4
+        /// rtc configure register
+        pub const DIG_PAD_HOLD = @intToPtr(*volatile u32, base_address + 0xd4);
+
+        /// address: 0x600080d8
+        /// rtc configure register
+        pub const BROWN_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// brown out interrupt wait cycles
+            INT_WAIT: u10,
+            /// enable close flash when brown out happens
+            CLOSE_FLASH_ENA: u1,
+            /// enable power down RF when brown out happens
+            PD_RF_ENA: u1,
+            /// brown out reset wait cycles
+            RST_WAIT: u10,
+            /// enable brown out reset
+            RST_ENA: u1,
+            /// 1: 4-pos reset
+            RST_SEL: u1,
+            /// brown_out origin reset enable
+            ANA_RST_EN: u1,
+            /// clear brown out counter
+            CNT_CLR: u1,
+            /// enable brown out
+            ENA: u1,
+            /// the flag of brown det from analog
+            DET: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600080dc
+        /// rtc configure register
+        pub const TIME_LOW1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer low 32 bits
+            RTC_TIMER_VALUE1_LOW: u32,
+        }), base_address + 0xdc);
+
+        /// address: 0x600080e0
+        /// rtc configure register
+        pub const TIME_HIGH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer high 16 bits
+            RTC_TIMER_VALUE1_HIGH: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600080e4
+        /// rtc configure register
+        pub const XTAL32K_CLK_FACTOR = @intToPtr(*volatile u32, base_address + 0xe4);
+
+        /// address: 0x600080e8
+        /// rtc configure register
+        pub const XTAL32K_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cycles to wait to return noral xtal 32k
+            XTAL32K_RETURN_WAIT: u4,
+            /// cycles to wait to repower on xtal 32k
+            XTAL32K_RESTART_WAIT: u16,
+            /// If no clock detected for this amount of time
+            XTAL32K_WDT_TIMEOUT: u8,
+            /// if restarted xtal32k period is smaller than this
+            XTAL32K_STABLE_THRES: u4,
+        }), base_address + 0xe8);
+
+        /// address: 0x600080ec
+        /// rtc configure register
+        pub const USB_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// disable io_mux reset
+            IO_MUX_RESET_DISABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0xec);
+
+        /// address: 0x600080f0
+        /// RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+        pub const SLP_REJECT_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep reject cause
+            REJECT_CAUSE: u18,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x600080f4
+        /// rtc configure register
+        pub const OPTION1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// force chip entry download mode
+            FORCE_DOWNLOAD_BOOT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600080f8
+        /// RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+        pub const SLP_WAKEUP_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup cause
+            WAKEUP_CAUSE: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600080fc
+        /// rtc configure register
+        pub const ULP_CP_TIMER_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// sleep cycles for ULP-coprocessor timer
+            ULP_CP_TIMER_SLP_CYCLE: u24,
+        }), base_address + 0xfc);
+
+        /// address: 0x60008100
+        /// rtc configure register
+        pub const INT_ENA_RTC_W1TS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable sleep wakeup interrupt
+            SLP_WAKEUP_INT_ENA_W1TS: u1,
+            /// enable sleep reject interrupt
+            SLP_REJECT_INT_ENA_W1TS: u1,
+            reserved0: u1,
+            /// enable RTC WDT interrupt
+            RTC_WDT_INT_ENA_W1TS: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// enable brown out interrupt
+            RTC_BROWN_OUT_INT_ENA_W1TS: u1,
+            /// enable RTC main timer interrupt
+            RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable super watch dog interrupt
+            RTC_SWD_INT_ENA_W1TS: u1,
+            /// enable xtal32k_dead interrupt
+            RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// enbale gitch det interrupt
+            RTC_GLITCH_DET_INT_ENA_W1TS: u1,
+            /// enbale bbpll cal interrupt
+            RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x60008104
+        /// rtc configure register
+        pub const INT_ENA_RTC_W1TC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clear sleep wakeup interrupt enable
+            SLP_WAKEUP_INT_ENA_W1TC: u1,
+            /// clear sleep reject interrupt enable
+            SLP_REJECT_INT_ENA_W1TC: u1,
+            reserved0: u1,
+            /// clear RTC WDT interrupt enable
+            RTC_WDT_INT_ENA_W1TC: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// clear brown out interrupt enable
+            RTC_BROWN_OUT_INT_ENA_W1TC: u1,
+            /// Clear RTC main timer interrupt enable
+            RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// clear super watch dog interrupt enable
+            RTC_SWD_INT_ENA_W1TC: u1,
+            /// clear xtal32k_dead interrupt enable
+            RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// clear gitch det interrupt enable
+            RTC_GLITCH_DET_INT_ENA_W1TC: u1,
+            /// clear bbpll cal interrupt enable
+            RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x104);
+
+        /// address: 0x60008108
+        /// rtc configure register
+        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// Retention clk sel
+            RETENTION_CLK_SEL: u1,
+            /// Retention done wait time
+            RETENTION_DONE_WAIT: u3,
+            /// Retention clkoff wait time
+            RETENTION_CLKOFF_WAIT: u4,
+            /// enable cpu retention when light sleep
+            RETENTION_EN: u1,
+            /// wait cycles for rention operation
+            RETENTION_WAIT: u5,
+        }), base_address + 0x108);
+
+        /// address: 0x6000810c
+        /// rtc configure register
+        pub const FIB_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// select use analog fib signal
+            RTC_FIB_SEL: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x10c);
+
+        /// address: 0x60008110
+        /// rtc configure register
+        pub const GPIO_WAKEUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc gpio wakeup flag
+            RTC_GPIO_WAKEUP_STATUS: u6,
+            /// clear rtc gpio wakeup flag
+            RTC_GPIO_WAKEUP_STATUS_CLR: u1,
+            /// enable rtc io clk gate
+            RTC_GPIO_PIN_CLK_GATE: u1,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN5_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN4_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN3_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN2_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN1_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN0_INT_TYPE: u3,
+            /// enable wakeup from rtc gpio5
+            RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio4
+            RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio3
+            RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio2
+            RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio1
+            RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio0
+            RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
+        }), base_address + 0x110);
+
+        /// address: 0x60008114
+        /// rtc configure register
+        pub const DBG_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// use for debug
+            RTC_DEBUG_12M_NO_GATING: u1,
+            /// use for debug
+            RTC_DEBUG_BIT_SEL: u5,
+            /// use for debug
+            RTC_DEBUG_SEL0: u5,
+            /// use for debug
+            RTC_DEBUG_SEL1: u5,
+            /// use for debug
+            RTC_DEBUG_SEL2: u5,
+            /// use for debug
+            RTC_DEBUG_SEL3: u5,
+            /// use for debug
+            RTC_DEBUG_SEL4: u5,
+        }), base_address + 0x114);
+
+        /// address: 0x60008118
+        /// rtc configure register
+        pub const DBG_MAP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// use for debug
+            RTC_GPIO_PIN5_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN4_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN3_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN2_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN1_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN0_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN5_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN4_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN3_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN2_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN1_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN0_FUN_SEL: u4,
+        }), base_address + 0x118);
+
+        /// address: 0x6000811c
+        /// rtc configure register
+        pub const SENSOR_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// reg_sar2_pwdet_cct
+            SAR2_PWDET_CCT: u3,
+            /// force power up SAR
+            FORCE_XPD_SAR: u2,
+        }), base_address + 0x11c);
+
+        /// address: 0x60008120
+        /// rtc configure register
+        pub const DBG_SAR_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// use for debug
+            SAR_DEBUG_SEL: u5,
+        }), base_address + 0x120);
+
+        /// address: 0x60008124
+        /// rtc configure register
+        pub const PG_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// power glitch desense
+            POWER_GLITCH_DSENSE: u2,
+            /// force disable power glitch
+            POWER_GLITCH_FORCE_PD: u1,
+            /// force enable power glitch
+            POWER_GLITCH_FORCE_PU: u1,
+            /// use efuse value control power glitch enable
+            POWER_GLITCH_EFUSE_SEL: u1,
+            /// enable power glitch
+            POWER_GLITCH_EN: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600081fc
+        /// rtc configure register
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// verision
+            RTC_CNTL_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1fc);
+    };
+
+    /// Sensitive
+    pub const SENSITIVE = struct {
+        pub const base_address = 0x600c1000;
+
+        /// address: 0x600c1000
+        /// SENSITIVE_ROM_TABLE_LOCK_REG
+        pub const ROM_TABLE_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
+
+        /// address: 0x600c1004
+        /// SENSITIVE_ROM_TABLE_REG
+        pub const ROM_TABLE = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x600c1008
+        /// SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+        pub const PRIVILEGE_MODE_SEL_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8);
+
+        /// address: 0x600c100c
+        /// SENSITIVE_PRIVILEGE_MODE_SEL_REG
+        pub const PRIVILEGE_MODE_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc);
+
+        /// address: 0x600c1010
+        /// SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+        pub const APB_PERIPHERAL_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// apb_peripheral_access_lock
+            APB_PERIPHERAL_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x600c1014
+        /// SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+        pub const APB_PERIPHERAL_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// apb_peripheral_access_split_burst
+            APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x600c1018
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+        pub const INTERNAL_SRAM_USAGE_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_lock
+            INTERNAL_SRAM_USAGE_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x600c101c
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+        pub const INTERNAL_SRAM_USAGE_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_cpu_cache
+            INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
+            /// internal_sram_usage_cpu_sram
+            INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c1020
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+        pub const INTERNAL_SRAM_USAGE_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_mac_dump_sram
+            INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
+            /// internal_sram_alloc_mac_dump
+            INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x600c1024
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+        pub const INTERNAL_SRAM_USAGE_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_log_sram
+            INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x600c1028
+        /// SENSITIVE_CACHE_TAG_ACCESS_0_REG
+        pub const CACHE_TAG_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cache_tag_access_lock
+            CACHE_TAG_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x600c102c
+        /// SENSITIVE_CACHE_TAG_ACCESS_1_REG
+        pub const CACHE_TAG_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pro_i_tag_rd_acs
+            PRO_I_TAG_RD_ACS: u1,
+            /// pro_i_tag_wr_acs
+            PRO_I_TAG_WR_ACS: u1,
+            /// pro_d_tag_rd_acs
+            PRO_D_TAG_RD_ACS: u1,
+            /// pro_d_tag_wr_acs
+            PRO_D_TAG_WR_ACS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x600c1030
+        /// SENSITIVE_CACHE_MMU_ACCESS_0_REG
+        pub const CACHE_MMU_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cache_mmu_access_lock
+            CACHE_MMU_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x600c1034
+        /// SENSITIVE_CACHE_MMU_ACCESS_1_REG
+        pub const CACHE_MMU_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pro_mmu_rd_acs
+            PRO_MMU_RD_ACS: u1,
+            /// pro_mmu_wr_acs
+            PRO_MMU_WR_ACS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x600c1038
+        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_spi2_pms_constrain_lock
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x600c103c
+        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x600c1040
+        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_uchi0_pms_constrain_lock
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c1044
+        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600c1048
+        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_i2s0_pms_constrain_lock
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x600c104c
+        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x600c1050
+        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_mac_pms_constrain_lock
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600c1054
+        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600c1058
+        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_backup_pms_constrain_lock
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600c105c
+        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x600c1060
+        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_lc_pms_constrain_lock
+            DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600c1064
+        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c1068
+        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_aes_pms_constrain_lock
+            DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600c106c
+        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600c1070
+        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_sha_pms_constrain_lock
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600c1074
+        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600c1078
+        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_adc_dac_pms_constrain_lock
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c107c
+        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c1080
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+        pub const DMA_APBPERI_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_lock
+            DMA_APBPERI_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c1084
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+        pub const DMA_APBPERI_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_clr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// dma_apbperi_pms_monitor_violate_en
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c1088
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+        pub const DMA_APBPERI_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_intr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// dma_apbperi_pms_monitor_violate_status_world
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// dma_apbperi_pms_monitor_violate_status_addr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c108c
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+        pub const DMA_APBPERI_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_status_wr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// dma_apbperi_pms_monitor_violate_status_byteen
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c1090
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_dram0_dma_split_line_constrain_lock
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c1094
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_dram0_dma_sram_category_0
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
+            /// core_x_iram0_dram0_dma_sram_category_1
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
+            /// core_x_iram0_dram0_dma_sram_category_2
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_dram0_dma_sram_splitaddr
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x600c1098
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_sram_line_0_category_0
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
+            /// core_x_iram0_sram_line_0_category_1
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
+            /// core_x_iram0_sram_line_0_category_2
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_sram_line_0_splitaddr
+            CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c109c
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_sram_line_1_category_0
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
+            /// core_x_iram0_sram_line_1_category_1
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
+            /// core_x_iram0_sram_line_1_category_2
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_sram_line_1_splitaddr
+            CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600c10a0
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_dma_sram_line_0_category_0
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
+            /// core_x_dram0_dma_sram_line_0_category_1
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
+            /// core_x_dram0_dma_sram_line_0_category_2
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_dma_sram_line_0_splitaddr
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600c10a4
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_dma_sram_line_1_category_0
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
+            /// core_x_dram0_dma_sram_line_1_category_1
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
+            /// core_x_dram0_dma_sram_line_1_category_2
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_dma_sram_line_1_splitaddr
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600c10a8
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_lock
+            CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600c10ac
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_1
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_2
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_3
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// core_x_iram0_pms_constrain_rom_world_1_pms
+            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600c10b0
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_1
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_2
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_3
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// core_x_iram0_pms_constrain_rom_world_0_pms
+            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600c10b4
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_lock
+            CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600c10b8
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_violate_clr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_iram0_pms_monitor_violate_en
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600c10bc
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_violate_intr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_iram0_pms_monitor_violate_status_wr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// core_0_iram0_pms_monitor_violate_status_loadstore
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
+            /// core_0_iram0_pms_monitor_violate_status_world
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// core_0_iram0_pms_monitor_violate_status_addr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600c10c0
+        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+        pub const CORE_X_DRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_pms_constrain_lock
+            CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600c10c4
+        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+        pub const CORE_X_DRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_0
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_1
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_2
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_3
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_0
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_1
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_2
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_3
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_pms_constrain_rom_world_0_pms
+            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
+            /// core_x_dram0_pms_constrain_rom_world_1_pms
+            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600c10c8
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_lock
+            CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600c10cc
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_clr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_dram0_pms_monitor_violate_en
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600c10d0
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_intr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_dram0_pms_monitor_violate_status_lock
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
+            /// core_0_dram0_pms_monitor_violate_status_world
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// core_0_dram0_pms_monitor_violate_status_addr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600c10d4
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_status_wr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// core_0_dram0_pms_monitor_violate_status_byteen
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600c10d8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_lock
+            CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600c10dc
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_uart
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
+            /// core_0_pif_pms_constrain_world_0_g0spi_1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
+            /// core_0_pif_pms_constrain_world_0_g0spi_0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
+            /// core_0_pif_pms_constrain_world_0_gpio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
+            /// core_0_pif_pms_constrain_world_0_fe2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
+            /// core_0_pif_pms_constrain_world_0_fe
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
+            /// core_0_pif_pms_constrain_world_0_timer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
+            /// core_0_pif_pms_constrain_world_0_rtc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
+            /// core_0_pif_pms_constrain_world_0_io_mux
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
+            /// core_0_pif_pms_constrain_world_0_wdg
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_misc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
+            /// core_0_pif_pms_constrain_world_0_i2c
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_0_uart1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
+        }), base_address + 0xdc);
+
+        /// address: 0x600c10e0
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_bt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_i2c_ext0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
+            /// core_0_pif_pms_constrain_world_0_uhci0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_rmt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_0_ledc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// core_0_pif_pms_constrain_world_0_bb
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_0_timergroup
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
+            /// core_0_pif_pms_constrain_world_0_timergroup1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
+            /// core_0_pif_pms_constrain_world_0_systimer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
+        }), base_address + 0xe0);
+
+        /// address: 0x600c10e4
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_spi_2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_apb_ctrl
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_0_can
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_0_i2s1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_0_rwbt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// core_0_pif_pms_constrain_world_0_wifimac
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
+            /// core_0_pif_pms_constrain_world_0_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x600c10e8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_usb_wrap
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
+            /// core_0_pif_pms_constrain_world_0_crypto_peri
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
+            /// core_0_pif_pms_constrain_world_0_crypto_dma
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
+            /// core_0_pif_pms_constrain_world_0_apb_adc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_bt_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
+            /// core_0_pif_pms_constrain_world_0_usb_device
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
+            /// core_0_pif_pms_constrain_world_0_system
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
+            /// core_0_pif_pms_constrain_world_0_sensitive
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
+            /// core_0_pif_pms_constrain_world_0_interrupt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
+            /// core_0_pif_pms_constrain_world_0_dma_copy
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
+            /// core_0_pif_pms_constrain_world_0_cache_config
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
+            /// core_0_pif_pms_constrain_world_0_ad
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
+            /// core_0_pif_pms_constrain_world_0_dio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
+            /// core_0_pif_pms_constrain_world_0_world_controller
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
+        }), base_address + 0xe8);
+
+        /// address: 0x600c10ec
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_uart
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
+            /// core_0_pif_pms_constrain_world_1_g0spi_1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
+            /// core_0_pif_pms_constrain_world_1_g0spi_0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
+            /// core_0_pif_pms_constrain_world_1_gpio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
+            /// core_0_pif_pms_constrain_world_1_fe2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
+            /// core_0_pif_pms_constrain_world_1_fe
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
+            /// core_0_pif_pms_constrain_world_1_timer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
+            /// core_0_pif_pms_constrain_world_1_rtc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
+            /// core_0_pif_pms_constrain_world_1_io_mux
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
+            /// core_0_pif_pms_constrain_world_1_wdg
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_misc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
+            /// core_0_pif_pms_constrain_world_1_i2c
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_1_uart1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
+        }), base_address + 0xec);
+
+        /// address: 0x600c10f0
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_bt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_i2c_ext0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
+            /// core_0_pif_pms_constrain_world_1_uhci0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_rmt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_1_ledc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// core_0_pif_pms_constrain_world_1_bb
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_1_timergroup
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
+            /// core_0_pif_pms_constrain_world_1_timergroup1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
+            /// core_0_pif_pms_constrain_world_1_systimer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
+        }), base_address + 0xf0);
+
+        /// address: 0x600c10f4
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_spi_2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_apb_ctrl
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_1_can
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_1_i2s1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_1_rwbt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// core_0_pif_pms_constrain_world_1_wifimac
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
+            /// core_0_pif_pms_constrain_world_1_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600c10f8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_usb_wrap
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
+            /// core_0_pif_pms_constrain_world_1_crypto_peri
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
+            /// core_0_pif_pms_constrain_world_1_crypto_dma
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
+            /// core_0_pif_pms_constrain_world_1_apb_adc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_bt_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
+            /// core_0_pif_pms_constrain_world_1_usb_device
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
+            /// core_0_pif_pms_constrain_world_1_system
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
+            /// core_0_pif_pms_constrain_world_1_sensitive
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
+            /// core_0_pif_pms_constrain_world_1_interrupt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
+            /// core_0_pif_pms_constrain_world_1_dma_copy
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
+            /// core_0_pif_pms_constrain_world_1_cache_config
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
+            /// core_0_pif_pms_constrain_world_1_ad
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
+            /// core_0_pif_pms_constrain_world_1_dio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
+            /// core_0_pif_pms_constrain_world_1_world_controller
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c10fc
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
+            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c1100
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_rtcfast_world_0_l
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_0_h
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_1_l
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_1_h
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c1104
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+        pub const REGION_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_lock
+            REGION_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x104);
+
+        /// address: 0x600c1108
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+        pub const REGION_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_world_0_area_0
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
+            /// region_pms_constrain_world_0_area_1
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
+            /// region_pms_constrain_world_0_area_2
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
+            /// region_pms_constrain_world_0_area_3
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
+            /// region_pms_constrain_world_0_area_4
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
+            /// region_pms_constrain_world_0_area_5
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
+            /// region_pms_constrain_world_0_area_6
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x108);
+
+        /// address: 0x600c110c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+        pub const REGION_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_world_1_area_0
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
+            /// region_pms_constrain_world_1_area_1
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
+            /// region_pms_constrain_world_1_area_2
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
+            /// region_pms_constrain_world_1_area_3
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
+            /// region_pms_constrain_world_1_area_4
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
+            /// region_pms_constrain_world_1_area_5
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
+            /// region_pms_constrain_world_1_area_6
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x10c);
+
+        /// address: 0x600c1110
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+        pub const REGION_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_0
+            REGION_PMS_CONSTRAIN_ADDR_0: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x110);
+
+        /// address: 0x600c1114
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+        pub const REGION_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_1
+            REGION_PMS_CONSTRAIN_ADDR_1: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x114);
+
+        /// address: 0x600c1118
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+        pub const REGION_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_2
+            REGION_PMS_CONSTRAIN_ADDR_2: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x118);
+
+        /// address: 0x600c111c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+        pub const REGION_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_3
+            REGION_PMS_CONSTRAIN_ADDR_3: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x11c);
+
+        /// address: 0x600c1120
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+        pub const REGION_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_4
+            REGION_PMS_CONSTRAIN_ADDR_4: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x120);
+
+        /// address: 0x600c1124
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+        pub const REGION_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_5
+            REGION_PMS_CONSTRAIN_ADDR_5: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600c1128
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+        pub const REGION_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_6
+            REGION_PMS_CONSTRAIN_ADDR_6: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x128);
+
+        /// address: 0x600c112c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+        pub const REGION_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_7
+            REGION_PMS_CONSTRAIN_ADDR_7: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x12c);
+
+        /// address: 0x600c1130
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+        pub const CORE_0_PIF_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_lock
+            CORE_0_PIF_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x600c1134
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+        pub const CORE_0_PIF_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_clr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_pif_pms_monitor_violate_en
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x600c1138
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+        pub const CORE_0_PIF_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_intr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_pif_pms_monitor_violate_status_hport_0
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
+            /// core_0_pif_pms_monitor_violate_status_hsize
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+            /// core_0_pif_pms_monitor_violate_status_hwrite
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+            /// core_0_pif_pms_monitor_violate_status_hworld
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x600c113c
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+        pub const CORE_0_PIF_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_status_haddr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
+        }), base_address + 0x13c);
+
+        /// address: 0x600c1140
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+        pub const CORE_0_PIF_PMS_MONITOR_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_clr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
+            /// core_0_pif_pms_monitor_nonword_violate_en
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x600c1144
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+        pub const CORE_0_PIF_PMS_MONITOR_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_intr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
+            /// core_0_pif_pms_monitor_nonword_violate_status_hsize
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
+            /// core_0_pif_pms_monitor_nonword_violate_status_hworld
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x600c1148
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+        pub const CORE_0_PIF_PMS_MONITOR_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_status_haddr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
+        }), base_address + 0x148);
+
+        /// address: 0x600c114c
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_lock
+            BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x600c1150
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_uart
+            BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
+            /// backup_bus_pms_constrain_g0spi_1
+            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
+            /// backup_bus_pms_constrain_g0spi_0
+            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
+            /// backup_bus_pms_constrain_gpio
+            BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
+            /// backup_bus_pms_constrain_fe2
+            BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
+            /// backup_bus_pms_constrain_fe
+            BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
+            /// backup_bus_pms_constrain_timer
+            BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
+            /// backup_bus_pms_constrain_rtc
+            BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
+            /// backup_bus_pms_constrain_io_mux
+            BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
+            /// backup_bus_pms_constrain_wdg
+            BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_misc
+            BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
+            /// backup_bus_pms_constrain_i2c
+            BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// backup_bus_pms_constrain_uart1
+            BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
+        }), base_address + 0x150);
+
+        /// address: 0x600c1154
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_bt
+            BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_i2c_ext0
+            BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
+            /// backup_bus_pms_constrain_uhci0
+            BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_rmt
+            BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// backup_bus_pms_constrain_ledc
+            BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// backup_bus_pms_constrain_bb
+            BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// backup_bus_pms_constrain_timergroup
+            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
+            /// backup_bus_pms_constrain_timergroup1
+            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
+            /// backup_bus_pms_constrain_systimer
+            BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
+        }), base_address + 0x154);
+
+        /// address: 0x600c1158
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_spi_2
+            BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_apb_ctrl
+            BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// backup_bus_pms_constrain_can
+            BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// backup_bus_pms_constrain_i2s1
+            BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// backup_bus_pms_constrain_rwbt
+            BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// backup_bus_pms_constrain_wifimac
+            BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
+            /// backup_bus_pms_constrain_pwr
+            BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x600c115c
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_usb_wrap
+            BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
+            /// backup_bus_pms_constrain_crypto_peri
+            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
+            /// backup_bus_pms_constrain_crypto_dma
+            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
+            /// backup_bus_pms_constrain_apb_adc
+            BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_bt_pwr
+            BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
+            /// backup_bus_pms_constrain_usb_device
+            BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x600c1160
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+        pub const BACKUP_BUS_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_lock
+            BACKUP_BUS_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x600c1164
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+        pub const BACKUP_BUS_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_clr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// backup_bus_pms_monitor_violate_en
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x600c1168
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+        pub const BACKUP_BUS_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_intr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// backup_bus_pms_monitor_violate_status_htrans
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
+            /// backup_bus_pms_monitor_violate_status_hsize
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+            /// backup_bus_pms_monitor_violate_status_hwrite
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x600c116c
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+        pub const BACKUP_BUS_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_haddr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
+        }), base_address + 0x16c);
+
+        /// address: 0x600c1170
+        /// SENSITIVE_CLOCK_GATE_REG
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x600c1ffc
+        /// SENSITIVE_DATE_REG
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
+    };
+
+    /// SHA (Secure Hash Algorithm) Accelerator
+    pub const SHA = struct {
+        pub const base_address = 0x6003b000;
+
+        /// address: 0x6003b000
+        /// Initial configuration register.
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x0);
+
+        /// address: 0x6003b004
+        /// SHA 512/t configuration register 0.
+        pub const T_STRING = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x6003b008
+        /// SHA 512/t configuration register 1.
+        pub const T_LENGTH = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8);
+
+        /// address: 0x6003b00c
+        /// DMA configuration register 0.
+        pub const DMA_BLOCK_NUM = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xc);
+
+        /// address: 0x6003b010
+        /// Typical SHA configuration register 0.
+        pub const START = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x10);
+
+        /// address: 0x6003b014
+        /// Typical SHA configuration register 1.
+        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x14);
+
+        /// address: 0x6003b018
+        /// Busy register.
+        pub const BUSY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Sha busy state. 1'b0: idle. 1'b1: busy.
+            STATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6003b01c
+        /// DMA configuration register 1.
+        pub const DMA_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c);
+
+        /// address: 0x6003b020
+        /// DMA configuration register 2.
+        pub const DMA_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
+
+        /// address: 0x6003b024
+        /// Interrupt clear register.
+        pub const CLEAR_IRQ = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Clear sha interrupt.
+            CLEAR_INTERRUPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6003b028
+        /// Interrupt enable register.
+        pub const IRQ_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+            INTERRUPT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6003b02c
+        /// Date register.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c);
+
+        /// address: 0x6003b040
+        /// Sha H memory which contains intermediate hash or finial hash.
+        pub const H_MEM = @intToPtr(*volatile [64]u8, base_address + 0x40);
+
+        /// address: 0x6003b080
+        /// Sha M memory which contains message.
+        pub const M_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI0 = struct {
+        pub const base_address = 0x60003000;
+
+        /// address: 0x60003008
+        /// SPI0 control register.
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller.
+            FDUMMY_OUT: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable
+            FCMD_QUAD: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
+            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+            FASTRD_MODE: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            FREAD_DUAL: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low
+            D_POL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            FREAD_QUAD: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
+            WP: u1,
+            reserved13: u1,
+            /// In the read operations address phase and read-data phase apply 2 signals. 1:
+            /// enable 0: disable.
+            FREAD_DIO: u1,
+            /// In the read operations address phase and read-data phase apply 4 signals. 1:
+            /// enable 0: disable.
+            FREAD_QIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000300c
+        /// SPI0 control1 register.
+        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on.
+            CLK_MODE: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            /// SPI0 RX FIFO reset signal.
+            RXFIFO_RST: u1,
+            padding0: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60003010
+        /// SPI0 control2 register.
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// (cycles-1) of prepare phase by spi clock this bits are combined with
+            /// spi_mem_cs_setup bit.
+            CS_SETUP_TIME: u5,
+            /// Spi cs signal is delayed to inactive by spi clock this bits are combined with
+            /// spi_mem_cs_hold bit.
+            CS_HOLD_TIME: u5,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// These bits are used to set the minimum CS high time tSHSL between SPI burst
+            /// transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+            /// core clock cycles.
+            CS_HOLD_DELAY: u6,
+            /// The FSM will be reset.
+            SYNC_RESET: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60003014
+        /// SPI clock division control register.
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_mem_clkcnt_N.
+            CLKCNT_L: u8,
+            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+            CLKCNT_H: u8,
+            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+            /// system/(spi_mem_clkcnt_N+1)
+            CLKCNT_N: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// Set this bit in 1-division mode.
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60003018
+        /// SPI0 user register.
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// spi cs keep low when spi is in done phase. 1: enable 0: disable.
+            CS_HOLD: u1,
+            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
+            CS_SETUP: u1,
+            reserved6: u1,
+            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
+            /// mode.
+            CK_OUT_EDGE: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// spi clock is disable in dummy phase when the bit is enable.
+            USR_DUMMY_IDLE: u1,
+            reserved23: u1,
+            reserved24: u1,
+            /// This bit enable the dummy phase of an operation.
+            USR_DUMMY: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000301c
+        /// SPI0 user1 register.
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1).
+            USR_DUMMY_CYCLELEN: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            USR_ADDR_BITLEN: u6,
+        }), base_address + 0x1c);
+
+        /// address: 0x60003020
+        /// SPI0 user2 register.
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1)
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x20);
+
+        /// address: 0x6000302c
+        /// SPI0 read control register.
+        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
+            /// bit.
+            WB_MODE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60003034
+        /// SPI0 misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to indicate the spi0_mst_st controlled transmitting is done.
+            TRANS_END: u1,
+            /// The bit is used to enable the interrupt of spi0_mst_st controlled transmitting
+            /// is done.
+            TRANS_END_INT_ENA: u1,
+            /// The bit is used to indicate the spi0_slv_st controlled transmitting is done.
+            CSPI_ST_TRANS_END: u1,
+            /// The bit is used to enable the interrupt of spi0_slv_st controlled transmitting
+            /// is done.
+            CSPI_ST_TRANS_END_INT_ENA: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set.
+            CS_KEEP_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x6000303c
+        /// SPI0 bit mode control register.
+        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For SPI0, Cache access enable, 1: enable, 0:disable.
+            CACHE_REQ_EN: u1,
+            /// For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
+            CACHE_USR_ADDR_4BYTE: u1,
+            /// For SPI0, cache read flash for user define command, 1: enable, 0:disable.
+            CACHE_FLASH_USR_CMD: u1,
+            /// For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FDIN_DUAL: u1,
+            /// For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FDOUT_DUAL: u1,
+            /// For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
+            /// the same with spi_mem_fread_dio.
+            FADDR_DUAL: u1,
+            /// For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FDIN_QUAD: u1,
+            /// For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FDOUT_QUAD: u1,
+            /// For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
+            /// the same with spi_mem_fread_qio.
+            FADDR_QUAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60003054
+        /// SPI0 FSM status register
+        pub const FSM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
+            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
+            /// state, 6:write data state, 7: done state, 8: read data end state.
+            CSPI_ST: u4,
+            /// The current status of SPI0 master FSM: spi0_mst_st. 0: idle state,
+            /// 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4:
+            /// wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+            EM_ST: u3,
+            /// The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+            CSPI_LOCK_DELAY_TIME: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600030a8
+        /// SPI0 timing calibration register
+        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable timing adjust clock for all reading operations.
+            TIMING_CLK_ENA: u1,
+            /// The bit is used to enable timing auto-calibration for all reading operations.
+            TIMING_CALI: u1,
+            /// add extra dummy spi clock cycle length for spi clock calibration.
+            EXTRA_DUMMY_CYCLELEN: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600030ac
+        /// SPI0 input delay mode control register
+        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN0_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN1_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN2_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN3_MODE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600030b0
+        /// SPI0 input delay number control register
+        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN0_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN1_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN2_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN3_NUM: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600030b4
+        /// SPI0 output delay mode control register
+        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT0_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT1_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT2_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT3_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600030dc
+        /// SPI0 clk_gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Register clock gate enable signal. 1: Enable. 0: Disable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600030e0
+        /// SPI0 module clock select register
+        pub const CORE_CLK_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the digital system clock selects PLL clock and the frequency of PLL clock
+            /// is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is
+            /// 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk)
+            /// 160MHz. 3: Not used. When the digital system clock selects PLL clock and the
+            /// frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1
+            /// module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1
+            /// module clock (clk) 160MHz. 3: Not used.
+            SPI01_CLK_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600033fc
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI1 = struct {
+        pub const base_address = 0x60002000;
+
+        /// address: 0x60002000
+        /// SPI1 memory command register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The current status of SPI1 master FSM.
+            SPI1_MST_ST: u4,
+            /// The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
+            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
+            /// state, 6:write data state, 7: done state, 8: read data end state.
+            MSPI_ST: u4,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In user mode, it is set to indicate that program/erase operation will be
+            /// triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared
+            /// once the operation done.1: enable 0: disable.
+            FLASH_PE: u1,
+            /// User define command enable. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            USR: u1,
+            /// Drive Flash into high performance mode. The bit will be cleared once the
+            /// operation done.1: enable 0: disable.
+            FLASH_HPM: u1,
+            /// This bit combined with reg_resandres bit releases Flash from the power-down
+            /// state or high performance mode and obtains the devices ID. The bit will be
+            /// cleared once the operation done.1: enable 0: disable.
+            FLASH_RES: u1,
+            /// Drive Flash into power down. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_DP: u1,
+            /// Chip erase enable. Chip erase operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_CE: u1,
+            /// Block erase enable(32KB) . Block erase operation will be triggered when the bit
+            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_BE: u1,
+            /// Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_SE: u1,
+            /// Page program enable(1 byte ~256 bytes data to be programmed). Page program
+            /// operation will be triggered when the bit is set. The bit will be cleared once
+            /// the operation done .1: enable 0: disable.
+            FLASH_PP: u1,
+            /// Write status register enable. Write status operation will be triggered when the
+            /// bit is set. The bit will be cleared once the operation done.1: enable 0:
+            /// disable.
+            FLASH_WRSR: u1,
+            /// Read status register-1. Read status operation will be triggered when the bit is
+            /// set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_RDSR: u1,
+            /// Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will
+            /// be cleared once the operation done. 1: enable 0: disable.
+            FLASH_RDID: u1,
+            /// Write flash disable. Write disable command will be sent when the bit is set. The
+            /// bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_WRDI: u1,
+            /// Write flash enable. Write enable command will be sent when the bit is set. The
+            /// bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_WREN: u1,
+            /// Read flash enable. Read flash operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_READ: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60002004
+        /// SPI1 address register
+        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In user mode, it is the memory address. other then the bit0-bit23 is the memory
+            /// address, the bit24-bit31 are the byte length of a transfer.
+            USR_ADDR_VALUE: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60002008
+        /// SPI1 control register.
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller.
+            FDUMMY_OUT: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable
+            FCMD_QUAD: u1,
+            reserved6: u1,
+            /// For SPI1, initialize crc32 module before writing encrypted data to flash. Active
+            /// low.
+            FCS_CRC_EN: u1,
+            /// For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+            TX_CRC_EN: u1,
+            reserved7: u1,
+            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
+            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+            FASTRD_MODE: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            FREAD_DUAL: u1,
+            /// The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
+            /// spi_mem_flash_res bit. 1: enable 0: disable.
+            RESANDRES: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low
+            D_POL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            FREAD_QUAD: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
+            WP: u1,
+            /// two bytes data will be written to status register when it is set. 1: enable 0:
+            /// disable.
+            WRSR_2B: u1,
+            /// In the read operations address phase and read-data phase apply 2 signals. 1:
+            /// enable 0: disable.
+            FREAD_DIO: u1,
+            /// In the read operations address phase and read-data phase apply 4 signals. 1:
+            /// enable 0: disable.
+            FREAD_QIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000200c
+        /// SPI1 control1 register.
+        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on.
+            CLK_MODE: u2,
+            /// After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
+            /// 512) SPI_CLK cycles.
+            CS_HOLD_DLY_RES: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60002010
+        /// SPI1 control2 register.
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// The FSM will be reset.
+            SYNC_RESET: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60002014
+        /// SPI1 clock division control register.
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_mem_clkcnt_N.
+            CLKCNT_L: u8,
+            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+            CLKCNT_H: u8,
+            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+            /// system/(spi_mem_clkcnt_N+1)
+            CLKCNT_N: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// reserved
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60002018
+        /// SPI1 user register.
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
+            /// mode.
+            CK_OUT_EDGE: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// In the write operations read-data phase apply 2 signals
+            FWRITE_DUAL: u1,
+            /// In the write operations read-data phase apply 4 signals
+            FWRITE_QUAD: u1,
+            /// In the write operations address phase and read-data phase apply 2 signals.
+            FWRITE_DIO: u1,
+            /// In the write operations address phase and read-data phase apply 4 signals.
+            FWRITE_QIO: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            /// read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+            /// 1: enable 0: disable.
+            USR_MISO_HIGHPART: u1,
+            /// write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+            /// 1: enable 0: disable.
+            USR_MOSI_HIGHPART: u1,
+            /// SPI clock is disable in dummy phase when the bit is enable.
+            USR_DUMMY_IDLE: u1,
+            /// This bit enable the write-data phase of an operation.
+            USR_MOSI: u1,
+            /// This bit enable the read-data phase of an operation.
+            USR_MISO: u1,
+            /// This bit enable the dummy phase of an operation.
+            USR_DUMMY: u1,
+            /// This bit enable the address phase of an operation.
+            USR_ADDR: u1,
+            /// This bit enable the command phase of an operation.
+            USR_COMMAND: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000201c
+        /// SPI1 user1 register.
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1).
+            USR_DUMMY_CYCLELEN: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            USR_ADDR_BITLEN: u6,
+        }), base_address + 0x1c);
+
+        /// address: 0x60002020
+        /// SPI1 user2 register.
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1)
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x20);
+
+        /// address: 0x60002024
+        /// SPI1 send data bit length control register.
+        pub const MOSI_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in bits of write-data. The register value shall be (bit_num-1).
+            USR_MOSI_DBITLEN: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60002028
+        /// SPI1 receive data bit length control register.
+        pub const MISO_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in bits of read-data. The register value shall be (bit_num-1).
+            USR_MISO_DBITLEN: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000202c
+        /// SPI1 status register.
+        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+            STATUS: u16,
+            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
+            /// bit.
+            WB_MODE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60002034
+        /// SPI1 misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+            /// device, such as flash, external RAM and so on.
+            CS0_DIS: u1,
+            /// SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+            /// device, such as flash, external RAM and so on.
+            CS1_DIS: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set.
+            CS_KEEP_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60002038
+        /// SPI1 TX CRC data register.
+        pub const TX_CRC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For SPI1, the value of crc32.
+            DATA: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6000203c
+        /// SPI1 bit mode control register.
+        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
+            CACHE_USR_ADDR_4BYTE: u1,
+            reserved1: u1,
+            /// For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_dio.
+            FDIN_DUAL: u1,
+            /// For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_dio.
+            FDOUT_DUAL: u1,
+            /// For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FADDR_DUAL: u1,
+            /// For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_qio.
+            FDIN_QUAD: u1,
+            /// For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_qio.
+            FDOUT_QUAD: u1,
+            /// For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FADDR_QUAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60002058
+        /// SPI1 memory data buffer0
+        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF0: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000205c
+        /// SPI1 memory data buffer1
+        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF1: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60002060
+        /// SPI1 memory data buffer2
+        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF2: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60002064
+        /// SPI1 memory data buffer3
+        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF3: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60002068
+        /// SPI1 memory data buffer4
+        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF4: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000206c
+        /// SPI1 memory data buffer5
+        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF5: u32,
+        }), base_address + 0x6c);
+
+        /// address: 0x60002070
+        /// SPI1 memory data buffer6
+        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF6: u32,
+        }), base_address + 0x70);
+
+        /// address: 0x60002074
+        /// SPI1 memory data buffer7
+        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF7: u32,
+        }), base_address + 0x74);
+
+        /// address: 0x60002078
+        /// SPI1 memory data buffer8
+        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF8: u32,
+        }), base_address + 0x78);
+
+        /// address: 0x6000207c
+        /// SPI1 memory data buffer9
+        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF9: u32,
+        }), base_address + 0x7c);
+
+        /// address: 0x60002080
+        /// SPI1 memory data buffer10
+        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF10: u32,
+        }), base_address + 0x80);
+
+        /// address: 0x60002084
+        /// SPI1 memory data buffer11
+        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF11: u32,
+        }), base_address + 0x84);
+
+        /// address: 0x60002088
+        /// SPI1 memory data buffer12
+        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF12: u32,
+        }), base_address + 0x88);
+
+        /// address: 0x6000208c
+        /// SPI1 memory data buffer13
+        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF13: u32,
+        }), base_address + 0x8c);
+
+        /// address: 0x60002090
+        /// SPI1 memory data buffer14
+        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF14: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x60002094
+        /// SPI1 memory data buffer15
+        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF15: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60002098
+        /// SPI1 wait idle control register
+        pub const FLASH_WAITI_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// The dummy phase enable when wait flash idle (RDSR)
+            WAITI_DUMMY: u1,
+            /// The command to wait flash idle(RDSR).
+            WAITI_CMD: u8,
+            /// The dummy cycle length when wait flash idle(RDSR).
+            WAITI_DUMMY_CYCLELEN: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6000209c
+        /// SPI1 flash suspend control register
+        pub const FLASH_SUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// program erase resume bit, program erase suspend operation will be triggered when
+            /// the bit is set. The bit will be cleared once the operation done.1: enable 0:
+            /// disable.
+            FLASH_PER: u1,
+            /// program erase suspend bit, program erase suspend operation will be triggered
+            /// when the bit is set. The bit will be cleared once the operation done.1: enable
+            /// 0: disable.
+            FLASH_PES: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+            /// program erase resume command is sent. 0: SPI1 does not wait after program erase
+            /// resume command is sent.
+            FLASH_PER_WAIT_EN: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+            /// program erase suspend command is sent. 0: SPI1 does not wait after program erase
+            /// suspend command is sent.
+            FLASH_PES_WAIT_EN: u1,
+            /// Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+            /// application should send PER after PES is done.
+            PES_PER_EN: u1,
+            /// Set this bit to enable Auto-suspending function.
+            FLASH_PES_EN: u1,
+            /// The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+            /// status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+            /// out, status_in[15:0] is valid when two bytes of data are read out),
+            /// SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+            PESR_END_MSK: u16,
+            /// 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte
+            /// when check flash SUS/SUS1/SUS2 status bit
+            RD_SUS_2B: u1,
+            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+            /// of flash. 0: Only need to check WIP is 0.
+            PER_END_EN: u1,
+            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend
+            /// status of flash. 0: Only need to check WIP is 0.
+            PES_END_EN: u1,
+            /// When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+            /// it will be treated as check pass.
+            SUS_TIMEOUT_CNT: u7,
+        }), base_address + 0x9c);
+
+        /// address: 0x600020a0
+        /// SPI1 flash suspend command register
+        pub const FLASH_SUS_CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Program/Erase resume command.
+            FLASH_PER_COMMAND: u8,
+            /// Program/Erase suspend command.
+            FLASH_PES_COMMAND: u8,
+            /// Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+            /// SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of
+            /// flash.
+            WAIT_PESR_COMMAND: u16,
+        }), base_address + 0xa0);
+
+        /// address: 0x600020a4
+        /// SPI1 flash suspend status register
+        pub const SUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status of flash suspend, only used in SPI1.
+            FLASH_SUS: u1,
+            /// 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+            /// SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+            WAIT_PESR_CMD_2B: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after HPM command is sent.
+            FLASH_HPM_DLY_128: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after RES command is sent.
+            FLASH_RES_DLY_128: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after DP command is sent.
+            FLASH_DP_DLY_128: u1,
+            /// Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
+            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
+            /// command is sent.
+            FLASH_PER_DLY_128: u1,
+            /// Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
+            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
+            /// command is sent.
+            FLASH_PES_DLY_128: u1,
+            /// 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+            SPI0_LOCK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600020a8
+        /// SPI1 timing control register
+        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// The bit is used to enable timing auto-calibration for all reading operations.
+            TIMING_CALI: u1,
+            /// add extra dummy spi clock cycle length for spi clock calibration.
+            EXTRA_DUMMY_CYCLELEN: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600020c0
+        /// SPI1 interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600020c4
+        /// SPI1 interrupt clear register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600020c8
+        /// SPI1 interrupt raw register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+            /// command (0x7A) is sent and flash is resumed. 0: Others.
+            PER_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+            /// command (0x75) is sent and flash is suspended. 0: Others.
+            PES_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
+            /// WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+            WPE_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
+            /// is changed from non idle state to idle state. It means that SPI_CS raises high.
+            /// 0: Others
+            SLV_ST_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
+            /// is changed from non idle state to idle state. 0: Others.
+            MST_ST_END_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600020cc
+        /// SPI1 interrupt status register
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600020dc
+        /// SPI1 clk_gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Register clock gate enable signal. 1: Enable. 0: Disable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600023fc
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI2 = struct {
+        pub const base_address = 0x60024000;
+
+        /// address: 0x60024000
+        /// Command control register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
+            CONF_BITLEN: u18,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// Set this bit to synchronize SPI registers from APB clock domain into SPI module
+            /// clock domain, which is only used in SPI master mode.
+            UPDATE: u1,
+            /// User define command enable. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+            /// changed by CONF_buf.
+            USR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60024004
+        /// Address value register
+        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Address to slave. Can be configured in CONF state.
+            USR_ADDR_VALUE: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60024008
+        /// SPI control register
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller. Can
+            /// be configured in CONF state.
+            DUMMY_OUT: u1,
+            reserved3: u1,
+            /// Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+            /// state.
+            FADDR_DUAL: u1,
+            /// Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+            /// state.
+            FADDR_QUAD: u1,
+            reserved4: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable. Can be configured in
+            /// CONF state.
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable. Can be configured in
+            /// CONF state.
+            FCMD_QUAD: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            /// Can be configured in CONF state.
+            FREAD_DUAL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            /// Can be configured in CONF state.
+            FREAD_QUAD: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+            /// CONF state.
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+            /// CONF state.
+            D_POL: u1,
+            /// SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+            /// configured in CONF state.
+            HOLD_POL: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low. Can
+            /// be configured in CONF state.
+            WP_POL: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+            /// state.
+            RD_BIT_ORDER: u1,
+            /// In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+            /// configured in CONF state.
+            WR_BIT_ORDER: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002400c
+        /// SPI clock control register
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must
+            /// be 0. Can be configured in CONF state.
+            CLKCNT_L: u6,
+            /// In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+            /// must be 0. Can be configured in CONF state.
+            CLKCNT_H: u6,
+            /// In the master mode it is the divider of spi_clk. So spi_clk frequency is
+            /// system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+            CLKCNT_N: u6,
+            /// In the master mode it is pre-divider of spi_clk. Can be configured in CONF
+            /// state.
+            CLKDIV_PRE: u4,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from
+            /// system clock. Can be configured in CONF state.
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60024010
+        /// SPI USER control register
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            DOUTDIN: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Both for master mode and slave mode. 1: spi controller is in QPI mode. 0:
+            /// others. Can be configured in CONF state.
+            QPI_MODE: u1,
+            reserved2: u1,
+            /// In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+            /// = spi_ck_i. 1:tsck = !spi_ck_i.
+            TSCK_I_EDGE: u1,
+            /// spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            CS_HOLD: u1,
+            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            CS_SETUP: u1,
+            /// In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+            /// = !spi_ck_i. 1:rsck = spi_ck_i.
+            RSCK_I_EDGE: u1,
+            /// the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.
+            /// Can be configured in CONF state.
+            CK_OUT_EDGE: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// In the write operations read-data phase apply 2 signals. Can be configured in
+            /// CONF state.
+            FWRITE_DUAL: u1,
+            /// In the write operations read-data phase apply 4 signals. Can be configured in
+            /// CONF state.
+            FWRITE_QUAD: u1,
+            reserved5: u1,
+            /// 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+            /// will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+            /// is not seg-trans mode. Can be configured in CONF state.
+            USR_CONF_NXT: u1,
+            reserved6: u1,
+            /// Set the bit to enable 3-line half duplex communication mosi and miso signals
+            /// share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+            SIO: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+            /// 0: disable. Can be configured in CONF state.
+            USR_MISO_HIGHPART: u1,
+            /// write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1:
+            /// enable 0: disable. Can be configured in CONF state.
+            USR_MOSI_HIGHPART: u1,
+            /// spi clock is disable in dummy phase when the bit is enable. Can be configured in
+            /// CONF state.
+            USR_DUMMY_IDLE: u1,
+            /// This bit enable the write-data phase of an operation. Can be configured in CONF
+            /// state.
+            USR_MOSI: u1,
+            /// This bit enable the read-data phase of an operation. Can be configured in CONF
+            /// state.
+            USR_MISO: u1,
+            /// This bit enable the dummy phase of an operation. Can be configured in CONF
+            /// state.
+            USR_DUMMY: u1,
+            /// This bit enable the address phase of an operation. Can be configured in CONF
+            /// state.
+            USR_ADDR: u1,
+            /// This bit enable the command phase of an operation. Can be configured in CONF
+            /// state.
+            USR_COMMAND: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60024014
+        /// SPI USER control register 1
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1). Can be configured in CONF state.
+            USR_DUMMY_CYCLELEN: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+            /// FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+            /// in GP-SPI master FD/HD-mode.
+            MST_WFULL_ERR_END_EN: u1,
+            /// (cycles+1) of prepare phase by spi clock this bits are combined with
+            /// spi_cs_setup bit. Can be configured in CONF state.
+            CS_SETUP_TIME: u5,
+            /// delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+            /// Can be configured in CONF state.
+            CS_HOLD_TIME: u5,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            /// Can be configured in CONF state.
+            USR_ADDR_BITLEN: u5,
+        }), base_address + 0x14);
+
+        /// address: 0x60024018
+        /// SPI USER control register 2
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command. Can be configured in CONF state.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+            /// master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty
+            /// error is valid in GP-SPI master FD/HD-mode.
+            MST_REMPTY_ERR_END_EN: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1).
+            /// Can be configured in CONF state.
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x18);
+
+        /// address: 0x6002401c
+        /// SPI data bit length control register
+        pub const MS_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of these bits is the configured SPI transmission data bit length in
+            /// master mode DMA controlled transfer or CPU controlled transfer. The value is
+            /// also the configured bit length in slave mode DMA RX controlled transfer. The
+            /// register value shall be (bit_num-1). Can be configured in CONF state.
+            MS_DATA_BITLEN: u18,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60024020
+        /// SPI misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be
+            /// configured in CONF state.
+            CS0_DIS: u1,
+            /// SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be
+            /// configured in CONF state.
+            CS1_DIS: u1,
+            /// SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be
+            /// configured in CONF state.
+            CS2_DIS: u1,
+            /// SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be
+            /// configured in CONF state.
+            CS3_DIS: u1,
+            /// SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be
+            /// configured in CONF state.
+            CS4_DIS: u1,
+            /// SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be
+            /// configured in CONF state.
+            CS5_DIS: u1,
+            /// 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
+            CK_DIS: u1,
+            /// In the master mode the bits are the polarity of spi cs line, the value is
+            /// equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+            MASTER_CS_POL: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// spi slave input cs polarity select. 1: inv 0: not change. Can be configured in
+            /// CONF state.
+            SLAVE_CS_POL: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be
+            /// configured in CONF state.
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set. Can be configured in CONF state.
+            CS_KEEP_ACTIVE: u1,
+            /// 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured
+            /// in CONF state.
+            QUAD_DIN_PIN_SWAP: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60024024
+        /// SPI input delay mode configuration
+        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN0_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN1_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN2_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN3_MODE: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in
+            /// CONF state.
+            TIMING_HCLK_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60024028
+        /// SPI input delay number configuration
+        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN0_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN1_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN2_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN3_NUM: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6002402c
+        /// SPI output delay mode configuration
+        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The output signal 0 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT0_MODE: u1,
+            /// The output signal 1 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT1_MODE: u1,
+            /// The output signal 2 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT2_MODE: u1,
+            /// The output signal 3 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT3_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60024030
+        /// SPI DMA control register
+        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+            DMA_SLV_SEG_TRANS_EN: u1,
+            /// 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+            /// spi_dma_infifo_full_vld is cleared by spi_trans_done.
+            SLV_RX_SEG_TRANS_CLR_EN: u1,
+            /// 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+            /// spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+            SLV_TX_SEG_TRANS_CLR_EN: u1,
+            /// 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal
+            /// to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0:
+            /// spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+            /// spi_dma_seg_trans_done in seg-trans.
+            RX_EOF_EN: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// Set this bit to enable SPI DMA controlled receive data mode.
+            DMA_RX_ENA: u1,
+            /// Set this bit to enable SPI DMA controlled send data mode.
+            DMA_TX_ENA: u1,
+            /// Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+            /// slave mode transfer.
+            RX_AFIFO_RST: u1,
+            /// Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+            /// controlled mode transfer and master mode transfer.
+            BUF_AFIFO_RST: u1,
+            /// Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+            /// DMA controlled mode transfer.
+            DMA_AFIFO_RST: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60024034
+        /// SPI DMA interrupt enable register
+        pub const DMA_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
+            /// The enable bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_ENA: u1,
+            /// The enable bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_ENA: u1,
+            /// The enable bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_APP2_INT interrupt.
+            APP2_INT_ENA: u1,
+            /// The enable bit for SPI_APP1_INT interrupt.
+            APP1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60024038
+        /// SPI DMA interrupt clear register
+        pub const DMA_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
+            /// The clear bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_CLR: u1,
+            /// The clear bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_CLR: u1,
+            /// The clear bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_APP2_INT interrupt.
+            APP2_INT_CLR: u1,
+            /// The clear bit for SPI_APP1_INT interrupt.
+            APP1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002403c
+        /// SPI DMA interrupt raw register
+        pub const DMA_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+            /// the receive data. 0: Others.
+            DMA_INFIFO_FULL_ERR_INT_RAW: u1,
+            /// 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+            /// master mode and send out all 0 in slave mode. 0: Others.
+            DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
+            /// The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI
+            /// transmission is ended. 0: Others.
+            SLV_EX_QPI_INT_RAW: u1,
+            /// The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI
+            /// transmission is ended. 0: Others.
+            SLV_EN_QPI_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+            /// ended. 0: Others.
+            SLV_CMD7_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+            /// ended. 0: Others.
+            SLV_CMD8_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+            /// ended. 0: Others.
+            SLV_CMD9_INT_RAW: u1,
+            /// The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+            /// ended. 0: Others.
+            SLV_CMDA_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+            /// transmission is ended. 0: Others.
+            SLV_RD_DMA_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+            /// transmission is ended. 0: Others.
+            SLV_WR_DMA_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+            /// transmission is ended. 0: Others.
+            SLV_RD_BUF_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+            /// transmission is ended. 0: Others.
+            SLV_WR_BUF_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+            /// ended. 0: others.
+            TRANS_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA
+            /// full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+            /// And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans
+            /// is not ended or not occurred.
+            DMA_SEG_TRANS_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF
+            /// buffer is error in the DMA seg-conf-trans. 0: others.
+            SEG_MAGIC_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data
+            /// address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF
+            /// transmission is bigger than 63. 0: Others.
+            SLV_BUF_ADDR_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+            /// current SPI slave HD mode transmission is not supported. 0: Others.
+            SLV_CMD_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+            /// write-full error when SPI inputs data in master mode. 0: Others.
+            MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+            /// AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+            MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_APP2_INT interrupt. The value is only controlled by
+            /// application.
+            APP2_INT_RAW: u1,
+            /// The raw bit for SPI_APP1_INT interrupt. The value is only controlled by
+            /// application.
+            APP1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60024040
+        /// SPI DMA interrupt status register
+        pub const DMA_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_ST: u1,
+            /// The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
+            /// The status bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_ST: u1,
+            /// The status bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_ST: u1,
+            /// The status bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_ST: u1,
+            /// The status bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_ST: u1,
+            /// The status bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_ST: u1,
+            /// The status bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_ST: u1,
+            /// The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_ST: u1,
+            /// The status bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_ST: u1,
+            /// The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_ST: u1,
+            /// The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_ST: u1,
+            /// The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_ST: u1,
+            /// The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_ST: u1,
+            /// The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
+            /// The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
+            /// The status bit for SPI_APP2_INT interrupt.
+            APP2_INT_ST: u1,
+            /// The status bit for SPI_APP1_INT interrupt.
+            APP1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60024098
+        /// SPI CPU-controlled buffer0
+        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF0: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6002409c
+        /// SPI CPU-controlled buffer1
+        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF1: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600240a0
+        /// SPI CPU-controlled buffer2
+        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF2: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600240a4
+        /// SPI CPU-controlled buffer3
+        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF3: u32,
+        }), base_address + 0xa4);
+
+        /// address: 0x600240a8
+        /// SPI CPU-controlled buffer4
+        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF4: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600240ac
+        /// SPI CPU-controlled buffer5
+        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF5: u32,
+        }), base_address + 0xac);
+
+        /// address: 0x600240b0
+        /// SPI CPU-controlled buffer6
+        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF6: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600240b4
+        /// SPI CPU-controlled buffer7
+        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF7: u32,
+        }), base_address + 0xb4);
+
+        /// address: 0x600240b8
+        /// SPI CPU-controlled buffer8
+        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF8: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600240bc
+        /// SPI CPU-controlled buffer9
+        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF9: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600240c0
+        /// SPI CPU-controlled buffer10
+        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF10: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600240c4
+        /// SPI CPU-controlled buffer11
+        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF11: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600240c8
+        /// SPI CPU-controlled buffer12
+        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF12: u32,
+        }), base_address + 0xc8);
+
+        /// address: 0x600240cc
+        /// SPI CPU-controlled buffer13
+        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF13: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600240d0
+        /// SPI CPU-controlled buffer14
+        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF14: u32,
+        }), base_address + 0xd0);
+
+        /// address: 0x600240d4
+        /// SPI CPU-controlled buffer15
+        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF15: u32,
+        }), base_address + 0xd4);
+
+        /// address: 0x600240e0
+        /// SPI slave control register
+        pub const SLAVE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+            CLK_MODE: u2,
+            /// {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+            /// 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+            CLK_MODE_13: u1,
+            /// It saves half a cycle when tsck is the same as rsck. 1: output data at rsck
+            /// posedge 0: output data at tsck posedge
+            RSCK_DATA_OUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
+            /// in DMA controlled mode(Rd_DMA). 0: others
+            SLV_RDDMA_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
+            /// length in DMA controlled mode(Wr_DMA). 0: others
+            SLV_WRDMA_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
+            /// in CPU controlled mode(Rd_BUF). 0: others
+            SLV_RDBUF_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
+            /// length in CPU controlled mode(Wr_BUF). 0: others
+            SLV_WRBUF_BITLEN_EN: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// The magic value of BM table in master DMA seg-trans.
+            DMA_SEG_MAGIC_VALUE: u4,
+            /// Set SPI work mode. 1: slave mode 0: master mode.
+            MODE: u1,
+            /// Software reset enable, reset the spi clock line cs line and data lines. Can be
+            /// configured in CONF state.
+            SOFT_RESET: u1,
+            /// 1: Enable the DMA CONF phase of current seg-trans operation, which means
+            /// seg-trans will start. 0: This is not seg-trans mode.
+            USR_CONF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600240e4
+        /// SPI slave control register 1
+        pub const SLAVE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The transferred data bit length in SPI slave FD and HD mode.
+            SLV_DATA_BITLEN: u18,
+            /// In the slave mode it is the value of command.
+            SLV_LAST_COMMAND: u8,
+            /// In the slave mode it is the value of address.
+            SLV_LAST_ADDR: u6,
+        }), base_address + 0xe4);
+
+        /// address: 0x600240e8
+        /// SPI module clock and register clock control
+        pub const CLK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable clk gate
+            CLK_EN: u1,
+            /// Set this bit to power on the SPI module clock.
+            MST_CLK_ACTIVE: u1,
+            /// This bit is used to select SPI module clock source in master mode. 1:
+            /// PLL_CLK_80M. 0: XTAL CLK.
+            MST_CLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xe8);
+
+        /// address: 0x600240f0
+        /// Version control
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xf0);
+    };
+
+    /// System
+    pub const SYSTEM = struct {
+        pub const base_address = 0x600c0000;
+
+        /// address: 0x600c0000
+        /// cpu_peripheral clock gating register
+        pub const CPU_PERI_CLK_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// reg_clk_en_assist_debug
+            CLK_EN_ASSIST_DEBUG: u1,
+            /// reg_clk_en_dedicated_gpio
+            CLK_EN_DEDICATED_GPIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600c0004
+        /// cpu_peripheral reset register
+        pub const CPU_PERI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// reg_rst_en_assist_debug
+            RST_EN_ASSIST_DEBUG: u1,
+            /// reg_rst_en_dedicated_gpio
+            RST_EN_DEDICATED_GPIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600c0008
+        /// cpu clock config register
+        pub const CPU_PER_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_cpuperiod_sel
+            CPUPERIOD_SEL: u2,
+            /// reg_pll_freq_sel
+            PLL_FREQ_SEL: u1,
+            /// reg_cpu_wait_mode_force_on
+            CPU_WAIT_MODE_FORCE_ON: u1,
+            /// reg_cpu_waiti_delay_num
+            CPU_WAITI_DELAY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600c000c
+        /// memory power down mask register
+        pub const MEM_PD_MASK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lslp_mem_pd_mask
+            LSLP_MEM_PD_MASK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600c0010
+        /// peripheral clock gating register
+        pub const PERIP_CLK_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timers_clk_en
+            TIMERS_CLK_EN: u1,
+            /// reg_spi01_clk_en
+            SPI01_CLK_EN: u1,
+            /// reg_uart_clk_en
+            UART_CLK_EN: u1,
+            /// reg_wdg_clk_en
+            WDG_CLK_EN: u1,
+            /// reg_i2s0_clk_en
+            I2S0_CLK_EN: u1,
+            /// reg_uart1_clk_en
+            UART1_CLK_EN: u1,
+            /// reg_spi2_clk_en
+            SPI2_CLK_EN: u1,
+            /// reg_ext0_clk_en
+            I2C_EXT0_CLK_EN: u1,
+            /// reg_uhci0_clk_en
+            UHCI0_CLK_EN: u1,
+            /// reg_rmt_clk_en
+            RMT_CLK_EN: u1,
+            /// reg_pcnt_clk_en
+            PCNT_CLK_EN: u1,
+            /// reg_ledc_clk_en
+            LEDC_CLK_EN: u1,
+            /// reg_uhci1_clk_en
+            UHCI1_CLK_EN: u1,
+            /// reg_timergroup_clk_en
+            TIMERGROUP_CLK_EN: u1,
+            /// reg_efuse_clk_en
+            EFUSE_CLK_EN: u1,
+            /// reg_timergroup1_clk_en
+            TIMERGROUP1_CLK_EN: u1,
+            /// reg_spi3_clk_en
+            SPI3_CLK_EN: u1,
+            /// reg_pwm0_clk_en
+            PWM0_CLK_EN: u1,
+            /// reg_ext1_clk_en
+            EXT1_CLK_EN: u1,
+            /// reg_can_clk_en
+            CAN_CLK_EN: u1,
+            /// reg_pwm1_clk_en
+            PWM1_CLK_EN: u1,
+            /// reg_i2s1_clk_en
+            I2S1_CLK_EN: u1,
+            /// reg_spi2_dma_clk_en
+            SPI2_DMA_CLK_EN: u1,
+            /// reg_usb_device_clk_en
+            USB_DEVICE_CLK_EN: u1,
+            /// reg_uart_mem_clk_en
+            UART_MEM_CLK_EN: u1,
+            /// reg_pwm2_clk_en
+            PWM2_CLK_EN: u1,
+            /// reg_pwm3_clk_en
+            PWM3_CLK_EN: u1,
+            /// reg_spi3_dma_clk_en
+            SPI3_DMA_CLK_EN: u1,
+            /// reg_apb_saradc_clk_en
+            APB_SARADC_CLK_EN: u1,
+            /// reg_systimer_clk_en
+            SYSTIMER_CLK_EN: u1,
+            /// reg_adc2_arb_clk_en
+            ADC2_ARB_CLK_EN: u1,
+            /// reg_spi4_clk_en
+            SPI4_CLK_EN: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x600c0014
+        /// peripheral clock gating register
+        pub const PERIP_CLK_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_crypto_aes_clk_en
+            CRYPTO_AES_CLK_EN: u1,
+            /// reg_crypto_sha_clk_en
+            CRYPTO_SHA_CLK_EN: u1,
+            /// reg_crypto_rsa_clk_en
+            CRYPTO_RSA_CLK_EN: u1,
+            /// reg_crypto_ds_clk_en
+            CRYPTO_DS_CLK_EN: u1,
+            /// reg_crypto_hmac_clk_en
+            CRYPTO_HMAC_CLK_EN: u1,
+            /// reg_dma_clk_en
+            DMA_CLK_EN: u1,
+            /// reg_sdio_host_clk_en
+            SDIO_HOST_CLK_EN: u1,
+            /// reg_lcd_cam_clk_en
+            LCD_CAM_CLK_EN: u1,
+            /// reg_uart2_clk_en
+            UART2_CLK_EN: u1,
+            /// reg_tsens_clk_en
+            TSENS_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x600c0018
+        /// reserved
+        pub const PERIP_RST_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timers_rst
+            TIMERS_RST: u1,
+            /// reg_spi01_rst
+            SPI01_RST: u1,
+            /// reg_uart_rst
+            UART_RST: u1,
+            /// reg_wdg_rst
+            WDG_RST: u1,
+            /// reg_i2s0_rst
+            I2S0_RST: u1,
+            /// reg_uart1_rst
+            UART1_RST: u1,
+            /// reg_spi2_rst
+            SPI2_RST: u1,
+            /// reg_ext0_rst
+            I2C_EXT0_RST: u1,
+            /// reg_uhci0_rst
+            UHCI0_RST: u1,
+            /// reg_rmt_rst
+            RMT_RST: u1,
+            /// reg_pcnt_rst
+            PCNT_RST: u1,
+            /// reg_ledc_rst
+            LEDC_RST: u1,
+            /// reg_uhci1_rst
+            UHCI1_RST: u1,
+            /// reg_timergroup_rst
+            TIMERGROUP_RST: u1,
+            /// reg_efuse_rst
+            EFUSE_RST: u1,
+            /// reg_timergroup1_rst
+            TIMERGROUP1_RST: u1,
+            /// reg_spi3_rst
+            SPI3_RST: u1,
+            /// reg_pwm0_rst
+            PWM0_RST: u1,
+            /// reg_ext1_rst
+            EXT1_RST: u1,
+            /// reg_can_rst
+            CAN_RST: u1,
+            /// reg_pwm1_rst
+            PWM1_RST: u1,
+            /// reg_i2s1_rst
+            I2S1_RST: u1,
+            /// reg_spi2_dma_rst
+            SPI2_DMA_RST: u1,
+            /// reg_usb_device_rst
+            USB_DEVICE_RST: u1,
+            /// reg_uart_mem_rst
+            UART_MEM_RST: u1,
+            /// reg_pwm2_rst
+            PWM2_RST: u1,
+            /// reg_pwm3_rst
+            PWM3_RST: u1,
+            /// reg_spi3_dma_rst
+            SPI3_DMA_RST: u1,
+            /// reg_apb_saradc_rst
+            APB_SARADC_RST: u1,
+            /// reg_systimer_rst
+            SYSTIMER_RST: u1,
+            /// reg_adc2_arb_rst
+            ADC2_ARB_RST: u1,
+            /// reg_spi4_rst
+            SPI4_RST: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x600c001c
+        /// peripheral reset register
+        pub const PERIP_RST_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_crypto_aes_rst
+            CRYPTO_AES_RST: u1,
+            /// reg_crypto_sha_rst
+            CRYPTO_SHA_RST: u1,
+            /// reg_crypto_rsa_rst
+            CRYPTO_RSA_RST: u1,
+            /// reg_crypto_ds_rst
+            CRYPTO_DS_RST: u1,
+            /// reg_crypto_hmac_rst
+            CRYPTO_HMAC_RST: u1,
+            /// reg_dma_rst
+            DMA_RST: u1,
+            /// reg_sdio_host_rst
+            SDIO_HOST_RST: u1,
+            /// reg_lcd_cam_rst
+            LCD_CAM_RST: u1,
+            /// reg_uart2_rst
+            UART2_RST: u1,
+            /// reg_tsens_rst
+            TSENS_RST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c0020
+        /// clock config register
+        pub const BT_LPCK_DIV_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_bt_lpck_div_num
+            BT_LPCK_DIV_NUM: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x600c0024
+        /// clock config register
+        pub const BT_LPCK_DIV_FRAC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_bt_lpck_div_b
+            BT_LPCK_DIV_B: u12,
+            /// reg_bt_lpck_div_a
+            BT_LPCK_DIV_A: u12,
+            /// reg_lpclk_sel_rtc_slow
+            LPCLK_SEL_RTC_SLOW: u1,
+            /// reg_lpclk_sel_8m
+            LPCLK_SEL_8M: u1,
+            /// reg_lpclk_sel_xtal
+            LPCLK_SEL_XTAL: u1,
+            /// reg_lpclk_sel_xtal32k
+            LPCLK_SEL_XTAL32K: u1,
+            /// reg_lpclk_rtc_en
+            LPCLK_RTC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x600c0028
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_0 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x28);
+
+        /// address: 0x600c002c
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_1 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x2c);
+
+        /// address: 0x600c0030
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_2 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30);
+
+        /// address: 0x600c0034
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_3 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x34);
+
+        /// address: 0x600c0038
+        /// rsa memory power control register
+        pub const RSA_PD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rsa_mem_pd
+            RSA_MEM_PD: u1,
+            /// reg_rsa_mem_force_pu
+            RSA_MEM_FORCE_PU: u1,
+            /// reg_rsa_mem_force_pd
+            RSA_MEM_FORCE_PD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x600c003c
+        /// edma clcok and reset register
+        pub const EDMA_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_edma_clk_on
+            EDMA_CLK_ON: u1,
+            /// reg_edma_reset
+            EDMA_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x600c0040
+        /// cache control register
+        pub const CACHE_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_icache_clk_on
+            ICACHE_CLK_ON: u1,
+            /// reg_icache_reset
+            ICACHE_RESET: u1,
+            /// reg_dcache_clk_on
+            DCACHE_CLK_ON: u1,
+            /// reg_dcache_reset
+            DCACHE_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c0044
+        /// SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+        pub const EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_enable_spi_manual_encrypt
+            ENABLE_SPI_MANUAL_ENCRYPT: u1,
+            /// reg_enable_download_db_encrypt
+            ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
+            /// reg_enable_download_g0cb_decrypt
+            ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
+            /// reg_enable_download_manual_encrypt
+            ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600c0048
+        /// fast memory config register
+        pub const RTC_FASTMEM_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// reg_rtc_mem_crc_start
+            RTC_MEM_CRC_START: u1,
+            /// reg_rtc_mem_crc_addr
+            RTC_MEM_CRC_ADDR: u11,
+            /// reg_rtc_mem_crc_len
+            RTC_MEM_CRC_LEN: u11,
+            /// reg_rtc_mem_crc_finish
+            RTC_MEM_CRC_FINISH: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x600c004c
+        /// reserved
+        pub const RTC_FASTMEM_CRC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rtc_mem_crc_res
+            RTC_MEM_CRC_RES: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x600c0050
+        /// eco register
+        pub const REDUNDANT_ECO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redundant_eco_drive
+            REDUNDANT_ECO_DRIVE: u1,
+            /// reg_redundant_eco_result
+            REDUNDANT_ECO_RESULT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600c0054
+        /// clock gating register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600c0058
+        /// system clock config register
+        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_pre_div_cnt
+            PRE_DIV_CNT: u10,
+            /// reg_soc_clk_sel
+            SOC_CLK_SEL: u2,
+            /// reg_clk_xtal_freq
+            CLK_XTAL_FREQ: u7,
+            /// reg_clk_div_en
+            CLK_DIV_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600c005c
+        /// mem pvt register
+        pub const MEM_PVT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_path_len
+            MEM_PATH_LEN: u4,
+            /// reg_mem_err_cnt_clr
+            MEM_ERR_CNT_CLR: u1,
+            /// reg_mem_pvt_monitor_en
+            MONITOR_EN: u1,
+            /// reg_mem_timing_err_cnt
+            MEM_TIMING_ERR_CNT: u16,
+            /// reg_mem_vt_sel
+            MEM_VT_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x600c0060
+        /// mem pvt register
+        pub const COMB_PVT_LVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_lvt
+            COMB_PATH_LEN_LVT: u5,
+            /// reg_comb_err_cnt_clr_lvt
+            COMB_ERR_CNT_CLR_LVT: u1,
+            /// reg_comb_pvt_monitor_en_lvt
+            COMB_PVT_MONITOR_EN_LVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600c0064
+        /// mem pvt register
+        pub const COMB_PVT_NVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_nvt
+            COMB_PATH_LEN_NVT: u5,
+            /// reg_comb_err_cnt_clr_nvt
+            COMB_ERR_CNT_CLR_NVT: u1,
+            /// reg_comb_pvt_monitor_en_nvt
+            COMB_PVT_MONITOR_EN_NVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c0068
+        /// mem pvt register
+        pub const COMB_PVT_HVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_hvt
+            COMB_PATH_LEN_HVT: u5,
+            /// reg_comb_err_cnt_clr_hvt
+            COMB_ERR_CNT_CLR_HVT: u1,
+            /// reg_comb_pvt_monitor_en_hvt
+            COMB_PVT_MONITOR_EN_HVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600c006c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site0
+            COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600c0070
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site0
+            COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600c0074
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site0
+            COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600c0078
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site1
+            COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c007c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site1
+            COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c0080
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site1
+            COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c0084
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site2
+            COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c0088
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site2
+            COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c008c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site2
+            COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c0090
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site3
+            COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c0094
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site3
+            COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x600c0098
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site3
+            COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c0ffc
+        /// Version register
+        pub const SYSTEM_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
+    };
+
+    /// System Timer
+    pub const SYSTIMER = struct {
+        pub const base_address = 0x60023000;
+
+        /// address: 0x60023000
+        /// SYSTIMER_CONF.
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// systimer clock force on
+            SYSTIMER_CLK_FO: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            /// target2 work enable
+            TARGET2_WORK_EN: u1,
+            /// target1 work enable
+            TARGET1_WORK_EN: u1,
+            /// target0 work enable
+            TARGET0_WORK_EN: u1,
+            /// If timer unit1 is stalled when core1 stalled
+            TIMER_UNIT1_CORE1_STALL_EN: u1,
+            /// If timer unit1 is stalled when core0 stalled
+            TIMER_UNIT1_CORE0_STALL_EN: u1,
+            /// If timer unit0 is stalled when core1 stalled
+            TIMER_UNIT0_CORE1_STALL_EN: u1,
+            /// If timer unit0 is stalled when core0 stalled
+            TIMER_UNIT0_CORE0_STALL_EN: u1,
+            /// timer unit1 work enable
+            TIMER_UNIT1_WORK_EN: u1,
+            /// timer unit0 work enable
+            TIMER_UNIT0_WORK_EN: u1,
+            /// register file clk gating
+            CLK_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60023004
+        /// SYSTIMER_UNIT0_OP.
+        pub const UNIT0_OP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_timer_unit0_value_valid
+            TIMER_UNIT0_VALUE_VALID: u1,
+            /// update timer_unit0
+            TIMER_UNIT0_UPDATE: u1,
+            padding0: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60023008
+        /// SYSTIMER_UNIT1_OP.
+        pub const UNIT1_OP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// timer value is sync and valid
+            TIMER_UNIT1_VALUE_VALID: u1,
+            /// update timer unit1
+            TIMER_UNIT1_UPDATE: u1,
+            padding0: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002300c
+        /// SYSTIMER_UNIT0_LOAD_HI.
+        pub const UNIT0_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load high 32 bit
+            TIMER_UNIT0_LOAD_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60023010
+        /// SYSTIMER_UNIT0_LOAD_LO.
+        pub const UNIT0_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load low 32 bit
+            TIMER_UNIT0_LOAD_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60023014
+        /// SYSTIMER_UNIT1_LOAD_HI.
+        pub const UNIT1_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load high 32 bit
+            TIMER_UNIT1_LOAD_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60023018
+        /// SYSTIMER_UNIT1_LOAD_LO.
+        pub const UNIT1_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load low 32 bit
+            TIMER_UNIT1_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002301c
+        /// SYSTIMER_TARGET0_HI.
+        pub const TARGET0_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget0 high 32 bit
+            TIMER_TARGET0_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60023020
+        /// SYSTIMER_TARGET0_LO.
+        pub const TARGET0_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget0 low 32 bit
+            TIMER_TARGET0_LO: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60023024
+        /// SYSTIMER_TARGET1_HI.
+        pub const TARGET1_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget1 high 32 bit
+            TIMER_TARGET1_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60023028
+        /// SYSTIMER_TARGET1_LO.
+        pub const TARGET1_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget1 low 32 bit
+            TIMER_TARGET1_LO: u32,
+        }), base_address + 0x28);
+
+        /// address: 0x6002302c
+        /// SYSTIMER_TARGET2_HI.
+        pub const TARGET2_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget2 high 32 bit
+            TIMER_TARGET2_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60023030
+        /// SYSTIMER_TARGET2_LO.
+        pub const TARGET2_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget2 low 32 bit
+            TIMER_TARGET2_LO: u32,
+        }), base_address + 0x30);
+
+        /// address: 0x60023034
+        /// SYSTIMER_TARGET0_CONF.
+        pub const TARGET0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target0 period
+            TARGET0_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target0 to period mode
+            TARGET0_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET0_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60023038
+        /// SYSTIMER_TARGET1_CONF.
+        pub const TARGET1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target1 period
+            TARGET1_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target1 to period mode
+            TARGET1_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET1_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002303c
+        /// SYSTIMER_TARGET2_CONF.
+        pub const TARGET2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target2 period
+            TARGET2_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target2 to period mode
+            TARGET2_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET2_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60023040
+        /// SYSTIMER_UNIT0_VALUE_HI.
+        pub const UNIT0_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value high 32bit
+            TIMER_UNIT0_VALUE_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60023044
+        /// SYSTIMER_UNIT0_VALUE_LO.
+        pub const UNIT0_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value low 32bit
+            TIMER_UNIT0_VALUE_LO: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60023048
+        /// SYSTIMER_UNIT1_VALUE_HI.
+        pub const UNIT1_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value high 32bit
+            TIMER_UNIT1_VALUE_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002304c
+        /// SYSTIMER_UNIT1_VALUE_LO.
+        pub const UNIT1_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value low 32bit
+            TIMER_UNIT1_VALUE_LO: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60023050
+        /// SYSTIMER_COMP0_LOAD.
+        pub const COMP0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp0 load value
+            TIMER_COMP0_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60023054
+        /// SYSTIMER_COMP1_LOAD.
+        pub const COMP1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp1 load value
+            TIMER_COMP1_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60023058
+        /// SYSTIMER_COMP2_LOAD.
+        pub const COMP2_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp2 load value
+            TIMER_COMP2_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002305c
+        /// SYSTIMER_UNIT0_LOAD.
+        pub const UNIT0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load value
+            TIMER_UNIT0_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60023060
+        /// SYSTIMER_UNIT1_LOAD.
+        pub const UNIT1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load value
+            TIMER_UNIT1_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60023064
+        /// SYSTIMER_INT_ENA.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 enable
+            TARGET0_INT_ENA: u1,
+            /// interupt1 enable
+            TARGET1_INT_ENA: u1,
+            /// interupt2 enable
+            TARGET2_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60023068
+        /// SYSTIMER_INT_RAW.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 raw
+            TARGET0_INT_RAW: u1,
+            /// interupt1 raw
+            TARGET1_INT_RAW: u1,
+            /// interupt2 raw
+            TARGET2_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002306c
+        /// SYSTIMER_INT_CLR.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 clear
+            TARGET0_INT_CLR: u1,
+            /// interupt1 clear
+            TARGET1_INT_CLR: u1,
+            /// interupt2 clear
+            TARGET2_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60023070
+        /// SYSTIMER_INT_ST.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_target0_int_st
+            TARGET0_INT_ST: u1,
+            /// reg_target1_int_st
+            TARGET1_INT_ST: u1,
+            /// reg_target2_int_st
+            TARGET2_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600230fc
+        /// SYSTIMER_DATE.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0xfc);
+    };
+
+    /// Timer Group
+    pub const TIMG0 = struct {
+        pub const base_address = 0x6001f000;
+
+        /// address: 0x6001f000
+        /// TIMG_T0CONFIG_REG.
+        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// reg_t0_use_xtal.
+            T0_USE_XTAL: u1,
+            /// reg_t0_alarm_en.
+            T0_ALARM_EN: u1,
+            reserved9: u1,
+            /// reg_t0_divcnt_rst.
+            T0_DIVCNT_RST: u1,
+            /// reg_t0_divider.
+            T0_DIVIDER: u16,
+            /// reg_t0_autoreload.
+            T0_AUTORELOAD: u1,
+            /// reg_t0_increase.
+            T0_INCREASE: u1,
+            /// reg_t0_en.
+            T0_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6001f004
+        /// TIMG_T0LO_REG.
+        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_lo
+            T0_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x6001f008
+        /// TIMG_T0HI_REG.
+        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_hi
+            T0_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001f00c
+        /// TIMG_T0UPDATE_REG.
+        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// t0_update
+            T0_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6001f010
+        /// TIMG_T0ALARMLO_REG.
+        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_lo.
+            T0_ALARM_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x6001f014
+        /// TIMG_T0ALARMHI_REG.
+        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_hi.
+            T0_ALARM_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6001f018
+        /// TIMG_T0LOADLO_REG.
+        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_lo.
+            T0_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6001f01c
+        /// TIMG_T0LOADHI_REG.
+        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_hi.
+            T0_LOAD_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6001f020
+        /// TIMG_T0LOAD_REG.
+        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_load
+            T0_LOAD: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x6001f048
+        /// TIMG_WDTCONFIG0_REG.
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_wdt_appcpu_reset_en.
+            WDT_APPCPU_RESET_EN: u1,
+            /// reg_wdt_procpu_reset_en.
+            WDT_PROCPU_RESET_EN: u1,
+            /// reg_wdt_flashboot_mod_en.
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// reg_wdt_sys_reset_length.
+            WDT_SYS_RESET_LENGTH: u3,
+            /// reg_wdt_cpu_reset_length.
+            WDT_CPU_RESET_LENGTH: u3,
+            /// reg_wdt_use_xtal.
+            WDT_USE_XTAL: u1,
+            /// reg_wdt_conf_update_en.
+            WDT_CONF_UPDATE_EN: u1,
+            /// reg_wdt_stg3.
+            WDT_STG3: u2,
+            /// reg_wdt_stg2.
+            WDT_STG2: u2,
+            /// reg_wdt_stg1.
+            WDT_STG1: u2,
+            /// reg_wdt_stg0.
+            WDT_STG0: u2,
+            /// reg_wdt_en.
+            WDT_EN: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001f04c
+        /// TIMG_WDTCONFIG1_REG.
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_divcnt_rst.
+            WDT_DIVCNT_RST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reg_wdt_clk_prescale.
+            WDT_CLK_PRESCALE: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x6001f050
+        /// TIMG_WDTCONFIG2_REG.
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg0_hold.
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x6001f054
+        /// TIMG_WDTCONFIG3_REG.
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg1_hold.
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x6001f058
+        /// TIMG_WDTCONFIG4_REG.
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg2_hold.
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6001f05c
+        /// TIMG_WDTCONFIG5_REG.
+        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg3_hold.
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x6001f060
+        /// TIMG_WDTFEED_REG.
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wdt_feed
+            WDT_FEED: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x6001f064
+        /// TIMG_WDTWPROTECT_REG.
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_wkey.
+            WDT_WKEY: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x6001f068
+        /// TIMG_RTCCALICFG_REG.
+        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_rtc_cali_start_cycling.
+            RTC_CALI_START_CYCLING: u1,
+            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+            RTC_CALI_CLK_SEL: u2,
+            /// rtc_cali_rdy
+            RTC_CALI_RDY: u1,
+            /// reg_rtc_cali_max.
+            RTC_CALI_MAX: u15,
+            /// reg_rtc_cali_start.
+            RTC_CALI_START: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001f06c
+        /// TIMG_RTCCALICFG1_REG.
+        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc_cali_cycling_data_vld
+            RTC_CALI_CYCLING_DATA_VLD: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// rtc_cali_value
+            RTC_CALI_VALUE: u25,
+        }), base_address + 0x6c);
+
+        /// address: 0x6001f070
+        /// INT_ENA_TIMG_REG
+        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_ena
+            T0_INT_ENA: u1,
+            /// wdt_int_ena
+            WDT_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6001f074
+        /// INT_RAW_TIMG_REG
+        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_raw
+            T0_INT_RAW: u1,
+            /// wdt_int_raw
+            WDT_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6001f078
+        /// INT_ST_TIMG_REG
+        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_st
+            T0_INT_ST: u1,
+            /// wdt_int_st
+            WDT_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001f07c
+        /// INT_CLR_TIMG_REG
+        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_clr
+            T0_INT_CLR: u1,
+            /// wdt_int_clr
+            WDT_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6001f080
+        /// TIMG_RTCCALICFG2_REG.
+        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timeoutindicator
+            RTC_CALI_TIMEOUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+            RTC_CALI_TIMEOUT_RST_CNT: u4,
+            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+            RTC_CALI_TIMEOUT_THRES: u25,
+        }), base_address + 0x80);
+
+        /// address: 0x6001f0f8
+        /// TIMG_NTIMG_DATE_REG.
+        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ntimers_date.
+            NTIMGS_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x6001f0fc
+        /// TIMG_REGCLK_REG.
+        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_wdt_clk_is_active.
+            WDT_CLK_IS_ACTIVE: u1,
+            /// reg_timer_clk_is_active.
+            TIMER_CLK_IS_ACTIVE: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// Timer Group
+    pub const TIMG1 = struct {
+        pub const base_address = 0x60020000;
+
+        /// address: 0x60020000
+        /// TIMG_T0CONFIG_REG.
+        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// reg_t0_use_xtal.
+            T0_USE_XTAL: u1,
+            /// reg_t0_alarm_en.
+            T0_ALARM_EN: u1,
+            reserved9: u1,
+            /// reg_t0_divcnt_rst.
+            T0_DIVCNT_RST: u1,
+            /// reg_t0_divider.
+            T0_DIVIDER: u16,
+            /// reg_t0_autoreload.
+            T0_AUTORELOAD: u1,
+            /// reg_t0_increase.
+            T0_INCREASE: u1,
+            /// reg_t0_en.
+            T0_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60020004
+        /// TIMG_T0LO_REG.
+        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_lo
+            T0_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60020008
+        /// TIMG_T0HI_REG.
+        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_hi
+            T0_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002000c
+        /// TIMG_T0UPDATE_REG.
+        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// t0_update
+            T0_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60020010
+        /// TIMG_T0ALARMLO_REG.
+        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_lo.
+            T0_ALARM_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60020014
+        /// TIMG_T0ALARMHI_REG.
+        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_hi.
+            T0_ALARM_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60020018
+        /// TIMG_T0LOADLO_REG.
+        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_lo.
+            T0_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002001c
+        /// TIMG_T0LOADHI_REG.
+        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_hi.
+            T0_LOAD_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60020020
+        /// TIMG_T0LOAD_REG.
+        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_load
+            T0_LOAD: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60020048
+        /// TIMG_WDTCONFIG0_REG.
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_wdt_appcpu_reset_en.
+            WDT_APPCPU_RESET_EN: u1,
+            /// reg_wdt_procpu_reset_en.
+            WDT_PROCPU_RESET_EN: u1,
+            /// reg_wdt_flashboot_mod_en.
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// reg_wdt_sys_reset_length.
+            WDT_SYS_RESET_LENGTH: u3,
+            /// reg_wdt_cpu_reset_length.
+            WDT_CPU_RESET_LENGTH: u3,
+            /// reg_wdt_use_xtal.
+            WDT_USE_XTAL: u1,
+            /// reg_wdt_conf_update_en.
+            WDT_CONF_UPDATE_EN: u1,
+            /// reg_wdt_stg3.
+            WDT_STG3: u2,
+            /// reg_wdt_stg2.
+            WDT_STG2: u2,
+            /// reg_wdt_stg1.
+            WDT_STG1: u2,
+            /// reg_wdt_stg0.
+            WDT_STG0: u2,
+            /// reg_wdt_en.
+            WDT_EN: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002004c
+        /// TIMG_WDTCONFIG1_REG.
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_divcnt_rst.
+            WDT_DIVCNT_RST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reg_wdt_clk_prescale.
+            WDT_CLK_PRESCALE: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x60020050
+        /// TIMG_WDTCONFIG2_REG.
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg0_hold.
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60020054
+        /// TIMG_WDTCONFIG3_REG.
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg1_hold.
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60020058
+        /// TIMG_WDTCONFIG4_REG.
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg2_hold.
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6002005c
+        /// TIMG_WDTCONFIG5_REG.
+        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg3_hold.
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60020060
+        /// TIMG_WDTFEED_REG.
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wdt_feed
+            WDT_FEED: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60020064
+        /// TIMG_WDTWPROTECT_REG.
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_wkey.
+            WDT_WKEY: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60020068
+        /// TIMG_RTCCALICFG_REG.
+        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_rtc_cali_start_cycling.
+            RTC_CALI_START_CYCLING: u1,
+            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+            RTC_CALI_CLK_SEL: u2,
+            /// rtc_cali_rdy
+            RTC_CALI_RDY: u1,
+            /// reg_rtc_cali_max.
+            RTC_CALI_MAX: u15,
+            /// reg_rtc_cali_start.
+            RTC_CALI_START: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002006c
+        /// TIMG_RTCCALICFG1_REG.
+        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc_cali_cycling_data_vld
+            RTC_CALI_CYCLING_DATA_VLD: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// rtc_cali_value
+            RTC_CALI_VALUE: u25,
+        }), base_address + 0x6c);
+
+        /// address: 0x60020070
+        /// INT_ENA_TIMG_REG
+        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_ena
+            T0_INT_ENA: u1,
+            /// wdt_int_ena
+            WDT_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60020074
+        /// INT_RAW_TIMG_REG
+        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_raw
+            T0_INT_RAW: u1,
+            /// wdt_int_raw
+            WDT_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60020078
+        /// INT_ST_TIMG_REG
+        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_st
+            T0_INT_ST: u1,
+            /// wdt_int_st
+            WDT_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6002007c
+        /// INT_CLR_TIMG_REG
+        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_clr
+            T0_INT_CLR: u1,
+            /// wdt_int_clr
+            WDT_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60020080
+        /// TIMG_RTCCALICFG2_REG.
+        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timeoutindicator
+            RTC_CALI_TIMEOUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+            RTC_CALI_TIMEOUT_RST_CNT: u4,
+            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+            RTC_CALI_TIMEOUT_THRES: u25,
+        }), base_address + 0x80);
+
+        /// address: 0x600200f8
+        /// TIMG_NTIMG_DATE_REG.
+        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ntimers_date.
+            NTIMGS_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600200fc
+        /// TIMG_REGCLK_REG.
+        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_wdt_clk_is_active.
+            WDT_CLK_IS_ACTIVE: u1,
+            /// reg_timer_clk_is_active.
+            TIMER_CLK_IS_ACTIVE: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// Two-Wire Automotive Interface
+    pub const TWAI = struct {
+        pub const base_address = 0x6002b000;
+
+        /// address: 0x6002b000
+        /// Mode Register
+        pub const MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to configure the operating mode of the TWAI Controller. 1:
+            /// Reset mode; 0: Operating mode.
+            RESET_MODE: u1,
+            /// 1: Listen only mode. In this mode the nodes will only receive messages from the
+            /// bus, without generating the acknowledge signal nor updating the RX error
+            /// counter.
+            LISTEN_ONLY_MODE: u1,
+            /// 1: Self test mode. In this mode the TX nodes can perform a successful
+            /// transmission without receiving the acknowledge signal. This mode is often used
+            /// to test a single node with the self reception request command.
+            SELF_TEST_MODE: u1,
+            /// This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single
+            /// filter mode.
+            RX_FILTER_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6002b004
+        /// Command Register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set the bit to 1 to allow the driving nodes start transmission.
+            TX_REQ: u1,
+            /// Set the bit to 1 to cancel a pending transmission request.
+            ABORT_TX: u1,
+            /// Set the bit to 1 to release the RX buffer.
+            RELEASE_BUF: u1,
+            /// Set the bit to 1 to clear the data overrun status bit.
+            CLR_OVERRUN: u1,
+            /// Self reception request command. Set the bit to 1 to allow a message be
+            /// transmitted and received simultaneously.
+            SELF_RX_REQ: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6002b008
+        /// Status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: The data in the RX buffer is not empty, with at least one received data
+            /// packet.
+            RX_BUF_ST: u1,
+            /// 1: The RX FIFO is full and data overrun has occurred.
+            OVERRUN_ST: u1,
+            /// 1: The TX buffer is empty, the CPU may write a message into it.
+            TX_BUF_ST: u1,
+            /// 1: The TWAI controller has successfully received a packet from the bus.
+            TX_COMPLETE: u1,
+            /// 1: The TWAI Controller is receiving a message from the bus.
+            RX_ST: u1,
+            /// 1: The TWAI Controller is transmitting a message to the bus.
+            TX_ST: u1,
+            /// 1: At least one of the RX/TX error counter has reached or exceeded the value set
+            /// in register TWAI_ERR_WARNING_LIMIT_REG.
+            ERR_ST: u1,
+            /// 1: In bus-off status, the TWAI Controller is no longer involved in bus
+            /// activities.
+            BUS_OFF_ST: u1,
+            /// This bit reflects whether the data packet in the RX FIFO is complete. 1: The
+            /// current packet is missing; 0: The current packet is complete
+            MISS_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002b00c
+        /// Interrupt Register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Receive interrupt. If this bit is set to 1, it indicates there are messages to
+            /// be handled in the RX FIFO.
+            RX_INT_ST: u1,
+            /// Transmit interrupt. If this bit is set to 1, it indicates the message
+            /// transmitting mis- sion is finished and a new transmission is able to execute.
+            TX_INT_ST: u1,
+            /// Error warning interrupt. If this bit is set to 1, it indicates the error status
+            /// signal and the bus-off status signal of Status register have changed (e.g.,
+            /// switched from 0 to 1 or from 1 to 0).
+            ERR_WARN_INT_ST: u1,
+            /// Data overrun interrupt. If this bit is set to 1, it indicates a data overrun
+            /// interrupt is generated in the RX FIFO.
+            OVERRUN_INT_ST: u1,
+            reserved0: u1,
+            /// Error passive interrupt. If this bit is set to 1, it indicates the TWAI
+            /// Controller is switched between error active status and error passive status due
+            /// to the change of error counters.
+            ERR_PASSIVE_INT_ST: u1,
+            /// Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration
+            /// lost interrupt is generated.
+            ARB_LOST_INT_ST: u1,
+            /// Error interrupt. If this bit is set to 1, it indicates an error is detected on
+            /// the bus.
+            BUS_ERR_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6002b010
+        /// Interrupt Enable Register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to 1 to enable receive interrupt.
+            RX_INT_ENA: u1,
+            /// Set this bit to 1 to enable transmit interrupt.
+            TX_INT_ENA: u1,
+            /// Set this bit to 1 to enable error warning interrupt.
+            ERR_WARN_INT_ENA: u1,
+            /// Set this bit to 1 to enable data overrun interrupt.
+            OVERRUN_INT_ENA: u1,
+            reserved0: u1,
+            /// Set this bit to 1 to enable error passive interrupt.
+            ERR_PASSIVE_INT_ENA: u1,
+            /// Set this bit to 1 to enable arbitration lost interrupt.
+            ARB_LOST_INT_ENA: u1,
+            /// Set this bit to 1 to enable error interrupt.
+            BUS_ERR_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6002b018
+        /// Bus Timing Register 0
+        pub const BUS_TIMING_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Baud Rate Prescaler, determines the frequency dividing ratio.
+            BAUD_PRESC: u13,
+            reserved0: u1,
+            /// Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+            SYNC_JUMP_WIDTH: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6002b01c
+        /// Bus Timing Register 1
+        pub const BUS_TIMING_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of PBS1.
+            TIME_SEG1: u4,
+            /// The width of PBS2.
+            TIME_SEG2: u3,
+            /// The number of sample points. 0: the bus is sampled once; 1: the bus is sampled
+            /// three times
+            TIME_SAMP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6002b02c
+        /// Arbitration Lost Capture Register
+        pub const ARB_LOST_CAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
+
+        /// address: 0x6002b030
+        /// Error Code Capture Register
+        pub const ERR_CODE_CAP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register contains information about the location of errors, see Table 181
+            /// for details.
+            ECC_SEGMENT: u5,
+            /// This register contains information about transmission direction of the node when
+            /// error occurs. 1: Error occurs when receiving a message; 0: Error occurs when
+            /// transmitting a message
+            ECC_DIRECTION: u1,
+            /// This register contains information about error types: 00: bit error; 01: form
+            /// error; 10: stuff error; 11: other type of error
+            ECC_TYPE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6002b034
+        /// Error Warning Limit Register
+        pub const ERR_WARNING_LIMIT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
+
+        /// address: 0x6002b038
+        /// Receive Error Counter Register
+        pub const RX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x38);
+
+        /// address: 0x6002b03c
+        /// Transmit Error Counter Register
+        pub const TX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x3c);
+
+        /// address: 0x6002b040
+        /// Data register 0
+        pub const DATA_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 0 with R/W Permission. In
+            /// operation mode, it stores the 0th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_0: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6002b044
+        /// Data register 1
+        pub const DATA_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 1 with R/W Permission. In
+            /// operation mode, it stores the 1st byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6002b048
+        /// Data register 2
+        pub const DATA_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 2 with R/W Permission. In
+            /// operation mode, it stores the 2nd byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_2: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002b04c
+        /// Data register 3
+        pub const DATA_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 3 with R/W Permission. In
+            /// operation mode, it stores the 3rd byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_3: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x6002b050
+        /// Data register 4
+        pub const DATA_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 0 with R/W Permission. In
+            /// operation mode, it stores the 4th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_4: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6002b054
+        /// Data register 5
+        pub const DATA_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 1 with R/W Permission. In
+            /// operation mode, it stores the 5th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_5: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6002b058
+        /// Data register 6
+        pub const DATA_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 2 with R/W Permission. In
+            /// operation mode, it stores the 6th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_6: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002b05c
+        /// Data register 7
+        pub const DATA_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 3 with R/W Permission. In
+            /// operation mode, it stores the 7th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_7: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6002b060
+        /// Data register 8
+        pub const DATA_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 8th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_8: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x6002b064
+        /// Data register 9
+        pub const DATA_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 9th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_9: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x6002b068
+        /// Data register 10
+        pub const DATA_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 10th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_10: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002b06c
+        /// Data register 11
+        pub const DATA_11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 11th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_11: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6002b070
+        /// Data register 12
+        pub const DATA_12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 12th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_12: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6002b074
+        /// Receive Message Counter Register
+        pub const RX_MESSAGE_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register reflects the number of messages available within the RX FIFO.
+            RX_MESSAGE_COUNTER: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6002b07c
+        /// Clock Divider register
+        pub const CLOCK_DIVIDER = @intToPtr(*volatile Mmio(32, packed struct {
+            /// These bits are used to configure frequency dividing coefficients of the external
+            /// CLKOUT pin.
+            CD: u8,
+            /// This bit can be configured under reset mode. 1: Disable the external CLKOUT pin;
+            /// 0: Enable the external CLKOUT pin
+            CLOCK_OFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x7c);
+    };
+
+    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
+    pub const UART0 = struct {
+        pub const base_address = 0x60000000;
+
+        /// address: 0x60000000
+        /// FIFO data register
+        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// UART 0 accesses FIFO via this register.
+            RXFIFO_RD_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60000004
+        /// Raw interrupt status
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// what rxfifo_full_thrhd specifies.
+            RXFIFO_FULL_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+            /// less than what txfifo_empty_thrhd specifies .
+            TXFIFO_EMPTY_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// in the data.
+            PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error .
+            FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// the FIFO can store.
+            RXFIFO_OVF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of DSRn signal.
+            DSR_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of CTSn signal.
+            CTS_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
+            /// stop bit.
+            BRK_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver takes more time than
+            /// rx_tout_thrhd to receive a byte.
+            RXFIFO_TOUT_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XON_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XOFF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
+            /// middle of a start bit.
+            GLITCH_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter completes sending
+            /// NULL characters, after all data in Tx-FIFO are sent.
+            TX_BRK_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has kept the
+            /// shortest duration after sending the last data.
+            TX_BRK_IDLE_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has send out all
+            /// data in FIFO.
+            TX_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// from the echo of transmitter in rs485 mode.
+            RS485_PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error from the echo of transmitter in rs485 mode.
+            RS485_FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when detects a clash between
+            /// transmitter and receiver in rs485 mode.
+            RS485_CLASH_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the configured
+            /// at_cmd char.
+            AT_CMD_CHAR_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when input rxd edge changes more
+            /// times than what reg_active_threshold specifies in light sleeping mode.
+            WAKEUP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60000008
+        /// Masked interrupt status
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
+            /// to 1.
+            RXFIFO_FULL_INT_ST: u1,
+            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
+            /// to 1.
+            TXFIFO_EMPTY_INT_ST: u1,
+            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+            /// 1.
+            PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+            FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+            /// 1.
+            RXFIFO_OVF_INT_ST: u1,
+            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+            DSR_CHG_INT_ST: u1,
+            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+            CTS_CHG_INT_ST: u1,
+            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+            BRK_DET_INT_ST: u1,
+            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
+            /// to 1.
+            RXFIFO_TOUT_INT_ST: u1,
+            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+            SW_XON_INT_ST: u1,
+            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+            SW_XOFF_INT_ST: u1,
+            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+            /// 1.
+            GLITCH_DET_INT_ST: u1,
+            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
+            /// to 1.
+            TX_BRK_DONE_INT_ST: u1,
+            /// This is the stauts bit for tx_brk_idle_done_int_raw when
+            /// tx_brk_idle_done_int_ena is set to 1.
+            TX_BRK_IDLE_DONE_INT_ST: u1,
+            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+            TX_DONE_INT_ST: u1,
+            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+            /// set to 1.
+            RS485_PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
+            /// set to 1.
+            RS485_FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
+            /// to 1.
+            RS485_CLASH_INT_ST: u1,
+            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
+            /// set to 1.
+            AT_CMD_CHAR_DET_INT_ST: u1,
+            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
+            /// to 1.
+            WAKEUP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000000c
+        /// Interrupt enable bits
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the enable bit for rxfifo_full_int_st register.
+            RXFIFO_FULL_INT_ENA: u1,
+            /// This is the enable bit for txfifo_empty_int_st register.
+            TXFIFO_EMPTY_INT_ENA: u1,
+            /// This is the enable bit for parity_err_int_st register.
+            PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for frm_err_int_st register.
+            FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_ovf_int_st register.
+            RXFIFO_OVF_INT_ENA: u1,
+            /// This is the enable bit for dsr_chg_int_st register.
+            DSR_CHG_INT_ENA: u1,
+            /// This is the enable bit for cts_chg_int_st register.
+            CTS_CHG_INT_ENA: u1,
+            /// This is the enable bit for brk_det_int_st register.
+            BRK_DET_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_tout_int_st register.
+            RXFIFO_TOUT_INT_ENA: u1,
+            /// This is the enable bit for sw_xon_int_st register.
+            SW_XON_INT_ENA: u1,
+            /// This is the enable bit for sw_xoff_int_st register.
+            SW_XOFF_INT_ENA: u1,
+            /// This is the enable bit for glitch_det_int_st register.
+            GLITCH_DET_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_done_int_st register.
+            TX_BRK_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_idle_done_int_st register.
+            TX_BRK_IDLE_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_done_int_st register.
+            TX_DONE_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_clash_int_st register.
+            RS485_CLASH_INT_ENA: u1,
+            /// This is the enable bit for at_cmd_char_det_int_st register.
+            AT_CMD_CHAR_DET_INT_ENA: u1,
+            /// This is the enable bit for uart_wakeup_int_st register.
+            WAKEUP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60000010
+        /// Interrupt clear bits
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
+            RXFIFO_FULL_INT_CLR: u1,
+            /// Set this bit to clear txfifo_empty_int_raw interrupt.
+            TXFIFO_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear parity_err_int_raw interrupt.
+            PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear frm_err_int_raw interrupt.
+            FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
+            RXFIFO_OVF_INT_CLR: u1,
+            /// Set this bit to clear the dsr_chg_int_raw interrupt.
+            DSR_CHG_INT_CLR: u1,
+            /// Set this bit to clear the cts_chg_int_raw interrupt.
+            CTS_CHG_INT_CLR: u1,
+            /// Set this bit to clear the brk_det_int_raw interrupt.
+            BRK_DET_INT_CLR: u1,
+            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
+            RXFIFO_TOUT_INT_CLR: u1,
+            /// Set this bit to clear the sw_xon_int_raw interrupt.
+            SW_XON_INT_CLR: u1,
+            /// Set this bit to clear the sw_xoff_int_raw interrupt.
+            SW_XOFF_INT_CLR: u1,
+            /// Set this bit to clear the glitch_det_int_raw interrupt.
+            GLITCH_DET_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
+            TX_BRK_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+            TX_BRK_IDLE_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_done_int_raw interrupt.
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
+            RS485_PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
+            RS485_FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_clash_int_raw interrupt.
+            RS485_CLASH_INT_CLR: u1,
+            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+            AT_CMD_CHAR_DET_INT_CLR: u1,
+            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
+            WAKEUP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60000014
+        /// Clock divider configuration
+        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The integral part of the frequency divider factor.
+            CLKDIV: u12,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// The decimal part of the frequency divider factor.
+            FRAG: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60000018
+        /// Rx Filter configuration
+        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// when input pulse width is lower than this value, the pulse is ignored.
+            GLITCH_FILT: u8,
+            /// Set this bit to enable Rx signal filter.
+            GLITCH_FILT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000001c
+        /// UART status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the byte number of valid data in Rx-FIFO.
+            RXFIFO_CNT: u10,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The register represent the level value of the internal uart dsr signal.
+            DSRN: u1,
+            /// This register represent the level value of the internal uart cts signal.
+            CTSN: u1,
+            /// This register represent the level value of the internal uart rxd signal.
+            RXD: u1,
+            /// Stores the byte number of data in Tx-FIFO.
+            TXFIFO_CNT: u10,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// This bit represents the level of the internal uart dtr signal.
+            DTRN: u1,
+            /// This bit represents the level of the internal uart rts signal.
+            RTSN: u1,
+            /// This bit represents the level of the internal uart txd signal.
+            TXD: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60000020
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the parity check mode.
+            PARITY: u1,
+            /// Set this bit to enable uart parity check.
+            PARITY_EN: u1,
+            /// This register is used to set the length of data.
+            BIT_NUM: u2,
+            /// This register is used to set the length of stop bit.
+            STOP_BIT_NUM: u2,
+            /// This register is used to configure the software rts signal which is used in
+            /// software flow control.
+            SW_RTS: u1,
+            /// This register is used to configure the software dtr signal which is used in
+            /// software flow control.
+            SW_DTR: u1,
+            /// Set this bit to enbale transmitter to send NULL when the process of sending data
+            /// is done.
+            TXD_BRK: u1,
+            /// Set this bit to enable IrDA loopback mode.
+            IRDA_DPLX: u1,
+            /// This is the start enable bit for IrDA transmitter.
+            IRDA_TX_EN: u1,
+            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+            /// transmitter's 11th bit to 0.
+            IRDA_WCTL: u1,
+            /// Set this bit to invert the level of IrDA transmitter.
+            IRDA_TX_INV: u1,
+            /// Set this bit to invert the level of IrDA receiver.
+            IRDA_RX_INV: u1,
+            /// Set this bit to enable uart loopback test mode.
+            LOOPBACK: u1,
+            /// Set this bit to enable flow control function for transmitter.
+            TX_FLOW_EN: u1,
+            /// Set this bit to enable IrDA protocol.
+            IRDA_EN: u1,
+            /// Set this bit to reset the uart receive-FIFO.
+            RXFIFO_RST: u1,
+            /// Set this bit to reset the uart transmit-FIFO.
+            TXFIFO_RST: u1,
+            /// Set this bit to inverse the level value of uart rxd signal.
+            RXD_INV: u1,
+            /// Set this bit to inverse the level value of uart cts signal.
+            CTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dsr signal.
+            DSR_INV: u1,
+            /// Set this bit to inverse the level value of uart txd signal.
+            TXD_INV: u1,
+            /// Set this bit to inverse the level value of uart rts signal.
+            RTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dtr signal.
+            DTR_INV: u1,
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+            /// stores the data even if the received data is wrong.
+            ERR_WR_MASK: u1,
+            /// This is the enable bit for detecting baudrate.
+            AUTOBAUD_EN: u1,
+            /// UART memory clock gate enable signal.
+            MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60000024
+        /// Configuration register 1
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
+            /// this register value.
+            RXFIFO_FULL_THRHD: u9,
+            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
+            /// less than this register value.
+            TXFIFO_EMPTY_THRHD: u9,
+            /// Disable UART Rx data overflow detect.
+            DIS_RX_DAT_OVF: u1,
+            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
+            RX_TOUT_FLOW_DIS: u1,
+            /// This is the flow enable bit for UART receiver.
+            RX_FLOW_EN: u1,
+            /// This is the enble bit for uart receiver's timeout function.
+            RX_TOUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60000028
+        /// Autobaud minimum low pulse duration register
+        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the minimum duration time of the low level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000002c
+        /// Autobaud minimum high pulse duration register
+        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the maxinum duration time for the high level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60000030
+        /// Autobaud edge change count register
+        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the count of rxd edge change. It is used in baud
+            /// rate-detect process.
+            RXD_EDGE_CNT: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60000034
+        /// Software flow-control configuration
+        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable software flow control. It is used with register sw_xon or
+            /// sw_xoff.
+            SW_FLOW_CON_EN: u1,
+            /// Set this bit to remove flow control char from the received data.
+            XONOFF_DEL: u1,
+            /// Set this bit to enable the transmitter to go on sending data.
+            FORCE_XON: u1,
+            /// Set this bit to stop the transmitter from sending data.
+            FORCE_XOFF: u1,
+            /// Set this bit to send Xon char. It is cleared by hardware automatically.
+            SEND_XON: u1,
+            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
+            SEND_XOFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60000038
+        /// Sleep-mode configuration
+        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The uart is activated from light sleeping mode when the input rxd edge changes
+            /// more times than this register value.
+            ACTIVE_THRESHOLD: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000003c
+        /// Software flow-control character configuration
+        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is more than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
+            XOFF_THRESHOLD: u9,
+            /// This register stores the Xoff flow control char.
+            XOFF_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60000040
+        /// Software flow-control character configuration
+        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is less than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
+            XON_THRESHOLD: u9,
+            /// This register stores the Xon flow control char.
+            XON_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60000044
+        /// Tx Break character configuration
+        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the number of 0 to be sent after the process
+            /// of sending data is done. It is active when txd_brk is set to 1.
+            TX_BRK_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60000048
+        /// Frame-end idle configuration
+        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce frame end signal when receiver takes more time to receive one
+            /// byte data than this register value.
+            RX_IDLE_THRHD: u10,
+            /// This register is used to configure the duration time between transfers.
+            TX_IDLE_NUM: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000004c
+        /// RS485 mode configuration
+        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to choose the rs485 mode.
+            RS485_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL0_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL1_EN: u1,
+            /// Set this bit to enable receiver could receive data when the transmitter is
+            /// transmitting data in rs485 mode.
+            RS485TX_RX_EN: u1,
+            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+            RS485RXBY_TX_EN: u1,
+            /// This register is used to delay the receiver's internal data signal.
+            RS485_RX_DLY_NUM: u1,
+            /// This register is used to delay the transmitter's internal data signal.
+            RS485_TX_DLY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60000050
+        /// Pre-sequence timing configuration
+        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the idle duration time before the first
+            /// at_cmd is received by receiver.
+            PRE_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60000054
+        /// Post-sequence timing configuration
+        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the last at_cmd and
+            /// the next data.
+            POST_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60000058
+        /// Timeout configuration
+        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the at_cmd chars.
+            RX_GAP_TOUT: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6000005c
+        /// AT escape sequence detection configuration
+        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the content of at_cmd char.
+            AT_CMD_CHAR: u8,
+            /// This register is used to configure the num of continuous at_cmd chars received
+            /// by receiver.
+            CHAR_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60000060
+        /// UART threshold and allocation configuration
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// This register is used to configure the amount of mem allocated for receive-FIFO.
+            /// The default number is 128 bytes.
+            RX_SIZE: u3,
+            /// This register is used to configure the amount of mem allocated for
+            /// transmit-FIFO. The default number is 128 bytes.
+            TX_SIZE: u3,
+            /// This register is used to configure the maximum amount of data that can be
+            /// received when hardware flow control works.
+            RX_FLOW_THRHD: u9,
+            /// This register is used to configure the threshold time that receiver takes to
+            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
+            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
+            RX_TOUT_THRHD: u10,
+            /// Set this bit to force power down UART memory.
+            MEM_FORCE_PD: u1,
+            /// Set this bit to force power up UART memory.
+            MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60000064
+        /// Tx-FIFO write and read offset address.
+        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+            /// via APB.
+            APB_TX_WADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+            /// Tx-FIFO_Ctrl.
+            TX_RADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60000068
+        /// Rx-FIFO write and read offset address.
+        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in RX-FIFO when software reads data from
+            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+            APB_RX_RADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+            RX_WADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6000006c
+        /// UART transmit and receive status.
+        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status register of receiver.
+            ST_URX_OUT: u4,
+            /// This is the status register of transmitter.
+            ST_UTX_OUT: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60000070
+        /// Autobaud high pulse register
+        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two positive edges.
+            /// It is used in boudrate-detect process.
+            POSEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60000074
+        /// Autobaud low pulse register
+        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two negative edges.
+            /// It is used in boudrate-detect process.
+            NEGEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60000078
+        /// UART core clock configuration
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The denominator of the frequency divider factor.
+            SCLK_DIV_B: u6,
+            /// The numerator of the frequency divider factor.
+            SCLK_DIV_A: u6,
+            /// The integral part of the frequency divider factor.
+            SCLK_DIV_NUM: u8,
+            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+            SCLK_SEL: u2,
+            /// Set this bit to enable UART Tx/Rx clock.
+            SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
+            RST_CORE: u1,
+            /// Set this bit to enable UART Tx clock.
+            TX_SCLK_EN: u1,
+            /// Set this bit to enable UART Rx clock.
+            RX_SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx.
+            TX_RST_CORE: u1,
+            /// Write 1 then write 0 to this bit, reset UART Rx.
+            RX_RST_CORE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000007c
+        /// UART Version register
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x60000080
+        /// UART ID register
+        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the uart_id.
+            ID: u30,
+            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
+            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
+            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
+            /// synchronize registers.
+            HIGH_SPEED: u1,
+            /// Software write 1 would synchronize registers into UART Core clock domain and
+            /// would be cleared by hardware after synchronization is done.
+            REG_UPDATE: u1,
+        }), base_address + 0x80);
+    };
+
+    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
+    pub const UART1 = struct {
+        pub const base_address = 0x60010000;
+
+        /// address: 0x60010000
+        /// FIFO data register
+        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// UART 0 accesses FIFO via this register.
+            RXFIFO_RD_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60010004
+        /// Raw interrupt status
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// what rxfifo_full_thrhd specifies.
+            RXFIFO_FULL_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+            /// less than what txfifo_empty_thrhd specifies .
+            TXFIFO_EMPTY_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// in the data.
+            PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error .
+            FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// the FIFO can store.
+            RXFIFO_OVF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of DSRn signal.
+            DSR_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of CTSn signal.
+            CTS_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
+            /// stop bit.
+            BRK_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver takes more time than
+            /// rx_tout_thrhd to receive a byte.
+            RXFIFO_TOUT_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XON_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XOFF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
+            /// middle of a start bit.
+            GLITCH_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter completes sending
+            /// NULL characters, after all data in Tx-FIFO are sent.
+            TX_BRK_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has kept the
+            /// shortest duration after sending the last data.
+            TX_BRK_IDLE_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has send out all
+            /// data in FIFO.
+            TX_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// from the echo of transmitter in rs485 mode.
+            RS485_PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error from the echo of transmitter in rs485 mode.
+            RS485_FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when detects a clash between
+            /// transmitter and receiver in rs485 mode.
+            RS485_CLASH_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the configured
+            /// at_cmd char.
+            AT_CMD_CHAR_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when input rxd edge changes more
+            /// times than what reg_active_threshold specifies in light sleeping mode.
+            WAKEUP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60010008
+        /// Masked interrupt status
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
+            /// to 1.
+            RXFIFO_FULL_INT_ST: u1,
+            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
+            /// to 1.
+            TXFIFO_EMPTY_INT_ST: u1,
+            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+            /// 1.
+            PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+            FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+            /// 1.
+            RXFIFO_OVF_INT_ST: u1,
+            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+            DSR_CHG_INT_ST: u1,
+            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+            CTS_CHG_INT_ST: u1,
+            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+            BRK_DET_INT_ST: u1,
+            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
+            /// to 1.
+            RXFIFO_TOUT_INT_ST: u1,
+            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+            SW_XON_INT_ST: u1,
+            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+            SW_XOFF_INT_ST: u1,
+            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+            /// 1.
+            GLITCH_DET_INT_ST: u1,
+            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
+            /// to 1.
+            TX_BRK_DONE_INT_ST: u1,
+            /// This is the stauts bit for tx_brk_idle_done_int_raw when
+            /// tx_brk_idle_done_int_ena is set to 1.
+            TX_BRK_IDLE_DONE_INT_ST: u1,
+            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+            TX_DONE_INT_ST: u1,
+            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+            /// set to 1.
+            RS485_PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
+            /// set to 1.
+            RS485_FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
+            /// to 1.
+            RS485_CLASH_INT_ST: u1,
+            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
+            /// set to 1.
+            AT_CMD_CHAR_DET_INT_ST: u1,
+            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
+            /// to 1.
+            WAKEUP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001000c
+        /// Interrupt enable bits
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the enable bit for rxfifo_full_int_st register.
+            RXFIFO_FULL_INT_ENA: u1,
+            /// This is the enable bit for txfifo_empty_int_st register.
+            TXFIFO_EMPTY_INT_ENA: u1,
+            /// This is the enable bit for parity_err_int_st register.
+            PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for frm_err_int_st register.
+            FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_ovf_int_st register.
+            RXFIFO_OVF_INT_ENA: u1,
+            /// This is the enable bit for dsr_chg_int_st register.
+            DSR_CHG_INT_ENA: u1,
+            /// This is the enable bit for cts_chg_int_st register.
+            CTS_CHG_INT_ENA: u1,
+            /// This is the enable bit for brk_det_int_st register.
+            BRK_DET_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_tout_int_st register.
+            RXFIFO_TOUT_INT_ENA: u1,
+            /// This is the enable bit for sw_xon_int_st register.
+            SW_XON_INT_ENA: u1,
+            /// This is the enable bit for sw_xoff_int_st register.
+            SW_XOFF_INT_ENA: u1,
+            /// This is the enable bit for glitch_det_int_st register.
+            GLITCH_DET_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_done_int_st register.
+            TX_BRK_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_idle_done_int_st register.
+            TX_BRK_IDLE_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_done_int_st register.
+            TX_DONE_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_clash_int_st register.
+            RS485_CLASH_INT_ENA: u1,
+            /// This is the enable bit for at_cmd_char_det_int_st register.
+            AT_CMD_CHAR_DET_INT_ENA: u1,
+            /// This is the enable bit for uart_wakeup_int_st register.
+            WAKEUP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60010010
+        /// Interrupt clear bits
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
+            RXFIFO_FULL_INT_CLR: u1,
+            /// Set this bit to clear txfifo_empty_int_raw interrupt.
+            TXFIFO_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear parity_err_int_raw interrupt.
+            PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear frm_err_int_raw interrupt.
+            FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
+            RXFIFO_OVF_INT_CLR: u1,
+            /// Set this bit to clear the dsr_chg_int_raw interrupt.
+            DSR_CHG_INT_CLR: u1,
+            /// Set this bit to clear the cts_chg_int_raw interrupt.
+            CTS_CHG_INT_CLR: u1,
+            /// Set this bit to clear the brk_det_int_raw interrupt.
+            BRK_DET_INT_CLR: u1,
+            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
+            RXFIFO_TOUT_INT_CLR: u1,
+            /// Set this bit to clear the sw_xon_int_raw interrupt.
+            SW_XON_INT_CLR: u1,
+            /// Set this bit to clear the sw_xoff_int_raw interrupt.
+            SW_XOFF_INT_CLR: u1,
+            /// Set this bit to clear the glitch_det_int_raw interrupt.
+            GLITCH_DET_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
+            TX_BRK_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+            TX_BRK_IDLE_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_done_int_raw interrupt.
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
+            RS485_PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
+            RS485_FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_clash_int_raw interrupt.
+            RS485_CLASH_INT_CLR: u1,
+            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+            AT_CMD_CHAR_DET_INT_CLR: u1,
+            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
+            WAKEUP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60010014
+        /// Clock divider configuration
+        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The integral part of the frequency divider factor.
+            CLKDIV: u12,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// The decimal part of the frequency divider factor.
+            FRAG: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60010018
+        /// Rx Filter configuration
+        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// when input pulse width is lower than this value, the pulse is ignored.
+            GLITCH_FILT: u8,
+            /// Set this bit to enable Rx signal filter.
+            GLITCH_FILT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001001c
+        /// UART status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the byte number of valid data in Rx-FIFO.
+            RXFIFO_CNT: u10,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The register represent the level value of the internal uart dsr signal.
+            DSRN: u1,
+            /// This register represent the level value of the internal uart cts signal.
+            CTSN: u1,
+            /// This register represent the level value of the internal uart rxd signal.
+            RXD: u1,
+            /// Stores the byte number of data in Tx-FIFO.
+            TXFIFO_CNT: u10,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// This bit represents the level of the internal uart dtr signal.
+            DTRN: u1,
+            /// This bit represents the level of the internal uart rts signal.
+            RTSN: u1,
+            /// This bit represents the level of the internal uart txd signal.
+            TXD: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60010020
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the parity check mode.
+            PARITY: u1,
+            /// Set this bit to enable uart parity check.
+            PARITY_EN: u1,
+            /// This register is used to set the length of data.
+            BIT_NUM: u2,
+            /// This register is used to set the length of stop bit.
+            STOP_BIT_NUM: u2,
+            /// This register is used to configure the software rts signal which is used in
+            /// software flow control.
+            SW_RTS: u1,
+            /// This register is used to configure the software dtr signal which is used in
+            /// software flow control.
+            SW_DTR: u1,
+            /// Set this bit to enbale transmitter to send NULL when the process of sending data
+            /// is done.
+            TXD_BRK: u1,
+            /// Set this bit to enable IrDA loopback mode.
+            IRDA_DPLX: u1,
+            /// This is the start enable bit for IrDA transmitter.
+            IRDA_TX_EN: u1,
+            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+            /// transmitter's 11th bit to 0.
+            IRDA_WCTL: u1,
+            /// Set this bit to invert the level of IrDA transmitter.
+            IRDA_TX_INV: u1,
+            /// Set this bit to invert the level of IrDA receiver.
+            IRDA_RX_INV: u1,
+            /// Set this bit to enable uart loopback test mode.
+            LOOPBACK: u1,
+            /// Set this bit to enable flow control function for transmitter.
+            TX_FLOW_EN: u1,
+            /// Set this bit to enable IrDA protocol.
+            IRDA_EN: u1,
+            /// Set this bit to reset the uart receive-FIFO.
+            RXFIFO_RST: u1,
+            /// Set this bit to reset the uart transmit-FIFO.
+            TXFIFO_RST: u1,
+            /// Set this bit to inverse the level value of uart rxd signal.
+            RXD_INV: u1,
+            /// Set this bit to inverse the level value of uart cts signal.
+            CTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dsr signal.
+            DSR_INV: u1,
+            /// Set this bit to inverse the level value of uart txd signal.
+            TXD_INV: u1,
+            /// Set this bit to inverse the level value of uart rts signal.
+            RTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dtr signal.
+            DTR_INV: u1,
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+            /// stores the data even if the received data is wrong.
+            ERR_WR_MASK: u1,
+            /// This is the enable bit for detecting baudrate.
+            AUTOBAUD_EN: u1,
+            /// UART memory clock gate enable signal.
+            MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60010024
+        /// Configuration register 1
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
+            /// this register value.
+            RXFIFO_FULL_THRHD: u9,
+            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
+            /// less than this register value.
+            TXFIFO_EMPTY_THRHD: u9,
+            /// Disable UART Rx data overflow detect.
+            DIS_RX_DAT_OVF: u1,
+            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
+            RX_TOUT_FLOW_DIS: u1,
+            /// This is the flow enable bit for UART receiver.
+            RX_FLOW_EN: u1,
+            /// This is the enble bit for uart receiver's timeout function.
+            RX_TOUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60010028
+        /// Autobaud minimum low pulse duration register
+        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the minimum duration time of the low level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001002c
+        /// Autobaud minimum high pulse duration register
+        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the maxinum duration time for the high level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60010030
+        /// Autobaud edge change count register
+        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the count of rxd edge change. It is used in baud
+            /// rate-detect process.
+            RXD_EDGE_CNT: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60010034
+        /// Software flow-control configuration
+        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable software flow control. It is used with register sw_xon or
+            /// sw_xoff.
+            SW_FLOW_CON_EN: u1,
+            /// Set this bit to remove flow control char from the received data.
+            XONOFF_DEL: u1,
+            /// Set this bit to enable the transmitter to go on sending data.
+            FORCE_XON: u1,
+            /// Set this bit to stop the transmitter from sending data.
+            FORCE_XOFF: u1,
+            /// Set this bit to send Xon char. It is cleared by hardware automatically.
+            SEND_XON: u1,
+            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
+            SEND_XOFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60010038
+        /// Sleep-mode configuration
+        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The uart is activated from light sleeping mode when the input rxd edge changes
+            /// more times than this register value.
+            ACTIVE_THRESHOLD: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001003c
+        /// Software flow-control character configuration
+        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is more than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
+            XOFF_THRESHOLD: u9,
+            /// This register stores the Xoff flow control char.
+            XOFF_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60010040
+        /// Software flow-control character configuration
+        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is less than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
+            XON_THRESHOLD: u9,
+            /// This register stores the Xon flow control char.
+            XON_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60010044
+        /// Tx Break character configuration
+        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the number of 0 to be sent after the process
+            /// of sending data is done. It is active when txd_brk is set to 1.
+            TX_BRK_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60010048
+        /// Frame-end idle configuration
+        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce frame end signal when receiver takes more time to receive one
+            /// byte data than this register value.
+            RX_IDLE_THRHD: u10,
+            /// This register is used to configure the duration time between transfers.
+            TX_IDLE_NUM: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001004c
+        /// RS485 mode configuration
+        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to choose the rs485 mode.
+            RS485_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL0_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL1_EN: u1,
+            /// Set this bit to enable receiver could receive data when the transmitter is
+            /// transmitting data in rs485 mode.
+            RS485TX_RX_EN: u1,
+            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+            RS485RXBY_TX_EN: u1,
+            /// This register is used to delay the receiver's internal data signal.
+            RS485_RX_DLY_NUM: u1,
+            /// This register is used to delay the transmitter's internal data signal.
+            RS485_TX_DLY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60010050
+        /// Pre-sequence timing configuration
+        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the idle duration time before the first
+            /// at_cmd is received by receiver.
+            PRE_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60010054
+        /// Post-sequence timing configuration
+        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the last at_cmd and
+            /// the next data.
+            POST_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60010058
+        /// Timeout configuration
+        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the at_cmd chars.
+            RX_GAP_TOUT: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001005c
+        /// AT escape sequence detection configuration
+        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the content of at_cmd char.
+            AT_CMD_CHAR: u8,
+            /// This register is used to configure the num of continuous at_cmd chars received
+            /// by receiver.
+            CHAR_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60010060
+        /// UART threshold and allocation configuration
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// This register is used to configure the amount of mem allocated for receive-FIFO.
+            /// The default number is 128 bytes.
+            RX_SIZE: u3,
+            /// This register is used to configure the amount of mem allocated for
+            /// transmit-FIFO. The default number is 128 bytes.
+            TX_SIZE: u3,
+            /// This register is used to configure the maximum amount of data that can be
+            /// received when hardware flow control works.
+            RX_FLOW_THRHD: u9,
+            /// This register is used to configure the threshold time that receiver takes to
+            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
+            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
+            RX_TOUT_THRHD: u10,
+            /// Set this bit to force power down UART memory.
+            MEM_FORCE_PD: u1,
+            /// Set this bit to force power up UART memory.
+            MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60010064
+        /// Tx-FIFO write and read offset address.
+        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+            /// via APB.
+            APB_TX_WADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+            /// Tx-FIFO_Ctrl.
+            TX_RADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60010068
+        /// Rx-FIFO write and read offset address.
+        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in RX-FIFO when software reads data from
+            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+            APB_RX_RADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+            RX_WADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001006c
+        /// UART transmit and receive status.
+        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status register of receiver.
+            ST_URX_OUT: u4,
+            /// This is the status register of transmitter.
+            ST_UTX_OUT: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60010070
+        /// Autobaud high pulse register
+        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two positive edges.
+            /// It is used in boudrate-detect process.
+            POSEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60010074
+        /// Autobaud low pulse register
+        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two negative edges.
+            /// It is used in boudrate-detect process.
+            NEGEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60010078
+        /// UART core clock configuration
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The denominator of the frequency divider factor.
+            SCLK_DIV_B: u6,
+            /// The numerator of the frequency divider factor.
+            SCLK_DIV_A: u6,
+            /// The integral part of the frequency divider factor.
+            SCLK_DIV_NUM: u8,
+            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+            SCLK_SEL: u2,
+            /// Set this bit to enable UART Tx/Rx clock.
+            SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
+            RST_CORE: u1,
+            /// Set this bit to enable UART Tx clock.
+            TX_SCLK_EN: u1,
+            /// Set this bit to enable UART Rx clock.
+            RX_SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx.
+            TX_RST_CORE: u1,
+            /// Write 1 then write 0 to this bit, reset UART Rx.
+            RX_RST_CORE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001007c
+        /// UART Version register
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x60010080
+        /// UART ID register
+        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the uart_id.
+            ID: u30,
+            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
+            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
+            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
+            /// synchronize registers.
+            HIGH_SPEED: u1,
+            /// Software write 1 would synchronize registers into UART Core clock domain and
+            /// would be cleared by hardware after synchronization is done.
+            REG_UPDATE: u1,
+        }), base_address + 0x80);
+    };
+
+    /// Universal Host Controller Interface
+    pub const UHCI0 = struct {
+        pub const base_address = 0x60014000;
+
+        /// address: 0x60014000
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write 1, then write 0 to this bit to reset decode state machine.
+            TX_RST: u1,
+            /// Write 1, then write 0 to this bit to reset encode state machine.
+            RX_RST: u1,
+            /// Set this bit to link up HCI and UART0.
+            UART0_CE: u1,
+            /// Set this bit to link up HCI and UART1.
+            UART1_CE: u1,
+            reserved0: u1,
+            /// Set this bit to separate the data frame using a special char.
+            SEPER_EN: u1,
+            /// Set this bit to encode the data packet with a formatting header.
+            HEAD_EN: u1,
+            /// Set this bit to enable UHCI to receive the 16 bit CRC.
+            CRC_REC_EN: u1,
+            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
+            /// has been in idle state.
+            UART_IDLE_EOF_EN: u1,
+            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
+            /// receiving byte count has reached the specified value. The value is payload
+            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
+            /// decoder receiving payload data is end when 0xc0 is received.
+            LEN_EOF_EN: u1,
+            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
+            /// to end of the payload.
+            ENCODE_CRC_EN: u1,
+            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
+            /// is received by UART.
+            UART_RX_BRK_EOF_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60014004
+        /// a
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_RAW: u1,
+            /// a
+            TX_START_INT_RAW: u1,
+            /// a
+            RX_HUNG_INT_RAW: u1,
+            /// a
+            TX_HUNG_INT_RAW: u1,
+            /// a
+            SEND_S_REG_Q_INT_RAW: u1,
+            /// a
+            SEND_A_REG_Q_INT_RAW: u1,
+            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
+            /// the
+            OUT_EOF_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL0_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60014008
+        /// a
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ST: u1,
+            /// a
+            TX_START_INT_ST: u1,
+            /// a
+            RX_HUNG_INT_ST: u1,
+            /// a
+            TX_HUNG_INT_ST: u1,
+            /// a
+            SEND_S_REG_Q_INT_ST: u1,
+            /// a
+            SEND_A_REG_Q_INT_ST: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ST: u1,
+            /// a
+            APP_CTRL0_INT_ST: u1,
+            /// a
+            APP_CTRL1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001400c
+        /// a
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ENA: u1,
+            /// a
+            TX_START_INT_ENA: u1,
+            /// a
+            RX_HUNG_INT_ENA: u1,
+            /// a
+            TX_HUNG_INT_ENA: u1,
+            /// a
+            SEND_S_REG_Q_INT_ENA: u1,
+            /// a
+            SEND_A_REG_Q_INT_ENA: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ENA: u1,
+            /// a
+            APP_CTRL0_INT_ENA: u1,
+            /// a
+            APP_CTRL1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60014010
+        /// a
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_CLR: u1,
+            /// a
+            TX_START_INT_CLR: u1,
+            /// a
+            RX_HUNG_INT_CLR: u1,
+            /// a
+            TX_HUNG_INT_CLR: u1,
+            /// a
+            SEND_S_REG_Q_INT_CLR: u1,
+            /// a
+            SEND_A_REG_Q_INT_CLR: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_CLR: u1,
+            /// a
+            APP_CTRL0_INT_CLR: u1,
+            /// a
+            APP_CTRL1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60014014
+        /// a
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            CHECK_SUM_EN: u1,
+            /// a
+            CHECK_SEQ_EN: u1,
+            /// a
+            CRC_DISABLE: u1,
+            /// a
+            SAVE_HEAD: u1,
+            /// a
+            TX_CHECK_SUM_RE: u1,
+            /// a
+            TX_ACK_NUM_RE: u1,
+            reserved0: u1,
+            /// a
+            WAIT_SW_START: u1,
+            /// a
+            SW_START: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60014018
+        /// a
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_ERR_CAUSE: u3,
+            /// a
+            DECODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001401c
+        /// a
+        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ENCODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60014020
+        /// a
+        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TX_C0_ESC_EN: u1,
+            /// a
+            TX_DB_ESC_EN: u1,
+            /// a
+            TX_11_ESC_EN: u1,
+            /// a
+            TX_13_ESC_EN: u1,
+            /// a
+            RX_C0_ESC_EN: u1,
+            /// a
+            RX_DB_ESC_EN: u1,
+            /// a
+            RX_11_ESC_EN: u1,
+            /// a
+            RX_13_ESC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60014024
+        /// a
+        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TXFIFO_TIMEOUT: u8,
+            /// a
+            TXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            TXFIFO_TIMEOUT_ENA: u1,
+            /// a
+            RXFIFO_TIMEOUT: u8,
+            /// a
+            RXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            RXFIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60014028
+        /// a
+        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ACK_NUM: u3,
+            /// a
+            LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001402c
+        /// a
+        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x60014030
+        /// a
+        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SINGLE_SEND_NUM: u3,
+            /// a
+            SINGLE_SEND_EN: u1,
+            /// a
+            ALWAYS_SEND_NUM: u3,
+            /// a
+            ALWAYS_SEND_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60014034
+        /// a
+        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD0: u32,
+        }), base_address + 0x34);
+
+        /// address: 0x60014038
+        /// a
+        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD1: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6001403c
+        /// a
+        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD0: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x60014040
+        /// a
+        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD1: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x60014044
+        /// a
+        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60014048
+        /// a
+        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD1: u32,
+        }), base_address + 0x48);
+
+        /// address: 0x6001404c
+        /// a
+        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD0: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60014050
+        /// a
+        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD1: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60014054
+        /// a
+        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD0: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60014058
+        /// a
+        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD1: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6001405c
+        /// a
+        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60014060
+        /// a
+        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60014064
+        /// a
+        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD0: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60014068
+        /// a
+        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD1: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6001406c
+        /// a
+        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEPER_CHAR: u8,
+            /// a
+            SEPER_ESC_CHAR0: u8,
+            /// a
+            SEPER_ESC_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60014070
+        /// a
+        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ0: u8,
+            /// a
+            ESC_SEQ0_CHAR0: u8,
+            /// a
+            ESC_SEQ0_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60014074
+        /// a
+        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ1: u8,
+            /// a
+            ESC_SEQ1_CHAR0: u8,
+            /// a
+            ESC_SEQ1_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60014078
+        /// a
+        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ2: u8,
+            /// a
+            ESC_SEQ2_CHAR0: u8,
+            /// a
+            ESC_SEQ2_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001407c
+        /// a
+        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            PKT_THRS: u13,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60014080
+        /// a
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// Universal Host Controller Interface
+    pub const UHCI1 = struct {
+        pub const base_address = 0x6000c000;
+
+        /// address: 0x6000c000
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write 1, then write 0 to this bit to reset decode state machine.
+            TX_RST: u1,
+            /// Write 1, then write 0 to this bit to reset encode state machine.
+            RX_RST: u1,
+            /// Set this bit to link up HCI and UART0.
+            UART0_CE: u1,
+            /// Set this bit to link up HCI and UART1.
+            UART1_CE: u1,
+            reserved0: u1,
+            /// Set this bit to separate the data frame using a special char.
+            SEPER_EN: u1,
+            /// Set this bit to encode the data packet with a formatting header.
+            HEAD_EN: u1,
+            /// Set this bit to enable UHCI to receive the 16 bit CRC.
+            CRC_REC_EN: u1,
+            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
+            /// has been in idle state.
+            UART_IDLE_EOF_EN: u1,
+            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
+            /// receiving byte count has reached the specified value. The value is payload
+            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
+            /// decoder receiving payload data is end when 0xc0 is received.
+            LEN_EOF_EN: u1,
+            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
+            /// to end of the payload.
+            ENCODE_CRC_EN: u1,
+            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
+            /// is received by UART.
+            UART_RX_BRK_EOF_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6000c004
+        /// a
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_RAW: u1,
+            /// a
+            TX_START_INT_RAW: u1,
+            /// a
+            RX_HUNG_INT_RAW: u1,
+            /// a
+            TX_HUNG_INT_RAW: u1,
+            /// a
+            SEND_S_REG_Q_INT_RAW: u1,
+            /// a
+            SEND_A_REG_Q_INT_RAW: u1,
+            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
+            /// the
+            OUT_EOF_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL0_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6000c008
+        /// a
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ST: u1,
+            /// a
+            TX_START_INT_ST: u1,
+            /// a
+            RX_HUNG_INT_ST: u1,
+            /// a
+            TX_HUNG_INT_ST: u1,
+            /// a
+            SEND_S_REG_Q_INT_ST: u1,
+            /// a
+            SEND_A_REG_Q_INT_ST: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ST: u1,
+            /// a
+            APP_CTRL0_INT_ST: u1,
+            /// a
+            APP_CTRL1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000c00c
+        /// a
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ENA: u1,
+            /// a
+            TX_START_INT_ENA: u1,
+            /// a
+            RX_HUNG_INT_ENA: u1,
+            /// a
+            TX_HUNG_INT_ENA: u1,
+            /// a
+            SEND_S_REG_Q_INT_ENA: u1,
+            /// a
+            SEND_A_REG_Q_INT_ENA: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ENA: u1,
+            /// a
+            APP_CTRL0_INT_ENA: u1,
+            /// a
+            APP_CTRL1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6000c010
+        /// a
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_CLR: u1,
+            /// a
+            TX_START_INT_CLR: u1,
+            /// a
+            RX_HUNG_INT_CLR: u1,
+            /// a
+            TX_HUNG_INT_CLR: u1,
+            /// a
+            SEND_S_REG_Q_INT_CLR: u1,
+            /// a
+            SEND_A_REG_Q_INT_CLR: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_CLR: u1,
+            /// a
+            APP_CTRL0_INT_CLR: u1,
+            /// a
+            APP_CTRL1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6000c014
+        /// a
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            CHECK_SUM_EN: u1,
+            /// a
+            CHECK_SEQ_EN: u1,
+            /// a
+            CRC_DISABLE: u1,
+            /// a
+            SAVE_HEAD: u1,
+            /// a
+            TX_CHECK_SUM_RE: u1,
+            /// a
+            TX_ACK_NUM_RE: u1,
+            reserved0: u1,
+            /// a
+            WAIT_SW_START: u1,
+            /// a
+            SW_START: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6000c018
+        /// a
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_ERR_CAUSE: u3,
+            /// a
+            DECODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000c01c
+        /// a
+        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ENCODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6000c020
+        /// a
+        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TX_C0_ESC_EN: u1,
+            /// a
+            TX_DB_ESC_EN: u1,
+            /// a
+            TX_11_ESC_EN: u1,
+            /// a
+            TX_13_ESC_EN: u1,
+            /// a
+            RX_C0_ESC_EN: u1,
+            /// a
+            RX_DB_ESC_EN: u1,
+            /// a
+            RX_11_ESC_EN: u1,
+            /// a
+            RX_13_ESC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6000c024
+        /// a
+        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TXFIFO_TIMEOUT: u8,
+            /// a
+            TXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            TXFIFO_TIMEOUT_ENA: u1,
+            /// a
+            RXFIFO_TIMEOUT: u8,
+            /// a
+            RXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            RXFIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6000c028
+        /// a
+        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ACK_NUM: u3,
+            /// a
+            LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000c02c
+        /// a
+        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x6000c030
+        /// a
+        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SINGLE_SEND_NUM: u3,
+            /// a
+            SINGLE_SEND_EN: u1,
+            /// a
+            ALWAYS_SEND_NUM: u3,
+            /// a
+            ALWAYS_SEND_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6000c034
+        /// a
+        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD0: u32,
+        }), base_address + 0x34);
+
+        /// address: 0x6000c038
+        /// a
+        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD1: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6000c03c
+        /// a
+        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD0: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x6000c040
+        /// a
+        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD1: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x6000c044
+        /// a
+        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x6000c048
+        /// a
+        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD1: u32,
+        }), base_address + 0x48);
+
+        /// address: 0x6000c04c
+        /// a
+        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD0: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x6000c050
+        /// a
+        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD1: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x6000c054
+        /// a
+        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD0: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x6000c058
+        /// a
+        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD1: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000c05c
+        /// a
+        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x6000c060
+        /// a
+        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x6000c064
+        /// a
+        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD0: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x6000c068
+        /// a
+        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD1: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000c06c
+        /// a
+        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEPER_CHAR: u8,
+            /// a
+            SEPER_ESC_CHAR0: u8,
+            /// a
+            SEPER_ESC_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6000c070
+        /// a
+        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ0: u8,
+            /// a
+            ESC_SEQ0_CHAR0: u8,
+            /// a
+            ESC_SEQ0_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6000c074
+        /// a
+        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ1: u8,
+            /// a
+            ESC_SEQ1_CHAR0: u8,
+            /// a
+            ESC_SEQ1_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6000c078
+        /// a
+        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ2: u8,
+            /// a
+            ESC_SEQ2_CHAR0: u8,
+            /// a
+            ESC_SEQ2_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000c07c
+        /// a
+        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            PKT_THRS: u13,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6000c080
+        /// a
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// Full-speed USB Serial/JTAG Controller
+    pub const USB_DEVICE = struct {
+        pub const base_address = 0x60043000;
+
+        /// address: 0x60043000
+        /// USB_DEVICE_EP1_REG.
+        pub const EP1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+            /// USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+            /// into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can
+            /// check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many
+            /// data is received, then read data from UART Rx FIFO.
+            RDWR_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60043004
+        /// USB_DEVICE_EP1_CONF_REG.
+        pub const EP1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to indicate writing byte data to UART Tx FIFO is done.
+            WR_DONE: u1,
+            /// 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
+            /// writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is
+            /// read by USB Host.
+            SERIAL_IN_EP_DATA_FREE: u1,
+            /// 1'b1: Indicate there is data in UART Rx FIFO.
+            SERIAL_OUT_EP_DATA_AVAIL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60043008
+        /// USB_DEVICE_INT_RAW_REG.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when flush cmd is received for IN
+            /// endpoint 2 of JTAG.
+            JTAG_IN_FLUSH_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when SOF frame is received.
+            SOF_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+            /// one packet.
+            SERIAL_OUT_RECV_PKT_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+            SERIAL_IN_EMPTY_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when pid error is detected.
+            PID_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when CRC5 error is detected.
+            CRC5_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when CRC16 error is detected.
+            CRC16_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when stuff error is detected.
+            STUFF_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+            /// received.
+            IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when usb bus reset is detected.
+            USB_BUS_RESET_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when OUT endpoint 1 received packet
+            /// with zero palyload.
+            OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when OUT endpoint 2 received packet
+            /// with zero palyload.
+            OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6004300c
+        /// USB_DEVICE_INT_ST_REG.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+            SOF_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT
+            /// interrupt.
+            SERIAL_OUT_RECV_PKT_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT
+            /// interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT
+            /// interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT
+            /// interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60043010
+        /// USB_DEVICE_INT_ENA_REG.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+            SOF_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+            SERIAL_OUT_RECV_PKT_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60043014
+        /// USB_DEVICE_INT_CLR_REG.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+            SOF_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+            SERIAL_OUT_RECV_PKT_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60043018
+        /// USB_DEVICE_CONF0_REG.
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Select internal/external PHY
+            PHY_SEL: u1,
+            /// Enable software control USB D+ D- exchange
+            EXCHG_PINS_OVERRIDE: u1,
+            /// USB D+ D- exchange
+            EXCHG_PINS: u1,
+            /// Control single-end input high threshold,1.76V to 2V, step 80mV
+            VREFH: u2,
+            /// Control single-end input low threshold,0.8V to 1.04V, step 80mV
+            VREFL: u2,
+            /// Enable software control input threshold
+            VREF_OVERRIDE: u1,
+            /// Enable software control USB D+ D- pullup pulldown
+            PAD_PULL_OVERRIDE: u1,
+            /// Control USB D+ pull up.
+            DP_PULLUP: u1,
+            /// Control USB D+ pull down.
+            DP_PULLDOWN: u1,
+            /// Control USB D- pull up.
+            DM_PULLUP: u1,
+            /// Control USB D- pull down.
+            DM_PULLDOWN: u1,
+            /// Control pull up value.
+            PULLUP_VALUE: u1,
+            /// Enable USB pad function.
+            USB_PAD_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6004301c
+        /// USB_DEVICE_TEST_REG.
+        pub const TEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Enable test of the USB pad
+            ENABLE: u1,
+            /// USB pad oen in test
+            USB_OE: u1,
+            /// USB D+ tx value in test
+            TX_DP: u1,
+            /// USB D- tx value in test
+            TX_DM: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60043020
+        /// USB_DEVICE_JFIFO_ST_REG.
+        pub const JFIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// JTAT in fifo counter.
+            IN_FIFO_CNT: u2,
+            /// 1: JTAG in fifo is empty.
+            IN_FIFO_EMPTY: u1,
+            /// 1: JTAG in fifo is full.
+            IN_FIFO_FULL: u1,
+            /// JTAT out fifo counter.
+            OUT_FIFO_CNT: u2,
+            /// 1: JTAG out fifo is empty.
+            OUT_FIFO_EMPTY: u1,
+            /// 1: JTAG out fifo is full.
+            OUT_FIFO_FULL: u1,
+            /// Write 1 to reset JTAG in fifo.
+            IN_FIFO_RESET: u1,
+            /// Write 1 to reset JTAG out fifo.
+            OUT_FIFO_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60043024
+        /// USB_DEVICE_FRAM_NUM_REG.
+        pub const FRAM_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Frame index of received SOF frame.
+            SOF_FRAME_INDEX: u11,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60043028
+        /// USB_DEVICE_IN_EP0_ST_REG.
+        pub const IN_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 0.
+            IN_EP0_STATE: u2,
+            /// Write data address of IN endpoint 0.
+            IN_EP0_WR_ADDR: u7,
+            /// Read data address of IN endpoint 0.
+            IN_EP0_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6004302c
+        /// USB_DEVICE_IN_EP1_ST_REG.
+        pub const IN_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 1.
+            IN_EP1_STATE: u2,
+            /// Write data address of IN endpoint 1.
+            IN_EP1_WR_ADDR: u7,
+            /// Read data address of IN endpoint 1.
+            IN_EP1_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60043030
+        /// USB_DEVICE_IN_EP2_ST_REG.
+        pub const IN_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 2.
+            IN_EP2_STATE: u2,
+            /// Write data address of IN endpoint 2.
+            IN_EP2_WR_ADDR: u7,
+            /// Read data address of IN endpoint 2.
+            IN_EP2_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60043034
+        /// USB_DEVICE_IN_EP3_ST_REG.
+        pub const IN_EP3_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 3.
+            IN_EP3_STATE: u2,
+            /// Write data address of IN endpoint 3.
+            IN_EP3_WR_ADDR: u7,
+            /// Read data address of IN endpoint 3.
+            IN_EP3_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60043038
+        /// USB_DEVICE_OUT_EP0_ST_REG.
+        pub const OUT_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 0.
+            OUT_EP0_STATE: u2,
+            /// Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+            OUT_EP0_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 0.
+            OUT_EP0_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6004303c
+        /// USB_DEVICE_OUT_EP1_ST_REG.
+        pub const OUT_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 1.
+            OUT_EP1_STATE: u2,
+            /// Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+            OUT_EP1_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 1.
+            OUT_EP1_RD_ADDR: u7,
+            /// Data count in OUT endpoint 1 when one packet is received.
+            OUT_EP1_REC_DATA_CNT: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60043040
+        /// USB_DEVICE_OUT_EP2_ST_REG.
+        pub const OUT_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 2.
+            OUT_EP2_STATE: u2,
+            /// Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+            OUT_EP2_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 2.
+            OUT_EP2_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60043044
+        /// USB_DEVICE_MISC_CONF_REG.
+        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60043048
+        /// USB_DEVICE_MEM_CONF_REG.
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: power down usb memory.
+            USB_MEM_PD: u1,
+            /// 1: Force clock on for usb memory.
+            USB_MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x60043080
+        /// USB_DEVICE_DATE_REG.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// XTS-AES-128 Flash Encryption
+    pub const XTS_AES = struct {
+        pub const base_address = 0x600cc000;
+
+        /// address: 0x600cc000
+        /// The memory that stores plaintext
+        pub const PLAIN_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
+
+        /// address: 0x600cc040
+        /// XTS-AES line-size register
+        pub const LINESIZE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
+
+        /// address: 0x600cc044
+        /// XTS-AES destination register
+        pub const DESTINATION = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44);
+
+        /// address: 0x600cc048
+        /// XTS-AES physical address register
+        pub const PHYSICAL_ADDRESS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x48);
+
+        /// address: 0x600cc04c
+        /// XTS-AES trigger register
+        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4c);
+
+        /// address: 0x600cc050
+        /// XTS-AES release register
+        pub const RELEASE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50);
+
+        /// address: 0x600cc054
+        /// XTS-AES destroy register
+        pub const DESTROY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x54);
+
+        /// address: 0x600cc058
+        /// XTS-AES status register
+        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x58);
+
+        /// address: 0x600cc05c
+        /// XTS-AES version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x5c);
+    };
+};
+
+const std = @import("std");
+
+pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) {
+    return @intToPtr(*volatile Mmio(size, PackedT), addr);
+}
+
+pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
+    if ((size % 8) != 0)
+        @compileError("size must be divisible by 8!");
+
+    if (!std.math.isPowerOfTwo(size / 8))
+        @compileError("size must encode a power of two number of bytes!");
+
+    const IntT = std.meta.Int(.unsigned, size);
+
+    if (@sizeOf(PackedT) != (size / 8))
+        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
+
+    return extern struct {
+        const Self = @This();
+
+        raw: IntT,
+
+        pub const underlying_type = PackedT;
+
+        pub inline fn read(addr: *volatile Self) PackedT {
+            return @bitCast(PackedT, addr.raw);
+        }
+
+        pub inline fn write(addr: *volatile Self, val: PackedT) void {
+            // This is a workaround for a compiler bug related to miscompilation
+            // If the tmp var is not used, result location will fuck things up
+            var tmp = @bitCast(IntT, val);
+            addr.raw = tmp;
+        }
+
+        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
+            var val = read(addr);
+            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
+                @field(val, field.name) = @field(fields, field.name);
+            }
+            write(addr, val);
+        }
+
+        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
+            var val = read(addr);
+            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
+                @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
+            }
+            write(addr, val);
+        }
+    };
+}
+
+pub fn MmioInt(comptime size: u8, comptime T: type) type {
+    return extern struct {
+        const Self = @This();
+
+        raw: std.meta.Int(.unsigned, size),
+
+        pub inline fn read(addr: *volatile Self) T {
+            return @truncate(T, addr.raw);
+        }
+
+        pub inline fn modify(addr: *volatile Self, val: T) void {
+            const Int = std.meta.Int(.unsigned, size);
+            const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1);
+
+            var tmp = addr.raw;
+            addr.raw = (tmp & mask) | val;
+        }
+    };
+}
+
+pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) {
+    return @intToPtr(*volatile MmioInt(size, T), addr);
+}
+
+pub const InterruptVector = extern union {
+    C: fn () callconv(.C) void,
+    Naked: fn () callconv(.Naked) void,
+    // Interrupt is not supported on arm
+};
+
+const unhandled = InterruptVector{
+    .C = struct {
+        fn tmp() callconv(.C) noreturn {
+            @panic("unhandled interrupt");
+        }
+    }.tmp,
+};

From e7e70cb96c5aaae4044ea903df1ac278f7d30f14 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 8 Oct 2022 13:02:39 +0200
Subject: [PATCH 04/29] LED 1 is RED. Reset loop tho

---
 build.zig                       | 59 +++++++++++++++++++--------------
 src/example/blinky.zig          | 29 ++++++++++++++++
 src/main.zig                    | 24 --------------
 src/package/esp32-c3.zig        | 45 +++++++++++++++++++++++++
 src/package/espressif-riscv.zig | 12 +++++++
 vendor/microzig                 |  2 +-
 6 files changed, 122 insertions(+), 49 deletions(-)
 create mode 100644 src/example/blinky.zig
 delete mode 100644 src/main.zig
 create mode 100644 src/package/esp32-c3.zig
 create mode 100644 src/package/espressif-riscv.zig

diff --git a/build.zig b/build.zig
index 035b12a..3f49cf7 100644
--- a/build.zig
+++ b/build.zig
@@ -1,34 +1,45 @@
 const std = @import("std");
+const microzig = @import("zpm.zig").sdks.microzig;
 
 pub fn build(b: *std.build.Builder) void {
-    // Standard target options allows the person running `zig build` to choose
-    // what target to build for. Here we do not override the defaults, which
-    // means any target is allowed, and the default is native. Other options
-    // for restricting supported target set are available.
-    const target = b.standardTargetOptions(.{});
-
-    // Standard release options allow the person running `zig build` to select
-    // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall.
     const mode = b.standardReleaseOptions();
 
-    const exe = b.addExecutable("esp32-c3-bringup", "src/main.zig");
-    exe.setTarget(target);
-    exe.setBuildMode(mode);
-    exe.install();
+    const esp32_c3_cpu = microzig.Cpu{
+        .name = "Espressif RISC-V",
+        .path = "src/package/espressif-riscv.zig",
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .riscv32,
+            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+            .cpu_features_add = std.Target.riscv.featureSet(&.{
+                std.Target.riscv.Feature.c,
+                std.Target.riscv.Feature.m,
+            }),
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
 
-    const run_cmd = exe.run();
-    run_cmd.step.dependOn(b.getInstallStep());
-    if (b.args) |args| {
-        run_cmd.addArgs(args);
-    }
+    const esp32_c3 = microzig.Chip{
+        .name = "ESP32 C3",
+        .path = "src/package/esp32-c3.zig",
+        .cpu = esp32_c3_cpu,
+        .memory_regions = &.{
+            .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+            .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+        },
+    };
 
-    const run_step = b.step("run", "Run the app");
-    run_step.dependOn(&run_cmd.step);
+    var exe = microzig.addEmbeddedExecutable(
+        b,
+        "esp-bringup",
+        "src/example/blinky.zig",
+        .{ .chip = esp32_c3 },
+        .{},
+    );
+    exe.setBuildMode(mode);
+    exe.install();
 
-    const exe_tests = b.addTest("src/main.zig");
-    exe_tests.setTarget(target);
-    exe_tests.setBuildMode(mode);
+    const raw_step = exe.installRaw("firmware.bin", .{});
 
-    const test_step = b.step("test", "Run unit tests");
-    test_step.dependOn(&exe_tests.step);
+    b.getInstallStep().dependOn(&raw_step.step);
 }
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
new file mode 100644
index 0000000..6bba15b
--- /dev/null
+++ b/src/example/blinky.zig
@@ -0,0 +1,29 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() !void {
+    // const led_r_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_R_PIN));
+    // const led_g_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_G_PIN));
+    // const led_b_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_B_PIN));
+
+    // led_r_mux.* = 0x80;
+
+    const gpio_out = @intToPtr(*volatile u32, GPIO_BASE + GPIO_OUT_REG);
+    const gpio_ena = @intToPtr(*volatile u32, GPIO_BASE + GPIO_ENABLE_REG);
+    gpio_ena.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
+    gpio_out.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
+}
+
+const GPIO_BASE = 0x6000_4000;
+const IO_MUX_BASE = 0x6000_9000;
+
+const GPIO_OUT_REG = 0x0004;
+const GPIO_ENABLE_REG = 0x0020;
+
+fn GPIO_FUNCn_OUT_SEL_CFG_REG(comptime n: comptime_int) comptime_int {
+    return 0x0554 + 4 * n;
+}
+
+const LED_R_PIN = 3;
+const LED_G_PIN = 4;
+const LED_B_PIN = 5;
diff --git a/src/main.zig b/src/main.zig
deleted file mode 100644
index c8a3f67..0000000
--- a/src/main.zig
+++ /dev/null
@@ -1,24 +0,0 @@
-const std = @import("std");
-
-pub fn main() !void {
-    // Prints to stderr (it's a shortcut based on `std.io.getStdErr()`)
-    std.debug.print("All your {s} are belong to us.\n", .{"codebase"});
-
-    // stdout is for the actual output of your application, for example if you
-    // are implementing gzip, then only the compressed bytes should be sent to
-    // stdout, not any debugging messages.
-    const stdout_file = std.io.getStdOut().writer();
-    var bw = std.io.bufferedWriter(stdout_file);
-    const stdout = bw.writer();
-
-    try stdout.print("Run `zig build test` to run the tests.\n", .{});
-
-    try bw.flush(); // don't forget to flush!
-}
-
-test "simple test" {
-    var list = std.ArrayList(i32).init(std.testing.allocator);
-    defer list.deinit(); // try commenting this out and see if zig detects the memory leak!
-    try list.append(42);
-    try std.testing.expectEqual(@as(i32, 42), list.pop());
-}
diff --git a/src/package/esp32-c3.zig b/src/package/esp32-c3.zig
new file mode 100644
index 0000000..0a0f4fe
--- /dev/null
+++ b/src/package/esp32-c3.zig
@@ -0,0 +1,45 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub const startup_logic = struct {
+    comptime {
+        // See this:
+        // https://github.com/espressif/esp32c3-direct-boot-example
+
+        // Direct Boot: does not support Security Boot and programs run directly in flash. To enable this mode, make
+        // sure that the first two words of the bin file downloading to flash (address: 0x42000000) are 0xaedb041d.
+
+        // In this case, the ROM bootloader sets up Flash MMU to map 4 MB of Flash to
+        // addresses 0x42000000 (for code execution) and 0x3C000000 (for read-only data
+        // access). The bootloader then jumps to address 0x42000008, i.e. to the
+        // instruction at offset 8 in flash, immediately after the magic numbers.
+
+        asm (std.fmt.comptimePrint(".equ MICROZIG_INITIAL_STACK, {}", .{microzig.config.end_of_stack}));
+
+        asm (
+            \\.extern _start
+            \\.section microzig_flash_start
+            \\.align 4
+            \\.byte 0x1d, 0x04, 0xdb, 0xae
+            \\.byte 0x1d, 0x04, 0xdb, 0xae
+        );
+    }
+
+    extern fn microzig_main() noreturn;
+
+    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
+        asm volatile (
+            \\li sp, MICROZIG_INITIAL_STACK
+            \\lui  a0, %%hi(_rv32_trap)
+            \\addi a0, a0, %%lo(_rv32_trap)
+            \\sw t0, 0x305(zero)
+        );
+
+        microzig.initializeSystemMemories();
+        microzig_main();
+    }
+
+    export fn _rv32_trap() callconv(.C) noreturn {
+        while (true) {}
+    }
+};
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
new file mode 100644
index 0000000..34dbffd
--- /dev/null
+++ b/src/package/espressif-riscv.zig
@@ -0,0 +1,12 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub inline fn cli() void {
+    asm volatile ("");
+}
+
+pub inline fn sei() void {
+    asm volatile ("");
+}
+
+pub const startup_logic = microzig.chip.startup_logic;
diff --git a/vendor/microzig b/vendor/microzig
index 15bc1fc..0d9721d 160000
--- a/vendor/microzig
+++ b/vendor/microzig
@@ -1 +1 @@
-Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1
+Subproject commit 0d9721d9070c356f4ffaf6f4a312bccdb574b8a9

From 33984fa9605172a8b8e55711738d2e1b4be97247 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 8 Oct 2022 13:13:43 +0200
Subject: [PATCH 05/29] one readme

---
 README.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 README.md

diff --git a/README.md b/README.md
deleted file mode 100644
index 2cd0dfa..0000000
--- a/README.md
+++ /dev/null
@@ -1 +0,0 @@
-# esp32-c3-bringup

From e84264e64ba5fc8cf5e01a5035c8e64e2fe2270a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 8 Oct 2022 16:19:20 +0200
Subject: [PATCH 06/29] Blinky! \o/

---
 build.zig                                  |  2 +-
 perform-flash.sh                           | 13 +++++
 src/example/blinky.zig                     | 59 +++++++++++++++-------
 src/hal/root.zig                           | 54 ++++++++++++++++++++
 src/package/esp32-c3.zig                   | 42 +++++++++++----
 src/package/espressif-riscv.zig            | 31 +++++++++++-
 src/{esp32c3.zig => package/registers.zig} |  0
 7 files changed, 171 insertions(+), 30 deletions(-)
 create mode 100755 perform-flash.sh
 create mode 100644 src/hal/root.zig
 rename src/{esp32c3.zig => package/registers.zig} (100%)

diff --git a/build.zig b/build.zig
index 3f49cf7..c0d71db 100644
--- a/build.zig
+++ b/build.zig
@@ -34,7 +34,7 @@ pub fn build(b: *std.build.Builder) void {
         "esp-bringup",
         "src/example/blinky.zig",
         .{ .chip = esp32_c3 },
-        .{},
+        .{ .hal_package_path = .{ .path = "src/hal/root.zig" } },
     );
     exe.setBuildMode(mode);
     exe.install();
diff --git a/perform-flash.sh b/perform-flash.sh
new file mode 100755
index 0000000..ce1f5de
--- /dev/null
+++ b/perform-flash.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -e
+
+clear
+zig build -Drelease-small
+llvm-objdump -S ./zig-out/bin/esp-bringup > /tmp/dump.txt
+esptool.py \
+  --port /dev/ttyUSB0 \
+  --baud 115200 \
+  write_flash 0x00000000 zig-out/bin/firmware.bin \
+  --verify
+picocom --baud 115200 /dev/ttyUSB0
\ No newline at end of file
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 6bba15b..0518c53 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -1,29 +1,52 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+const dogfood: u32 = 0x50D83AA1;
+const super_dogfood: u32 = 0x8F1D312A;
+
 pub fn main() !void {
-    // const led_r_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_R_PIN));
-    // const led_g_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_G_PIN));
-    // const led_b_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_B_PIN));
+    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = dogfood;
+    microzig.chip.registers.TIMG0.WDTCONFIG0.raw = 0;
+    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = 0;
 
-    // led_r_mux.* = 0x80;
+    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    microzig.chip.registers.RTC_CNTL.WDTCONFIG0.raw = 0;
+    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = 0;
 
-    const gpio_out = @intToPtr(*volatile u32, GPIO_BASE + GPIO_OUT_REG);
-    const gpio_ena = @intToPtr(*volatile u32, GPIO_BASE + GPIO_ENABLE_REG);
-    gpio_ena.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
-    gpio_out.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
-}
+    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    microzig.chip.registers.RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = 0;
+
+    microzig.chip.registers.INTERRUPT_CORE0.CPU_INT_ENABLE.* = 0;
 
-const GPIO_BASE = 0x6000_4000;
-const IO_MUX_BASE = 0x6000_9000;
+    microzig.hal.gpio.init(LED_R_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_G_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_B_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
 
-const GPIO_OUT_REG = 0x0004;
-const GPIO_ENABLE_REG = 0x0020;
+    microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
-fn GPIO_FUNCn_OUT_SEL_CFG_REG(comptime n: comptime_int) comptime_int {
-    return 0x0554 + 4 * n;
+    while (true) {
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        microzig.hal.uart.write(0, "R");
+        microzig.debug.busySleep(1_000_000);
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.hal.uart.write(0, "G");
+        microzig.debug.busySleep(1_000_000);
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.hal.uart.write(0, "B");
+        microzig.debug.busySleep(1_000_000);
+    }
 }
 
-const LED_R_PIN = 3;
-const LED_G_PIN = 4;
-const LED_B_PIN = 5;
+const LED_R_PIN = 3; // GPIO
+const LED_G_PIN = 16; // GPIO
+const LED_B_PIN = 17; // GPIO
diff --git a/src/hal/root.zig b/src/hal/root.zig
new file mode 100644
index 0000000..d87dab8
--- /dev/null
+++ b/src/hal/root.zig
@@ -0,0 +1,54 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const regz = microzig.chip.registers;
+
+pub const gpio = struct {
+    fn getRegNamed(comptime fld: []const u8) @TypeOf(@field(regz.GPIO, fld)) {
+        return @field(regz.GPIO, fld);
+    }
+
+    fn getReg(comptime template: []const u8, comptime pin: comptime_int) @TypeOf(@field(regz.GPIO, std.fmt.comptimePrint(template, .{pin}))) {
+        return getRegNamed(comptime std.fmt.comptimePrint(template, .{pin}));
+    }
+
+    fn assertRange(comptime p: comptime_int) void {
+        if (p < 0 or p >= 21)
+            @compileError(std.fmt.comptimePrint("GPIO {} does not exist. GPIO pins can be between 0 and 21", .{p}));
+    }
+
+    pub const Config = struct {
+        function: u8 = 0x80,
+        invert_function: bool = false,
+        direction: microzig.gpio.Direction,
+        direct_io: bool = false,
+        invert_direct_io: bool = false,
+    };
+
+    pub fn init(comptime pin: comptime_int, comptime config: Config) void {
+        assertRange(pin);
+        getReg("FUNC{}_OUT_SEL_CFG", pin).modify(.{
+            .OUT_SEL = config.function,
+            .INV_SEL = @boolToInt(config.invert_function),
+            .OEN_SEL = @boolToInt(config.direct_io),
+            .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
+        });
+        switch (config.direction) {
+            .input => microzig.chip.registers.GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
+            .output => microzig.chip.registers.GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
+        }
+    }
+};
+
+pub const uart = struct {
+    fn reg(comptime index: comptime_int) @TypeOf(@field(regz, std.fmt.comptimePrint("UART{}", .{index}))) {
+        return @field(regz, std.fmt.comptimePrint("UART{}", .{index}));
+    }
+
+    pub fn write(comptime index: comptime_int, slice: []const u8) void {
+        const r = reg(index);
+        for (slice) |c| {
+            while (r.STATUS.read().TXFIFO_CNT > 8) {}
+            r.FIFO.raw = c;
+        }
+    }
+};
diff --git a/src/package/esp32-c3.zig b/src/package/esp32-c3.zig
index 0a0f4fe..0ab4944 100644
--- a/src/package/esp32-c3.zig
+++ b/src/package/esp32-c3.zig
@@ -1,6 +1,8 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+pub const registers = @import("registers.zig").registers;
+
 pub const startup_logic = struct {
     comptime {
         // See this:
@@ -14,8 +16,6 @@ pub const startup_logic = struct {
         // access). The bootloader then jumps to address 0x42000008, i.e. to the
         // instruction at offset 8 in flash, immediately after the magic numbers.
 
-        asm (std.fmt.comptimePrint(".equ MICROZIG_INITIAL_STACK, {}", .{microzig.config.end_of_stack}));
-
         asm (
             \\.extern _start
             \\.section microzig_flash_start
@@ -27,14 +27,14 @@ pub const startup_logic = struct {
 
     extern fn microzig_main() noreturn;
 
-    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
-        asm volatile (
-            \\li sp, MICROZIG_INITIAL_STACK
-            \\lui  a0, %%hi(_rv32_trap)
-            \\addi a0, a0, %%lo(_rv32_trap)
-            \\sw t0, 0x305(zero)
+    export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
+        microzig.cpu.cli();
+        asm volatile ("mv sp, %[eos]"
+            :
+            : [eos] "r" (@as(u32, microzig.config.end_of_stack)),
         );
-
+        asm volatile ("la gp, __global_pointer$");
+        microzig.cpu.setStatusBit(.mtvec, microzig.config.end_of_stack);
         microzig.initializeSystemMemories();
         microzig_main();
     }
@@ -42,4 +42,28 @@ pub const startup_logic = struct {
     export fn _rv32_trap() callconv(.C) noreturn {
         while (true) {}
     }
+
+    const vector_table = [_]fn () callconv(.C) noreturn{
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+    };
 };
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
index 34dbffd..06d7bc4 100644
--- a/src/package/espressif-riscv.zig
+++ b/src/package/espressif-riscv.zig
@@ -1,12 +1,39 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+pub const StatusRegister = enum(u8) {
+    // machine information
+    mvendorid,
+    marchid,
+    mimpid,
+    mhartid,
+
+    // machine trap setup
+    mstatus,
+    misa,
+    mtvec,
+};
+
+pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
 pub inline fn cli() void {
-    asm volatile ("");
+    clearStatusBit(.mstatus, 0x08);
 }
 
 pub inline fn sei() void {
-    asm volatile ("");
+    setStatusBit(.mstatus, 0x08);
 }
 
 pub const startup_logic = microzig.chip.startup_logic;
diff --git a/src/esp32c3.zig b/src/package/registers.zig
similarity index 100%
rename from src/esp32c3.zig
rename to src/package/registers.zig

From 24bb6dced705bef2d5db29a4cdb398327ff1dffb Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:03:20 -0800
Subject: [PATCH 07/29] add microzig submodule (#1)

---
 .gitmodules   | 3 +++
 deps/microzig | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 deps/microzig

diff --git a/.gitmodules b/.gitmodules
index 54620ef..911b8cf 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "vendor/microzig"]
 	path = vendor/microzig
 	url = https://github.com/ZigEmbeddedGroup/microzig
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 0000000..4bb6561
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b

From f625be1dff15eb1dac1fd5c29e2c7dec4604d3bd Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:11:54 -0800
Subject: [PATCH 08/29] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4bb6561..831cfff 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From 92d7d14d124c799f20c3074633565993fbc2585b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:37:40 -0800
Subject: [PATCH 09/29] Update microzig (#3)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 25 ++++++++++++++++---------
 deps/microzig |  2 +-
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/build.zig b/build.zig
index c0d71db..dd5a65c 100644
--- a/build.zig
+++ b/build.zig
@@ -2,7 +2,7 @@ const std = @import("std");
 const microzig = @import("zpm.zig").sdks.microzig;
 
 pub fn build(b: *std.build.Builder) void {
-    const mode = b.standardReleaseOptions();
+    const optimize = b.standardOptimizeOption(.{});
 
     const esp32_c3_cpu = microzig.Cpu{
         .name = "Espressif RISC-V",
@@ -21,7 +21,13 @@ pub fn build(b: *std.build.Builder) void {
 
     const esp32_c3 = microzig.Chip{
         .name = "ESP32 C3",
-        .path = "src/package/esp32-c3.zig",
+        .source = .{
+            .path = "src/package/esp32-c3.zig",
+        },
+        .hal = .{
+            .source = "src/hal/root.zig",
+        },
+
         .cpu = esp32_c3_cpu,
         .memory_regions = &.{
             .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
@@ -29,13 +35,14 @@ pub fn build(b: *std.build.Builder) void {
         },
     };
 
-    var exe = microzig.addEmbeddedExecutable(
-        b,
-        "esp-bringup",
-        "src/example/blinky.zig",
-        .{ .chip = esp32_c3 },
-        .{ .hal_package_path = .{ .path = "src/hal/root.zig" } },
-    );
+    var exe = microzig.addEmbeddedExecutable(b, .{
+        .name = "esp-bringup",
+        .source_file = .{
+            .path = "src/example/blinky.zig",
+        },
+        .backing = .{ .chip = esp32_c3 },
+        .optimize = optimize,
+    });
     exe.setBuildMode(mode);
     exe.install();
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff..b6fc3ab 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 52092330a2a251962bf8681f0148b5dafb682c4a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:46:44 -0800
Subject: [PATCH 10/29] update microzig (#4)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3ab..08e7d5b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 2381f96b9afee214b3e7f84beab937038e0b947b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 2 Mar 2023 01:13:42 -0800
Subject: [PATCH 11/29] organzie (#5)

* organzie

* add buildkite pipeline
---
 .buildkite/pipeline.yml                       |     4 +
 build.zig                                     |    43 +-
 src/chips.zig                                 |    23 +
 src/chips/ESP32_C3.json                       | 33570 ++++++++++++++
 src/chips/ESP32_C3.zig                        | 12378 +++++
 src/cpus.zig                                  |    23 +
 .../esp32-c3.zig => cpus/espressif-riscv.zig} |    38 +-
 src/example/blinky.zig                        |    37 +-
 src/{hal/root.zig => hals/ESP32_C3.zig}       |    23 +-
 src/package/espressif-riscv.zig               |    39 -
 src/package/registers.zig                     | 37956 ----------------
 11 files changed, 46068 insertions(+), 38066 deletions(-)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 src/chips.zig
 create mode 100644 src/chips/ESP32_C3.json
 create mode 100644 src/chips/ESP32_C3.zig
 create mode 100644 src/cpus.zig
 rename src/{package/esp32-c3.zig => cpus/espressif-riscv.zig} (72%)
 rename src/{hal/root.zig => hals/ESP32_C3.zig} (57%)
 delete mode 100644 src/package/espressif-riscv.zig
 delete mode 100644 src/package/registers.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 0000000..7767bbb
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build
diff --git a/build.zig b/build.zig
index dd5a65c..f96f446 100644
--- a/build.zig
+++ b/build.zig
@@ -1,52 +1,19 @@
 const std = @import("std");
-const microzig = @import("zpm.zig").sdks.microzig;
+const microzig = @import("deps/microzig/build.zig");
+
+pub const chips = @import("src/chips.zig");
+pub const cpus = @import("src/cpus.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
 
-    const esp32_c3_cpu = microzig.Cpu{
-        .name = "Espressif RISC-V",
-        .path = "src/package/espressif-riscv.zig",
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .riscv32,
-            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-            .cpu_features_add = std.Target.riscv.featureSet(&.{
-                std.Target.riscv.Feature.c,
-                std.Target.riscv.Feature.m,
-            }),
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    const esp32_c3 = microzig.Chip{
-        .name = "ESP32 C3",
-        .source = .{
-            .path = "src/package/esp32-c3.zig",
-        },
-        .hal = .{
-            .source = "src/hal/root.zig",
-        },
-
-        .cpu = esp32_c3_cpu,
-        .memory_regions = &.{
-            .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-            .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-        },
-    };
-
     var exe = microzig.addEmbeddedExecutable(b, .{
         .name = "esp-bringup",
         .source_file = .{
             .path = "src/example/blinky.zig",
         },
-        .backing = .{ .chip = esp32_c3 },
+        .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.setBuildMode(mode);
     exe.install();
-
-    const raw_step = exe.installRaw("firmware.bin", .{});
-
-    b.getInstallStep().dependOn(&raw_step.step);
 }
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 0000000..14769f3
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+const cpus = @import("cpus.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Chip{
+    .name = "ESP32-C3",
+    .source = .{
+        .path = root_dir() ++ "/chips/ESP32_C3.zig",
+    },
+    .hal = .{
+        .path = root_dir() ++ "/hals/ESP32_C3.zig",
+    },
+
+    .cpu = cpus.esp32_c3,
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+    },
+};
diff --git a/src/chips/ESP32_C3.json b/src/chips/ESP32_C3.json
new file mode 100644
index 0000000..4691dc7
--- /dev/null
+++ b/src/chips/ESP32_C3.json
@@ -0,0 +1,33570 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "AES": {
+        "description": "AES (Advanced Encryption Standard) Accelerator",
+        "children": {
+          "registers": {
+            "KEY_0": {
+              "description": "Key material key_0 configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_0": {
+                    "description": "This bits stores key_0 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_1": {
+              "description": "Key material key_1 configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_1": {
+                    "description": "This bits stores key_1 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_2": {
+              "description": "Key material key_2 configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_2": {
+                    "description": "This bits stores key_2 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_3": {
+              "description": "Key material key_3 configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_3": {
+                    "description": "This bits stores key_3 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_4": {
+              "description": "Key material key_4 configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_4": {
+                    "description": "This bits stores key_4 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_5": {
+              "description": "Key material key_5 configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_5": {
+                    "description": "This bits stores key_5 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_6": {
+              "description": "Key material key_6 configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_6": {
+                    "description": "This bits stores key_6 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_7": {
+              "description": "Key material key_7 configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_7": {
+                    "description": "This bits stores key_7 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_0": {
+              "description": "source text material text_in_0 configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_0": {
+                    "description": "This bits stores text_in_0 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_1": {
+              "description": "source text material text_in_1 configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_1": {
+                    "description": "This bits stores text_in_1 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_2": {
+              "description": "source text material text_in_2 configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_2": {
+                    "description": "This bits stores text_in_2 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_3": {
+              "description": "source text material text_in_3 configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_3": {
+                    "description": "This bits stores text_in_3 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_0": {
+              "description": "result text material text_out_0 configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_0": {
+                    "description": "This bits stores text_out_0 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_1": {
+              "description": "result text material text_out_1 configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_1": {
+                    "description": "This bits stores text_out_1 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_2": {
+              "description": "result text material text_out_2 configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_2": {
+                    "description": "This bits stores text_out_2 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_3": {
+              "description": "result text material text_out_3 configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_3": {
+                    "description": "This bits stores text_out_3 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "AES Mode register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "ENDIAN": {
+              "description": "AES Endian configure register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDIAN": {
+                    "description": "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "TRIGGER": {
+              "description": "AES trigger register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGER": {
+                    "description": "Set this bit to start AES calculation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "AES state register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IV_MEM": {
+              "description": "The memory that stores initialization vector",
+              "offset": 80,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "H_MEM": {
+              "description": "The memory that stores GCM hash subkey",
+              "offset": 96,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "J0_MEM": {
+              "description": "The memory that stores J0",
+              "offset": 112,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "T0_MEM": {
+              "description": "The memory that stores T0",
+              "offset": 128,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "DMA_ENABLE": {
+              "description": "DMA-AES working mode register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_ENABLE": {
+                    "description": "1'b0: typical AES working mode, 1'b1: DMA-AES working mode.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BLOCK_MODE": {
+              "description": "AES cipher block mode register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BLOCK_MODE": {
+                    "description": "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "BLOCK_NUM": {
+              "description": "AES block number register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BLOCK_NUM": {
+                    "description": "Those bits stores the number of Plaintext/ciphertext block.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INC_SEL": {
+              "description": "Standard incrementing function configure register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INC_SEL": {
+                    "description": "This bit decides the standard incrementing function. 0: INC32. 1: INC128.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AAD_BLOCK_NUM": {
+              "description": "Additional Authential Data block number register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AAD_BLOCK_NUM": {
+                    "description": "Those bits stores the number of AAD block.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REMAINDER_BIT_NUM": {
+              "description": "AES remainder bit number register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REMAINDER_BIT_NUM": {
+                    "description": "Those bits stores the number of remainder bit.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CONTINUE": {
+              "description": "AES continue register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONTINUE": {
+                    "description": "Set this bit to continue GCM operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_CLEAR": {
+              "description": "AES Interrupt clear register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_CLEAR": {
+                    "description": "Set this bit to clear the AES interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "AES Interrupt enable register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_ENA": {
+                    "description": "Set this bit to enable interrupt that occurs when DMA-AES calculation is done.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "AES version control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 538513936,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "This bits stores the version information of AES.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "DMA_EXIT": {
+              "description": "AES-DMA exit config",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_EXIT": {
+                    "description": "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "APB_CTRL": {
+        "description": "Advanced Peripheral Bus Controller",
+        "children": {
+          "registers": {
+            "SYSCLK_CONF": {
+              "description": "APB_CTRL_SYSCLK_CONF_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_DIV_CNT": {
+                    "description": "reg_pre_div_cnt",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "CLK_320M_EN": {
+                    "description": "reg_clk_320m_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RST_TICK_CNT": {
+                    "description": "reg_rst_tick_cnt",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TICK_CONF": {
+              "description": "APB_CTRL_TICK_CONF_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 67367,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL_TICK_NUM": {
+                    "description": "reg_xtal_tick_num",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CK8M_TICK_NUM": {
+                    "description": "reg_ck8m_tick_num",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "TICK_ENABLE": {
+                    "description": "reg_tick_enable",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLK_OUT_EN": {
+              "description": "APB_CTRL_CLK_OUT_EN_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2047,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK20_OEN": {
+                    "description": "reg_clk20_oen",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CLK22_OEN": {
+                    "description": "reg_clk22_oen",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLK44_OEN": {
+                    "description": "reg_clk44_oen",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CLK_BB_OEN": {
+                    "description": "reg_clk_bb_oen",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CLK80_OEN": {
+                    "description": "reg_clk80_oen",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CLK160_OEN": {
+                    "description": "reg_clk160_oen",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CLK_320M_OEN": {
+                    "description": "reg_clk_320m_oen",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CLK_ADC_INF_OEN": {
+                    "description": "reg_clk_adc_inf_oen",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CLK_DAC_CPU_OEN": {
+                    "description": "reg_clk_dac_cpu_oen",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CLK40X_BB_OEN": {
+                    "description": "reg_clk40x_bb_oen",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CLK_XTAL_OEN": {
+                    "description": "reg_clk_xtal_oen",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WIFI_BB_CFG": {
+              "description": "APB_CTRL_WIFI_BB_CFG_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_BB_CFG": {
+                    "description": "reg_wifi_bb_cfg",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_BB_CFG_2": {
+              "description": "APB_CTRL_WIFI_BB_CFG_2_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_BB_CFG_2": {
+                    "description": "reg_wifi_bb_cfg_2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_CLK_EN": {
+              "description": "APB_CTRL_WIFI_CLK_EN_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294762544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_CLK_EN": {
+                    "description": "reg_wifi_clk_en",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_RST_EN": {
+              "description": "APB_CTRL_WIFI_RST_EN_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_RST": {
+                    "description": "reg_wifi_rst",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_INF_SEL": {
+              "description": "APB_CTRL_HOST_INF_SEL_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IO_SWAP": {
+                    "description": "reg_peri_io_swap",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "EXT_MEM_PMS_LOCK": {
+              "description": "APB_CTRL_EXT_MEM_PMS_LOCK_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXT_MEM_PMS_LOCK": {
+                    "description": "reg_ext_mem_pms_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE0_ATTR_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE0_ATTR": {
+                    "description": "reg_flash_ace0_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE1_ATTR_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE1_ATTR": {
+                    "description": "reg_flash_ace1_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE2_ATTR_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE2_ATTR": {
+                    "description": "reg_flash_ace2_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE3_ATTR_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE3_ATTR": {
+                    "description": "reg_flash_ace3_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE0_ADDR_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace0_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE1_ADDR_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4194304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace1_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE2_ADDR_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace2_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE3_ADDR_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace3_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE0_SIZE_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE0_SIZE": {
+                    "description": "reg_flash_ace0_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE1_SIZE_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE1_SIZE": {
+                    "description": "reg_flash_ace1_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE2_SIZE_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE2_SIZE": {
+                    "description": "reg_flash_ace2_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE3_SIZE_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE3_SIZE": {
+                    "description": "reg_flash_ace3_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "SPI_MEM_PMS_CTRL": {
+              "description": "APB_CTRL_SPI_MEM_PMS_CTRL_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_INT": {
+                    "description": "reg_spi_mem_reject_int",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SPI_MEM_REJECT_CLR": {
+                    "description": "reg_spi_mem_reject_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SPI_MEM_REJECT_CDE": {
+                    "description": "reg_spi_mem_reject_cde",
+                    "offset": 2,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SPI_MEM_REJECT_ADDR": {
+              "description": "APB_CTRL_SPI_MEM_REJECT_ADDR_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_ADDR": {
+                    "description": "reg_spi_mem_reject_addr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SDIO_CTRL": {
+              "description": "APB_CTRL_SDIO_CTRL_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_WIN_ACCESS_EN": {
+                    "description": "reg_sdio_win_access_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REDCY_SIG0": {
+              "description": "APB_CTRL_REDCY_SIG0_REG",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDCY_SIG0": {
+                    "description": "reg_redcy_sig0",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "REDCY_ANDOR": {
+                    "description": "reg_redcy_andor",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "REDCY_SIG1": {
+              "description": "APB_CTRL_REDCY_SIG1_REG",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDCY_SIG1": {
+                    "description": "reg_redcy_sig1",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "REDCY_NANDOR": {
+                    "description": "reg_redcy_nandor",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FRONT_END_MEM_PD": {
+              "description": "APB_CTRL_FRONT_END_MEM_PD_REG",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 21,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AGC_MEM_FORCE_PU": {
+                    "description": "reg_agc_mem_force_pu",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "AGC_MEM_FORCE_PD": {
+                    "description": "reg_agc_mem_force_pd",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PBUS_MEM_FORCE_PU": {
+                    "description": "reg_pbus_mem_force_pu",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PBUS_MEM_FORCE_PD": {
+                    "description": "reg_pbus_mem_force_pd",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DC_MEM_FORCE_PU": {
+                    "description": "reg_dc_mem_force_pu",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DC_MEM_FORCE_PD": {
+                    "description": "reg_dc_mem_force_pd",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RETENTION_CTRL": {
+              "description": "APB_CTRL_RETENTION_CTRL_REG",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RETENTION_LINK_ADDR": {
+                    "description": "reg_retention_link_addr",
+                    "offset": 0,
+                    "size": 27
+                  },
+                  "NOBYPASS_CPU_ISO_RST": {
+                    "description": "reg_nobypass_cpu_iso_rst",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLKGATE_FORCE_ON": {
+              "description": "APB_CTRL_CLKGATE_FORCE_ON_REG",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_CLKGATE_FORCE_ON": {
+                    "description": "reg_rom_clkgate_force_on",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_CLKGATE_FORCE_ON": {
+                    "description": "reg_sram_clkgate_force_on",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_POWER_DOWN": {
+              "description": "APB_CTRL_MEM_POWER_DOWN_REG",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_POWER_DOWN": {
+                    "description": "reg_rom_power_down",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_POWER_DOWN": {
+                    "description": "reg_sram_power_down",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_POWER_UP": {
+              "description": "APB_CTRL_MEM_POWER_UP_REG",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_POWER_UP": {
+                    "description": "reg_rom_power_up",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_POWER_UP": {
+                    "description": "reg_sram_power_up",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RND_DATA": {
+              "description": "APB_CTRL_RND_DATA_REG",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RND_DATA": {
+                    "description": "reg_rnd_data",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_CONFIG": {
+              "description": "APB_CTRL_PERI_BACKUP_CONFIG_REG",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 25728,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_FLOW_ERR": {
+                    "description": "reg_peri_backup_flow_err",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_BURST_LIMIT": {
+                    "description": "reg_peri_backup_burst_limit",
+                    "offset": 4,
+                    "size": 5
+                  },
+                  "PERI_BACKUP_TOUT_THRES": {
+                    "description": "reg_peri_backup_tout_thres",
+                    "offset": 9,
+                    "size": 10
+                  },
+                  "PERI_BACKUP_SIZE": {
+                    "description": "reg_peri_backup_size",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "PERI_BACKUP_START": {
+                    "description": "reg_peri_backup_start",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PERI_BACKUP_TO_MEM": {
+                    "description": "reg_peri_backup_to_mem",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PERI_BACKUP_ENA": {
+                    "description": "reg_peri_backup_ena",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_APB_ADDR": {
+              "description": "APB_CTRL_PERI_BACKUP_APB_ADDR_REG",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_APB_START_ADDR": {
+                    "description": "reg_backup_apb_start_addr",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_MEM_ADDR": {
+              "description": "APB_CTRL_PERI_BACKUP_MEM_ADDR_REG",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_MEM_START_ADDR": {
+                    "description": "reg_backup_mem_start_addr",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_RAW": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_RAW_REG",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_RAW": {
+                    "description": "reg_peri_backup_done_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_RAW": {
+                    "description": "reg_peri_backup_err_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_ST": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_ST_REG",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_ST": {
+                    "description": "reg_peri_backup_done_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_ST": {
+                    "description": "reg_peri_backup_err_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_ENA": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_ENA_REG",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_ENA": {
+                    "description": "reg_peri_backup_done_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PERI_BACKUP_ERR_INT_ENA": {
+                    "description": "reg_peri_backup_err_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_CLR": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_CLR_REG",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_CLR": {
+                    "description": "reg_peri_backup_done_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_CLR": {
+                    "description": "reg_peri_backup_err_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "APB_CTRL_DATE_REG",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583632,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_dateVersion control",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "APB_SARADC": {
+        "description": "Successive Approximation Register Analog to Digital Converter",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1073971776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_START_FORCE": {
+                    "description": "select software enable saradc sample",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SARADC_START": {
+                    "description": "software enable saradc sample",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SARADC_SAR_CLK_GATED": {
+                    "description": "SAR clock gated",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SARADC_SAR_CLK_DIV": {
+                    "description": "SAR clock divider",
+                    "offset": 7,
+                    "size": 8
+                  },
+                  "SARADC_SAR_PATT_LEN": {
+                    "description": "0 ~ 15 means length 1 ~ 16",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SARADC_SAR_PATT_P_CLEAR": {
+                    "description": "clear the pointer of pattern table for DIG ADC1 CTRL",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SARADC_XPD_SAR_FORCE": {
+                    "description": "force option to xpd sar blocks",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "SARADC_WAIT_ARB_CYCLE": {
+                    "description": "wait arbit signal stable after sar_done",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "digital saradc configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 41470,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_MEAS_NUM_LIMIT": {
+                    "description": "enable max meas num",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SARADC_MAX_MEAS_NUM": {
+                    "description": "max conversion number",
+                    "offset": 1,
+                    "size": 8
+                  },
+                  "SARADC_SAR1_INV": {
+                    "description": "1: data to DIG ADC1 CTRL is inverted, otherwise not",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SARADC_SAR2_INV": {
+                    "description": "1: data to DIG ADC2 CTRL is inverted, otherwise not",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SARADC_TIMER_TARGET": {
+                    "description": "to set saradc timer target",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "SARADC_TIMER_EN": {
+                    "description": "to enable saradc timer trigger",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FILTER_CTRL1": {
+              "description": "digital saradc configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_FILTER_FACTOR1": {
+                    "description": "Factor of saradc filter1",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "APB_SARADC_FILTER_FACTOR0": {
+                    "description": "Factor of saradc filter0",
+                    "offset": 29,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "FSM_WAIT": {
+              "description": "digital saradc configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 16713736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_XPD_WAIT": {
+                    "description": "saradc_xpd_wait",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SARADC_RSTB_WAIT": {
+                    "description": "saradc_rstb_wait",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SARADC_STANDBY_WAIT": {
+                    "description": "saradc_standby_wait",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SAR1_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR1_STATUS": {
+                    "description": "saradc1 status about data and channel",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR2_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR2_STATUS": {
+                    "description": "saradc2 status about data and channel",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR_PATT_TAB1": {
+              "description": "digital saradc configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR_PATT_TAB1": {
+                    "description": "item 0 ~ 3 for pattern table 1 (each item one byte)",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SAR_PATT_TAB2": {
+              "description": "digital saradc configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR_PATT_TAB2": {
+                    "description": "Item 4 ~ 7 for pattern table 1 (each item one byte)",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ONETIME_SAMPLE": {
+              "description": "digital saradc configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 436207616,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_ONETIME_ATTEN": {
+                    "description": "configure onetime atten",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "SARADC_ONETIME_CHANNEL": {
+                    "description": "configure onetime channel",
+                    "offset": 25,
+                    "size": 4
+                  },
+                  "SARADC_ONETIME_START": {
+                    "description": "trigger adc onetime sample",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SARADC2_ONETIME_SAMPLE": {
+                    "description": "enable adc2 onetime sample",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SARADC1_ONETIME_SAMPLE": {
+                    "description": "enable adc1 onetime sample",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ARB_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 2304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADC_ARB_APB_FORCE": {
+                    "description": "adc2 arbiter force to enableapb controller",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADC_ARB_RTC_FORCE": {
+                    "description": "adc2 arbiter force to enable rtc controller",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADC_ARB_WIFI_FORCE": {
+                    "description": "adc2 arbiter force to enable wifi controller",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADC_ARB_GRANT_FORCE": {
+                    "description": "adc2 arbiter force grant",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADC_ARB_APB_PRIORITY": {
+                    "description": "Set adc2 arbiterapb priority",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "ADC_ARB_RTC_PRIORITY": {
+                    "description": "Set adc2 arbiter rtc priority",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADC_ARB_WIFI_PRIORITY": {
+                    "description": "Set adc2 arbiter wifi priority",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "ADC_ARB_FIX_PRIORITY": {
+                    "description": "adc2 arbiter uses fixed priority",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FILTER_CTRL0": {
+              "description": "digital saradc configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 57933824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_FILTER_CHANNEL1": {
+                    "description": "configure filter1 to adc channel",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "APB_SARADC_FILTER_CHANNEL0": {
+                    "description": "configure filter0 to adc channel",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "APB_SARADC_FILTER_RESET": {
+                    "description": "enable apb_adc1_filter",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAR1DATA_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC1_DATA": {
+                    "description": "saradc1 data",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR2DATA_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC2_DATA": {
+                    "description": "saradc2 data",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "THRES0_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 262125,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES0_CHANNEL": {
+                    "description": "configure thres0 to adc channel",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "APB_SARADC_THRES0_HIGH": {
+                    "description": "saradc thres0 monitor thres",
+                    "offset": 5,
+                    "size": 13
+                  },
+                  "APB_SARADC_THRES0_LOW": {
+                    "description": "saradc thres0 monitor thres",
+                    "offset": 18,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "THRES1_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 262125,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_CHANNEL": {
+                    "description": "configure thres1 to adc channel",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "APB_SARADC_THRES1_HIGH": {
+                    "description": "saradc thres1 monitor thres",
+                    "offset": 5,
+                    "size": 13
+                  },
+                  "APB_SARADC_THRES1_LOW": {
+                    "description": "saradc thres1 monitor thres",
+                    "offset": 18,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "THRES_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES_ALL_EN": {
+                    "description": "enable thres to all channel",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES1_EN": {
+                    "description": "enable thres1",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_EN": {
+                    "description": "enable thres0",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "digital saradc int register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_ENA": {
+                    "description": "saradc thres1 low  interrupt enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_ENA": {
+                    "description": "saradc thres0 low interrupt enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_ENA": {
+                    "description": "saradc thres1 high interrupt enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_ENA": {
+                    "description": "saradc thres0 high interrupt enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "APB_SARADC2_DONE_INT_ENA": {
+                    "description": "saradc2 done interrupt enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_SARADC1_DONE_INT_ENA": {
+                    "description": "saradc1 done interrupt enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "digital saradc int register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_RAW": {
+                    "description": "saradc thres1 low  interrupt raw",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_RAW": {
+                    "description": "saradc thres0 low interrupt raw",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_RAW": {
+                    "description": "saradc thres1 high interrupt raw",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_RAW": {
+                    "description": "saradc thres0 high interrupt raw",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC2_DONE_INT_RAW": {
+                    "description": "saradc2 done interrupt raw",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC1_DONE_INT_RAW": {
+                    "description": "saradc1 done interrupt raw",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "digital saradc int register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_ST": {
+                    "description": "saradc thres1 low  interrupt state",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_ST": {
+                    "description": "saradc thres0 low interrupt state",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_ST": {
+                    "description": "saradc thres1 high interrupt state",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_ST": {
+                    "description": "saradc thres0 high interrupt state",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC2_DONE_INT_ST": {
+                    "description": "saradc2 done interrupt state",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC1_DONE_INT_ST": {
+                    "description": "saradc1 done interrupt state",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "digital saradc int register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_CLR": {
+                    "description": "saradc thres1 low  interrupt clear",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_CLR": {
+                    "description": "saradc thres0 low interrupt clear",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_CLR": {
+                    "description": "saradc thres1 high interrupt clear",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_CLR": {
+                    "description": "saradc thres0 high interrupt clear",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC2_DONE_INT_CLR": {
+                    "description": "saradc2 done interrupt clear",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC1_DONE_INT_CLR": {
+                    "description": "saradc1 done interrupt clear",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_CONF": {
+              "description": "digital saradc configure register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_ADC_EOF_NUM": {
+                    "description": "the dma_in_suc_eof gen when sample cnt = spi_eof_num",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "APB_ADC_RESET_FSM": {
+                    "description": "reset_apb_adc_state",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_ADC_TRANS": {
+                    "description": "enable apb_adc use spi_dma",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLKM_CONF": {
+              "description": "digital saradc configure register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKM_DIV_NUM": {
+                    "description": "Integral I2S clock divider value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKM_DIV_B": {
+                    "description": "Fractional clock divider numerator value",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "CLKM_DIV_A": {
+                    "description": "Fractional clock divider denominator value",
+                    "offset": 14,
+                    "size": 6
+                  },
+                  "CLK_EN": {
+                    "description": "reg clk en",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CLK_SEL": {
+                    "description": "Set this bit to enable clk_apll",
+                    "offset": 21,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "APB_TSENS_CTRL": {
+              "description": "digital tsens configure register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 98304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSENS_OUT": {
+                    "description": "temperature sensor data out",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TSENS_IN_INV": {
+                    "description": "invert temperature sensor data",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TSENS_CLK_DIV": {
+                    "description": "temperature sensor clock divider",
+                    "offset": 14,
+                    "size": 8
+                  },
+                  "TSENS_PU": {
+                    "description": "temperature sensor power up",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSENS_CTRL2": {
+              "description": "digital tsens configure register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 16386,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSENS_XPD_WAIT": {
+                    "description": "the time that power up tsens need wait",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "TSENS_XPD_FORCE": {
+                    "description": "force power up tsens",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "TSENS_CLK_INV": {
+                    "description": "inv tsens clk",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TSENS_CLK_SEL": {
+                    "description": "tsens clk select",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CALI": {
+              "description": "digital saradc configure register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_CALI_CFG": {
+                    "description": "saradc cali factor",
+                    "offset": 0,
+                    "size": 17
+                  }
+                }
+              }
+            },
+            "CTRL_DATE": {
+              "description": "version",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583473,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "version",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ASSIST_DEBUG": {
+        "description": "Debug Assist",
+        "children": {
+          "registers": {
+            "C0RE_0_MONTR_ENA": {
+              "description": "ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_ENA": {
+                    "description": "reg_core_0_area_dram0_0_rd_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_wr_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_ENA": {
+                    "description": "reg_core_0_area_dram0_1_rd_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_wr_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_ENA": {
+                    "description": "reg_core_0_area_pif_0_rd_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_ENA": {
+                    "description": "reg_core_0_area_pif_0_wr_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_ENA": {
+                    "description": "reg_core_0_area_pif_1_rd_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_ENA": {
+                    "description": "reg_core_0_area_pif_1_wr_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_ENA": {
+                    "description": "reg_core_0_sp_spill_min_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_ENA": {
+                    "description": "reg_core_0_sp_spill_max_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_ENA": {
+                    "description": "reg_core_0_iram0_exception_monitor_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_ENA": {
+                    "description": "reg_core_0_dram0_exception_monitor_ena",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_RAW": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_RAW_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_RAW": {
+                    "description": "reg_core_0_area_dram0_0_rd_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_RAW": {
+                    "description": "reg_core_0_area_dram0_0_wr_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_RAW": {
+                    "description": "reg_core_0_area_dram0_1_rd_raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_RAW": {
+                    "description": "reg_core_0_area_dram0_1_wr_raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_0_RD_RAW": {
+                    "description": "reg_core_0_area_pif_0_rd_raw",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_0_WR_RAW": {
+                    "description": "reg_core_0_area_pif_0_wr_raw",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_1_RD_RAW": {
+                    "description": "reg_core_0_area_pif_1_rd_raw",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_1_WR_RAW": {
+                    "description": "reg_core_0_area_pif_1_wr_raw",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_SP_SPILL_MIN_RAW": {
+                    "description": "reg_core_0_sp_spill_min_raw",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_SP_SPILL_MAX_RAW": {
+                    "description": "reg_core_0_sp_spill_max_raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RAW": {
+                    "description": "reg_core_0_iram0_exception_monitor_raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RAW": {
+                    "description": "reg_core_0_dram0_exception_monitor_raw",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_ENA": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_ENA_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_rd_intr_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_wr_intr_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_rd_intr_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_wr_intr_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_0_rd_intr_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_0_wr_intr_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_1_rd_intr_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_1_wr_intr_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_INTR_ENA": {
+                    "description": "reg_core_0_sp_spill_min_intr_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_INTR_ENA": {
+                    "description": "reg_core_0_sp_spill_max_intr_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RLS": {
+                    "description": "reg_core_0_iram0_exception_monitor_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RLS": {
+                    "description": "reg_core_0_dram0_exception_monitor_ena",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_CLR": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_CLR_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_CLR": {
+                    "description": "reg_core_0_area_dram0_0_rd_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_CLR": {
+                    "description": "reg_core_0_area_dram0_0_wr_clr",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_CLR": {
+                    "description": "reg_core_0_area_dram0_1_rd_clr",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_CLR": {
+                    "description": "reg_core_0_area_dram0_1_wr_clr",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_CLR": {
+                    "description": "reg_core_0_area_pif_0_rd_clr",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_CLR": {
+                    "description": "reg_core_0_area_pif_0_wr_clr",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_CLR": {
+                    "description": "reg_core_0_area_pif_1_rd_clr",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_CLR": {
+                    "description": "reg_core_0_area_pif_1_wr_clr",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_CLR": {
+                    "description": "reg_core_0_sp_spill_min_clr",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_CLR": {
+                    "description": "reg_core_0_sp_spill_max_clr",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_CLR": {
+                    "description": "reg_core_0_iram0_exception_monitor_clr",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_CLR": {
+                    "description": "reg_core_0_dram0_exception_monitor_clr",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_0_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_MIN": {
+                    "description": "reg_core_0_area_dram0_0_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_0_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_MAX": {
+                    "description": "reg_core_0_area_dram0_0_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_1_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_1_MIN": {
+                    "description": "reg_core_0_area_dram0_1_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_1_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_1_MAX": {
+                    "description": "reg_core_0_area_dram0_1_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_0_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_0_MIN": {
+                    "description": "reg_core_0_area_pif_0_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_0_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_0_MAX": {
+                    "description": "reg_core_0_area_pif_0_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_1_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_1_MIN": {
+                    "description": "reg_core_0_area_pif_1_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_1_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_1_MAX": {
+                    "description": "reg_core_0_area_pif_1_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PC": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PC_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PC": {
+                    "description": "reg_core_0_area_pc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_SP": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_SP_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_SP": {
+                    "description": "reg_core_0_area_sp",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_MIN_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_MIN": {
+                    "description": "reg_core_0_sp_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_MAX_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_MAX": {
+                    "description": "reg_core_0_sp_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_PC": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_PC_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_PC": {
+                    "description": "reg_core_0_sp_pc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_EN": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_EN_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_RECORDEN": {
+                    "description": "reg_core_0_rcd_recorden",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_RCD_PDEBUGEN": {
+                    "description": "reg_core_0_rcd_pdebugen",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_PDEBUGPC": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_PDEBUGPC": {
+                    "description": "reg_core_0_rcd_pdebugpc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_PDEBUGSP": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_PDEBUGSP": {
+                    "description": "reg_core_0_rcd_pdebugsp",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_RECORDING_ADDR_0": {
+                    "description": "reg_core_0_iram0_recording_addr_0",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_WR_0": {
+                    "description": "reg_core_0_iram0_recording_wr_0",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_LOADSTORE_0": {
+                    "description": "reg_core_0_iram0_recording_loadstore_0",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_RECORDING_ADDR_1": {
+                    "description": "reg_core_0_iram0_recording_addr_1",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_WR_1": {
+                    "description": "reg_core_0_iram0_recording_wr_1",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_LOADSTORE_1": {
+                    "description": "reg_core_0_iram0_recording_loadstore_1",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_ADDR_0": {
+                    "description": "reg_core_0_dram0_recording_addr_0",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_WR_0": {
+                    "description": "reg_core_0_dram0_recording_wr_0",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_BYTEEN_0": {
+                    "description": "reg_core_0_dram0_recording_byteen_0",
+                    "offset": 25,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_PC_0": {
+                    "description": "reg_core_0_dram0_recording_pc_0",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_2": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_ADDR_1": {
+                    "description": "reg_core_0_dram0_recording_addr_1",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_WR_1": {
+                    "description": "reg_core_0_dram0_recording_wr_1",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_BYTEEN_1": {
+                    "description": "reg_core_0_dram0_recording_byteen_1",
+                    "offset": 25,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_3": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_PC_1": {
+                    "description": "reg_core_0_dram0_recording_pc_1",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0": {
+                    "description": "reg_core_x_iram0_dram0_limit_cycle_0",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1": {
+                    "description": "reg_core_x_iram0_dram0_limit_cycle_1",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "LOG_SETTING": {
+              "description": "ASSIST_DEBUG_LOG_SETTING",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_ENA": {
+                    "description": "reg_log_ena",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "LOG_MODE": {
+                    "description": "reg_log_mode",
+                    "offset": 3,
+                    "size": 4
+                  },
+                  "LOG_MEM_LOOP_ENABLE": {
+                    "description": "reg_log_mem_loop_enable",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOG_DATA_0": {
+              "description": "ASSIST_DEBUG_LOG_DATA_0_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_DATA_0": {
+                    "description": "reg_log_data_0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_DATA_MASK": {
+              "description": "ASSIST_DEBUG_LOG_DATA_MASK_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_DATA_SIZE": {
+                    "description": "reg_log_data_size",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "LOG_MIN": {
+              "description": "ASSIST_DEBUG_LOG_MIN_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MIN": {
+                    "description": "reg_log_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MAX": {
+              "description": "ASSIST_DEBUG_LOG_MAX_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MAX": {
+                    "description": "reg_log_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_START": {
+              "description": "ASSIST_DEBUG_LOG_MEM_START_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_START": {
+                    "description": "reg_log_mem_start",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_END": {
+              "description": "ASSIST_DEBUG_LOG_MEM_END_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_END": {
+                    "description": "reg_log_mem_end",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_WRITING_ADDR": {
+              "description": "ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_WRITING_ADDR": {
+                    "description": "reg_log_mem_writing_addr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LOG_MEM_FULL_FLAG": {
+              "description": "ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_FULL_FLAG": {
+                    "description": "reg_log_mem_full_flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLR_LOG_MEM_FULL_FLAG": {
+                    "description": "reg_clr_log_mem_full_flag",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "C0RE_0_LASTPC_BEFORE_EXCEPTION": {
+              "description": "ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_LASTPC_BEFORE_EXC": {
+                    "description": "reg_core_0_lastpc_before_exc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "C0RE_0_DEBUG_MODE": {
+              "description": "ASSIST_DEBUG_C0RE_0_DEBUG_MODE",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DEBUG_MODE": {
+                    "description": "reg_core_0_debug_mode",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DEBUG_MODULE_ACTIVE": {
+                    "description": "reg_core_0_debug_module_active",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "ASSIST_DEBUG_DATE_REG",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33587216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASSIST_DEBUG_DATE": {
+                    "description": "reg_assist_debug_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA": {
+        "description": "DMA (Direct Memory Access) Controller",
+        "children": {
+          "registers": {
+            "INT_RAW_CH0": {
+              "description": "DMA_INT_RAW_CH0_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH0": {
+              "description": "DMA_INT_ST_CH0_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH0": {
+              "description": "DMA_INT_ENA_CH0_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH0": {
+              "description": "DMA_INT_CLR_CH0_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW_CH1": {
+              "description": "DMA_INT_RAW_CH1_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH1": {
+              "description": "DMA_INT_ST_CH1_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH1": {
+              "description": "DMA_INT_ENA_CH1_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH1": {
+              "description": "DMA_INT_CLR_CH1_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW_CH2": {
+              "description": "DMA_INT_RAW_CH2_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH2": {
+              "description": "DMA_INT_ST_CH2_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH2": {
+              "description": "DMA_INT_ENA_CH2_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH2": {
+              "description": "DMA_INT_CLR_CH2_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "AHB_TEST": {
+              "description": "DMA_AHB_TEST_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHB_TESTMODE": {
+                    "description": "reserved",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "AHB_TESTADDR": {
+                    "description": "reserved",
+                    "offset": 4,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "MISC_CONF": {
+              "description": "DMA_MISC_CONF_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHBM_RST_INTER": {
+                    "description": "Set this bit, then clear this bit to reset the internal ahb FSM.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ARB_PRI_DIS": {
+                    "description": "Set this bit to disable priority arbitration function.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "DMA_DATE_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 33587792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "register version.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH0": {
+              "description": "DMA_IN_CONF0_CH0_REG.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH0": {
+                    "description": "This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH0": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH0": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH0": {
+              "description": "DMA_IN_CONF1_CH0_REG.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH0": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH0": {
+              "description": "DMA_INFIFO_STATUS_CH0_REG.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH0": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH0": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH0": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH0": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH0": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH0": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH0": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH0": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH0": {
+              "description": "DMA_IN_POP_CH0_REG.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH0": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH0": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH0": {
+              "description": "DMA_IN_LINK_CH0_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH0": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH0": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH0": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH0": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH0": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH0": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH0": {
+              "description": "DMA_IN_STATE_CH0_REG.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH0": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH0": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH0": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH0": {
+              "description": "DMA_IN_DSCR_CH0_REG.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH0": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH0": {
+              "description": "DMA_IN_DSCR_BF0_CH0_REG.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH0": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH0": {
+              "description": "DMA_IN_DSCR_BF1_CH0_REG.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH0": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH0": {
+              "description": "DMA_IN_PRI_CH0_REG.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH0": {
+                    "description": "The priority of Rx channel 0. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH0": {
+              "description": "DMA_IN_PERI_SEL_CH0_REG.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH0": {
+                    "description": "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH0": {
+              "description": "DMA_OUT_CONF0_CH0_REG.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH0": {
+                    "description": "This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH0": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH0": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH0": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH0": {
+              "description": "DMA_OUT_CONF1_CH0_REG.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH0": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH0": {
+              "description": "DMA_OUTFIFO_STATUS_CH0_REG.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH0": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH0": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH0": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH0": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH0": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH0": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH0": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH0": {
+              "description": "DMA_OUT_PUSH_CH0_REG.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH0": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH0": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH0": {
+              "description": "DMA_OUT_LINK_CH0_REG.",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH0": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH0": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH0": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH0": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH0": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH0": {
+              "description": "DMA_OUT_STATE_CH0_REG.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH0": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH0": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH0_REG.",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH0": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH0": {
+              "description": "DMA_OUT_DSCR_CH0_REG.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH0": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH0": {
+              "description": "DMA_OUT_DSCR_BF0_CH0_REG.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH0": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH0": {
+              "description": "DMA_OUT_DSCR_BF1_CH0_REG.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH0": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH0": {
+              "description": "DMA_OUT_PRI_CH0_REG.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH0": {
+                    "description": "The priority of Tx channel 0. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH0": {
+              "description": "DMA_OUT_PERI_SEL_CH0_REG.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH0": {
+                    "description": "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH1": {
+              "description": "DMA_IN_CONF0_CH1_REG.",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH1": {
+                    "description": "This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH1": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH1": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH1": {
+              "description": "DMA_IN_CONF1_CH1_REG.",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH1": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH1": {
+              "description": "DMA_INFIFO_STATUS_CH1_REG.",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH1": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH1": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH1": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH1": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH1": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH1": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH1": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH1": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH1": {
+              "description": "DMA_IN_POP_CH1_REG.",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH1": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH1": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH1": {
+              "description": "DMA_IN_LINK_CH1_REG.",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH1": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH1": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH1": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH1": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH1": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH1": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH1": {
+              "description": "DMA_IN_STATE_CH1_REG.",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH1": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH1": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH1": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH1": {
+              "description": "DMA_IN_DSCR_CH1_REG.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH1": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH1": {
+              "description": "DMA_IN_DSCR_BF0_CH1_REG.",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH1": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH1": {
+              "description": "DMA_IN_DSCR_BF1_CH1_REG.",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH1": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH1": {
+              "description": "DMA_IN_PRI_CH1_REG.",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH1": {
+                    "description": "The priority of Rx channel 1. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH1": {
+              "description": "DMA_IN_PERI_SEL_CH1_REG.",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH1": {
+                    "description": "This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH1": {
+              "description": "DMA_OUT_CONF0_CH1_REG.",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH1": {
+                    "description": "This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH1": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH1": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH1": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH1": {
+              "description": "DMA_OUT_CONF1_CH1_REG.",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH1": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH1": {
+              "description": "DMA_OUTFIFO_STATUS_CH1_REG.",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH1": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH1": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH1": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH1": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH1": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH1": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH1": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH1": {
+              "description": "DMA_OUT_PUSH_CH1_REG.",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH1": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH1": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH1": {
+              "description": "DMA_OUT_LINK_CH1_REG.",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH1": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH1": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH1": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH1": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH1": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH1": {
+              "description": "DMA_OUT_STATE_CH1_REG.",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH1": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH1": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH1_REG.",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH1": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH1": {
+              "description": "DMA_OUT_DSCR_CH1_REG.",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH1": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH1": {
+              "description": "DMA_OUT_DSCR_BF0_CH1_REG.",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH1": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH1": {
+              "description": "DMA_OUT_DSCR_BF1_CH1_REG.",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH1": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH1": {
+              "description": "DMA_OUT_PRI_CH1_REG.",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH1": {
+                    "description": "The priority of Tx channel 1. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH1": {
+              "description": "DMA_OUT_PERI_SEL_CH1_REG.",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH1": {
+                    "description": "This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH2": {
+              "description": "DMA_IN_CONF0_CH2_REG.",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH2": {
+                    "description": "This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH2": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH2": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH2": {
+              "description": "DMA_IN_CONF1_CH2_REG.",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH2": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH2": {
+              "description": "DMA_INFIFO_STATUS_CH2_REG.",
+              "offset": 504,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH2": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH2": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH2": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH2": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH2": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH2": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH2": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH2": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH2": {
+              "description": "DMA_IN_POP_CH2_REG.",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH2": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH2": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH2": {
+              "description": "DMA_IN_LINK_CH2_REG.",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH2": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH2": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH2": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH2": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH2": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH2": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH2": {
+              "description": "DMA_IN_STATE_CH2_REG.",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH2": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH2": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH2": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH2": {
+              "description": "DMA_IN_DSCR_CH2_REG.",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH2": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH2": {
+              "description": "DMA_IN_DSCR_BF0_CH2_REG.",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH2": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH2": {
+              "description": "DMA_IN_DSCR_BF1_CH2_REG.",
+              "offset": 536,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH2": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH2": {
+              "description": "DMA_IN_PRI_CH2_REG.",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH2": {
+                    "description": "The priority of Rx channel 2. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH2": {
+              "description": "DMA_IN_PERI_SEL_CH2_REG.",
+              "offset": 544,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH2": {
+                    "description": "This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH2": {
+              "description": "DMA_OUT_CONF0_CH2_REG.",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH2": {
+                    "description": "This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH2": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH2": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH2": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH2": {
+              "description": "DMA_OUT_CONF1_CH2_REG.",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH2": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH2": {
+              "description": "DMA_OUTFIFO_STATUS_CH2_REG.",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH2": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH2": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH2": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH2": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH2": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH2": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH2": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH2": {
+              "description": "DMA_OUT_PUSH_CH2_REG.",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH2": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH2": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH2": {
+              "description": "DMA_OUT_LINK_CH2_REG.",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH2": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH2": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH2": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH2": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH2": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH2": {
+              "description": "DMA_OUT_STATE_CH2_REG.",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH2": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH2": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH2_REG.",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH2": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH2": {
+              "description": "DMA_OUT_DSCR_CH2_REG.",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH2": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH2": {
+              "description": "DMA_OUT_DSCR_BF0_CH2_REG.",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH2": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH2": {
+              "description": "DMA_OUT_DSCR_BF1_CH2_REG.",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH2": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH2": {
+              "description": "DMA_OUT_PRI_CH2_REG.",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH2": {
+                    "description": "The priority of Tx channel 2. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH2": {
+              "description": "DMA_OUT_PERI_SEL_CH2_REG.",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH2": {
+                    "description": "This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DS": {
+        "description": "Digital Signature",
+        "children": {
+          "registers": {
+            "Y_MEM": {
+              "description": "memory that stores Y",
+              "offset": 0,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_MEM": {
+              "description": "memory that stores M",
+              "offset": 512,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "RB_MEM": {
+              "description": "memory that stores Rb",
+              "offset": 1024,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "BOX_MEM": {
+              "description": "memory that stores BOX",
+              "offset": 1536,
+              "size": 8,
+              "count": 48,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "X_MEM": {
+              "description": "memory that stores X",
+              "offset": 2048,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Z_MEM": {
+              "description": "memory that stores Z",
+              "offset": 2560,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SET_START": {
+              "description": "DS start control register",
+              "offset": 3584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START": {
+                    "description": "set this bit to start DS operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_CONTINUE": {
+              "description": "DS continue control register",
+              "offset": 3588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_CONTINUE": {
+                    "description": "set this bit to continue DS operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_FINISH": {
+              "description": "DS finish control register",
+              "offset": 3592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_FINISH": {
+                    "description": "Set this bit to finish DS process.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_BUSY": {
+              "description": "DS query busy register",
+              "offset": 3596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_BUSY": {
+                    "description": "digital signature state. 1'b0: idle, 1'b1: busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_KEY_WRONG": {
+              "description": "DS query key-wrong counter register",
+              "offset": 3600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_KEY_WRONG": {
+                    "description": "digital signature key wrong counter",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_CHECK": {
+              "description": "DS query check result register",
+              "offset": 3604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MD_ERROR": {
+                    "description": "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PADDING_BAD": {
+                    "description": "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "DS version control register",
+              "offset": 3616,
+              "size": 32,
+              "reset_value": 538969624,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "ds version information",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EFUSE": {
+        "description": "eFuse Controller",
+        "children": {
+          "registers": {
+            "PGM_DATA0": {
+              "description": "Register 0 that stores data to be programmed.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_0": {
+                    "description": "The content of the 0th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA1": {
+              "description": "Register 1 that stores data to be programmed.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_1": {
+                    "description": "The content of the 1st 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA2": {
+              "description": "Register 2 that stores data to be programmed.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_2": {
+                    "description": "The content of the 2nd 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA3": {
+              "description": "Register 3 that stores data to be programmed.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_3": {
+                    "description": "The content of the 3rd 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA4": {
+              "description": "Register 4 that stores data to be programmed.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_4": {
+                    "description": "The content of the 4th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA5": {
+              "description": "Register 5 that stores data to be programmed.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_5": {
+                    "description": "The content of the 5th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA6": {
+              "description": "Register 6 that stores data to be programmed.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_6": {
+                    "description": "The content of the 6th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA7": {
+              "description": "Register 7 that stores data to be programmed.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_7": {
+                    "description": "The content of the 7th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE0": {
+              "description": "Register 0 that stores the RS code to be programmed.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_0": {
+                    "description": "The content of the 0th 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE1": {
+              "description": "Register 1 that stores the RS code to be programmed.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_1": {
+                    "description": "The content of the 1st 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE2": {
+              "description": "Register 2 that stores the RS code to be programmed.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_2": {
+                    "description": "The content of the 2nd 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RD_WR_DIS": {
+              "description": "BLOCK0 data register 0.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_DIS": {
+                    "description": "Disable programming of individual eFuses.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA0": {
+              "description": "BLOCK0 data register 1.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RD_DIS": {
+                    "description": "Set this bit to disable reading from BlOCK4-10.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "DIS_RTC_RAM_BOOT": {
+                    "description": "Set this bit to disable boot from RTC RAM.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_ICACHE": {
+                    "description": "Set this bit to disable Icache.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_JTAG": {
+                    "description": "Set this bit to disable function of usb switch to jtag in module of usb device.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_ICACHE": {
+                    "description": "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DEVICE": {
+                    "description": "Set this bit to disable usb device.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_FORCE_DOWNLOAD": {
+                    "description": "Set this bit to disable the function that forces chip into download mode.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED6": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_CAN": {
+                    "description": "Set this bit to disable CAN function.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_SEL_ENABLE": {
+                    "description": "Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOFT_DIS_JTAG": {
+                    "description": "Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DIS_PAD_JTAG": {
+                    "description": "Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_MANUAL_ENCRYPT": {
+                    "description": "Set this bit to disable flash encryption when in download boot modes.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_DREFH": {
+                    "description": "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.",
+                    "offset": 21,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_DREFL": {
+                    "description": "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.",
+                    "offset": 23,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_EXCHG_PINS": {
+                    "description": "Set this bit to exchange USB D+ and D- pins.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VDD_SPI_AS_GPIO": {
+                    "description": "Set this bit to vdd spi pin function as gpio.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTLC_GPIO_ENABLE": {
+                    "description": "Enable btlc gpio.",
+                    "offset": 27,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "POWERGLITCH_EN": {
+                    "description": "Set this bit to enable power glitch function.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POWER_GLITCH_DSENSE": {
+                    "description": "Sample delay configuration of power glitch.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA1": {
+              "description": "BLOCK0 data register 2.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED2": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "WDT_DELAY_SEL": {
+                    "description": "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.",
+                    "offset": 16,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SPI_BOOT_CRYPT_CNT": {
+                    "description": "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.",
+                    "offset": 18,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE0": {
+                    "description": "Set this bit to enable revoking first secure boot key.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE1": {
+                    "description": "Set this bit to enable revoking second secure boot key.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE2": {
+                    "description": "Set this bit to enable revoking third secure boot key.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_0": {
+                    "description": "Purpose of Key0.",
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_1": {
+                    "description": "Purpose of Key1.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA2": {
+              "description": "BLOCK0 data register 3.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_PURPOSE_2": {
+                    "description": "Purpose of Key2.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_3": {
+                    "description": "Purpose of Key3.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_4": {
+                    "description": "Purpose of Key4.",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_5": {
+                    "description": "Purpose of Key5.",
+                    "offset": 12,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED3": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_EN": {
+                    "description": "Set this bit to enable secure boot.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_AGGRESSIVE_REVOKE": {
+                    "description": "Set this bit to enable revoking aggressive secure boot.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED0": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 22,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "FLASH_TPUW": {
+                    "description": "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA3": {
+              "description": "BLOCK0 data register 4.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIS_DOWNLOAD_MODE": {
+                    "description": "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_LEGACY_SPI_BOOT": {
+                    "description": "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CHANNEL": {
+                    "description": "Selectes the default UART print channel. 0: UART0. 1: UART1.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_MODE": {
+                    "description": "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DOWNLOAD_MODE": {
+                    "description": "Set this bit to disable UART download mode through USB.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLE_SECURITY_DOWNLOAD": {
+                    "description": "Set this bit to enable secure UART download mode.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CONTROL": {
+                    "description": "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PIN_POWER_SELECTION": {
+                    "description": "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_TYPE": {
+                    "description": "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_PAGE_SIZE": {
+                    "description": "Set Flash page size.",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_EN": {
+                    "description": "Set 1 to enable ECC for flash boot.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FORCE_SEND_RESUME": {
+                    "description": "Set this bit to force ROM code to send a resume command during SPI boot.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_VERSION": {
+                    "description": "Secure version (used by ESP-IDF anti-rollback feature).",
+                    "offset": 14,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED1": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA4": {
+              "description": "BLOCK0 data register 5.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED4": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_0": {
+              "description": "BLOCK1 data register 0.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_0": {
+                    "description": "Stores the low 32 bits of MAC address.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_1": {
+              "description": "BLOCK1 data register 1.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_1": {
+                    "description": "Stores the high 16 bits of MAC address.",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "SPI_PAD_CONF_0": {
+                    "description": "Stores the zeroth part of SPI_PAD_CONF.",
+                    "offset": 16,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_2": {
+              "description": "BLOCK1 data register 2.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_PAD_CONF_1": {
+                    "description": "Stores the first part of SPI_PAD_CONF.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_3": {
+              "description": "BLOCK1 data register 3.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_PAD_CONF_2": {
+                    "description": "Stores the second part of SPI_PAD_CONF.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "SYS_DATA_PART0_0": {
+                    "description": "Stores the fist 14 bits of the zeroth part of system data.",
+                    "offset": 18,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_4": {
+              "description": "BLOCK1 data register 4.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART0_1": {
+                    "description": "Stores the fist 32 bits of the zeroth part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_5": {
+              "description": "BLOCK1 data register 5.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART0_2": {
+                    "description": "Stores the second 32 bits of the zeroth part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA0": {
+              "description": "Register 0 of BLOCK2 (system).",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_0": {
+                    "description": "Stores the zeroth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA1": {
+              "description": "Register 1 of BLOCK2 (system).",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_1": {
+                    "description": "Stores the first 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA2": {
+              "description": "Register 2 of BLOCK2 (system).",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_2": {
+                    "description": "Stores the second 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA3": {
+              "description": "Register 3 of BLOCK2 (system).",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_3": {
+                    "description": "Stores the third 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA4": {
+              "description": "Register 4 of BLOCK2 (system).",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_4": {
+                    "description": "Stores the fourth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA5": {
+              "description": "Register 5 of BLOCK2 (system).",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_5": {
+                    "description": "Stores the fifth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA6": {
+              "description": "Register 6 of BLOCK2 (system).",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_6": {
+                    "description": "Stores the sixth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA7": {
+              "description": "Register 7 of BLOCK2 (system).",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_7": {
+                    "description": "Stores the seventh 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA0": {
+              "description": "Register 0 of BLOCK3 (user).",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA0": {
+                    "description": "Stores the zeroth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA1": {
+              "description": "Register 1 of BLOCK3 (user).",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA1": {
+                    "description": "Stores the first 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA2": {
+              "description": "Register 2 of BLOCK3 (user).",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA2": {
+                    "description": "Stores the second 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA3": {
+              "description": "Register 3 of BLOCK3 (user).",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA3": {
+                    "description": "Stores the third 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA4": {
+              "description": "Register 4 of BLOCK3 (user).",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA4": {
+                    "description": "Stores the fourth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA5": {
+              "description": "Register 5 of BLOCK3 (user).",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA5": {
+                    "description": "Stores the fifth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA6": {
+              "description": "Register 6 of BLOCK3 (user).",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA6": {
+                    "description": "Stores the sixth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA7": {
+              "description": "Register 7 of BLOCK3 (user).",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA7": {
+                    "description": "Stores the seventh 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA0": {
+              "description": "Register 0 of BLOCK4 (KEY0).",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA1": {
+              "description": "Register 1 of BLOCK4 (KEY0).",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA1": {
+                    "description": "Stores the first 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA2": {
+              "description": "Register 2 of BLOCK4 (KEY0).",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA2": {
+                    "description": "Stores the second 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA3": {
+              "description": "Register 3 of BLOCK4 (KEY0).",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA3": {
+                    "description": "Stores the third 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA4": {
+              "description": "Register 4 of BLOCK4 (KEY0).",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA5": {
+              "description": "Register 5 of BLOCK4 (KEY0).",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA6": {
+              "description": "Register 6 of BLOCK4 (KEY0).",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA7": {
+              "description": "Register 7 of BLOCK4 (KEY0).",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA0": {
+              "description": "Register 0 of BLOCK5 (KEY1).",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA1": {
+              "description": "Register 1 of BLOCK5 (KEY1).",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA1": {
+                    "description": "Stores the first 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA2": {
+              "description": "Register 2 of BLOCK5 (KEY1).",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA2": {
+                    "description": "Stores the second 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA3": {
+              "description": "Register 3 of BLOCK5 (KEY1).",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA3": {
+                    "description": "Stores the third 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA4": {
+              "description": "Register 4 of BLOCK5 (KEY1).",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA5": {
+              "description": "Register 5 of BLOCK5 (KEY1).",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA6": {
+              "description": "Register 6 of BLOCK5 (KEY1).",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA7": {
+              "description": "Register 7 of BLOCK5 (KEY1).",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA0": {
+              "description": "Register 0 of BLOCK6 (KEY2).",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA1": {
+              "description": "Register 1 of BLOCK6 (KEY2).",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA1": {
+                    "description": "Stores the first 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA2": {
+              "description": "Register 2 of BLOCK6 (KEY2).",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA2": {
+                    "description": "Stores the second 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA3": {
+              "description": "Register 3 of BLOCK6 (KEY2).",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA3": {
+                    "description": "Stores the third 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA4": {
+              "description": "Register 4 of BLOCK6 (KEY2).",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA5": {
+              "description": "Register 5 of BLOCK6 (KEY2).",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA6": {
+              "description": "Register 6 of BLOCK6 (KEY2).",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA7": {
+              "description": "Register 7 of BLOCK6 (KEY2).",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA0": {
+              "description": "Register 0 of BLOCK7 (KEY3).",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA1": {
+              "description": "Register 1 of BLOCK7 (KEY3).",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA1": {
+                    "description": "Stores the first 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA2": {
+              "description": "Register 2 of BLOCK7 (KEY3).",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA2": {
+                    "description": "Stores the second 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA3": {
+              "description": "Register 3 of BLOCK7 (KEY3).",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA3": {
+                    "description": "Stores the third 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA4": {
+              "description": "Register 4 of BLOCK7 (KEY3).",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA5": {
+              "description": "Register 5 of BLOCK7 (KEY3).",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA6": {
+              "description": "Register 6 of BLOCK7 (KEY3).",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA7": {
+              "description": "Register 7 of BLOCK7 (KEY3).",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA0": {
+              "description": "Register 0 of BLOCK8 (KEY4).",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA1": {
+              "description": "Register 1 of BLOCK8 (KEY4).",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA1": {
+                    "description": "Stores the first 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA2": {
+              "description": "Register 2 of BLOCK8 (KEY4).",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA2": {
+                    "description": "Stores the second 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA3": {
+              "description": "Register 3 of BLOCK8 (KEY4).",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA3": {
+                    "description": "Stores the third 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA4": {
+              "description": "Register 4 of BLOCK8 (KEY4).",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA5": {
+              "description": "Register 5 of BLOCK8 (KEY4).",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA6": {
+              "description": "Register 6 of BLOCK8 (KEY4).",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA7": {
+              "description": "Register 7 of BLOCK8 (KEY4).",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA0": {
+              "description": "Register 0 of BLOCK9 (KEY5).",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA1": {
+              "description": "Register 1 of BLOCK9 (KEY5).",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA1": {
+                    "description": "Stores the first 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA2": {
+              "description": "Register 2 of BLOCK9 (KEY5).",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA2": {
+                    "description": "Stores the second 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA3": {
+              "description": "Register 3 of BLOCK9 (KEY5).",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA3": {
+                    "description": "Stores the third 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA4": {
+              "description": "Register 4 of BLOCK9 (KEY5).",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA5": {
+              "description": "Register 5 of BLOCK9 (KEY5).",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA6": {
+              "description": "Register 6 of BLOCK9 (KEY5).",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA7": {
+              "description": "Register 7 of BLOCK9 (KEY5).",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA0": {
+              "description": "Register 0 of BLOCK10 (system).",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_0": {
+                    "description": "Stores the 0th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA1": {
+              "description": "Register 1 of BLOCK9 (KEY5).",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_1": {
+                    "description": "Stores the 1st 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA2": {
+              "description": "Register 2 of BLOCK10 (system).",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_2": {
+                    "description": "Stores the 2nd 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA3": {
+              "description": "Register 3 of BLOCK10 (system).",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_3": {
+                    "description": "Stores the 3rd 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA4": {
+              "description": "Register 4 of BLOCK10 (system).",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_4": {
+                    "description": "Stores the 4th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA5": {
+              "description": "Register 5 of BLOCK10 (system).",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_5": {
+                    "description": "Stores the 5th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA6": {
+              "description": "Register 6 of BLOCK10 (system).",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_6": {
+                    "description": "Stores the 6th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA7": {
+              "description": "Register 7 of BLOCK10 (system).",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_7": {
+                    "description": "Stores the 7th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR0": {
+              "description": "Programming error record register 0 of BLOCK0.",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RD_DIS_ERR": {
+                    "description": "If any bit in RD_DIS is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "DIS_RTC_RAM_BOOT_ERR": {
+                    "description": "If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_ICACHE_ERR": {
+                    "description": "If DIS_ICACHE is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_JTAG_ERR": {
+                    "description": "If DIS_USB_JTAG is 1, then it indicates a programming error.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_ICACHE_ERR": {
+                    "description": "If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DEVICE_ERR": {
+                    "description": "If DIS_USB_DEVICE is 1, then it indicates a programming error.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_FORCE_DOWNLOAD_ERR": {
+                    "description": "If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED6_ERR": {
+                    "description": "Reserved.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_CAN_ERR": {
+                    "description": "If DIS_CAN is 1, then it indicates a programming error.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_SEL_ENABLE_ERR": {
+                    "description": "If JTAG_SEL_ENABLE is 1, then it indicates a programming error.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOFT_DIS_JTAG_ERR": {
+                    "description": "If SOFT_DIS_JTAG is 1, then it indicates a programming error.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DIS_PAD_JTAG_ERR": {
+                    "description": "If DIS_PAD_JTAG is 1, then it indicates a programming error.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR": {
+                    "description": "If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_DREFH_ERR": {
+                    "description": "If any bit in USB_DREFH is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_DREFL_ERR": {
+                    "description": "If any bit in USB_DREFL is 1, then it indicates a programming error.",
+                    "offset": 23,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_EXCHG_PINS_ERR": {
+                    "description": "If USB_EXCHG_PINS is 1, then it indicates a programming error.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VDD_SPI_AS_GPIO_ERR": {
+                    "description": "If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTLC_GPIO_ENABLE_ERR": {
+                    "description": "If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.",
+                    "offset": 27,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "POWERGLITCH_EN_ERR": {
+                    "description": "If POWERGLITCH_EN is 1, then it indicates a programming error.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POWER_GLITCH_DSENSE_ERR": {
+                    "description": "If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR1": {
+              "description": "Programming error record register 1 of BLOCK0.",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED2_ERR": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "WDT_DELAY_SEL_ERR": {
+                    "description": "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.",
+                    "offset": 16,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SPI_BOOT_CRYPT_CNT_ERR": {
+                    "description": "If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.",
+                    "offset": 18,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE0_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE1_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE2_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_0_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.",
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_1_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR2": {
+              "description": "Programming error record register 2 of BLOCK0.",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_PURPOSE_2_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_3_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_4_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_5_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED3_ERR": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_EN_ERR": {
+                    "description": "If SECURE_BOOT_EN is 1, then it indicates a programming error.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_AGGRESSIVE_REVOKE_ERR": {
+                    "description": "If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED0_ERR": {
+                    "description": "Reserved.",
+                    "offset": 22,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "FLASH_TPUW_ERR": {
+                    "description": "If any bit in FLASH_TPUM is 1, then it indicates a programming error.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR3": {
+              "description": "Programming error record register 3 of BLOCK0.",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIS_DOWNLOAD_MODE_ERR": {
+                    "description": "If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_LEGACY_SPI_BOOT_ERR": {
+                    "description": "If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CHANNEL_ERR": {
+                    "description": "If UART_PRINT_CHANNEL is 1, then it indicates a programming error.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_MODE_ERR": {
+                    "description": "If FLASH_ECC_MODE is 1, then it indicates a programming error.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DOWNLOAD_MODE_ERR": {
+                    "description": "If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLE_SECURITY_DOWNLOAD_ERR": {
+                    "description": "If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CONTROL_ERR": {
+                    "description": "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PIN_POWER_SELECTION_ERR": {
+                    "description": "If PIN_POWER_SELECTION is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_TYPE_ERR": {
+                    "description": "If FLASH_TYPE is 1, then it indicates a programming error.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_PAGE_SIZE_ERR": {
+                    "description": "If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_EN_ERR": {
+                    "description": "If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FORCE_SEND_RESUME_ERR": {
+                    "description": "If FORCE_SEND_RESUME is 1, then it indicates a programming error.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_VERSION_ERR": {
+                    "description": "If any bit in SECURE_VERSION is 1, then it indicates a programming error.",
+                    "offset": 14,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED1_ERR": {
+                    "description": "Reserved.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR4": {
+              "description": "Programming error record register 4 of BLOCK0.",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED4_ERR": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_RS_ERR0": {
+              "description": "Programming error record register 0 of BLOCK1-10.",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_SPI_8M_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MAC_SPI_8M_FAIL": {
+                    "description": "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SYS_PART1_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SYS_PART1_FAIL": {
+                    "description": "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USR_DATA_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 8,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "USR_DATA_FAIL": {
+                    "description": "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY0_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 12,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY0_FAIL": {
+                    "description": "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY1_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY1_FAIL": {
+                    "description": "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY2_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY2_FAIL": {
+                    "description": "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY3_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY3_FAIL": {
+                    "description": "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY4_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 28,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY4_FAIL": {
+                    "description": "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_RS_ERR1": {
+              "description": "Programming error record register 1 of BLOCK1-10.",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY5_FAIL": {
+                    "description": "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SYS_PART2_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SYS_PART2_FAIL": {
+                    "description": "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLK": {
+              "description": "eFuse clcok configuration register.",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_MEM_FORCE_PD": {
+                    "description": "Set this bit to force eFuse SRAM into power-saving mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_CLK_FORCE_ON": {
+                    "description": "Set this bit and force to activate clock signal of eFuse SRAM.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EFUSE_MEM_FORCE_PU": {
+                    "description": "Set this bit to force eFuse SRAM into working mode.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Set this bit and force to enable clock signal of eFuse memory.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CONF": {
+              "description": "eFuse operation mode configuraiton register;",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OP_CODE": {
+                    "description": "0x5A5A: Operate programming command 0x5AA5: Operate read command.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "eFuse status register.",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Indicates the state of the eFuse state machine.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "OTP_LOAD_SW": {
+                    "description": "The value of OTP_LOAD_SW.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_VDDQ_C_SYNC2": {
+                    "description": "The value of OTP_VDDQ_C_SYNC2.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_STROBE_SW": {
+                    "description": "The value of OTP_STROBE_SW.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_CSB_SW": {
+                    "description": "The value of OTP_CSB_SW.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_PGENB_SW": {
+                    "description": "The value of OTP_PGENB_SW.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_VDDQ_IS_SW": {
+                    "description": "The value of OTP_VDDQ_IS_SW.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "REPEAT_ERR_CNT": {
+                    "description": "Indicates the number of error bits during programming BLOCK0.",
+                    "offset": 10,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "eFuse command register.",
+              "offset": 468,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_CMD": {
+                    "description": "Set this bit to send read command.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_CMD": {
+                    "description": "Set this bit to send programming command.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BLK_NUM": {
+                    "description": "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "eFuse raw interrupt register.",
+              "offset": 472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_RAW": {
+                    "description": "The raw bit signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_DONE_INT_RAW": {
+                    "description": "The raw bit signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "eFuse interrupt status register.",
+              "offset": 476,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_ST": {
+                    "description": "The status signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PGM_DONE_INT_ST": {
+                    "description": "The status signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "eFuse interrupt enable register.",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_ENA": {
+                    "description": "The enable signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_DONE_INT_ENA": {
+                    "description": "The enable signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "eFuse interrupt clear register.",
+              "offset": 484,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_CLR": {
+                    "description": "The clear signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PGM_DONE_INT_CLR": {
+                    "description": "The clear signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DAC_CONF": {
+              "description": "Controls the eFuse programming voltage.",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 130588,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC_CLK_DIV": {
+                    "description": "Controls the division factor of the rising clock of the programming voltage.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DAC_CLK_PAD_SEL": {
+                    "description": "Don't care.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DAC_NUM": {
+                    "description": "Controls the rising period of the programming voltage.",
+                    "offset": 9,
+                    "size": 8
+                  },
+                  "OE_CLR": {
+                    "description": "Reduces the power supply of the programming voltage.",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RD_TIM_CONF": {
+              "description": "Configures read timing parameters.",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 301989888,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_INIT_NUM": {
+                    "description": "Configures the initial read time of eFuse.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WR_TIM_CONF1": {
+              "description": "Configurarion register 1 of eFuse programming timing parameters.",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 2654208,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_ON_NUM": {
+                    "description": "Configures the power up time for VDDQ.",
+                    "offset": 8,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "WR_TIM_CONF2": {
+              "description": "Configurarion register 2 of eFuse programming timing parameters.",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_OFF_NUM": {
+                    "description": "Configures the power outage time for VDDQ.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "eFuse version register.",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33583616,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Stores eFuse version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTMEM": {
+        "description": "External Memory",
+        "children": {
+          "registers": {
+            "ICACHE_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_ENABLE": {
+                    "description": "The bit is used to activate the data cache. 0: disable, 1: enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_CTRL1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SHUT_IBUS": {
+                    "description": "The bit is used to disable core0 ibus, 0: enable, 1: disable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_SHUT_DBUS": {
+                    "description": "The bit is used to disable core1 ibus, 0: enable, 1: disable",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_TAG_POWER_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_TAG_MEM_FORCE_ON": {
+                    "description": "The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_TAG_MEM_FORCE_PD": {
+                    "description": "The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_TAG_MEM_FORCE_PU": {
+                    "description": "The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT0_EN": {
+                    "description": "The bit is used to enable the first section of prelock function.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOCK_SCT1_EN": {
+                    "description": "The bit is used to enable the second section of prelock function.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT0_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT0_ADDR": {
+                    "description": "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT1_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT1_ADDR": {
+                    "description": "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT1_SIZE": {
+                    "description": "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "ICACHE_PRELOCK_SCT0_SIZE": {
+                    "description": "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_ENA": {
+                    "description": "The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_UNLOCK_ENA": {
+                    "description": "The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_LOCK_DONE": {
+                    "description": "The bit is used to indicate unlock/lock operation is finished.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_SIZE": {
+                    "description": "The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_INVALIDATE_ENA": {
+                    "description": "The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_SYNC_DONE": {
+                    "description": "The bit is used to indicate invalidate operation is finished.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_SIZE": {
+                    "description": "The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.",
+                    "offset": 0,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_ENA": {
+                    "description": "The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_DONE": {
+                    "description": "The bit is used to indicate preload operation is finished.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_ORDER": {
+                    "description": "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_SIZE": {
+                    "description": "The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_ENA": {
+                    "description": "The bits are used to enable the first section for autoload operation.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_SCT1_ENA": {
+                    "description": "The bits are used to enable the second section for autoload operation.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_ENA": {
+                    "description": "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_DONE": {
+                    "description": "The bit is used to indicate autoload operation is finished.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_AUTOLOAD_ORDER": {
+                    "description": "The bits are used to configure the direction of autoload. 1: descending, 0: ascending.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_RQST": {
+                    "description": "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.",
+                    "offset": 5,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT0_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_ADDR": {
+                    "description": "The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT0_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_SIZE": {
+                    "description": "The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
+                    "offset": 0,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT1_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT1_ADDR": {
+                    "description": "The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT1_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT1_SIZE": {
+                    "description": "The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
+                    "offset": 0,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "IBUS_TO_FLASH_START_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1107296256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_TO_FLASH_START_VADDR": {
+                    "description": "The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IBUS_TO_FLASH_END_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1115684863,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_TO_FLASH_END_VADDR": {
+                    "description": "The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBUS_TO_FLASH_START_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1006632960,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_TO_FLASH_START_VADDR": {
+                    "description": "The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBUS_TO_FLASH_END_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 1015021567,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_TO_FLASH_END_VADDR": {
+                    "description": "The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CACHE_ACS_CNT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_CNT_CLR": {
+                    "description": "The bit is used to clear ibus counter.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DBUS_ACS_CNT_CLR": {
+                    "description": "The bit is used to clear dbus counter.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "IBUS_ACS_MISS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_MISS_CNT": {
+                    "description": "The bits are used to count the number of the cache miss caused by ibus access flash.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IBUS_ACS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_CNT": {
+                    "description": "The bits are used to count the number of ibus access flash through icache.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DBUS_ACS_FLASH_MISS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_ACS_FLASH_MISS_CNT": {
+                    "description": "The bits are used to count the number of the cache miss caused by dbus access flash.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DBUS_ACS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_ACS_CNT": {
+                    "description": "The bits are used to count the number of dbus access flash through icache.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MMU_ENTRY_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IBUS_CNT_OVF_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by ibus counter overflow.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DBUS_CNT_OVF_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by dbus counter overflow.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MMU_ENTRY_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IBUS_CNT_OVF_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by ibus counter overflow.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DBUS_CNT_OVF_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by dbus counter overflow.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMU_ENTRY_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IBUS_ACS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IBUS_ACS_MISS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBUS_ACS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBUS_ACS_FLASH_MISS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus access flash miss counter overflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE0_IBUS_WR_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE0_IBUS_REJECT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_ACS_MSK_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_REJECT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_WR_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_IBUS_WR_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_IBUS_REJECT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_ACS_MSK_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_REJECT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_WR_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_WR_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_REJECT_ST": {
+                    "description": "The bit is used to indicate interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_ACS_MSK_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_REJECT_ST": {
+                    "description": "The bit is used to indicate interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_WR_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_DBUS_REJECT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_DBUS_ATTR": {
+                    "description": "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_WORLD": {
+                    "description": "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_DBUS_REJECT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_DBUS_VADDR": {
+                    "description": "The bits are used to indicate the virtual address of CPU access dbus when authentication fail.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_IBUS_REJECT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ATTR": {
+                    "description": "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_WORLD": {
+                    "description": "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_IBUS_REJECT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_VADDR": {
+                    "description": "The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_FAULT_CONTENT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_FAULT_CONTENT": {
+                    "description": "The bits are used to indicate the content of mmu entry which cause mmu fault..",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "CACHE_MMU_FAULT_CODE": {
+                    "description": "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.",
+                    "offset": 10,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_FAULT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_FAULT_VADDR": {
+                    "description": "The bits are used to indicate the virtual address which cause mmu fault..",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_WRAP_AROUND_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_FLASH_WRAP_AROUND": {
+                    "description": "The bit is used to enable wrap around mode when read data from flash.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_POWER_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_MEM_FORCE_ON": {
+                    "description": "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_MMU_MEM_FORCE_PD": {
+                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_MMU_MEM_FORCE_PU": {
+                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_STATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_STATE": {
+                    "description": "The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RECORD_DISABLE_DB_ENCRYPT": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RECORD_DISABLE_G0CB_DECRYPT": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON": {
+              "description": "This description will be updated in the near future.",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_FORCE_ON_MANUAL_CRYPT": {
+                    "description": "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CLK_FORCE_ON_AUTO_CRYPT": {
+                    "description": "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLK_FORCE_ON_CRYPT": {
+                    "description": "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_PRELOAD_INT_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_INT_ST": {
+                    "description": "The bit is used to indicate the interrupt by  icache pre-load done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt by  icache pre-load done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_INT_CLR": {
+                    "description": "The bit is used to clear the interrupt by  icache pre-load done.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_SYNC_INT_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_INT_ST": {
+                    "description": "The bit is used to indicate the interrupt by  icache sync done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_SYNC_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt by  icache sync done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_SYNC_INT_CLR": {
+                    "description": "The bit is used to clear the interrupt by  icache sync done.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_OWNER": {
+              "description": "This description will be updated in the near future.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_OWNER": {
+                    "description": "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CACHE_CONF_MISC": {
+              "description": "This description will be updated in the near future.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT": {
+                    "description": "The bit is used to disable checking mmu entry fault by preload operation.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT": {
+                    "description": "The bit is used to disable checking mmu entry fault by sync operation.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_TRACE_ENA": {
+                    "description": "The bit is used to enable cache trace function.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_FREEZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENA": {
+                    "description": "The bit is used to enable icache freeze mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MODE": {
+                    "description": "The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DONE": {
+                    "description": "The bit is used to indicate icache freeze success",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_ATOMIC_OPERATE_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_ATOMIC_OPERATE_ENA": {
+                    "description": "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_REQUEST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BYPASS": {
+                    "description": "The bit is used to disable request recording which could cause performance issue",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_LOCK": {
+              "description": "This description will be updated in the near future.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_LOCK": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY0": {
+              "description": "This description will be updated in the near future.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY0": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY1": {
+                    "description": "The bit is used to configure the ibus permission control section boundary1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY2": {
+              "description": "This description will be updated in the near future.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY2": {
+                    "description": "The bit is used to configure the ibus permission control section boundary2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_ATTR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_SCT1_ATTR": {
+                    "description": "The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "IBUS_PMS_SCT2_ATTR": {
+                    "description": "The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
+                    "offset": 4,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_LOCK": {
+              "description": "This description will be updated in the near future.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_LOCK": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY0": {
+              "description": "This description will be updated in the near future.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY0": {
+                    "description": "The bit is used to configure the dbus permission control section boundary0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY1": {
+                    "description": "The bit is used to configure the dbus permission control section boundary1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY2": {
+              "description": "This description will be updated in the near future.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY2": {
+                    "description": "The bit is used to configure the dbus permission control section boundary2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_ATTR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_SCT1_ATTR": {
+                    "description": "The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DBUS_PMS_SCT2_ATTR": {
+                    "description": "The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1",
+                    "offset": 2,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "clock gate enable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REG_DATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "version information",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIO": {
+        "description": "General Purpose Input/Output",
+        "children": {
+          "registers": {
+            "BT_SELECT": {
+              "description": "GPIO bit select register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_SEL": {
+                    "description": "GPIO bit select register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OUT": {
+              "description": "GPIO output register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA_ORIG": {
+                    "description": "GPIO output register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "OUT_W1TS": {
+              "description": "GPIO output set register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_W1TS": {
+                    "description": "GPIO output set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "OUT_W1TC": {
+              "description": "GPIO output clear register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_W1TC": {
+                    "description": "GPIO output clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SDIO_SELECT": {
+              "description": "GPIO sdio select register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_SEL": {
+                    "description": "GPIO sdio select register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "GPIO output enable register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "GPIO output enable register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "ENABLE_W1TS": {
+              "description": "GPIO output enable set register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_W1TS": {
+                    "description": "GPIO output enable set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "ENABLE_W1TC": {
+              "description": "GPIO output enable clear register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_W1TC": {
+                    "description": "GPIO output enable clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STRAP": {
+              "description": "pad strapping register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRAPPING": {
+                    "description": "pad strapping register",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN": {
+              "description": "GPIO input register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA_NEXT": {
+                    "description": "GPIO input register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "GPIO interrupt status register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT": {
+                    "description": "GPIO interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "STATUS_W1TS": {
+              "description": "GPIO interrupt status set register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_W1TS": {
+                    "description": "GPIO interrupt status set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATUS_W1TC": {
+              "description": "GPIO interrupt status clear register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_W1TC": {
+                    "description": "GPIO interrupt status clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "PCPU_INT": {
+              "description": "GPIO PRO_CPU interrupt status register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROCPU_INT": {
+                    "description": "GPIO PRO_CPU interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PCPU_NMI_INT": {
+              "description": "GPIO PRO_CPU(not shielded) interrupt status register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROCPU_NMI_INT": {
+                    "description": "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CPUSDIO_INT": {
+              "description": "GPIO CPUSDIO interrupt status register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_INT": {
+                    "description": "GPIO CPUSDIO interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PIN": {
+              "description": "GPIO pin configuration register",
+              "offset": 116,
+              "size": 32,
+              "count": 26,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN_SYNC2_BYPASS": {
+                    "description": "set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PIN_PAD_DRIVER": {
+                    "description": "set this bit to select pad driver. 1:open-drain. :normal.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PIN_SYNC1_BYPASS": {
+                    "description": "set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "PIN_INT_TYPE": {
+                    "description": "set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level",
+                    "offset": 7,
+                    "size": 3
+                  },
+                  "PIN_WAKEUP_ENABLE": {
+                    "description": "set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PIN_CONFIG": {
+                    "description": "reserved",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "PIN_INT_ENA": {
+                    "description": "set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.",
+                    "offset": 13,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "STATUS_NEXT": {
+              "description": "GPIO interrupt source register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_INTERRUPT_NEXT": {
+                    "description": "GPIO interrupt source register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FUNC_IN_SEL_CFG": {
+              "description": "GPIO input function configuration register",
+              "offset": 340,
+              "size": 32,
+              "count": 128,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SEL": {
+                    "description": "set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "IN_INV_SEL": {
+                    "description": "set this bit to invert input signal. 1:invert. :not invert.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SEL": {
+                    "description": "set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FUNC_OUT_SEL_CFG": {
+              "description": "GPIO output function select register",
+              "offset": 1364,
+              "size": 32,
+              "count": 26,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_SEL": {
+                    "description": "The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "INV_SEL": {
+                    "description": "set this bit to invert output signal.1:invert.:not invert.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OEN_SEL": {
+                    "description": "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OEN_INV_SEL": {
+                    "description": "set this bit to invert output enable signal.1:invert.:not invert.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "GPIO clock gate register",
+              "offset": 1580,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "set this bit to enable GPIO clock gate",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REG_DATE": {
+              "description": "GPIO version register",
+              "offset": 1788,
+              "size": 32,
+              "reset_value": 33579312,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_DATE": {
+                    "description": "version register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOSD": {
+        "description": "Sigma-Delta Modulation",
+        "children": {
+          "registers": {
+            "SIGMADELTA": {
+              "description": "Duty Cycle Configure Register of SDM%s",
+              "offset": 0,
+              "size": 32,
+              "count": 4,
+              "reset_value": 65280,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SD0_IN": {
+                    "description": "This field is used to configure the duty cycle of sigma delta modulation output.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SD0_PRESCALE": {
+                    "description": "This field is used to set a divider value to divide APB clock.",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_CG": {
+              "description": "Clock Gating Configure Register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Clock enable bit of configuration registers for sigma delta modulation.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_MISC": {
+              "description": "MISC Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FUNCTION_CLK_EN": {
+                    "description": "Clock enable bit of sigma delta modulation.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI_SWAP": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_VERSION": {
+              "description": "Version Control Register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 33579568,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_SD_DATE": {
+                    "description": "Version control register.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "HMAC": {
+        "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
+        "children": {
+          "registers": {
+            "SET_START": {
+              "description": "Process control register 0.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START": {
+                    "description": "Start hmac operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_PURPOSE": {
+              "description": "Configure purpose.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PURPOSE_SET": {
+                    "description": "Set hmac parameter purpose.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_KEY": {
+              "description": "Configure key.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_SET": {
+                    "description": "Set hmac parameter key.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_FINISH": {
+              "description": "Finish initial configuration.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_PARA_END": {
+                    "description": "Finish hmac configuration.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_ONE": {
+              "description": "Process control register 1.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_ONE": {
+                    "description": "Call SHA to calculate one message block.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_ING": {
+              "description": "Process control register 2.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_ING": {
+                    "description": "Continue typical hmac.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_END": {
+              "description": "Process control register 3.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_END": {
+                    "description": "Start hardware padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_RESULT_FINISH": {
+              "description": "Process control register 4.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_RESULT_END": {
+                    "description": "After read result from upstream, then let hmac back to idle.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_INVALIDATE_JTAG": {
+              "description": "Invalidate register 0.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_INVALIDATE_JTAG": {
+                    "description": "Clear result from hmac downstream JTAG.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_INVALIDATE_DS": {
+              "description": "Invalidate register 1.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_INVALIDATE_DS": {
+                    "description": "Clear result from hmac downstream DS.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_ERROR": {
+              "description": "Error register.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUREY_CHECK": {
+                    "description": "Hmac configuration state. 0: key are agree with purpose. 1: error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_BUSY": {
+              "description": "Busy register.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUSY_STATE": {
+                    "description": "Hmac state. 1'b0: idle. 1'b1: busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "WR_MESSAGE_MEM": {
+              "description": "Message block memory.",
+              "offset": 128,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "RD_RESULT_MEM": {
+              "description": "Result from upstream.",
+              "offset": 192,
+              "size": 8,
+              "count": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SET_MESSAGE_PAD": {
+              "description": "Process control register 5.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_PAD": {
+                    "description": "Start software padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "ONE_BLOCK": {
+              "description": "Process control register 6.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_ONE_BLOCK": {
+                    "description": "Don't have to do padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SOFT_JTAG_CTRL": {
+              "description": "Jtag register 0.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFT_JTAG_CTRL": {
+                    "description": "Turn on JTAG verification.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WR_JTAG": {
+              "description": "Jtag register 1.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_JTAG": {
+                    "description": "32-bit of key to be compared.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C0": {
+        "description": "I2C (Inter-Integrated Circuit) Controller",
+        "children": {
+          "registers": {
+            "SCL_LOW_PERIOD": {
+              "description": "I2C_SCL_LOW_PERIOD_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_LOW_PERIOD": {
+                    "description": "reg_scl_low_period",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "CTR": {
+              "description": "I2C_CTR_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 523,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDA_FORCE_OUT": {
+                    "description": "reg_sda_force_out",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCL_FORCE_OUT": {
+                    "description": "reg_scl_force_out",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SAMPLE_SCL_LEVEL": {
+                    "description": "reg_sample_scl_level",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_FULL_ACK_LEVEL": {
+                    "description": "reg_rx_full_ack_level",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MS_MODE": {
+                    "description": "reg_ms_mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRANS_START": {
+                    "description": "reg_trans_start",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_LSB_FIRST": {
+                    "description": "reg_tx_lsb_first",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RX_LSB_FIRST": {
+                    "description": "reg_rx_lsb_first",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ARBITRATION_EN": {
+                    "description": "reg_arbitration_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSM_RST": {
+                    "description": "reg_fsm_rst",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPGATE": {
+                    "description": "reg_conf_upgate",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_TX_AUTO_START_EN": {
+                    "description": "reg_slv_tx_auto_start_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ADDR_10BIT_RW_CHECK_EN": {
+                    "description": "reg_addr_10bit_rw_check_en",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ADDR_BROADCASTING_EN": {
+                    "description": "reg_addr_broadcasting_en",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "I2C_SR_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 49152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESP_REC": {
+                    "description": "reg_resp_rec",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_RW": {
+                    "description": "reg_slave_rw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARB_LOST": {
+                    "description": "reg_arb_lost",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_BUSY": {
+                    "description": "reg_bus_busy",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_ADDRESSED": {
+                    "description": "reg_slave_addressed",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_CNT": {
+                    "description": "reg_rxfifo_cnt",
+                    "offset": 8,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "STRETCH_CAUSE": {
+                    "description": "reg_stretch_cause",
+                    "offset": 14,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_CNT": {
+                    "description": "reg_txfifo_cnt",
+                    "offset": 18,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_STATE_LAST": {
+                    "description": "reg_scl_main_state_last",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SCL_STATE_LAST": {
+                    "description": "reg_scl_state_last",
+                    "offset": 28,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TO": {
+              "description": "I2C_TO_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME_OUT_VALUE": {
+                    "description": "reg_time_out_value",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "TIME_OUT_EN": {
+                    "description": "reg_time_out_en",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLAVE_ADDR": {
+              "description": "I2C_SLAVE_ADDR_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLAVE_ADDR": {
+                    "description": "reg_slave_addr",
+                    "offset": 0,
+                    "size": 15
+                  },
+                  "ADDR_10BIT_EN": {
+                    "description": "reg_addr_10bit_en",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFO_ST": {
+              "description": "I2C_FIFO_ST_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_RADDR": {
+                    "description": "reg_rxfifo_raddr",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_WADDR": {
+                    "description": "reg_rxfifo_waddr",
+                    "offset": 5,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_RADDR": {
+                    "description": "reg_txfifo_raddr",
+                    "offset": 10,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WADDR": {
+                    "description": "reg_txfifo_waddr",
+                    "offset": 15,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "SLAVE_RW_POINT": {
+                    "description": "reg_slave_rw_point",
+                    "offset": 22,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FIFO_CONF": {
+              "description": "I2C_FIFO_CONF_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 16523,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_THRHD": {
+                    "description": "reg_rxfifo_wm_thrhd",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "TXFIFO_WM_THRHD": {
+                    "description": "reg_txfifo_wm_thrhd",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "NONFIFO_EN": {
+                    "description": "reg_nonfifo_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FIFO_ADDR_CFG_EN": {
+                    "description": "reg_fifo_addr_cfg_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RX_FIFO_RST": {
+                    "description": "reg_rx_fifo_rst",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_FIFO_RST": {
+                    "description": "reg_tx_fifo_rst",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FIFO_PRT_EN": {
+                    "description": "reg_fifo_prt_en",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "I2C_FIFO_DATA_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIFO_RDATA": {
+                    "description": "reg_fifo_rdata",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "I2C_INT_RAW_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_RAW": {
+                    "description": "reg_rxfifo_wm_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WM_INT_RAW": {
+                    "description": "reg_txfifo_wm_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_RAW": {
+                    "description": "reg_rxfifo_ovf_int_raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "END_DETECT_INT_RAW": {
+                    "description": "reg_end_detect_int_raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_RAW": {
+                    "description": "reg_byte_trans_done_int_raw",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARBITRATION_LOST_INT_RAW": {
+                    "description": "reg_arbitration_lost_int_raw",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_RAW": {
+                    "description": "reg_mst_txfifo_udf_int_raw",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE_INT_RAW": {
+                    "description": "reg_trans_complete_int_raw",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIME_OUT_INT_RAW": {
+                    "description": "reg_time_out_int_raw",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_START_INT_RAW": {
+                    "description": "reg_trans_start_int_raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NACK_INT_RAW": {
+                    "description": "reg_nack_int_raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_OVF_INT_RAW": {
+                    "description": "reg_txfifo_ovf_int_raw",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_UDF_INT_RAW": {
+                    "description": "reg_rxfifo_udf_int_raw",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_ST_TO_INT_RAW": {
+                    "description": "reg_scl_st_to_int_raw",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_RAW": {
+                    "description": "reg_scl_main_st_to_int_raw",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DET_START_INT_RAW": {
+                    "description": "reg_det_start_int_raw",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_STRETCH_INT_RAW": {
+                    "description": "reg_slave_stretch_int_raw",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GENERAL_CALL_INT_RAW": {
+                    "description": "reg_general_call_int_raw",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "I2C_INT_CLR_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_CLR": {
+                    "description": "reg_rxfifo_wm_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_WM_INT_CLR": {
+                    "description": "reg_txfifo_wm_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_OVF_INT_CLR": {
+                    "description": "reg_rxfifo_ovf_int_clr",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "END_DETECT_INT_CLR": {
+                    "description": "reg_end_detect_int_clr",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_CLR": {
+                    "description": "reg_byte_trans_done_int_clr",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ARBITRATION_LOST_INT_CLR": {
+                    "description": "reg_arbitration_lost_int_clr",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_CLR": {
+                    "description": "reg_mst_txfifo_udf_int_clr",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_COMPLETE_INT_CLR": {
+                    "description": "reg_trans_complete_int_clr",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TIME_OUT_INT_CLR": {
+                    "description": "reg_time_out_int_clr",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_START_INT_CLR": {
+                    "description": "reg_trans_start_int_clr",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "NACK_INT_CLR": {
+                    "description": "reg_nack_int_clr",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_OVF_INT_CLR": {
+                    "description": "reg_txfifo_ovf_int_clr",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_UDF_INT_CLR": {
+                    "description": "reg_rxfifo_udf_int_clr",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SCL_ST_TO_INT_CLR": {
+                    "description": "reg_scl_st_to_int_clr",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_CLR": {
+                    "description": "reg_scl_main_st_to_int_clr",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DET_START_INT_CLR": {
+                    "description": "reg_det_start_int_clr",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLAVE_STRETCH_INT_CLR": {
+                    "description": "reg_slave_stretch_int_clr",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "GENERAL_CALL_INT_CLR": {
+                    "description": "reg_general_call_int_clr",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "I2C_INT_ENA_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_ENA": {
+                    "description": "reg_rxfifo_wm_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFIFO_WM_INT_ENA": {
+                    "description": "reg_txfifo_wm_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFIFO_OVF_INT_ENA": {
+                    "description": "reg_rxfifo_ovf_int_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "END_DETECT_INT_ENA": {
+                    "description": "reg_end_detect_int_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BYTE_TRANS_DONE_INT_ENA": {
+                    "description": "reg_byte_trans_done_int_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ARBITRATION_LOST_INT_ENA": {
+                    "description": "reg_arbitration_lost_int_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MST_TXFIFO_UDF_INT_ENA": {
+                    "description": "reg_mst_txfifo_udf_int_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TRANS_COMPLETE_INT_ENA": {
+                    "description": "reg_trans_complete_int_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIME_OUT_INT_ENA": {
+                    "description": "reg_time_out_int_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TRANS_START_INT_ENA": {
+                    "description": "reg_trans_start_int_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NACK_INT_ENA": {
+                    "description": "reg_nack_int_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXFIFO_OVF_INT_ENA": {
+                    "description": "reg_txfifo_ovf_int_ena",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXFIFO_UDF_INT_ENA": {
+                    "description": "reg_rxfifo_udf_int_ena",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SCL_ST_TO_INT_ENA": {
+                    "description": "reg_scl_st_to_int_ena",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SCL_MAIN_ST_TO_INT_ENA": {
+                    "description": "reg_scl_main_st_to_int_ena",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DET_START_INT_ENA": {
+                    "description": "reg_det_start_int_ena",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLAVE_STRETCH_INT_ENA": {
+                    "description": "reg_slave_stretch_int_ena",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GENERAL_CALL_INT_ENA": {
+                    "description": "reg_general_call_int_ena",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_STATUS": {
+              "description": "I2C_INT_STATUS_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_ST": {
+                    "description": "reg_rxfifo_wm_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WM_INT_ST": {
+                    "description": "reg_txfifo_wm_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_ST": {
+                    "description": "reg_rxfifo_ovf_int_st",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "END_DETECT_INT_ST": {
+                    "description": "reg_end_detect_int_st",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_ST": {
+                    "description": "reg_byte_trans_done_int_st",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARBITRATION_LOST_INT_ST": {
+                    "description": "reg_arbitration_lost_int_st",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_ST": {
+                    "description": "reg_mst_txfifo_udf_int_st",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE_INT_ST": {
+                    "description": "reg_trans_complete_int_st",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIME_OUT_INT_ST": {
+                    "description": "reg_time_out_int_st",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_START_INT_ST": {
+                    "description": "reg_trans_start_int_st",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NACK_INT_ST": {
+                    "description": "reg_nack_int_st",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_OVF_INT_ST": {
+                    "description": "reg_txfifo_ovf_int_st",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_UDF_INT_ST": {
+                    "description": "reg_rxfifo_udf_int_st",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_ST_TO_INT_ST": {
+                    "description": "reg_scl_st_to_int_st",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_ST": {
+                    "description": "reg_scl_main_st_to_int_st",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DET_START_INT_ST": {
+                    "description": "reg_det_start_int_st",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_STRETCH_INT_ST": {
+                    "description": "reg_slave_stretch_int_st",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GENERAL_CALL_INT_ST": {
+                    "description": "reg_general_call_int_st",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SDA_HOLD": {
+              "description": "I2C_SDA_HOLD_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_sda_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SDA_SAMPLE": {
+              "description": "I2C_SDA_SAMPLE_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_sda_sample_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_HIGH_PERIOD": {
+              "description": "I2C_SCL_HIGH_PERIOD_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_HIGH_PERIOD": {
+                    "description": "reg_scl_high_period",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "SCL_WAIT_HIGH_PERIOD": {
+                    "description": "reg_scl_wait_high_period",
+                    "offset": 9,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "SCL_START_HOLD": {
+              "description": "I2C_SCL_START_HOLD_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_start_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_RSTART_SETUP": {
+              "description": "I2C_SCL_RSTART_SETUP_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_rstart_setup_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_STOP_HOLD": {
+              "description": "I2C_SCL_STOP_HOLD_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_stop_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_STOP_SETUP": {
+              "description": "I2C_SCL_STOP_SETUP_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_stop_setup_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "FILTER_CFG": {
+              "description": "I2C_FILTER_CFG_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_FILTER_THRES": {
+                    "description": "reg_scl_filter_thres",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "SDA_FILTER_THRES": {
+                    "description": "reg_sda_filter_thres",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "SCL_FILTER_EN": {
+                    "description": "reg_scl_filter_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SDA_FILTER_EN": {
+                    "description": "reg_sda_filter_en",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "I2C_CLK_CONF_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 2097152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLK_DIV_NUM": {
+                    "description": "reg_sclk_div_num",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "reg_sclk_div_a",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "SCLK_DIV_B": {
+                    "description": "reg_sclk_div_b",
+                    "offset": 14,
+                    "size": 6
+                  },
+                  "SCLK_SEL": {
+                    "description": "reg_sclk_sel",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SCLK_ACTIVE": {
+                    "description": "reg_sclk_active",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMD": {
+              "description": "I2C_COMD%s_REG",
+              "offset": 88,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMMAND": {
+                    "description": "reg_command",
+                    "offset": 0,
+                    "size": 14
+                  },
+                  "COMMAND_DONE": {
+                    "description": "reg_command_done",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SCL_ST_TIME_OUT": {
+              "description": "I2C_SCL_ST_TIME_OUT_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_ST_TO_I2C": {
+                    "description": "reg_scl_st_to_regno more than 23",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SCL_MAIN_ST_TIME_OUT": {
+              "description": "I2C_SCL_MAIN_ST_TIME_OUT_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_MAIN_ST_TO_I2C": {
+                    "description": "reg_scl_main_st_to_regno more than 23",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SCL_SP_CONF": {
+              "description": "I2C_SCL_SP_CONF_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_RST_SLV_EN": {
+                    "description": "reg_scl_rst_slv_en",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCL_RST_SLV_NUM": {
+                    "description": "reg_scl_rst_slv_num",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SCL_PD_EN": {
+                    "description": "reg_scl_pd_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDA_PD_EN": {
+                    "description": "reg_sda_pd_en",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SCL_STRETCH_CONF": {
+              "description": "I2C_SCL_STRETCH_CONF_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRETCH_PROTECT_NUM": {
+                    "description": "reg_stretch_protect_num",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "SLAVE_SCL_STRETCH_EN": {
+                    "description": "reg_slave_scl_stretch_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLAVE_SCL_STRETCH_CLR": {
+                    "description": "reg_slave_scl_stretch_clr",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLAVE_BYTE_ACK_CTL_EN": {
+                    "description": "reg_slave_byte_ack_ctl_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SLAVE_BYTE_ACK_LVL": {
+                    "description": "reg_slave_byte_ack_lvl",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "I2C_DATE_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 537330177,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TXFIFO_START_ADDR": {
+              "description": "I2C_TXFIFO_START_ADDR_REG",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFIFO_START_ADDR": {
+                    "description": "reg_txfifo_start_addr.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXFIFO_START_ADDR": {
+              "description": "I2C_RXFIFO_START_ADDR_REG",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_START_ADDR": {
+                    "description": "reg_rxfifo_start_addr.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2S": {
+        "description": "I2S (Inter-IC Sound) Controller",
+        "children": {
+          "registers": {
+            "INT_RAW": {
+              "description": "I2S interrupt raw register, valid in level.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "I2S interrupt status register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "I2S interrupt enable register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_DONE_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RX_HUNG_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_HUNG_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "I2S interrupt clear register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_HUNG_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_HUNG_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RX_CONF": {
+              "description": "I2S RX configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 38400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_RESET": {
+                    "description": "Set this bit to reset receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_FIFO_RESET": {
+                    "description": "Set this bit to reset Rx AFIFO",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_START": {
+                    "description": "Set this bit to start receiving data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_SLAVE_MOD": {
+                    "description": "Set this bit to enable slave receiver mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_MONO": {
+                    "description": "Set this bit to enable receiver  in mono mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RX_BIG_ENDIAN": {
+                    "description": "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RX_UPDATE": {
+                    "description": "Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RX_MONO_FST_VLD": {
+                    "description": "1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RX_PCM_CONF": {
+                    "description": "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "RX_PCM_BYPASS": {
+                    "description": "Set this bit to bypass Compress/Decompress module for received data.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RX_STOP_MODE": {
+                    "description": "0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "RX_LEFT_ALIGN": {
+                    "description": "1: I2S RX left alignment mode. 0: I2S RX right alignment mode.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RX_24_FILL_EN": {
+                    "description": "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RX_WS_IDLE_POL": {
+                    "description": "0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RX_BIT_ORDER": {
+                    "description": "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RX_TDM_EN": {
+                    "description": "1: Enable I2S TDM Rx mode . 0: Disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RX_PDM_EN": {
+                    "description": "1: Enable I2S PDM Rx mode . 0: Disable.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CONF": {
+              "description": "I2S TX configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 45568,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_RESET": {
+                    "description": "Set this bit to reset transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_FIFO_RESET": {
+                    "description": "Set this bit to reset Tx AFIFO",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_START": {
+                    "description": "Set this bit to start transmitting data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_SLAVE_MOD": {
+                    "description": "Set this bit to enable slave transmitter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TX_MONO": {
+                    "description": "Set this bit to enable transmitter in mono mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TX_CHAN_EQUAL": {
+                    "description": "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TX_BIG_ENDIAN": {
+                    "description": "I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TX_UPDATE": {
+                    "description": "Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TX_MONO_FST_VLD": {
+                    "description": "1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_PCM_CONF": {
+                    "description": "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "TX_PCM_BYPASS": {
+                    "description": "Set this bit to bypass  Compress/Decompress module for transmitted data.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_STOP_EN": {
+                    "description": "Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_LEFT_ALIGN": {
+                    "description": "1: I2S TX left alignment mode. 0: I2S TX right alignment mode.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TX_24_FILL_EN": {
+                    "description": "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TX_WS_IDLE_POL": {
+                    "description": "0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TX_BIT_ORDER": {
+                    "description": "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TX_TDM_EN": {
+                    "description": "1: Enable I2S TDM Tx mode . 0: Disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TX_PDM_EN": {
+                    "description": "1: Enable I2S PDM Tx mode . 0: Disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TX_CHAN_MOD": {
+                    "description": "I2S transmitter channel mode configuration bits.",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SIG_LOOPBACK": {
+                    "description": "Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CONF1": {
+              "description": "I2S RX configure register 1",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 792584960,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_TDM_WS_WIDTH": {
+                    "description": "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "RX_BCK_DIV_NUM": {
+                    "description": "Bit clock configuration bits in receiver mode.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "RX_BITS_MOD": {
+                    "description": "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
+                    "offset": 13,
+                    "size": 5
+                  },
+                  "RX_HALF_SAMPLE_BITS": {
+                    "description": "I2S Rx half sample bits -1.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "RX_TDM_CHAN_BITS": {
+                    "description": "The Rx bit number for each channel minus 1in TDM mode.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "RX_MSB_SHIFT": {
+                    "description": "Set this bit to enable receiver in Phillips standard mode",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CONF1": {
+              "description": "I2S TX configure register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1866326784,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_TDM_WS_WIDTH": {
+                    "description": "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "TX_BCK_DIV_NUM": {
+                    "description": "Bit clock configuration bits in transmitter mode.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "TX_BITS_MOD": {
+                    "description": "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
+                    "offset": 13,
+                    "size": 5
+                  },
+                  "TX_HALF_SAMPLE_BITS": {
+                    "description": "I2S Tx half sample bits -1.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "TX_TDM_CHAN_BITS": {
+                    "description": "The Tx bit number for each channel minus 1in TDM mode.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TX_MSB_SHIFT": {
+                    "description": "Set this bit to enable transmitter in Phillips standard mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TX_BCK_NO_DLY": {
+                    "description": "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CLKM_CONF": {
+              "description": "I2S RX clock configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_CLKM_DIV_NUM": {
+                    "description": "Integral I2S clock divider value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RX_CLK_ACTIVE": {
+                    "description": "I2S Rx module clock enable signal.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RX_CLK_SEL": {
+                    "description": "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "MCLK_SEL": {
+                    "description": "0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CLKM_CONF": {
+              "description": "I2S TX clock configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_CLKM_DIV_NUM": {
+                    "description": "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "TX_CLK_ACTIVE": {
+                    "description": "I2S Tx module clock enable signal.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TX_CLK_SEL": {
+                    "description": "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "CLK_EN": {
+                    "description": "Set this bit to enable clk gate",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CLKM_DIV_CONF": {
+              "description": "I2S RX module clock divider configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_CLKM_DIV_Z": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_Y": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_X": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.",
+                    "offset": 18,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_YN1": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CLKM_DIV_CONF": {
+              "description": "I2S TX module clock divider configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_CLKM_DIV_Z": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_Y": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_X": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.",
+                    "offset": 18,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_YN1": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_PCM2PDM_CONF": {
+              "description": "I2S TX PCM2PDM configuration register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 4890628,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PDM_HP_BYPASS": {
+                    "description": "I2S TX PDM bypass hp filter or not. The option has been removed.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_PDM_SINC_OSR2": {
+                    "description": "I2S TX PDM OSR2 value",
+                    "offset": 1,
+                    "size": 4
+                  },
+                  "TX_PDM_PRESCALE": {
+                    "description": "I2S TX PDM prescale for sigmadelta",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "TX_PDM_HP_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TX_PDM_LP_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "TX_PDM_SINC_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 17,
+                    "size": 2
+                  },
+                  "TX_PDM_SIGMADELTA_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "TX_PDM_SIGMADELTA_DITHER2": {
+                    "description": "I2S TX PDM sigmadelta dither2 value",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TX_PDM_SIGMADELTA_DITHER": {
+                    "description": "I2S TX PDM sigmadelta dither value",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TX_PDM_DAC_2OUT_EN": {
+                    "description": "I2S TX PDM dac mode enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TX_PDM_DAC_MODE_EN": {
+                    "description": "I2S TX PDM dac 2channel enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PCM2PDM_CONV_EN": {
+                    "description": "I2S TX PDM Converter enable",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_PCM2PDM_CONF1": {
+              "description": "I2S TX PCM2PDM configuration register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 66552768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PDM_FP": {
+                    "description": "I2S TX PDM Fp",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "TX_PDM_FS": {
+                    "description": "I2S TX PDM Fs",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "TX_IIR_HP_MULT12_5": {
+                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TX_IIR_HP_MULT12_0": {
+                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])",
+                    "offset": 23,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RX_TDM_CTRL": {
+              "description": "I2S TX TDM mode control register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_TDM_PDM_CHAN0_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN1_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN2_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN3_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN4_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN5_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN6_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN7_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN8_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN9_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN10_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN11_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN12_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN13_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN14_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN15_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RX_TDM_TOT_CHAN_NUM": {
+                    "description": "The total channel number of I2S TX TDM mode.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TX_TDM_CTRL": {
+              "description": "I2S TX TDM mode control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_TDM_CHAN0_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN1_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN2_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN3_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN4_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN5_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN6_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN7_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN8_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN9_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN10_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN11_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN12_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN13_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN14_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN15_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TX_TDM_TOT_CHAN_NUM": {
+                    "description": "The total channel number of I2S TX TDM mode.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "TX_TDM_SKIP_MSK_EN": {
+                    "description": "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_TIMING": {
+              "description": "I2S RX timing control register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_SD_IN_DM": {
+                    "description": "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "RX_WS_OUT_DM": {
+                    "description": "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "RX_BCK_OUT_DM": {
+                    "description": "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "RX_WS_IN_DM": {
+                    "description": "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "RX_BCK_IN_DM": {
+                    "description": "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "TX_TIMING": {
+              "description": "I2S TX timing control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_SD_OUT_DM": {
+                    "description": "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TX_SD1_OUT_DM": {
+                    "description": "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "TX_WS_OUT_DM": {
+                    "description": "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "TX_BCK_OUT_DM": {
+                    "description": "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "TX_WS_IN_DM": {
+                    "description": "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TX_BCK_IN_DM": {
+                    "description": "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "LC_HUNG_CONF": {
+              "description": "I2S HUNG configure register.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 2064,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LC_FIFO_TIMEOUT": {
+                    "description": "the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LC_FIFO_TIMEOUT_SHIFT": {
+                    "description": "The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "LC_FIFO_TIMEOUT_ENA": {
+                    "description": "The enable bit for FIFO timeout",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RXEOF_NUM": {
+              "description": "I2S RX data number control register.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EOF_NUM": {
+                    "description": "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CONF_SIGLE_DATA": {
+              "description": "I2S signal data register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SINGLE_DATA": {
+                    "description": "The configured constant channel data to be sent out.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "I2S TX status register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_IDLE": {
+                    "description": "1: i2s_tx is idle state. 0: i2s_tx is working.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 33583648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "I2S version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "INTERRUPT_CORE0": {
+        "description": "Interrupt Core",
+        "children": {
+          "registers": {
+            "MAC_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_INTR_MAP": {
+                    "description": "core0_mac_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MAC_NMI_MAP": {
+              "description": "mac nmi_intr map register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_NMI_MAP": {
+                    "description": "reg_core0_mac_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "PWR_INTR_MAP": {
+              "description": "pwr intr map register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_INTR_MAP": {
+                    "description": "reg_core0_pwr_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BB_INT_MAP": {
+              "description": "bb intr map register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BB_INT_MAP": {
+                    "description": "reg_core0_bb_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_MAC_INT_MAP": {
+              "description": "bt intr map register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_MAC_INT_MAP": {
+                    "description": "reg_core0_bt_mac_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_BB_INT_MAP": {
+              "description": "bb_bt intr map register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_BB_INT_MAP": {
+                    "description": "reg_core0_bt_bb_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_BB_NMI_MAP": {
+              "description": "bb_bt_nmi intr map register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_BB_NMI_MAP": {
+                    "description": "reg_core0_bt_bb_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBT_IRQ_MAP": {
+              "description": "rwbt intr map register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBT_IRQ_MAP": {
+                    "description": "reg_core0_rwbt_irq_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBLE_IRQ_MAP": {
+              "description": "rwble intr map register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBLE_IRQ_MAP": {
+                    "description": "reg_core0_rwble_irq_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBT_NMI_MAP": {
+              "description": "rwbt_nmi intr map register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBT_NMI_MAP": {
+                    "description": "reg_core0_rwbt_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBLE_NMI_MAP": {
+              "description": "rwble_nmi intr map register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBLE_NMI_MAP": {
+                    "description": "reg_core0_rwble_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2C_MST_INT_MAP": {
+              "description": "i2c intr map register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2C_MST_INT_MAP": {
+                    "description": "reg_core0_i2c_mst_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SLC0_INTR_MAP": {
+              "description": "slc0 intr map register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLC0_INTR_MAP": {
+                    "description": "reg_core0_slc0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SLC1_INTR_MAP": {
+              "description": "slc1 intr map register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLC1_INTR_MAP": {
+                    "description": "reg_core0_slc1_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "APB_CTRL_INTR_MAP": {
+              "description": "apb_ctrl intr map register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_CTRL_INTR_MAP": {
+                    "description": "reg_core0_apb_ctrl_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UHCI0_INTR_MAP": {
+              "description": "uchi0 intr map register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UHCI0_INTR_MAP": {
+                    "description": "reg_core0_uhci0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "GPIO_INTERRUPT_PRO_MAP": {
+              "description": "gpio intr map register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_INTERRUPT_PRO_MAP": {
+                    "description": "reg_core0_gpio_interrupt_pro_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "GPIO_INTERRUPT_PRO_NMI_MAP": {
+              "description": "gpio_pro intr map register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_INTERRUPT_PRO_NMI_MAP": {
+                    "description": "reg_core0_gpio_interrupt_pro_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_INTR_1_MAP": {
+              "description": "gpio_pro_nmi intr map register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_INTR_1_MAP": {
+                    "description": "reg_core0_spi_intr_1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_INTR_2_MAP": {
+              "description": "spi1 intr map register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_INTR_2_MAP": {
+                    "description": "reg_core0_spi_intr_2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2S1_INT_MAP": {
+              "description": "spi2 intr map register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2S1_INT_MAP": {
+                    "description": "reg_core0_i2s1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UART_INTR_MAP": {
+              "description": "i2s1 intr map register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UART_INTR_MAP": {
+                    "description": "reg_core0_uart_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UART1_INTR_MAP": {
+              "description": "uart1 intr map register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UART1_INTR_MAP": {
+                    "description": "reg_core0_uart1_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "LEDC_INT_MAP": {
+              "description": "ledc intr map register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDC_INT_MAP": {
+                    "description": "reg_core0_ledc_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "EFUSE_INT_MAP": {
+              "description": "efuse intr map register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_INT_MAP": {
+                    "description": "reg_core0_efuse_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CAN_INT_MAP": {
+              "description": "can intr map register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAN_INT_MAP": {
+                    "description": "reg_core0_can_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "USB_INTR_MAP": {
+              "description": "usb intr map register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USB_INTR_MAP": {
+                    "description": "reg_core0_usb_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RTC_CORE_INTR_MAP": {
+              "description": "rtc intr map register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CORE_INTR_MAP": {
+                    "description": "reg_core0_rtc_core_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RMT_INTR_MAP": {
+              "description": "rmt intr map register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RMT_INTR_MAP": {
+                    "description": "reg_core0_rmt_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2C_EXT0_INTR_MAP": {
+              "description": "i2c intr map register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2C_EXT0_INTR_MAP": {
+                    "description": "reg_core0_i2c_ext0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMER_INT1_MAP": {
+              "description": "timer1 intr map register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_INT1_MAP": {
+                    "description": "reg_core0_timer_int1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMER_INT2_MAP": {
+              "description": "timer2 intr map register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_INT2_MAP": {
+                    "description": "reg_core0_timer_int2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG_T0_INT_MAP": {
+              "description": "tg to intr map register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG_T0_INT_MAP": {
+                    "description": "reg_core0_tg_t0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG_WDT_INT_MAP": {
+              "description": "tg wdt intr map register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG_WDT_INT_MAP": {
+                    "description": "reg_core0_tg_wdt_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG1_T0_INT_MAP": {
+              "description": "tg1 to intr map register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG1_T0_INT_MAP": {
+                    "description": "reg_core0_tg1_t0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG1_WDT_INT_MAP": {
+              "description": "tg1 wdt intr map register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG1_WDT_INT_MAP": {
+                    "description": "reg_core0_tg1_wdt_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CACHE_IA_INT_MAP": {
+              "description": "cache ia intr map register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_IA_INT_MAP": {
+                    "description": "reg_core0_cache_ia_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET0_INT_MAP": {
+              "description": "systimer intr map register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET0_INT_MAP": {
+                    "description": "reg_core0_systimer_target0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET1_INT_MAP": {
+              "description": "systimer target1 intr map register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET1_INT_MAP": {
+                    "description": "reg_core0_systimer_target1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET2_INT_MAP": {
+              "description": "systimer target2 intr map register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET2_INT_MAP": {
+                    "description": "reg_core0_systimer_target2_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_MEM_REJECT_INTR_MAP": {
+              "description": "spi mem reject intr map register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_INTR_MAP": {
+                    "description": "reg_core0_spi_mem_reject_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_INT_MAP": {
+              "description": "icache perload intr map register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_INT_MAP": {
+                    "description": "reg_core0_icache_preload_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_INT_MAP": {
+              "description": "icache sync intr map register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_INT_MAP": {
+                    "description": "reg_core0_icache_sync_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "APB_ADC_INT_MAP": {
+              "description": "adc intr map register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_ADC_INT_MAP": {
+                    "description": "reg_core0_apb_adc_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH0_INT_MAP": {
+              "description": "dma ch0 intr map register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH0_INT_MAP": {
+                    "description": "reg_core0_dma_ch0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH1_INT_MAP": {
+              "description": "dma ch1 intr map register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH1_INT_MAP": {
+                    "description": "reg_core0_dma_ch1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH2_INT_MAP": {
+              "description": "dma ch2 intr map register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH2_INT_MAP": {
+                    "description": "reg_core0_dma_ch2_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSA_INT_MAP": {
+              "description": "rsa intr map register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSA_INT_MAP": {
+                    "description": "reg_core0_rsa_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "AES_INT_MAP": {
+              "description": "aes intr map register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AES_INT_MAP": {
+                    "description": "reg_core0_aes_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SHA_INT_MAP": {
+              "description": "sha intr map register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHA_INT_MAP": {
+                    "description": "reg_core0_sha_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_0_MAP": {
+              "description": "cpu from cpu 0 intr map register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_0_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_0_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_1_MAP": {
+              "description": "cpu from cpu 0 intr map register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_1_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_2_MAP": {
+              "description": "cpu from cpu 1 intr map register",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_2_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_3_MAP": {
+              "description": "cpu from cpu 3 intr map register",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_3_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_3_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ASSIST_DEBUG_INTR_MAP": {
+              "description": "assist debug intr map register",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASSIST_DEBUG_INTR_MAP": {
+                    "description": "reg_core0_assist_debug_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "dma pms violatile intr map register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_dma_apbperi_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "iram0 pms violatile intr map register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_iram0_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_dram0_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_pif_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
+                    "description": "reg_core0_core_0_pif_pms_monitor_violate_size_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BACKUP_PMS_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_PMS_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_backup_pms_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CACHE_CORE0_ACS_INT_MAP": {
+              "description": "mac intr map register",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_CORE0_ACS_INT_MAP": {
+                    "description": "reg_core0_cache_core0_acs_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTR_STATUS_REG_0": {
+              "description": "mac intr map register",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTR_STATUS_0": {
+                    "description": "reg_core0_intr_status_0",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR_STATUS_REG_1": {
+              "description": "mac intr map register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTR_STATUS_1": {
+                    "description": "reg_core0_intr_status_1",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "mac intr map register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_CLK_EN": {
+                    "description": "reg_core0_reg_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INT_ENABLE": {
+              "description": "mac intr map register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_ENABLE": {
+                    "description": "reg_core0_cpu_int_enable",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_TYPE": {
+              "description": "mac intr map register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_TYPE": {
+                    "description": "reg_core0_cpu_int_type",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_CLEAR": {
+              "description": "mac intr map register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_CLEAR": {
+                    "description": "reg_core0_cpu_int_clear",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_EIP_STATUS": {
+              "description": "mac intr map register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_EIP_STATUS": {
+                    "description": "reg_core0_cpu_int_eip_status",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_0": {
+              "description": "mac intr map register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_0_MAP": {
+                    "description": "reg_core0_cpu_pri_0_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_1": {
+              "description": "mac intr map register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_1_MAP": {
+                    "description": "reg_core0_cpu_pri_1_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_2": {
+              "description": "mac intr map register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_2_MAP": {
+                    "description": "reg_core0_cpu_pri_2_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_3": {
+              "description": "mac intr map register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_3_MAP": {
+                    "description": "reg_core0_cpu_pri_3_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_4": {
+              "description": "mac intr map register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_4_MAP": {
+                    "description": "reg_core0_cpu_pri_4_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_5": {
+              "description": "mac intr map register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_5_MAP": {
+                    "description": "reg_core0_cpu_pri_5_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_6": {
+              "description": "mac intr map register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_6_MAP": {
+                    "description": "reg_core0_cpu_pri_6_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_7": {
+              "description": "mac intr map register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_7_MAP": {
+                    "description": "reg_core0_cpu_pri_7_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_8": {
+              "description": "mac intr map register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_8_MAP": {
+                    "description": "reg_core0_cpu_pri_8_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_9": {
+              "description": "mac intr map register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_9_MAP": {
+                    "description": "reg_core0_cpu_pri_9_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_10": {
+              "description": "mac intr map register",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_10_MAP": {
+                    "description": "reg_core0_cpu_pri_10_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_11": {
+              "description": "mac intr map register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_11_MAP": {
+                    "description": "reg_core0_cpu_pri_11_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_12": {
+              "description": "mac intr map register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_12_MAP": {
+                    "description": "reg_core0_cpu_pri_12_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_13": {
+              "description": "mac intr map register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_13_MAP": {
+                    "description": "reg_core0_cpu_pri_13_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_14": {
+              "description": "mac intr map register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_14_MAP": {
+                    "description": "reg_core0_cpu_pri_14_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_15": {
+              "description": "mac intr map register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_15_MAP": {
+                    "description": "reg_core0_cpu_pri_15_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_16": {
+              "description": "mac intr map register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_16_MAP": {
+                    "description": "reg_core0_cpu_pri_16_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_17": {
+              "description": "mac intr map register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_17_MAP": {
+                    "description": "reg_core0_cpu_pri_17_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_18": {
+              "description": "mac intr map register",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_18_MAP": {
+                    "description": "reg_core0_cpu_pri_18_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_19": {
+              "description": "mac intr map register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_19_MAP": {
+                    "description": "reg_core0_cpu_pri_19_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_20": {
+              "description": "mac intr map register",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_20_MAP": {
+                    "description": "reg_core0_cpu_pri_20_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_21": {
+              "description": "mac intr map register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_21_MAP": {
+                    "description": "reg_core0_cpu_pri_21_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_22": {
+              "description": "mac intr map register",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_22_MAP": {
+                    "description": "reg_core0_cpu_pri_22_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_23": {
+              "description": "mac intr map register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_23_MAP": {
+                    "description": "reg_core0_cpu_pri_23_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_24": {
+              "description": "mac intr map register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_24_MAP": {
+                    "description": "reg_core0_cpu_pri_24_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_25": {
+              "description": "mac intr map register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_25_MAP": {
+                    "description": "reg_core0_cpu_pri_25_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_26": {
+              "description": "mac intr map register",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_26_MAP": {
+                    "description": "reg_core0_cpu_pri_26_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_27": {
+              "description": "mac intr map register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_27_MAP": {
+                    "description": "reg_core0_cpu_pri_27_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_28": {
+              "description": "mac intr map register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_28_MAP": {
+                    "description": "reg_core0_cpu_pri_28_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_29": {
+              "description": "mac intr map register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_29_MAP": {
+                    "description": "reg_core0_cpu_pri_29_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_30": {
+              "description": "mac intr map register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_30_MAP": {
+                    "description": "reg_core0_cpu_pri_30_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_31": {
+              "description": "mac intr map register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_31_MAP": {
+                    "description": "reg_core0_cpu_pri_31_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_THRESH": {
+              "description": "mac intr map register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_THRESH": {
+                    "description": "reg_core0_cpu_int_thresh",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "INTERRUPT_REG_DATE": {
+              "description": "mac intr map register",
+              "offset": 2044,
+              "size": 32,
+              "reset_value": 33583632,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT_REG_DATE": {
+                    "description": "reg_core0_interrupt_reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IO_MUX": {
+        "description": "Input/Output Multiplexer",
+        "children": {
+          "registers": {
+            "PIN_CTRL": {
+              "description": "Clock Output Configuration Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2047,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_OUT1": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_OUT2": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CLK_OUT3": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.",
+                    "offset": 8,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GPIO": {
+              "description": "IO MUX Configure Register for pad XTAL_32K_P",
+              "offset": 4,
+              "size": 32,
+              "count": 22,
+              "reset_value": 2816,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCU_OE": {
+                    "description": "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SLP_SEL": {
+                    "description": "Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MCU_WPD": {
+                    "description": "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCU_WPU": {
+                    "description": "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCU_IE": {
+                    "description": "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FUN_WPD": {
+                    "description": "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FUN_WPU": {
+                    "description": "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FUN_IE": {
+                    "description": "Input enable of the pad. 1: input enabled; 0: input disabled.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FUN_DRV": {
+                    "description": "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MCU_SEL": {
+                    "description": "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "FILTER_EN": {
+                    "description": "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "IO MUX Version Control Register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 33579088,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_DATE": {
+                    "description": "Version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LEDC": {
+        "description": "LED Control PWM (Pulse Width Modulation)",
+        "children": {
+          "registers": {
+            "LSCH0_CONF0": {
+              "description": "LEDC_LSCH0_CONF0.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH0": {
+                    "description": "reg_timer_sel_lsch0.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH0": {
+                    "description": "reg_sig_out_en_lsch0.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH0": {
+                    "description": "reg_idle_lv_lsch0.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH0": {
+                    "description": "reg_para_up_lsch0.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH0": {
+                    "description": "reg_ovf_num_lsch0.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH0": {
+                    "description": "reg_ovf_cnt_en_lsch0.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH0": {
+                    "description": "reg_ovf_cnt_reset_lsch0.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH0_HPOINT": {
+              "description": "LEDC_LSCH0_HPOINT.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH0": {
+                    "description": "reg_hpoint_lsch0.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH0_DUTY": {
+              "description": "LEDC_LSCH0_DUTY.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH0": {
+                    "description": "reg_duty_lsch0.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH0_CONF1": {
+              "description": "LEDC_LSCH0_CONF1.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH0": {
+                    "description": "reg_duty_scale_lsch0.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH0": {
+                    "description": "reg_duty_cycle_lsch0.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH0": {
+                    "description": "reg_duty_num_lsch0.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH0": {
+                    "description": "reg_duty_inc_lsch0.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH0": {
+                    "description": "reg_duty_start_lsch0.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH0_DUTY_R": {
+              "description": "LEDC_LSCH0_DUTY_R.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH0_R": {
+                    "description": "reg_duty_lsch0_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH1_CONF0": {
+              "description": "LEDC_LSCH1_CONF0.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH1": {
+                    "description": "reg_timer_sel_lsch1.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH1": {
+                    "description": "reg_sig_out_en_lsch1.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH1": {
+                    "description": "reg_idle_lv_lsch1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH1": {
+                    "description": "reg_para_up_lsch1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH1": {
+                    "description": "reg_ovf_num_lsch1.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH1": {
+                    "description": "reg_ovf_cnt_en_lsch1.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH1": {
+                    "description": "reg_ovf_cnt_reset_lsch1.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH1_HPOINT": {
+              "description": "LEDC_LSCH1_HPOINT.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH1": {
+                    "description": "reg_hpoint_lsch1.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH1_DUTY": {
+              "description": "LEDC_LSCH1_DUTY.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH1": {
+                    "description": "reg_duty_lsch1.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH1_CONF1": {
+              "description": "LEDC_LSCH1_CONF1.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH1": {
+                    "description": "reg_duty_scale_lsch1.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH1": {
+                    "description": "reg_duty_cycle_lsch1.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH1": {
+                    "description": "reg_duty_num_lsch1.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH1": {
+                    "description": "reg_duty_inc_lsch1.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH1": {
+                    "description": "reg_duty_start_lsch1.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH1_DUTY_R": {
+              "description": "LEDC_LSCH1_DUTY_R.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH1_R": {
+                    "description": "reg_duty_lsch1_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH2_CONF0": {
+              "description": "LEDC_LSCH2_CONF0.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH2": {
+                    "description": "reg_timer_sel_lsch2.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH2": {
+                    "description": "reg_sig_out_en_lsch2.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH2": {
+                    "description": "reg_idle_lv_lsch2.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH2": {
+                    "description": "reg_para_up_lsch2.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH2": {
+                    "description": "reg_ovf_num_lsch2.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH2": {
+                    "description": "reg_ovf_cnt_en_lsch2.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH2": {
+                    "description": "reg_ovf_cnt_reset_lsch2.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH2_HPOINT": {
+              "description": "LEDC_LSCH2_HPOINT.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH2": {
+                    "description": "reg_hpoint_lsch2.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH2_DUTY": {
+              "description": "LEDC_LSCH2_DUTY.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH2": {
+                    "description": "reg_duty_lsch2.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH2_CONF1": {
+              "description": "LEDC_LSCH2_CONF1.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH2": {
+                    "description": "reg_duty_scale_lsch2.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH2": {
+                    "description": "reg_duty_cycle_lsch2.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH2": {
+                    "description": "reg_duty_num_lsch2.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH2": {
+                    "description": "reg_duty_inc_lsch2.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH2": {
+                    "description": "reg_duty_start_lsch2.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH2_DUTY_R": {
+              "description": "LEDC_LSCH2_DUTY_R.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH2_R": {
+                    "description": "reg_duty_lsch2_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH3_CONF0": {
+              "description": "LEDC_LSCH3_CONF0.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH3": {
+                    "description": "reg_timer_sel_lsch3.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH3": {
+                    "description": "reg_sig_out_en_lsch3.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH3": {
+                    "description": "reg_idle_lv_lsch3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH3": {
+                    "description": "reg_para_up_lsch3.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH3": {
+                    "description": "reg_ovf_num_lsch3.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH3": {
+                    "description": "reg_ovf_cnt_en_lsch3.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH3": {
+                    "description": "reg_ovf_cnt_reset_lsch3.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH3_HPOINT": {
+              "description": "LEDC_LSCH3_HPOINT.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH3": {
+                    "description": "reg_hpoint_lsch3.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH3_DUTY": {
+              "description": "LEDC_LSCH3_DUTY.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH3": {
+                    "description": "reg_duty_lsch3.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH3_CONF1": {
+              "description": "LEDC_LSCH3_CONF1.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH3": {
+                    "description": "reg_duty_scale_lsch3.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH3": {
+                    "description": "reg_duty_cycle_lsch3.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH3": {
+                    "description": "reg_duty_num_lsch3.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH3": {
+                    "description": "reg_duty_inc_lsch3.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH3": {
+                    "description": "reg_duty_start_lsch3.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH3_DUTY_R": {
+              "description": "LEDC_LSCH3_DUTY_R.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH3_R": {
+                    "description": "reg_duty_lsch3_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH4_CONF0": {
+              "description": "LEDC_LSCH4_CONF0.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH4": {
+                    "description": "reg_timer_sel_lsch4.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH4": {
+                    "description": "reg_sig_out_en_lsch4.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH4": {
+                    "description": "reg_idle_lv_lsch4.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH4": {
+                    "description": "reg_para_up_lsch4.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH4": {
+                    "description": "reg_ovf_num_lsch4.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH4": {
+                    "description": "reg_ovf_cnt_en_lsch4.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH4": {
+                    "description": "reg_ovf_cnt_reset_lsch4.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH4_HPOINT": {
+              "description": "LEDC_LSCH4_HPOINT.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH4": {
+                    "description": "reg_hpoint_lsch4.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH4_DUTY": {
+              "description": "LEDC_LSCH4_DUTY.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH4": {
+                    "description": "reg_duty_lsch4.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH4_CONF1": {
+              "description": "LEDC_LSCH4_CONF1.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH4": {
+                    "description": "reg_duty_scale_lsch4.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH4": {
+                    "description": "reg_duty_cycle_lsch4.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH4": {
+                    "description": "reg_duty_num_lsch4.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH4": {
+                    "description": "reg_duty_inc_lsch4.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH4": {
+                    "description": "reg_duty_start_lsch4.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH4_DUTY_R": {
+              "description": "LEDC_LSCH4_DUTY_R.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH4_R": {
+                    "description": "reg_duty_lsch4_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH5_CONF0": {
+              "description": "LEDC_LSCH5_CONF0.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH5": {
+                    "description": "reg_timer_sel_lsch5.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH5": {
+                    "description": "reg_sig_out_en_lsch5.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH5": {
+                    "description": "reg_idle_lv_lsch5.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH5": {
+                    "description": "reg_para_up_lsch5.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH5": {
+                    "description": "reg_ovf_num_lsch5.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH5": {
+                    "description": "reg_ovf_cnt_en_lsch5.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH5": {
+                    "description": "reg_ovf_cnt_reset_lsch5.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH5_HPOINT": {
+              "description": "LEDC_LSCH5_HPOINT.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH5": {
+                    "description": "reg_hpoint_lsch5.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH5_DUTY": {
+              "description": "LEDC_LSCH5_DUTY.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH5": {
+                    "description": "reg_duty_lsch5.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH5_CONF1": {
+              "description": "LEDC_LSCH5_CONF1.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH5": {
+                    "description": "reg_duty_scale_lsch5.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH5": {
+                    "description": "reg_duty_cycle_lsch5.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH5": {
+                    "description": "reg_duty_num_lsch5.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH5": {
+                    "description": "reg_duty_inc_lsch5.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH5": {
+                    "description": "reg_duty_start_lsch5.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH5_DUTY_R": {
+              "description": "LEDC_LSCH5_DUTY_R.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH5_R": {
+                    "description": "reg_duty_lsch5_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER0_CONF": {
+              "description": "LEDC_LSTIMER0_CONF.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_DUTY_RES": {
+                    "description": "reg_lstimer0_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER0": {
+                    "description": "reg_clk_div_lstimer0.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER0_PAUSE": {
+                    "description": "reg_lstimer0_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER0_RST": {
+                    "description": "reg_lstimer0_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER0": {
+                    "description": "reg_tick_sel_lstimer0.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER0_PARA_UP": {
+                    "description": "reg_lstimer0_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER0_VALUE": {
+              "description": "LEDC_LSTIMER0_VALUE.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_CNT": {
+                    "description": "reg_lstimer0_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER1_CONF": {
+              "description": "LEDC_LSTIMER1_CONF.",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER1_DUTY_RES": {
+                    "description": "reg_lstimer1_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER1": {
+                    "description": "reg_clk_div_lstimer1.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER1_PAUSE": {
+                    "description": "reg_lstimer1_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER1_RST": {
+                    "description": "reg_lstimer1_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER1": {
+                    "description": "reg_tick_sel_lstimer1.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER1_PARA_UP": {
+                    "description": "reg_lstimer1_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER1_VALUE": {
+              "description": "LEDC_LSTIMER1_VALUE.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER1_CNT": {
+                    "description": "reg_lstimer1_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER2_CONF": {
+              "description": "LEDC_LSTIMER2_CONF.",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER2_DUTY_RES": {
+                    "description": "reg_lstimer2_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER2": {
+                    "description": "reg_clk_div_lstimer2.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER2_PAUSE": {
+                    "description": "reg_lstimer2_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER2_RST": {
+                    "description": "reg_lstimer2_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER2": {
+                    "description": "reg_tick_sel_lstimer2.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER2_PARA_UP": {
+                    "description": "reg_lstimer2_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER2_VALUE": {
+              "description": "LEDC_LSTIMER2_VALUE.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER2_CNT": {
+                    "description": "reg_lstimer2_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER3_CONF": {
+              "description": "LEDC_LSTIMER3_CONF.",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER3_DUTY_RES": {
+                    "description": "reg_lstimer3_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER3": {
+                    "description": "reg_clk_div_lstimer3.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER3_PAUSE": {
+                    "description": "reg_lstimer3_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER3_RST": {
+                    "description": "reg_lstimer3_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER3": {
+                    "description": "reg_tick_sel_lstimer3.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER3_PARA_UP": {
+                    "description": "reg_lstimer3_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER3_VALUE": {
+              "description": "LEDC_LSTIMER3_VALUE.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER3_CNT": {
+                    "description": "reg_lstimer3_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "LEDC_INT_RAW.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_RAW": {
+                    "description": "reg_lstimer0_ovf_int_raw.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER1_OVF_INT_RAW": {
+                    "description": "reg_lstimer1_ovf_int_raw.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER2_OVF_INT_RAW": {
+                    "description": "reg_lstimer2_ovf_int_raw.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER3_OVF_INT_RAW": {
+                    "description": "reg_lstimer3_ovf_int_raw.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch0_int_raw.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch1_int_raw.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch2_int_raw.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch3_int_raw.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch4_int_raw.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch5_int_raw.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch0_int_raw.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch1_int_raw.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch2_int_raw.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch3_int_raw.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch4_int_raw.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch5_int_raw.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "LEDC_INT_ST.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_ST": {
+                    "description": "reg_lstimer0_ovf_int_st.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER1_OVF_INT_ST": {
+                    "description": "reg_lstimer1_ovf_int_st.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER2_OVF_INT_ST": {
+                    "description": "reg_lstimer2_ovf_int_st.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER3_OVF_INT_ST": {
+                    "description": "reg_lstimer3_ovf_int_st.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch0_int_st.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch1_int_st.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch2_int_st.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch3_int_st.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch4_int_st.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch5_int_st.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch0_int_st.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch1_int_st.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch2_int_st.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch3_int_st.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch4_int_st.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch5_int_st.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "LEDC_INT_ENA.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_ENA": {
+                    "description": "reg_lstimer0_ovf_int_ena.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSTIMER1_OVF_INT_ENA": {
+                    "description": "reg_lstimer1_ovf_int_ena.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LSTIMER2_OVF_INT_ENA": {
+                    "description": "reg_lstimer2_ovf_int_ena.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSTIMER3_OVF_INT_ENA": {
+                    "description": "reg_lstimer3_ovf_int_ena.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch0_int_ena.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch1_int_ena.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch2_int_ena.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch3_int_ena.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch4_int_ena.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch5_int_ena.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH0_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch0_int_ena.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH1_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch1_int_ena.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH2_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch2_int_ena.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH3_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch3_int_ena.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH4_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch4_int_ena.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH5_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch5_int_ena.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "LEDC_INT_CLR.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_CLR": {
+                    "description": "reg_lstimer0_ovf_int_clr.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER1_OVF_INT_CLR": {
+                    "description": "reg_lstimer1_ovf_int_clr.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER2_OVF_INT_CLR": {
+                    "description": "reg_lstimer2_ovf_int_clr.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER3_OVF_INT_CLR": {
+                    "description": "reg_lstimer3_ovf_int_clr.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch0_int_clr.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch1_int_clr.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch2_int_clr.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch3_int_clr.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch4_int_clr.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch5_int_clr.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch0_int_clr.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch1_int_clr.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch2_int_clr.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch3_int_clr.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch4_int_clr.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch5_int_clr.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONF": {
+              "description": "LEDC_CONF.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_CLK_SEL": {
+                    "description": "reg_apb_clk_sel.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "LEDC_DATE.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 419829504,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDC_DATE": {
+                    "description": "reg_ledc_date.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RMT": {
+        "description": "Remote Control Peripheral",
+        "children": {
+          "registers": {
+            "CH0DATA": {
+              "description": "RMT_CH0DATA_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1DATA": {
+              "description": "RMT_CH1DATA_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2DATA": {
+              "description": "RMT_CH2DATA_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3DATA": {
+              "description": "RMT_CH3DATA_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2CONF1": {
+              "description": "RMT_CH2CONF1_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 488,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EN": {
+                    "description": "reg_rx_en_ch2.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_WR_RST": {
+                    "description": "reg_mem_wr_rst_ch2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_MEM_RST": {
+                    "description": "reg_apb_mem_rst_ch2.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MEM_OWNER": {
+                    "description": "reg_mem_owner_ch2.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_FILTER_EN": {
+                    "description": "reg_rx_filter_en_ch2.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_FILTER_THRES": {
+                    "description": "reg_rx_filter_thres_ch2.",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "MEM_RX_WRAP_EN": {
+                    "description": "reg_mem_rx_wrap_en_ch2.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AFIFO_RST": {
+                    "description": "reg_afifo_rst_ch2.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPDATE": {
+                    "description": "reg_conf_update_ch2.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH3CONF1": {
+              "description": "RMT_CH3CONF1_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 488,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EN": {
+                    "description": "reg_rx_en_ch3.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_WR_RST": {
+                    "description": "reg_mem_wr_rst_ch3.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_MEM_RST": {
+                    "description": "reg_apb_mem_rst_ch3.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MEM_OWNER": {
+                    "description": "reg_mem_owner_ch3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_FILTER_EN": {
+                    "description": "reg_rx_filter_en_ch3.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_FILTER_THRES": {
+                    "description": "reg_rx_filter_thres_ch3.",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "MEM_RX_WRAP_EN": {
+                    "description": "reg_mem_rx_wrap_en_ch3.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AFIFO_RST": {
+                    "description": "reg_afifo_rst_ch3.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPDATE": {
+                    "description": "reg_conf_update_ch3.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH0STATUS": {
+              "description": "RMT_CH0STATUS_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_RADDR_EX": {
+                    "description": "reg_mem_raddr_ex_ch0.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch0.",
+                    "offset": 9,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WADDR": {
+                    "description": "reg_apb_mem_waddr_ch0.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch0.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_EMPTY": {
+                    "description": "reg_mem_empty_ch0.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WR_ERR": {
+                    "description": "reg_apb_mem_wr_err_ch0.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch0.",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH1STATUS": {
+              "description": "RMT_CH1STATUS_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_RADDR_EX": {
+                    "description": "reg_mem_raddr_ex_ch1.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch1.",
+                    "offset": 9,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WADDR": {
+                    "description": "reg_apb_mem_waddr_ch1.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch1.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_EMPTY": {
+                    "description": "reg_mem_empty_ch1.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WR_ERR": {
+                    "description": "reg_apb_mem_wr_err_ch1.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch1.",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH2STATUS": {
+              "description": "RMT_CH2STATUS_REG.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_WADDR_EX": {
+                    "description": "reg_mem_waddr_ex_ch2.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch2.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch2.",
+                    "offset": 22,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MEM_OWNER_ERR": {
+                    "description": "reg_mem_owner_err_ch2.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_FULL": {
+                    "description": "reg_mem_full_ch2.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch2.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH3STATUS": {
+              "description": "RMT_CH3STATUS_REG.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_WADDR_EX": {
+                    "description": "reg_mem_waddr_ex_ch3.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch3.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch3.",
+                    "offset": 22,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MEM_OWNER_ERR": {
+                    "description": "reg_mem_owner_err_ch3.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_FULL": {
+                    "description": "reg_mem_full_ch3.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch3.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "RMT_INT_RAW_REG.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_RAW": {
+                    "description": "reg_ch2_rx_thr_event_int_raw.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_RAW": {
+                    "description": "reg_ch3_rx_thr_event_int_raw.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "RMT_INT_ST_REG.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_ST": {
+                    "description": "reg_ch2_rx_thr_event_int_st.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_ST": {
+                    "description": "reg_ch3_rx_thr_event_int_st.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "RMT_INT_ENA_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_ENA": {
+                    "description": "reg_ch2_rx_thr_event_int_ena.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH3_RX_THR_EVENT_INT_ENA": {
+                    "description": "reg_ch3_rx_thr_event_int_ena.",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "RMT_INT_CLR_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_CLR": {
+                    "description": "reg_ch2_rx_thr_event_int_clr.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_CLR": {
+                    "description": "reg_ch3_rx_thr_event_int_clr.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH0CARRIER_DUTY": {
+              "description": "RMT_CH0CARRIER_DUTY_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 4194368,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW": {
+                    "description": "reg_carrier_low_ch0.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH": {
+                    "description": "reg_carrier_high_ch0.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1CARRIER_DUTY": {
+              "description": "RMT_CH1CARRIER_DUTY_REG.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 4194368,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW": {
+                    "description": "reg_carrier_low_ch1.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH": {
+                    "description": "reg_carrier_high_ch1.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2_RX_CARRIER_RM": {
+              "description": "RMT_CH2_RX_CARRIER_RM_REG.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW_THRES": {
+                    "description": "reg_carrier_low_thres_ch2.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH_THRES": {
+                    "description": "reg_carrier_high_thres_ch2.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3_RX_CARRIER_RM": {
+              "description": "RMT_CH3_RX_CARRIER_RM_REG.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW_THRES": {
+                    "description": "reg_carrier_low_thres_ch3.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH_THRES": {
+                    "description": "reg_carrier_high_thres_ch3.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SYS_CONF": {
+              "description": "RMT_SYS_CONF_REG.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 83886096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_FIFO_MASK": {
+                    "description": "reg_apb_fifo_mask.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_CLK_FORCE_ON": {
+                    "description": "reg_mem_clk_force_on.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PD": {
+                    "description": "reg_rmt_mem_force_pd.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PU": {
+                    "description": "reg_rmt_mem_force_pu.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SCLK_DIV_NUM": {
+                    "description": "reg_rmt_sclk_div_num.",
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "reg_rmt_sclk_div_a.",
+                    "offset": 12,
+                    "size": 6
+                  },
+                  "SCLK_DIV_B": {
+                    "description": "reg_rmt_sclk_div_b.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "SCLK_SEL": {
+                    "description": "reg_rmt_sclk_sel.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "SCLK_ACTIVE": {
+                    "description": "reg_rmt_sclk_active.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_SIM": {
+              "description": "RMT_TX_SIM_REG.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_SIM_CH0": {
+                    "description": "reg_rmt_tx_sim_ch0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_SIM_CH1": {
+                    "description": "reg_rmt_tx_sim_ch1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_SIM_EN": {
+                    "description": "reg_rmt_tx_sim_en.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REF_CNT_RST": {
+              "description": "RMT_REF_CNT_RST_REG.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "reg_ref_cnt_rst_ch0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH1": {
+                    "description": "reg_ref_cnt_rst_ch1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH2": {
+                    "description": "reg_ref_cnt_rst_ch2.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH3": {
+                    "description": "reg_ref_cnt_rst_ch3.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "RMT_DATE_REG.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 33579569,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_rmt_date.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RNG": {
+        "description": "Hardware random number generator",
+        "children": {
+          "registers": {
+            "DATA": {
+              "description": "Random number data",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            }
+          }
+        }
+      },
+      "RSA": {
+        "description": "RSA (Rivest Shamir Adleman) Accelerator",
+        "children": {
+          "registers": {
+            "M_MEM": {
+              "description": "The memory that stores M",
+              "offset": 0,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Z_MEM": {
+              "description": "The memory that stores Z",
+              "offset": 512,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Y_MEM": {
+              "description": "The memory that stores Y",
+              "offset": 1024,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "X_MEM": {
+              "description": "The memory that stores X",
+              "offset": 1536,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_PRIME": {
+              "description": "RSA M_prime register",
+              "offset": 2048,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M_PRIME": {
+                    "description": "Those bits stores m'",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "RSA mode register",
+              "offset": 2052,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "rsa mode (rsa length).",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "QUERY_CLEAN": {
+              "description": "RSA query clean register",
+              "offset": 2056,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_CLEAN": {
+                    "description": "query clean",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MODEXP": {
+              "description": "RSA modular exponentiation trigger register.",
+              "offset": 2060,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MODEXP": {
+                    "description": "start modular exponentiation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MODMULT": {
+              "description": "RSA modular multiplication trigger register.",
+              "offset": 2064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MODMULT": {
+                    "description": "start modular multiplication",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MULT": {
+              "description": "RSA normal multiplication trigger register.",
+              "offset": 2068,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MULT": {
+                    "description": "start multiplicaiton",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_IDLE": {
+              "description": "RSA query idle register",
+              "offset": 2072,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_IDLE": {
+                    "description": "query rsa idle. 1'b0: busy, 1'b1: idle",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "RSA interrupt clear register",
+              "offset": 2076,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLEAR_INTERRUPT": {
+                    "description": "set this bit to clear RSA interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONSTANT_TIME": {
+              "description": "RSA constant time option register",
+              "offset": 2080,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTANT_TIME": {
+                    "description": "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SEARCH_ENABLE": {
+              "description": "RSA search option",
+              "offset": 2084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEARCH_ENABLE": {
+                    "description": "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SEARCH_POS": {
+              "description": "RSA search position configure register",
+              "offset": 2088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEARCH_POS": {
+                    "description": "Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "RSA interrupt enable register",
+              "offset": 2092,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_ENA": {
+                    "description": "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "RSA version control register",
+              "offset": 2096,
+              "size": 32,
+              "reset_value": 538969624,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "rsa version information",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC_CNTL": {
+        "description": "Real-Time Clock Control",
+        "children": {
+          "registers": {
+            "OPTIONS0": {
+              "description": "rtc configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 469803008,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_STALL_APPCPU_C0": {
+                    "description": "{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SW_STALL_PROCPU_C0": {
+                    "description": "{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "SW_APPCPU_RST": {
+                    "description": "APP CPU SW reset",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_PROCPU_RST": {
+                    "description": "PRO CPU SW reset",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BB_I2C_FORCE_PD": {
+                    "description": "BB_I2C force power down",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BB_I2C_FORCE_PU": {
+                    "description": "BB_I2C force power up",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBPLL_I2C_FORCE_PD": {
+                    "description": "BB_PLL _I2C force power down",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BBPLL_I2C_FORCE_PU": {
+                    "description": "BB_PLL_I2C force power up",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BBPLL_FORCE_PD": {
+                    "description": "BB_PLL force power down",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BBPLL_FORCE_PU": {
+                    "description": "BB_PLL force power up",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "XTL_FORCE_PD": {
+                    "description": "crystall force power down",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "XTL_FORCE_PU": {
+                    "description": "crystall force power up",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "XTL_EN_WAIT": {
+                    "description": "wait bias_sleep and current source wakeup",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "XTL_EXT_CTR_SEL": {
+                    "description": "analog configure",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "XTL_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PLL_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ANALOG_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "XTL_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLL_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ANALOG_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_RST": {
+                    "description": "digital wrap force reset in deep sleep",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_NORST": {
+                    "description": "digital core force no reset in deep sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SW_SYS_RST": {
+                    "description": "SW system reset",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SLP_TIMER0": {
+              "description": "rtc configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_VAL_LO": {
+                    "description": "configure the  sleep time",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SLP_TIMER1": {
+              "description": "rtc configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_VAL_HI": {
+                    "description": "RTC sleep timer high 16 bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RTC_MAIN_TIMER_ALARM_EN": {
+                    "description": "timer alarm enable bit",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "TIME_UPDATE": {
+              "description": "rtc configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SYS_STALL": {
+                    "description": "Enable to record system stall time",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "TIMER_XTL_OFF": {
+                    "description": "Enable to record 40M XTAL OFF time",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "TIMER_SYS_RST": {
+                    "description": "enable to record system reset time",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_TIME_UPDATE": {
+                    "description": "Set 1: to update register with RTC timer",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "TIME_LOW0": {
+              "description": "rtc configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE0_LOW": {
+                    "description": "RTC timer low 32 bits",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_HIGH0": {
+              "description": "rtc configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE0_HIGH": {
+                    "description": "RTC timer high 16 bits",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STATE0": {
+              "description": "rtc configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SW_CPU_INT": {
+                    "description": "rtc software interrupt to main cpu",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SLP_REJECT_CAUSE_CLR": {
+                    "description": "clear rtc sleep reject cause",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB2RTC_BRIDGE_SEL": {
+                    "description": "1: APB to RTC using bridge",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SDIO_ACTIVE_IND": {
+                    "description": "SDIO active indication",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_WAKEUP": {
+                    "description": "leep wakeup bit",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SLP_REJECT": {
+                    "description": "leep reject bit",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SLEEP_EN": {
+                    "description": "sleep enable bit",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TIMER1": {
+              "description": "rtc configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 672400387,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_STALL_EN": {
+                    "description": "CPU stall enable bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CPU_STALL_WAIT": {
+                    "description": "CPU stall wait cycles in fast_clk_rtc",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "CK8M_WAIT": {
+                    "description": "CK8M wait cycles in slow_clk_rtc",
+                    "offset": 6,
+                    "size": 8
+                  },
+                  "XTL_BUF_WAIT": {
+                    "description": "XTAL wait cycles in slow_clk_rtc",
+                    "offset": 14,
+                    "size": 10
+                  },
+                  "PLL_BUF_WAIT": {
+                    "description": "PLL wait cycles in slow_clk_rtc",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER2": {
+              "description": "rtc configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 16777216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_TIME_CK8M_OFF": {
+                    "description": "minimal cycles in slow_clk_rtc for CK8M in power down state",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER3": {
+              "description": "rtc configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 168299016,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_WAIT_TIMER": {
+                    "description": "wifi power domain wakeup time",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "WIFI_POWERUP_TIMER": {
+                    "description": "wifi power domain power on time",
+                    "offset": 9,
+                    "size": 7
+                  },
+                  "BT_WAIT_TIMER": {
+                    "description": "bt power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "BT_POWERUP_TIMER": {
+                    "description": "bt power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TIMER4": {
+              "description": "rtc configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 270535176,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_TOP_WAIT_TIMER": {
+                    "description": "cpu top power domain wakeup time",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "CPU_TOP_POWERUP_TIMER": {
+                    "description": "cpu top power domain power on time",
+                    "offset": 9,
+                    "size": 7
+                  },
+                  "DG_WRAP_WAIT_TIMER": {
+                    "description": "digital wrap power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "DG_WRAP_POWERUP_TIMER": {
+                    "description": "digital wrap power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TIMER5": {
+              "description": "rtc configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_SLP_VAL": {
+                    "description": "minimal sleep cycles in slow_clk_rtc",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER6": {
+              "description": "rtc configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 168296448,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DG_PERI_WAIT_TIMER": {
+                    "description": "digital peri power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "DG_PERI_POWERUP_TIMER": {
+                    "description": "digital peri power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ANA_CONF": {
+              "description": "rtc configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 12845056,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_POR_FORCE_PD": {
+                    "description": "force no bypass i2c power on reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RESET_POR_FORCE_PU": {
+                    "description": "force bypass i2c power on reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GLITCH_RST_EN": {
+                    "description": "enable glitch reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SAR_I2C_PU": {
+                    "description": "PLLA force power up",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PLLA_FORCE_PD": {
+                    "description": "PLLA force power down",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PLLA_FORCE_PU": {
+                    "description": "PLLA force power up",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BBPLL_CAL_SLP_START": {
+                    "description": "start BBPLL calibration during sleep",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PVTMON_PU": {
+                    "description": "1: PVTMON power up",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TXRF_I2C_PU": {
+                    "description": "1: TXRF_I2C power up",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RFRX_PBUS_PU": {
+                    "description": "1: RFRX_PBUS power up",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CKGEN_I2C_PU": {
+                    "description": "1: CKGEN_I2C power up",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PLL_I2C_PU": {
+                    "description": "power up pll i2c",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RESET_STATE": {
+              "description": "rtc configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 12288,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_CAUSE_PROCPU": {
+                    "description": "reset cause of PRO CPU",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "RESET_CAUSE_APPCPU": {
+                    "description": "reset cause of APP CPU",
+                    "offset": 6,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "STAT_VECTOR_SEL_APPCPU": {
+                    "description": "APP CPU state vector sel",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STAT_VECTOR_SEL_PROCPU": {
+                    "description": "PRO CPU state vector sel",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ALL_RESET_FLAG_PROCPU": {
+                    "description": "PRO CPU reset_flag",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALL_RESET_FLAG_APPCPU": {
+                    "description": "APP CPU reset flag",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALL_RESET_FLAG_CLR_PROCPU": {
+                    "description": "clear PRO CPU reset_flag",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ALL_RESET_FLAG_CLR_APPCPU": {
+                    "description": "clear APP CPU reset flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OCD_HALT_ON_RESET_APPCPU": {
+                    "description": "APPCPU OcdHaltOnReset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OCD_HALT_ON_RESET_PROCPU": {
+                    "description": "PROCPU OcdHaltOnReset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "JTAG_RESET_FLAG_PROCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_RESET_FLAG_APPCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_RESET_FLAG_CLR_PROCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "JTAG_RESET_FLAG_CLR_APPCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_DRESET_MASK_APPCPU": {
+                    "description": "configure dreset configure",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RTC_DRESET_MASK_PROCPU": {
+                    "description": "configure dreset configure",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WAKEUP_STATE": {
+              "description": "rtc configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 393216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_WAKEUP_ENA": {
+                    "description": "wakeup enable bitmap",
+                    "offset": 15,
+                    "size": 17
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC": {
+              "description": "rtc configure register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA": {
+                    "description": "enable sleep wakeup interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SLP_REJECT_INT_ENA": {
+                    "description": "enable sleep reject interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_WDT_INT_ENA": {
+                    "description": "enable RTC WDT interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_BROWN_OUT_INT_ENA": {
+                    "description": "enable brown out interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA": {
+                    "description": "enable RTC main timer interrupt",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RTC_SWD_INT_ENA": {
+                    "description": "enable super watch dog interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA": {
+                    "description": "enable xtal32k_dead  interrupt",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RTC_GLITCH_DET_INT_ENA": {
+                    "description": "enbale gitch det interrupt",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA": {
+                    "description": "enbale bbpll cal end interrupt",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW_RTC": {
+              "description": "rtc configure register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_RAW": {
+                    "description": "sleep wakeup interrupt raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_REJECT_INT_RAW": {
+                    "description": "sleep reject interrupt raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_WDT_INT_RAW": {
+                    "description": "RTC WDT interrupt raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BROWN_OUT_INT_RAW": {
+                    "description": "brown out interrupt raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_RAW": {
+                    "description": "RTC main timer interrupt raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_SWD_INT_RAW": {
+                    "description": "super watch dog interrupt raw",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_RAW": {
+                    "description": "xtal32k dead detection interrupt raw",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_GLITCH_DET_INT_RAW": {
+                    "description": "glitch_det_interrupt_raw",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_RAW": {
+                    "description": "bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_RTC": {
+              "description": "rtc configure register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ST": {
+                    "description": "sleep wakeup interrupt state",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_REJECT_INT_ST": {
+                    "description": "sleep reject interrupt state",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_WDT_INT_ST": {
+                    "description": "RTC WDT interrupt state",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ST": {
+                    "description": "brown out interrupt state",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ST": {
+                    "description": "RTC main timer interrupt state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_SWD_INT_ST": {
+                    "description": "super watch dog interrupt state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ST": {
+                    "description": "xtal32k dead detection interrupt state",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ST": {
+                    "description": "glitch_det_interrupt state",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ST": {
+                    "description": "bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR_RTC": {
+              "description": "rtc configure register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_CLR": {
+                    "description": "Clear sleep wakeup interrupt state",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_CLR": {
+                    "description": "Clear sleep reject interrupt state",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_CLR": {
+                    "description": "Clear RTC WDT interrupt state",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_CLR": {
+                    "description": "Clear brown out interrupt state",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_CLR": {
+                    "description": "Clear RTC main timer interrupt state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_CLR": {
+                    "description": "Clear super watch dog interrupt state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_CLR": {
+                    "description": "Clear RTC WDT interrupt state",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_CLR": {
+                    "description": "Clear glitch det interrupt state",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_CLR": {
+                    "description": "clear bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STORE0": {
+              "description": "rtc configure register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH0": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE1": {
+              "description": "rtc configure register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH1": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE2": {
+              "description": "rtc configure register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH2": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE3": {
+              "description": "rtc configure register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH3": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "EXT_XTL_CONF": {
+              "description": "rtc configure register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 420992,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_WDT_EN": {
+                    "description": "xtal 32k watch dog enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "XTAL32K_WDT_CLK_FO": {
+                    "description": "xtal 32k watch dog clock force on",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XTAL32K_WDT_RESET": {
+                    "description": "xtal 32k watch dog sw reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "XTAL32K_EXT_CLK_FO": {
+                    "description": "xtal 32k external xtal clock force on",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_BACKUP": {
+                    "description": "xtal 32k switch to back up clock when xtal is dead",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_RESTART": {
+                    "description": "xtal 32k restart xtal when xtal is dead",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_RETURN": {
+                    "description": "xtal 32k switch back xtal when xtal is restarted",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "XTAL32K_XPD_FORCE": {
+                    "description": "Xtal 32k xpd control by sw or fsm",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ENCKINIT_XTAL_32K": {
+                    "description": "apply an internal clock to help xtal 32k to start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBUF_XTAL_32K": {
+                    "description": "0: single-end buffer 1: differential buffer",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DGM_XTAL_32K": {
+                    "description": "xtal_32k gm control",
+                    "offset": 10,
+                    "size": 3
+                  },
+                  "DRES_XTAL_32K": {
+                    "description": "DRES_XTAL_32K",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "XPD_XTAL_32K": {
+                    "description": "XPD_XTAL_32K",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DAC_XTAL_32K": {
+                    "description": "DAC_XTAL_32K",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "RTC_WDT_STATE": {
+                    "description": "state of 32k_wdt",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_GPIO_SEL": {
+                    "description": "XTAL_32K sel. 0: external XTAL_32K",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "XTL_EXT_CTR_LV": {
+                    "description": "0: power down XTAL at high level",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "XTL_EXT_CTR_EN": {
+                    "description": "enable gpio configure xtal power on",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXT_WAKEUP_CONF": {
+              "description": "rtc configure register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_WAKEUP_FILTER": {
+                    "description": "enable filter for gpio wakeup event",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_REJECT_CONF": {
+              "description": "rtc configure register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SLEEP_REJECT_ENA": {
+                    "description": "sleep reject enable",
+                    "offset": 12,
+                    "size": 18
+                  },
+                  "LIGHT_SLP_REJECT_EN": {
+                    "description": "enable reject for light sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEEP_SLP_REJECT_EN": {
+                    "description": "enable reject for deep sleep",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PERIOD_CONF": {
+              "description": "rtc configure register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CPUSEL_CONF": {
+                    "description": "CPU sel option",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_CPUPERIOD_SEL": {
+                    "description": "CPU clk sel option",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "rtc configure register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 290992664,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_CLK_FORCE_GATING": {
+                    "description": "efuse_clk_force_gating",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EFUSE_CLK_FORCE_NOGATING": {
+                    "description": "efuse_clk_force_nogating",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CK8M_DIV_SEL_VLD": {
+                    "description": "used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CK8M_DIV": {
+                    "description": "CK8M_D256_OUT divider. 00: div128",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "ENB_CK8M": {
+                    "description": "disable CK8M and CK8M_D256_OUT",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENB_CK8M_DIV": {
+                    "description": "1: CK8M_D256_OUT is actually CK8M",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DIG_XTAL32K_EN": {
+                    "description": "enable CK_XTAL_32K for digital core (no relationship with RTC core)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIG_CLK8M_D256_EN": {
+                    "description": "enable CK8M_D256_OUT for digital core (no relationship with RTC core)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DIG_CLK8M_EN": {
+                    "description": "enable CK8M for digital core (no relationship with RTC core)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CK8M_DIV_SEL": {
+                    "description": "divider = reg_ck8m_div_sel + 1",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "XTAL_FORCE_NOGATING": {
+                    "description": "XTAL force no gating during sleep",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CK8M_FORCE_NOGATING": {
+                    "description": "CK8M force no gating during sleep",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CK8M_DFREQ": {
+                    "description": "CK8M_DFREQ",
+                    "offset": 17,
+                    "size": 8
+                  },
+                  "CK8M_FORCE_PD": {
+                    "description": "CK8M force power down",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CK8M_FORCE_PU": {
+                    "description": "CK8M force power up",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "XTAL_GLOBAL_FORCE_GATING": {
+                    "description": "force enable xtal clk gating",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "XTAL_GLOBAL_FORCE_NOGATING": {
+                    "description": "force bypass xtal clk gating",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FAST_CLK_RTC_SEL": {
+                    "description": "fast_clk_rtc sel. 0: XTAL div 4",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ANA_CLK_RTC_SEL": {
+                    "description": "slelect rtc slow clk",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SLOW_CLK_CONF": {
+              "description": "rtc configure register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 4194304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_ANA_CLK_DIV_VLD": {
+                    "description": "used to sync div bus. clear vld before set reg_rtc_ana_clk_div",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RTC_ANA_CLK_DIV": {
+                    "description": "the clk divider num of RTC_CLK",
+                    "offset": 23,
+                    "size": 8
+                  },
+                  "RTC_SLOW_CLK_NEXT_EDGE": {
+                    "description": "flag rtc_slow_clk_next_edge",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SDIO_CONF": {
+              "description": "rtc configure register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 179355146,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_TIMER_TARGET": {
+                    "description": "timer count to apply reg_sdio_dcap after sdio power on",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SDIO_DTHDRV": {
+                    "description": "Tieh = 1 mode drive ability. Initially set to 0 to limit charge current",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SDIO_DCAP": {
+                    "description": "ability to prevent LDO from overshoot",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "SDIO_INITI": {
+                    "description": "add resistor from ldo output to ground. 0: no res",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "SDIO_EN_INITI": {
+                    "description": "0 to set init[1:0]=0",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SDIO_DCURLIM": {
+                    "description": "tune current limit threshold when tieh = 0. About 800mA/(8+d)",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "SDIO_MODECURLIM": {
+                    "description": "select current limit mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SDIO_ENCURLIM": {
+                    "description": "enable current limit",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SDIO_REG_PD_EN": {
+                    "description": "power down SDIO_REG in sleep. Only active when reg_sdio_force = 0",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SDIO_FORCE": {
+                    "description": "1: use SW option to control SDIO_REG",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SDIO_TIEH": {
+                    "description": "SW option for SDIO_TIEH. Only active when reg_sdio_force = 1",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "_1P8_READY": {
+                    "description": "read only register for REG1P8_READY",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DREFL_SDIO": {
+                    "description": "SW option for DREFL_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 25,
+                    "size": 2
+                  },
+                  "DREFM_SDIO": {
+                    "description": "SW option for DREFM_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "DREFH_SDIO": {
+                    "description": "SW option for DREFH_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "XPD_SDIO": {
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BIAS_CONF": {
+              "description": "rtc configure register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 67584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DG_VDD_DRV_B_SLP": {
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DG_VDD_DRV_B_SLP_EN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIAS_BUF_IDLE": {
+                    "description": "bias buf when rtc in normal work state",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BIAS_BUF_WAKE": {
+                    "description": "bias buf when rtc in wakeup state",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BIAS_BUF_DEEP_SLP": {
+                    "description": "bias buf when rtc in sleep state",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BIAS_BUF_MONITOR": {
+                    "description": "bias buf when rtc in monitor state",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PD_CUR_DEEP_SLP": {
+                    "description": "xpd cur when rtc in sleep_state",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PD_CUR_MONITOR": {
+                    "description": "xpd cur when rtc in monitor state",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIAS_SLEEP_DEEP_SLP": {
+                    "description": "bias_sleep when rtc in sleep_state",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BIAS_SLEEP_MONITOR": {
+                    "description": "bias_sleep when rtc in monitor state",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_ATTEN_DEEP_SLP": {
+                    "description": "DBG_ATTEN when rtc in sleep state",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "DBG_ATTEN_MONITOR": {
+                    "description": "DBG_ATTEN when rtc in monitor state",
+                    "offset": 22,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RTC_CNTL": {
+              "description": "rtc configure register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 2684354560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIG_REG_CAL_EN": {
+                    "description": "software enable digital regulator cali",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SCK_DCAP": {
+                    "description": "SCK_DCAP",
+                    "offset": 14,
+                    "size": 8
+                  },
+                  "DBOOST_FORCE_PD": {
+                    "description": "RTC_DBOOST force power down",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DBOOST_FORCE_PU": {
+                    "description": "RTC_DBOOST force power up",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "REGULATOR_FORCE_PD": {
+                    "description": "RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "REGULATOR_FORCE_PU": {
+                    "description": "RTC_REG force power up",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PWC": {
+              "description": "rtc configure register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_PAD_FORCE_HOLD": {
+                    "description": "rtc pad force hold",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_PWC": {
+              "description": "rtc configure register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 5591056,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VDD_SPI_PWR_DRV": {
+                    "description": "vdd_spi drv's software value",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "VDD_SPI_PWR_FORCE": {
+                    "description": "vdd_spi drv use software value",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSLP_MEM_FORCE_PD": {
+                    "description": "memories in digital core force PD in sleep",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LSLP_MEM_FORCE_PU": {
+                    "description": "memories in digital core force PU in sleep",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BT_FORCE_PD": {
+                    "description": "bt force power down",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BT_FORCE_PU": {
+                    "description": "bt force power up",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_PD": {
+                    "description": "digital peri force power down",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_PU": {
+                    "description": "digital peri force power up",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RTC_FASTMEM_FORCE_LPD": {
+                    "description": "fastmemory  retention mode in sleep",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTC_FASTMEM_FORCE_LPU": {
+                    "description": "fastmemory donlt entry retention mode in sleep",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_PD": {
+                    "description": "wifi force power down",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_PU": {
+                    "description": "wifi force power up",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_PD": {
+                    "description": "digital core force power down",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_PU": {
+                    "description": "digital core force power up",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_PD": {
+                    "description": "cpu core force power down",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_PU": {
+                    "description": "cpu force power up",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BT_PD_EN": {
+                    "description": "enable power down bt in sleep",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "DG_PERI_PD_EN": {
+                    "description": "enable power down digital peri in sleep",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CPU_TOP_PD_EN": {
+                    "description": "enable power down cpu in sleep",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "WIFI_PD_EN": {
+                    "description": "enable power down wifi in sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DG_WRAP_PD_EN": {
+                    "description": "enable power down digital wrap in sleep",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_ISO": {
+              "description": "rtc configure register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 2860535936,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FORCE_OFF": {
+                    "description": "DIG_ISO force off",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FORCE_ON": {
+                    "description": "DIG_ISO force on",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DG_PAD_AUTOHOLD": {
+                    "description": "read only register to indicate digital pad auto-hold status",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLR_DG_PAD_AUTOHOLD": {
+                    "description": "wtite only register to clear digital pad auto-hold",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DG_PAD_AUTOHOLD_EN": {
+                    "description": "digital pad enable auto-hold",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_NOISO": {
+                    "description": "digital pad force no ISO",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_ISO": {
+                    "description": "digital pad force ISO",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_UNHOLD": {
+                    "description": "digital pad force un-hold",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_HOLD": {
+                    "description": "digital pad force hold",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BT_FORCE_ISO": {
+                    "description": "bt force ISO",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BT_FORCE_NOISO": {
+                    "description": "bt force no ISO",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_ISO": {
+                    "description": "Digital peri force ISO",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_NOISO": {
+                    "description": "digital peri force no ISO",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_ISO": {
+                    "description": "cpu force ISO",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_NOISO": {
+                    "description": "cpu force no ISO",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_ISO": {
+                    "description": "wifi force ISO",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_NOISO": {
+                    "description": "wifi force no ISO",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_ISO": {
+                    "description": "digital core force ISO",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_NOISO": {
+                    "description": "digital core force no ISO",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG0": {
+              "description": "rtc configure register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 78356,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_CHIP_RESET_WIDTH": {
+                    "description": "chip reset siginal pulse width",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "WDT_CHIP_RESET_EN": {
+                    "description": "wdt reset whole chip enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WDT_PAUSE_IN_SLP": {
+                    "description": "pause WDT in sleep",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WDT_APPCPU_RESET_EN": {
+                    "description": "enable WDT reset APP CPU",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WDT_PROCPU_RESET_EN": {
+                    "description": "enable WDT reset PRO CPU",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WDT_FLASHBOOT_MOD_EN": {
+                    "description": "enable WDT in flash boot",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WDT_SYS_RESET_LENGTH": {
+                    "description": "system reset counter length",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "WDT_CPU_RESET_LENGTH": {
+                    "description": "CPU reset counter length",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "WDT_STG3": {
+                    "description": "1: interrupt stage en",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "WDT_STG2": {
+                    "description": "1: interrupt stage en",
+                    "offset": 22,
+                    "size": 3
+                  },
+                  "WDT_STG1": {
+                    "description": "1: interrupt stage en",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "WDT_STG0": {
+                    "description": "1: interrupt stage en",
+                    "offset": 28,
+                    "size": 3
+                  },
+                  "WDT_EN": {
+                    "description": "enable rtc wdt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG1": {
+              "description": "rtc configure register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 200000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG0_HOLD": {
+                    "description": "the hold time of stage0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG2": {
+              "description": "rtc configure register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 80000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG1_HOLD": {
+                    "description": "the hold time of stage1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG3": {
+              "description": "rtc configure register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG2_HOLD": {
+                    "description": "the hold time of stage2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG4": {
+              "description": "rtc configure register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG3_HOLD": {
+                    "description": "the hold time of stage3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTFEED": {
+              "description": "rtc configure register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_WDT_FEED": {
+                    "description": "sw feed rtc wdt",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTWPROTECT": {
+              "description": "rtc configure register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_WKEY": {
+                    "description": "the key of rtc wdt",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SWD_CONF": {
+              "description": "rtc configure register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 78643200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWD_RESET_FLAG": {
+                    "description": "swd reset flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWD_FEED_INT": {
+                    "description": "swd interrupt for feeding",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWD_BYPASS_RST": {
+                    "description": "Bypass swd rst",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWD_SIGNAL_WIDTH": {
+                    "description": "adjust signal width send to swd",
+                    "offset": 18,
+                    "size": 10
+                  },
+                  "SWD_RST_FLAG_CLR": {
+                    "description": "reset swd reset flag",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SWD_FEED": {
+                    "description": "Sw feed swd",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SWD_DISABLE": {
+                    "description": "disabel SWD",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SWD_AUTO_FEED_EN": {
+                    "description": "automatically feed swd when int comes",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWD_WPROTECT": {
+              "description": "rtc configure register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWD_WKEY": {
+                    "description": "the key of super wdt",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SW_CPU_STALL": {
+              "description": "rtc configure register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_STALL_APPCPU_C1": {
+                    "description": "{reg_sw_stall_appcpu_c1[5:0]",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "SW_STALL_PROCPU_C1": {
+                    "description": "stall cpu by software",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "STORE4": {
+              "description": "rtc configure register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH4": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE5": {
+              "description": "rtc configure register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH5": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE6": {
+              "description": "rtc configure register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH6": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE7": {
+              "description": "rtc configure register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH7": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOW_POWER_ST": {
+              "description": "rtc configure register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XPD_ROM0": {
+                    "description": "rom0 power down",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_DIG_DCDC": {
+                    "description": "External DCDC power down",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_PERI_ISO": {
+                    "description": "rtc peripheral iso",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_RTC_PERI": {
+                    "description": "rtc peripheral power down",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WIFI_ISO": {
+                    "description": "wifi iso",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_WIFI": {
+                    "description": "wifi wrap power down",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIG_ISO": {
+                    "description": "digital wrap iso",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_DIG": {
+                    "description": "digital wrap power down",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_START": {
+                    "description": "touch should start to work",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_SWITCH": {
+                    "description": "touch is about to working. Switch rtc main state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_SLP": {
+                    "description": "touch is in sleep state",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_DONE": {
+                    "description": "touch is done",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_START": {
+                    "description": "ulp/cocpu should start to work",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_SWITCH": {
+                    "description": "ulp/cocpu is about to working. Switch rtc main state",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_SLP": {
+                    "description": "ulp/cocpu is in sleep state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_DONE": {
+                    "description": "ulp/cocpu is done",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_XTAL_ISO": {
+                    "description": "no use any more",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_PLL_ON": {
+                    "description": "rtc main state machine is in states that pll should be running",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_RDY_FOR_WAKEUP": {
+                    "description": "rtc is ready to receive wake up trigger from wake up source",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_WAIT_END": {
+                    "description": "rtc main state machine has been waited for some cycles",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_IN_WAKEUP_STATE": {
+                    "description": "rtc main state machine is in the states of wakeup process",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_IN_LOW_POWER_STATE": {
+                    "description": "rtc main state machine is in the states of low power",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_8M": {
+                    "description": "rtc main state machine is in wait 8m state",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_PLL": {
+                    "description": "rtc main state machine is in wait pll state",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_XTL": {
+                    "description": "rtc main state machine is in wait xtal state",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_SLP": {
+                    "description": "rtc main state machine is in sleep state",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_IDLE": {
+                    "description": "rtc main state machine is in idle state",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE": {
+                    "description": "rtc main state machine status",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIAG0": {
+              "description": "rtc configure register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_LOW_POWER_DIAG1": {
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PAD_HOLD": {
+              "description": "rtc configure register",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_PIN0_HOLD": {
+                    "description": "the hold configure of rtc gpio0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_HOLD": {
+                    "description": "the hold configure of rtc gpio1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_HOLD": {
+                    "description": "the hold configure of rtc gpio2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_HOLD": {
+                    "description": "the hold configure of rtc gpio3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_HOLD": {
+                    "description": "the hold configure of rtc gpio4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_HOLD": {
+                    "description": "the hold configure of rtc gpio5",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_PAD_HOLD": {
+              "description": "rtc configure register",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIG_PAD_HOLD": {
+                    "description": "the configure of digital pad",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BROWN_OUT": {
+              "description": "rtc configure register",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 1140785168,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_WAIT": {
+                    "description": "brown out interrupt wait cycles",
+                    "offset": 4,
+                    "size": 10
+                  },
+                  "CLOSE_FLASH_ENA": {
+                    "description": "enable close flash when brown out happens",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PD_RF_ENA": {
+                    "description": "enable power down RF when brown out happens",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RST_WAIT": {
+                    "description": "brown out reset wait cycles",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "RST_ENA": {
+                    "description": "enable brown out reset",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RST_SEL": {
+                    "description": "1:  4-pos reset",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ANA_RST_EN": {
+                    "description": "brown_out origin reset enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CNT_CLR": {
+                    "description": "clear brown out counter",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ENA": {
+                    "description": "enable brown out",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DET": {
+                    "description": "the flag of brown det from analog",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_LOW1": {
+              "description": "rtc configure register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE1_LOW": {
+                    "description": "RTC timer low 32 bits",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_HIGH1": {
+              "description": "rtc configure register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE1_HIGH": {
+                    "description": "RTC timer high 16 bits",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "XTAL32K_CLK_FACTOR": {
+              "description": "rtc configure register",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_CLK_FACTOR": {
+                    "description": "xtal 32k watch dog backup clock factor",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "XTAL32K_CONF": {
+              "description": "rtc configure register",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 267386880,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_RETURN_WAIT": {
+                    "description": "cycles to wait to return noral xtal 32k",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "XTAL32K_RESTART_WAIT": {
+                    "description": "cycles to wait to repower on xtal 32k",
+                    "offset": 4,
+                    "size": 16
+                  },
+                  "XTAL32K_WDT_TIMEOUT": {
+                    "description": "If no clock detected for this amount of time",
+                    "offset": 20,
+                    "size": 8
+                  },
+                  "XTAL32K_STABLE_THRES": {
+                    "description": "if restarted xtal32k period is smaller than this",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "USB_CONF": {
+              "description": "rtc configure register",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IO_MUX_RESET_DISABLE": {
+                    "description": "disable io_mux reset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_REJECT_CAUSE": {
+              "description": "RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REJECT_CAUSE": {
+                    "description": "sleep reject cause",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OPTION1": {
+              "description": "rtc configure register",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FORCE_DOWNLOAD_BOOT": {
+                    "description": "force chip entry download mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_WAKEUP_CAUSE": {
+              "description": "RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WAKEUP_CAUSE": {
+                    "description": "sleep wakeup cause",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ULP_CP_TIMER_1": {
+              "description": "rtc configure register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 51200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ULP_CP_TIMER_SLP_CYCLE": {
+                    "description": "sleep cycles for ULP-coprocessor timer",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC_W1TS": {
+              "description": "rtc configure register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA_W1TS": {
+                    "description": "enable sleep wakeup interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_ENA_W1TS": {
+                    "description": "enable sleep reject interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_ENA_W1TS": {
+                    "description": "enable RTC WDT interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ENA_W1TS": {
+                    "description": "enable brown out interrupt",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA_W1TS": {
+                    "description": "enable RTC main timer interrupt",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_ENA_W1TS": {
+                    "description": "enable super watch dog interrupt",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA_W1TS": {
+                    "description": "enable xtal32k_dead  interrupt",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ENA_W1TS": {
+                    "description": "enbale gitch det interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA_W1TS": {
+                    "description": "enbale bbpll cal interrupt",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC_W1TC": {
+              "description": "rtc configure register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA_W1TC": {
+                    "description": "clear sleep wakeup interrupt enable",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_ENA_W1TC": {
+                    "description": "clear sleep reject interrupt enable",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_ENA_W1TC": {
+                    "description": "clear RTC WDT interrupt enable",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ENA_W1TC": {
+                    "description": "clear brown out interrupt enable",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA_W1TC": {
+                    "description": "Clear RTC main timer interrupt enable",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_ENA_W1TC": {
+                    "description": "clear super watch dog interrupt enable",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA_W1TC": {
+                    "description": "clear xtal32k_dead  interrupt enable",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ENA_W1TC": {
+                    "description": "clear gitch det interrupt enable",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA_W1TC": {
+                    "description": "clear bbpll cal interrupt enable",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RETENTION_CTRL": {
+              "description": "rtc configure register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 2697986048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RETENTION_CLK_SEL": {
+                    "description": "Retention clk sel",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RETENTION_DONE_WAIT": {
+                    "description": "Retention done wait time",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "RETENTION_CLKOFF_WAIT": {
+                    "description": "Retention clkoff wait time",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "RETENTION_EN": {
+                    "description": "enable cpu retention when light sleep",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RETENTION_WAIT": {
+                    "description": "wait cycles for rention operation",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "FIB_SEL": {
+              "description": "rtc configure register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_FIB_SEL": {
+                    "description": "select use analog fib signal",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "GPIO_WAKEUP": {
+              "description": "rtc configure register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_WAKEUP_STATUS": {
+                    "description": "rtc gpio wakeup flag",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "RTC_GPIO_WAKEUP_STATUS_CLR": {
+                    "description": "clear rtc gpio wakeup flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN_CLK_GATE": {
+                    "description": "enable rtc io clk gate",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN4_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN3_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 14,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN2_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN1_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN0_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 23,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN5_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio5",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio4",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio3",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio2",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio1",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN0_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio0",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBG_SEL": {
+              "description": "rtc configure register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_DEBUG_12M_NO_GATING": {
+                    "description": "use for debug",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_DEBUG_BIT_SEL": {
+                    "description": "use for debug",
+                    "offset": 2,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL0": {
+                    "description": "use for debug",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL1": {
+                    "description": "use for debug",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL2": {
+                    "description": "use for debug",
+                    "offset": 17,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL3": {
+                    "description": "use for debug",
+                    "offset": 22,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL4": {
+                    "description": "use for debug",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DBG_MAP": {
+              "description": "rtc configure register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_PIN5_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN0_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN4_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN3_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN2_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN1_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN0_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SENSOR_CTRL": {
+              "description": "rtc configure register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAR2_PWDET_CCT": {
+                    "description": "reg_sar2_pwdet_cct",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "FORCE_XPD_SAR": {
+                    "description": "force power up SAR",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DBG_SAR_SEL": {
+              "description": "rtc configure register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAR_DEBUG_SEL": {
+                    "description": "use for debug",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "PG_CTRL": {
+              "description": "rtc configure register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POWER_GLITCH_DSENSE": {
+                    "description": "power glitch desense",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "POWER_GLITCH_FORCE_PD": {
+                    "description": "force disable power glitch",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_FORCE_PU": {
+                    "description": "force enable power glitch",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_EFUSE_SEL": {
+                    "description": "use efuse value control power glitch enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_EN": {
+                    "description": "enable power glitch",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "rtc configure register",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33583728,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CNTL_DATE": {
+                    "description": "verision",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SENSITIVE": {
+        "description": "Sensitive",
+        "children": {
+          "registers": {
+            "ROM_TABLE_LOCK": {
+              "description": "SENSITIVE_ROM_TABLE_LOCK_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_TABLE_LOCK": {
+                    "description": "rom_table_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ROM_TABLE": {
+              "description": "SENSITIVE_ROM_TABLE_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_TABLE": {
+                    "description": "rom_table",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PRIVILEGE_MODE_SEL_LOCK": {
+              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRIVILEGE_MODE_SEL_LOCK": {
+                    "description": "privilege_mode_sel_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PRIVILEGE_MODE_SEL": {
+              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRIVILEGE_MODE_SEL": {
+                    "description": "privilege_mode_sel",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB_PERIPHERAL_ACCESS_0": {
+              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_PERIPHERAL_ACCESS_LOCK": {
+                    "description": "apb_peripheral_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB_PERIPHERAL_ACCESS_1": {
+              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_PERIPHERAL_ACCESS_SPLIT_BURST": {
+                    "description": "apb_peripheral_access_split_burst",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_0": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_0_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_LOCK": {
+                    "description": "internal_sram_usage_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_1": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_1_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_CPU_CACHE": {
+                    "description": "internal_sram_usage_cpu_cache",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTERNAL_SRAM_USAGE_CPU_SRAM": {
+                    "description": "internal_sram_usage_cpu_sram",
+                    "offset": 1,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_3": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_3_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM": {
+                    "description": "internal_sram_usage_mac_dump_sram",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "INTERNAL_SRAM_ALLOC_MAC_DUMP": {
+                    "description": "internal_sram_alloc_mac_dump",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_4": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_4_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_LOG_SRAM": {
+                    "description": "internal_sram_usage_log_sram",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_TAG_ACCESS_0": {
+              "description": "SENSITIVE_CACHE_TAG_ACCESS_0_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_TAG_ACCESS_LOCK": {
+                    "description": "cache_tag_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_TAG_ACCESS_1": {
+              "description": "SENSITIVE_CACHE_TAG_ACCESS_1_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRO_I_TAG_RD_ACS": {
+                    "description": "pro_i_tag_rd_acs",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PRO_I_TAG_WR_ACS": {
+                    "description": "pro_i_tag_wr_acs",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRO_D_TAG_RD_ACS": {
+                    "description": "pro_d_tag_rd_acs",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRO_D_TAG_WR_ACS": {
+                    "description": "pro_d_tag_wr_acs",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_ACCESS_0": {
+              "description": "SENSITIVE_CACHE_MMU_ACCESS_0_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_ACCESS_LOCK": {
+                    "description": "cache_mmu_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_ACCESS_1": {
+              "description": "SENSITIVE_CACHE_MMU_ACCESS_1_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRO_MMU_RD_ACS": {
+                    "description": "pro_mmu_rd_acs",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PRO_MMU_WR_ACS": {
+                    "description": "pro_mmu_wr_acs",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_spi2_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_MAC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_mac_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_MAC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_backup_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_LC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_lc_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_LC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_AES_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_aes_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_AES_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SHA_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_sha_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SHA_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_0": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_LOCK": {
+                    "description": "dma_apbperi_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_1": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "dma_apbperi_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "dma_apbperi_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_2": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "dma_apbperi_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_world",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_addr",
+                    "offset": 3,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_3": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_wr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_byteen",
+                    "offset": 1,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK": {
+                    "description": "core_x_iram0_dram0_dma_split_line_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR": {
+                    "description": "core_x_iram0_dram0_dma_sram_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0": {
+                    "description": "core_x_iram0_sram_line_0_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1": {
+                    "description": "core_x_iram0_sram_line_0_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2": {
+                    "description": "core_x_iram0_sram_line_0_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR": {
+                    "description": "core_x_iram0_sram_line_0_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0": {
+                    "description": "core_x_iram0_sram_line_1_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1": {
+                    "description": "core_x_iram0_sram_line_1_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2": {
+                    "description": "core_x_iram0_sram_line_1_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR": {
+                    "description": "core_x_iram0_sram_line_1_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR": {
+                    "description": "core_x_dram0_dma_sram_line_0_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR": {
+                    "description": "core_x_dram0_dma_sram_line_1_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_x_iram0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 1867775,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
+                    "description": "core_x_iram0_pms_constrain_rom_world_1_pms",
+                    "offset": 18,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 1867775,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
+                    "description": "core_x_iram0_pms_constrain_rom_world_0_pms",
+                    "offset": 18,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_LOCK": {
+                    "description": "core_0_iram0_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_iram0_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_iram0_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_iram0_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_wr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_loadstore",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_world",
+                    "offset": 3,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_addr",
+                    "offset": 5,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_DRAM0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_x_dram0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_DRAM0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 252702975,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
+                    "description": "core_x_dram0_pms_constrain_rom_world_0_pms",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
+                    "description": "core_x_dram0_pms_constrain_rom_world_1_pms",
+                    "offset": 26,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_LOCK": {
+                    "description": "core_0_dram0_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_dram0_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_dram0_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_dram0_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_lock",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_world",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_addr",
+                    "offset": 4,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_3": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_wr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_byteen",
+                    "offset": 1,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_0_pif_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART": {
+                    "description": "core_0_pif_pms_constrain_world_0_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1": {
+                    "description": "core_0_pif_pms_constrain_world_0_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0": {
+                    "description": "core_0_pif_pms_constrain_world_0_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO": {
+                    "description": "core_0_pif_pms_constrain_world_0_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2": {
+                    "description": "core_0_pif_pms_constrain_world_0_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE": {
+                    "description": "core_0_pif_pms_constrain_world_0_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER": {
+                    "description": "core_0_pif_pms_constrain_world_0_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC": {
+                    "description": "core_0_pif_pms_constrain_world_0_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX": {
+                    "description": "core_0_pif_pms_constrain_world_0_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG": {
+                    "description": "core_0_pif_pms_constrain_world_0_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC": {
+                    "description": "core_0_pif_pms_constrain_world_0_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1": {
+                    "description": "core_0_pif_pms_constrain_world_0_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT": {
+                    "description": "core_0_pif_pms_constrain_world_0_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0": {
+                    "description": "core_0_pif_pms_constrain_world_0_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT": {
+                    "description": "core_0_pif_pms_constrain_world_0_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC": {
+                    "description": "core_0_pif_pms_constrain_world_0_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB": {
+                    "description": "core_0_pif_pms_constrain_world_0_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP": {
+                    "description": "core_0_pif_pms_constrain_world_0_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1": {
+                    "description": "core_0_pif_pms_constrain_world_0_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER": {
+                    "description": "core_0_pif_pms_constrain_world_0_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2": {
+                    "description": "core_0_pif_pms_constrain_world_0_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL": {
+                    "description": "core_0_pif_pms_constrain_world_0_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN": {
+                    "description": "core_0_pif_pms_constrain_world_0_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT": {
+                    "description": "core_0_pif_pms_constrain_world_0_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC": {
+                    "description": "core_0_pif_pms_constrain_world_0_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_0_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 4294964220,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP": {
+                    "description": "core_0_pif_pms_constrain_world_0_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI": {
+                    "description": "core_0_pif_pms_constrain_world_0_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA": {
+                    "description": "core_0_pif_pms_constrain_world_0_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC": {
+                    "description": "core_0_pif_pms_constrain_world_0_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_0_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE": {
+                    "description": "core_0_pif_pms_constrain_world_0_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM": {
+                    "description": "core_0_pif_pms_constrain_world_0_system",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE": {
+                    "description": "core_0_pif_pms_constrain_world_0_sensitive",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT": {
+                    "description": "core_0_pif_pms_constrain_world_0_interrupt",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY": {
+                    "description": "core_0_pif_pms_constrain_world_0_dma_copy",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG": {
+                    "description": "core_0_pif_pms_constrain_world_0_cache_config",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD": {
+                    "description": "core_0_pif_pms_constrain_world_0_ad",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO": {
+                    "description": "core_0_pif_pms_constrain_world_0_dio",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER": {
+                    "description": "core_0_pif_pms_constrain_world_0_world_controller",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_5": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART": {
+                    "description": "core_0_pif_pms_constrain_world_1_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1": {
+                    "description": "core_0_pif_pms_constrain_world_1_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0": {
+                    "description": "core_0_pif_pms_constrain_world_1_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO": {
+                    "description": "core_0_pif_pms_constrain_world_1_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2": {
+                    "description": "core_0_pif_pms_constrain_world_1_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE": {
+                    "description": "core_0_pif_pms_constrain_world_1_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER": {
+                    "description": "core_0_pif_pms_constrain_world_1_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC": {
+                    "description": "core_0_pif_pms_constrain_world_1_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX": {
+                    "description": "core_0_pif_pms_constrain_world_1_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG": {
+                    "description": "core_0_pif_pms_constrain_world_1_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC": {
+                    "description": "core_0_pif_pms_constrain_world_1_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1": {
+                    "description": "core_0_pif_pms_constrain_world_1_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_6": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT": {
+                    "description": "core_0_pif_pms_constrain_world_1_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0": {
+                    "description": "core_0_pif_pms_constrain_world_1_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT": {
+                    "description": "core_0_pif_pms_constrain_world_1_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC": {
+                    "description": "core_0_pif_pms_constrain_world_1_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB": {
+                    "description": "core_0_pif_pms_constrain_world_1_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP": {
+                    "description": "core_0_pif_pms_constrain_world_1_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1": {
+                    "description": "core_0_pif_pms_constrain_world_1_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER": {
+                    "description": "core_0_pif_pms_constrain_world_1_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_7": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2": {
+                    "description": "core_0_pif_pms_constrain_world_1_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL": {
+                    "description": "core_0_pif_pms_constrain_world_1_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN": {
+                    "description": "core_0_pif_pms_constrain_world_1_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT": {
+                    "description": "core_0_pif_pms_constrain_world_1_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC": {
+                    "description": "core_0_pif_pms_constrain_world_1_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_1_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_8": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 4294964220,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP": {
+                    "description": "core_0_pif_pms_constrain_world_1_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI": {
+                    "description": "core_0_pif_pms_constrain_world_1_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA": {
+                    "description": "core_0_pif_pms_constrain_world_1_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC": {
+                    "description": "core_0_pif_pms_constrain_world_1_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_1_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE": {
+                    "description": "core_0_pif_pms_constrain_world_1_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM": {
+                    "description": "core_0_pif_pms_constrain_world_1_system",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE": {
+                    "description": "core_0_pif_pms_constrain_world_1_sensitive",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT": {
+                    "description": "core_0_pif_pms_constrain_world_1_interrupt",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY": {
+                    "description": "core_0_pif_pms_constrain_world_1_dma_copy",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG": {
+                    "description": "core_0_pif_pms_constrain_world_1_cache_config",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD": {
+                    "description": "core_0_pif_pms_constrain_world_1_ad",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO": {
+                    "description": "core_0_pif_pms_constrain_world_1_dio",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER": {
+                    "description": "core_0_pif_pms_constrain_world_1_world_controller",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_9": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 4194303,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
+                    "offset": 11,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_10": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_l",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_h",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_l",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_h",
+                    "offset": 9,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_0_REG",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_LOCK": {
+                    "description": "region_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_1_REG",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_0": {
+                    "description": "region_pms_constrain_world_0_area_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_1": {
+                    "description": "region_pms_constrain_world_0_area_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_2": {
+                    "description": "region_pms_constrain_world_0_area_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_3": {
+                    "description": "region_pms_constrain_world_0_area_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_4": {
+                    "description": "region_pms_constrain_world_0_area_4",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_5": {
+                    "description": "region_pms_constrain_world_0_area_5",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_6": {
+                    "description": "region_pms_constrain_world_0_area_6",
+                    "offset": 12,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_2_REG",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_0": {
+                    "description": "region_pms_constrain_world_1_area_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_1": {
+                    "description": "region_pms_constrain_world_1_area_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_2": {
+                    "description": "region_pms_constrain_world_1_area_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_3": {
+                    "description": "region_pms_constrain_world_1_area_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_4": {
+                    "description": "region_pms_constrain_world_1_area_4",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_5": {
+                    "description": "region_pms_constrain_world_1_area_5",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_6": {
+                    "description": "region_pms_constrain_world_1_area_6",
+                    "offset": 12,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_3_REG",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_0": {
+                    "description": "region_pms_constrain_addr_0",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_4_REG",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_1": {
+                    "description": "region_pms_constrain_addr_1",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_5": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_5_REG",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_2": {
+                    "description": "region_pms_constrain_addr_2",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_6": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_6_REG",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_3": {
+                    "description": "region_pms_constrain_addr_3",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_7": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_7_REG",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_4": {
+                    "description": "region_pms_constrain_addr_4",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_8": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_8_REG",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_5": {
+                    "description": "region_pms_constrain_addr_5",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_9": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_9_REG",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_6": {
+                    "description": "region_pms_constrain_addr_6",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_10": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_10_REG",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_7": {
+                    "description": "region_pms_constrain_addr_7",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_LOCK": {
+                    "description": "core_0_pif_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_pif_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_pif_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_pif_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hport_0",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hsize",
+                    "offset": 2,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hwrite",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hworld",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_3": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR": {
+                    "description": "core_0_pif_pms_monitor_violate_status_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_4": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_5": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hsize",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hworld",
+                    "offset": 3,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_6": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_LOCK": {
+                    "description": "backup_bus_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_UART": {
+                    "description": "backup_bus_pms_constrain_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1": {
+                    "description": "backup_bus_pms_constrain_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0": {
+                    "description": "backup_bus_pms_constrain_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_GPIO": {
+                    "description": "backup_bus_pms_constrain_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_FE2": {
+                    "description": "backup_bus_pms_constrain_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_FE": {
+                    "description": "backup_bus_pms_constrain_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMER": {
+                    "description": "backup_bus_pms_constrain_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RTC": {
+                    "description": "backup_bus_pms_constrain_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_IO_MUX": {
+                    "description": "backup_bus_pms_constrain_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_WDG": {
+                    "description": "backup_bus_pms_constrain_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_MISC": {
+                    "description": "backup_bus_pms_constrain_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2C": {
+                    "description": "backup_bus_pms_constrain_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_UART1": {
+                    "description": "backup_bus_pms_constrain_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_BT": {
+                    "description": "backup_bus_pms_constrain_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0": {
+                    "description": "backup_bus_pms_constrain_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_UHCI0": {
+                    "description": "backup_bus_pms_constrain_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RMT": {
+                    "description": "backup_bus_pms_constrain_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_LEDC": {
+                    "description": "backup_bus_pms_constrain_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_BB": {
+                    "description": "backup_bus_pms_constrain_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP": {
+                    "description": "backup_bus_pms_constrain_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1": {
+                    "description": "backup_bus_pms_constrain_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER": {
+                    "description": "backup_bus_pms_constrain_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_SPI_2": {
+                    "description": "backup_bus_pms_constrain_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL": {
+                    "description": "backup_bus_pms_constrain_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CAN": {
+                    "description": "backup_bus_pms_constrain_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2S1": {
+                    "description": "backup_bus_pms_constrain_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RWBT": {
+                    "description": "backup_bus_pms_constrain_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC": {
+                    "description": "backup_bus_pms_constrain_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_PWR": {
+                    "description": "backup_bus_pms_constrain_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 62460,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP": {
+                    "description": "backup_bus_pms_constrain_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI": {
+                    "description": "backup_bus_pms_constrain_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA": {
+                    "description": "backup_bus_pms_constrain_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_APB_ADC": {
+                    "description": "backup_bus_pms_constrain_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_BT_PWR": {
+                    "description": "backup_bus_pms_constrain_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE": {
+                    "description": "backup_bus_pms_constrain_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_0": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_LOCK": {
+                    "description": "backup_bus_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_1": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "backup_bus_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "backup_bus_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_2": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "backup_bus_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS": {
+                    "description": "backup_bus_pms_monitor_violate_status_htrans",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
+                    "description": "backup_bus_pms_monitor_violate_status_hsize",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
+                    "description": "backup_bus_pms_monitor_violate_status_hwrite",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_3": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR": {
+                    "description": "backup_bus_pms_monitor_violate_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SENSITIVE_CLOCK_GATE_REG",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "SENSITIVE_DATE_REG",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 33620480,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SHA": {
+        "description": "SHA (Secure Hash Algorithm) Accelerator",
+        "children": {
+          "registers": {
+            "MODE": {
+              "description": "Initial configuration register.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Sha mode.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "T_STRING": {
+              "description": "SHA 512/t configuration register 0.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T_STRING": {
+                    "description": "Sha t_string (used if and only if mode == SHA_512/t).",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T_LENGTH": {
+              "description": "SHA 512/t configuration register 1.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T_LENGTH": {
+                    "description": "Sha t_length (used if and only if mode == SHA_512/t).",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "DMA_BLOCK_NUM": {
+              "description": "DMA configuration register 0.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_BLOCK_NUM": {
+                    "description": "Dma-sha block number.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "START": {
+              "description": "Typical SHA configuration register 0.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "START": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 31,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CONTINUE": {
+              "description": "Typical SHA configuration register 1.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONTINUE": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 31,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BUSY": {
+              "description": "Busy register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Sha busy state. 1'b0: idle. 1'b1: busy.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMA_START": {
+              "description": "DMA configuration register 1.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_START": {
+                    "description": "Start dma-sha.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_CONTINUE": {
+              "description": "DMA configuration register 2.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CONTINUE": {
+                    "description": "Continue dma-sha.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLEAR_IRQ": {
+              "description": "Interrupt clear register.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLEAR_INTERRUPT": {
+                    "description": "Clear sha interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "IRQ_ENA": {
+              "description": "Interrupt enable register.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT_ENA": {
+                    "description": "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Date register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 538969622,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Sha date information/ sha version information.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "H_MEM": {
+              "description": "Sha H memory which contains intermediate hash or finial hash.",
+              "offset": 64,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_MEM": {
+              "description": "Sha M memory which contains message.",
+              "offset": 128,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SPI0 control register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2891776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FDUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FASTRD_MODE": {
+                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FREAD_DIO": {
+                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FREAD_QIO": {
+                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTRL1": {
+              "description": "SPI0 control1 register.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "RXFIFO_RST": {
+                    "description": "SPI0 RX FIFO reset signal.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "SPI0 control2 register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS_SETUP_TIME": {
+                    "description": "(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "CS_HOLD_TIME": {
+                    "description": "Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "CS_HOLD_DELAY": {
+                    "description": "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.",
+                    "offset": 25,
+                    "size": 6
+                  },
+                  "SYNC_RESET": {
+                    "description": "The FSM will be reset.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI clock division control register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 196867,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "Set this bit in 1-division mode.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI0 user register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS_HOLD": {
+                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CS_SETUP": {
+                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "spi clock is disable in dummy phase when the bit is enable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation.",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI0 user1 register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 1543503879,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI0 user2 register.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1879048192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RD_STATUS": {
+              "description": "SPI0 read control register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WB_MODE": {
+                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI0 misc register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRANS_END": {
+                    "description": "The bit is used to indicate the  spi0_mst_st controlled transmitting is done.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TRANS_END_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CSPI_ST_TRANS_END": {
+                    "description": "The bit is used to indicate the  spi0_slv_st controlled transmitting is done.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CSPI_ST_TRANS_END_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_FCTRL": {
+              "description": "SPI0 bit mode control register.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_REQ_EN": {
+                    "description": "For SPI0, Cache access enable, 1: enable, 0:disable.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_USR_ADDR_4BYTE": {
+                    "description": "For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_FLASH_USR_CMD": {
+                    "description": "For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FDIN_DUAL": {
+                    "description": "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FDOUT_DUAL": {
+                    "description": "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FDIN_QUAD": {
+                    "description": "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FDOUT_QUAD": {
+                    "description": "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FSM": {
+              "description": "SPI0 FSM status register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSPI_ST": {
+                    "description": "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "EM_ST": {
+                    "description": "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CSPI_LOCK_DELAY_TIME": {
+                    "description": "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.",
+                    "offset": 7,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMING_CALI": {
+              "description": "SPI0 timing calibration register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMING_CLK_ENA": {
+                    "description": "The bit is used to enable timing adjust clock for all reading operations.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIMING_CALI": {
+                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXTRA_DUMMY_CYCLELEN": {
+                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
+                    "offset": 2,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIN_MODE": {
+              "description": "SPI0 input delay mode control register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DIN_NUM": {
+              "description": "SPI0 input delay number control register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DOUT_MODE": {
+              "description": "SPI0 output delay mode control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUT0_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DOUT1_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DOUT2_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DOUT3_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SPI0 clk_gate register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_CLK_SEL": {
+              "description": "SPI0 module clock select register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI01_CLK_SEL": {
+                    "description": "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583408,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "SPI register version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CMD": {
+              "description": "SPI1 memory command register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI1_MST_ST": {
+                    "description": "The current status of SPI1 master FSM.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "MSPI_ST": {
+                    "description": "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "FLASH_PE": {
+                    "description": "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USR": {
+                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FLASH_HPM": {
+                    "description": "Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FLASH_RES": {
+                    "description": "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FLASH_DP": {
+                    "description": "Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FLASH_CE": {
+                    "description": "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FLASH_BE": {
+                    "description": "Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FLASH_SE": {
+                    "description": "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FLASH_PP": {
+                    "description": "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FLASH_WRSR": {
+                    "description": "Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FLASH_RDSR": {
+                    "description": "Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FLASH_RDID": {
+                    "description": "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FLASH_WRDI": {
+                    "description": "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FLASH_WREN": {
+                    "description": "Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FLASH_READ": {
+                    "description": "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADDR": {
+              "description": "SPI1 address register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_ADDR_VALUE": {
+                    "description": "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "SPI1 control register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2924544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FDUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FCS_CRC_EN": {
+                    "description": "For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TX_CRC_EN": {
+                    "description": "For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FASTRD_MODE": {
+                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RESANDRES": {
+                    "description": "The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "WRSR_2B": {
+                    "description": "two bytes data will be written to status register when it is set. 1: enable 0: disable.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FREAD_DIO": {
+                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FREAD_QIO": {
+                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTRL1": {
+              "description": "SPI1 control1 register.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4092,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CS_HOLD_DLY_RES": {
+                    "description": "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.",
+                    "offset": 2,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "SPI1 control2 register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYNC_RESET": {
+                    "description": "The FSM will be reset.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI1 clock division control register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 196867,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "reserved",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI1 user register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FWRITE_DUAL": {
+                    "description": "In the write operations read-data phase apply 2 signals",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FWRITE_QUAD": {
+                    "description": "In the write operations read-data phase apply 4 signals",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FWRITE_DIO": {
+                    "description": "In the write operations address phase and read-data phase apply 2 signals.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FWRITE_QIO": {
+                    "description": "In the write operations address phase and read-data phase apply 4 signals.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USR_MISO_HIGHPART": {
+                    "description": "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "USR_MOSI_HIGHPART": {
+                    "description": "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "SPI clock is disable in dummy phase when the bit is enable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_MOSI": {
+                    "description": "This bit enable the write-data phase of an operation.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_MISO": {
+                    "description": "This bit enable the read-data phase of an operation.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "USR_ADDR": {
+                    "description": "This bit enable the address phase of an operation.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "USR_COMMAND": {
+                    "description": "This bit enable the command phase of an operation.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI1 user1 register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 1543503879,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI1 user2 register.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1879048192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MOSI_DLEN": {
+              "description": "SPI1 send data bit length control register.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_MOSI_DBITLEN": {
+                    "description": "The length in bits of write-data. The register value shall be (bit_num-1).",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "MISO_DLEN": {
+              "description": "SPI1 receive data bit length control register.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_MISO_DBITLEN": {
+                    "description": "The length in bits of  read-data. The register value shall be (bit_num-1).",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "RD_STATUS": {
+              "description": "SPI1 status register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "WB_MODE": {
+                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI1 misc register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS0_DIS": {
+                    "description": "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CS1_DIS": {
+                    "description": "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CRC": {
+              "description": "SPI1 TX CRC data register.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "For SPI1, the value of crc32.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_FCTRL": {
+              "description": "SPI1 bit mode control register.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_USR_ADDR_4BYTE": {
+                    "description": "For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FDIN_DUAL": {
+                    "description": "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FDOUT_DUAL": {
+                    "description": "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FDIN_QUAD": {
+                    "description": "For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FDOUT_QUAD": {
+                    "description": "For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "W0": {
+              "description": "SPI1 memory data buffer0",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF0": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W1": {
+              "description": "SPI1 memory data buffer1",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF1": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W2": {
+              "description": "SPI1 memory data buffer2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF2": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W3": {
+              "description": "SPI1 memory data buffer3",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF3": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W4": {
+              "description": "SPI1 memory data buffer4",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF4": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W5": {
+              "description": "SPI1 memory data buffer5",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF5": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W6": {
+              "description": "SPI1 memory data buffer6",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF6": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W7": {
+              "description": "SPI1 memory data buffer7",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF7": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W8": {
+              "description": "SPI1 memory data buffer8",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF8": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W9": {
+              "description": "SPI1 memory data buffer9",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF9": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W10": {
+              "description": "SPI1 memory data buffer10",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF10": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W11": {
+              "description": "SPI1 memory data buffer11",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF11": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W12": {
+              "description": "SPI1 memory data buffer12",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF12": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W13": {
+              "description": "SPI1 memory data buffer13",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF13": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W14": {
+              "description": "SPI1 memory data buffer14",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF14": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W15": {
+              "description": "SPI1 memory data buffer15",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF15": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_WAITI_CTRL": {
+              "description": "SPI1 wait idle control register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WAITI_DUMMY": {
+                    "description": "The dummy phase enable when wait flash idle (RDSR)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WAITI_CMD": {
+                    "description": "The command to wait flash idle(RDSR).",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "WAITI_DUMMY_CYCLELEN": {
+                    "description": "The dummy cycle length when wait flash idle(RDSR).",
+                    "offset": 10,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "FLASH_SUS_CTRL": {
+              "description": "SPI1 flash suspend control register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 134225920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_PER": {
+                    "description": "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FLASH_PES": {
+                    "description": "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FLASH_PER_WAIT_EN": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLASH_PES_WAIT_EN": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PES_PER_EN": {
+                    "description": "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FLASH_PES_EN": {
+                    "description": "Set this bit to enable Auto-suspending function.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PESR_END_MSK": {
+                    "description": "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].",
+                    "offset": 6,
+                    "size": 16
+                  },
+                  "RD_SUS_2B": {
+                    "description": "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PER_END_EN": {
+                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PES_END_EN": {
+                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "SUS_TIMEOUT_CNT": {
+                    "description": "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "FLASH_SUS_CMD": {
+              "description": "SPI1 flash suspend command register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 357754,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_PER_COMMAND": {
+                    "description": "Program/Erase resume command.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "FLASH_PES_COMMAND": {
+                    "description": "Program/Erase suspend command.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "WAIT_PESR_COMMAND": {
+                    "description": "Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SUS_STATUS": {
+              "description": "SPI1 flash suspend status register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_SUS": {
+                    "description": "The status of flash suspend, only used in SPI1.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "WAIT_PESR_CMD_2B": {
+                    "description": "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FLASH_HPM_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLASH_RES_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FLASH_DP_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FLASH_PER_DLY_128": {
+                    "description": "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FLASH_PES_DLY_128": {
+                    "description": "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SPI0_LOCK_EN": {
+                    "description": "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TIMING_CALI": {
+              "description": "SPI1 timing control register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMING_CALI": {
+                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXTRA_DUMMY_CYCLELEN": {
+                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
+                    "offset": 2,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "SPI1 interrupt enable register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PES_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WPE_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_ST_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MST_ST_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "SPI1 interrupt clear register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PES_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WPE_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_ST_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_ST_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "SPI1 interrupt raw register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PES_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WPE_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_ST_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_ST_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "SPI1 interrupt status register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PES_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WPE_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_ST_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_ST_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SPI1 clk_gate register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583472,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI2": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CMD": {
+              "description": "Command control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONF_BITLEN": {
+                    "description": "Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 18
+                  },
+                  "UPDATE": {
+                    "description": "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "USR": {
+                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADDR": {
+              "description": "Address value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_ADDR_VALUE": {
+                    "description": "Address to slave. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "SPI control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 3932160,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "HOLD_POL": {
+                    "description": "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP_POL": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "RD_BIT_ORDER": {
+                    "description": "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "WR_BIT_ORDER": {
+                    "description": "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI clock control register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2147496003,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 6
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.",
+                    "offset": 12,
+                    "size": 6
+                  },
+                  "CLKDIV_PRE": {
+                    "description": "In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI USER control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 2147483840,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUTDIN": {
+                    "description": "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "QPI_MODE": {
+                    "description": "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSCK_I_EDGE": {
+                    "description": "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CS_HOLD": {
+                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CS_SETUP": {
+                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RSCK_I_EDGE": {
+                    "description": "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FWRITE_DUAL": {
+                    "description": "In the write operations read-data phase apply 2 signals. Can be configured in CONF state.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FWRITE_QUAD": {
+                    "description": "In the write operations read-data phase apply 4 signals. Can be configured in CONF state.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USR_CONF_NXT": {
+                    "description": "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SIO": {
+                    "description": "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USR_MISO_HIGHPART": {
+                    "description": "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "USR_MOSI_HIGHPART": {
+                    "description": "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_MOSI": {
+                    "description": "This bit enable the write-data phase of an operation. Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_MISO": {
+                    "description": "This bit enable the read-data phase of an operation. Can be configured in CONF state.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation. Can be configured in CONF state.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "USR_ADDR": {
+                    "description": "This bit enable the address phase of an operation. Can be configured in CONF state.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "USR_COMMAND": {
+                    "description": "This bit enable the command phase of an operation. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI USER control register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 3091267591,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "MST_WFULL_ERR_END_EN": {
+                    "description": "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CS_SETUP_TIME": {
+                    "description": "(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.",
+                    "offset": 17,
+                    "size": 5
+                  },
+                  "CS_HOLD_TIME": {
+                    "description": "delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.",
+                    "offset": 22,
+                    "size": 5
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI USER control register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 2013265920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MST_REMPTY_ERR_END_EN": {
+                    "description": "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MS_DLEN": {
+              "description": "SPI data bit length control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MS_DATA_BITLEN": {
+                    "description": "The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI misc register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 62,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS0_DIS": {
+                    "description": "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CS1_DIS": {
+                    "description": "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CS2_DIS": {
+                    "description": "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CS3_DIS": {
+                    "description": "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CS4_DIS": {
+                    "description": "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CS5_DIS": {
+                    "description": "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CK_DIS": {
+                    "description": "1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MASTER_CS_POL": {
+                    "description": "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "SLAVE_CS_POL": {
+                    "description": "spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set. Can be configured in CONF state.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "QUAD_DIN_PIN_SWAP": {
+                    "description": "1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN_MODE": {
+              "description": "SPI input delay mode configuration",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TIMING_HCLK_ACTIVE": {
+                    "description": "1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN_NUM": {
+              "description": "SPI input delay number configuration",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DOUT_MODE": {
+              "description": "SPI output delay mode configuration",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUT0_MODE": {
+                    "description": "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DOUT1_MODE": {
+                    "description": "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DOUT2_MODE": {
+                    "description": "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DOUT3_MODE": {
+                    "description": "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_CONF": {
+              "description": "SPI DMA control register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_SLV_SEG_TRANS_EN": {
+                    "description": "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SLV_RX_SEG_TRANS_CLR_EN": {
+                    "description": "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SLV_TX_SEG_TRANS_CLR_EN": {
+                    "description": "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RX_EOF_EN": {
+                    "description": "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DMA_RX_ENA": {
+                    "description": "Set this bit to enable SPI DMA controlled receive data mode.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "DMA_TX_ENA": {
+                    "description": "Set this bit to enable SPI DMA controlled send data mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "RX_AFIFO_RST": {
+                    "description": "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BUF_AFIFO_RST": {
+                    "description": "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_AFIFO_RST": {
+                    "description": "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_INT_ENA": {
+              "description": "SPI DMA interrupt enable register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLV_EX_QPI_INT_ENA": {
+                    "description": "The enable bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_EN_QPI_INT_ENA": {
+                    "description": "The enable bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_CMD7_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SLV_CMD8_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SLV_CMD9_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SLV_CMDA_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SLV_RD_DMA_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WR_DMA_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RD_BUF_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WR_BUF_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TRANS_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SEG_MAGIC_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLV_CMD_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "APP2_INT_ENA": {
+                    "description": "The enable bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "APP1_INT_ENA": {
+                    "description": "The enable bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_INT_CLR": {
+              "description": "SPI DMA interrupt clear register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_EX_QPI_INT_CLR": {
+                    "description": "The clear bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_EN_QPI_INT_CLR": {
+                    "description": "The clear bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD7_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD8_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD9_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMDA_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_RD_DMA_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_WR_DMA_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_RD_BUF_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_WR_BUF_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SEG_MAGIC_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP2_INT_CLR": {
+                    "description": "The clear bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP1_INT_CLR": {
+                    "description": "The clear bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_INT_RAW": {
+              "description": "SPI DMA interrupt raw register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_RAW": {
+                    "description": "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_RAW": {
+                    "description": "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLV_EX_QPI_INT_RAW": {
+                    "description": "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_EN_QPI_INT_RAW": {
+                    "description": "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_CMD7_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SLV_CMD8_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SLV_CMD9_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SLV_CMDA_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SLV_RD_DMA_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WR_DMA_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RD_BUF_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WR_BUF_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TRANS_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SEG_MAGIC_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLV_CMD_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "APP2_INT_RAW": {
+                    "description": "The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "APP1_INT_RAW": {
+                    "description": "The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_INT_ST": {
+              "description": "SPI DMA interrupt status register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_ST": {
+                    "description": "The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_ST": {
+                    "description": "The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_EX_QPI_INT_ST": {
+                    "description": "The status bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_EN_QPI_INT_ST": {
+                    "description": "The status bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD7_INT_ST": {
+                    "description": "The status bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD8_INT_ST": {
+                    "description": "The status bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD9_INT_ST": {
+                    "description": "The status bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMDA_INT_ST": {
+                    "description": "The status bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_RD_DMA_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_WR_DMA_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_RD_BUF_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_WR_BUF_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_DONE_INT_ST": {
+                    "description": "The status bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_ST": {
+                    "description": "The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEG_MAGIC_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_ST": {
+                    "description": "The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_ST": {
+                    "description": "The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP2_INT_ST": {
+                    "description": "The status bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP1_INT_ST": {
+                    "description": "The status bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "W0": {
+              "description": "SPI CPU-controlled buffer0",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF0": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W1": {
+              "description": "SPI CPU-controlled buffer1",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF1": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W2": {
+              "description": "SPI CPU-controlled buffer2",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF2": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W3": {
+              "description": "SPI CPU-controlled buffer3",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF3": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W4": {
+              "description": "SPI CPU-controlled buffer4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF4": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W5": {
+              "description": "SPI CPU-controlled buffer5",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF5": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W6": {
+              "description": "SPI CPU-controlled buffer6",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF6": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W7": {
+              "description": "SPI CPU-controlled buffer7",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF7": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W8": {
+              "description": "SPI CPU-controlled buffer8",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF8": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W9": {
+              "description": "SPI CPU-controlled buffer9",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF9": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W10": {
+              "description": "SPI CPU-controlled buffer10",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF10": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W11": {
+              "description": "SPI CPU-controlled buffer11",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF11": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W12": {
+              "description": "SPI CPU-controlled buffer12",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF12": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W13": {
+              "description": "SPI CPU-controlled buffer13",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF13": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W14": {
+              "description": "SPI CPU-controlled buffer14",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF14": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W15": {
+              "description": "SPI CPU-controlled buffer15",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF15": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SLAVE": {
+              "description": "SPI slave control register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 41943040,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CLK_MODE_13": {
+                    "description": "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RSCK_DATA_OUT": {
+                    "description": "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_RDDMA_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WRDMA_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RDBUF_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WRBUF_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA_SEG_MAGIC_VALUE": {
+                    "description": "The magic value of BM table in master DMA seg-trans.",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "MODE": {
+                    "description": "Set SPI work mode. 1: slave mode 0: master mode.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SOFT_RESET": {
+                    "description": "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "USR_CONF": {
+                    "description": "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLAVE1": {
+              "description": "SPI slave control register 1",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLV_DATA_BITLEN": {
+                    "description": "The transferred data bit length in SPI slave FD and HD mode.",
+                    "offset": 0,
+                    "size": 18
+                  },
+                  "SLV_LAST_COMMAND": {
+                    "description": "In the slave mode it is the value of command.",
+                    "offset": 18,
+                    "size": 8
+                  },
+                  "SLV_LAST_ADDR": {
+                    "description": "In the slave mode it is the value of address.",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CLK_GATE": {
+              "description": "SPI module clock and register clock control",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Set this bit to enable clk gate",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MST_CLK_ACTIVE": {
+                    "description": "Set this bit to power on the SPI module clock.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MST_CLK_SEL": {
+                    "description": "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 33583648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "SPI register version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSTEM": {
+        "description": "System",
+        "children": {
+          "registers": {
+            "CPU_PERI_CLK_EN": {
+              "description": "cpu_peripheral clock gating register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN_ASSIST_DEBUG": {
+                    "description": "reg_clk_en_assist_debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CLK_EN_DEDICATED_GPIO": {
+                    "description": "reg_clk_en_dedicated_gpio",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PERI_RST_EN": {
+              "description": "cpu_peripheral reset register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RST_EN_ASSIST_DEBUG": {
+                    "description": "reg_rst_en_assist_debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RST_EN_DEDICATED_GPIO": {
+                    "description": "reg_rst_en_dedicated_gpio",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PER_CONF": {
+              "description": "cpu clock config register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPUPERIOD_SEL": {
+                    "description": "reg_cpuperiod_sel",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PLL_FREQ_SEL": {
+                    "description": "reg_pll_freq_sel",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPU_WAIT_MODE_FORCE_ON": {
+                    "description": "reg_cpu_wait_mode_force_on",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CPU_WAITI_DELAY_NUM": {
+                    "description": "reg_cpu_waiti_delay_num",
+                    "offset": 4,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_PD_MASK": {
+              "description": "memory power down mask register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSLP_MEM_PD_MASK": {
+                    "description": "reg_lslp_mem_pd_mask",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_CLK_EN0": {
+              "description": "peripheral clock gating register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4190232687,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMERS_CLK_EN": {
+                    "description": "reg_timers_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SPI01_CLK_EN": {
+                    "description": "reg_spi01_clk_en",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART_CLK_EN": {
+                    "description": "reg_uart_clk_en",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDG_CLK_EN": {
+                    "description": "reg_wdg_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "I2S0_CLK_EN": {
+                    "description": "reg_i2s0_clk_en",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UART1_CLK_EN": {
+                    "description": "reg_uart1_clk_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SPI2_CLK_EN": {
+                    "description": "reg_spi2_clk_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "I2C_EXT0_CLK_EN": {
+                    "description": "reg_ext0_clk_en",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UHCI0_CLK_EN": {
+                    "description": "reg_uhci0_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RMT_CLK_EN": {
+                    "description": "reg_rmt_clk_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCNT_CLK_EN": {
+                    "description": "reg_pcnt_clk_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LEDC_CLK_EN": {
+                    "description": "reg_ledc_clk_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UHCI1_CLK_EN": {
+                    "description": "reg_uhci1_clk_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMERGROUP_CLK_EN": {
+                    "description": "reg_timergroup_clk_en",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EFUSE_CLK_EN": {
+                    "description": "reg_efuse_clk_en",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIMERGROUP1_CLK_EN": {
+                    "description": "reg_timergroup1_clk_en",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI3_CLK_EN": {
+                    "description": "reg_spi3_clk_en",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PWM0_CLK_EN": {
+                    "description": "reg_pwm0_clk_en",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EXT1_CLK_EN": {
+                    "description": "reg_ext1_clk_en",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CAN_CLK_EN": {
+                    "description": "reg_can_clk_en",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PWM1_CLK_EN": {
+                    "description": "reg_pwm1_clk_en",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2S1_CLK_EN": {
+                    "description": "reg_i2s1_clk_en",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SPI2_DMA_CLK_EN": {
+                    "description": "reg_spi2_dma_clk_en",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USB_DEVICE_CLK_EN": {
+                    "description": "reg_usb_device_clk_en",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "UART_MEM_CLK_EN": {
+                    "description": "reg_uart_mem_clk_en",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PWM2_CLK_EN": {
+                    "description": "reg_pwm2_clk_en",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PWM3_CLK_EN": {
+                    "description": "reg_pwm3_clk_en",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SPI3_DMA_CLK_EN": {
+                    "description": "reg_spi3_dma_clk_en",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_CLK_EN": {
+                    "description": "reg_apb_saradc_clk_en",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "SYSTIMER_CLK_EN": {
+                    "description": "reg_systimer_clk_en",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ADC2_ARB_CLK_EN": {
+                    "description": "reg_adc2_arb_clk_en",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI4_CLK_EN": {
+                    "description": "reg_spi4_clk_en",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_CLK_EN1": {
+              "description": "peripheral clock gating register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRYPTO_AES_CLK_EN": {
+                    "description": "reg_crypto_aes_clk_en",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CRYPTO_SHA_CLK_EN": {
+                    "description": "reg_crypto_sha_clk_en",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CRYPTO_RSA_CLK_EN": {
+                    "description": "reg_crypto_rsa_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRYPTO_DS_CLK_EN": {
+                    "description": "reg_crypto_ds_clk_en",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRYPTO_HMAC_CLK_EN": {
+                    "description": "reg_crypto_hmac_clk_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMA_CLK_EN": {
+                    "description": "reg_dma_clk_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDIO_HOST_CLK_EN": {
+                    "description": "reg_sdio_host_clk_en",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCD_CAM_CLK_EN": {
+                    "description": "reg_lcd_cam_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UART2_CLK_EN": {
+                    "description": "reg_uart2_clk_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TSENS_CLK_EN": {
+                    "description": "reg_tsens_clk_en",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_RST_EN0": {
+              "description": "reserved",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMERS_RST": {
+                    "description": "reg_timers_rst",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SPI01_RST": {
+                    "description": "reg_spi01_rst",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART_RST": {
+                    "description": "reg_uart_rst",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDG_RST": {
+                    "description": "reg_wdg_rst",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "I2S0_RST": {
+                    "description": "reg_i2s0_rst",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UART1_RST": {
+                    "description": "reg_uart1_rst",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SPI2_RST": {
+                    "description": "reg_spi2_rst",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "I2C_EXT0_RST": {
+                    "description": "reg_ext0_rst",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UHCI0_RST": {
+                    "description": "reg_uhci0_rst",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RMT_RST": {
+                    "description": "reg_rmt_rst",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCNT_RST": {
+                    "description": "reg_pcnt_rst",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LEDC_RST": {
+                    "description": "reg_ledc_rst",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UHCI1_RST": {
+                    "description": "reg_uhci1_rst",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMERGROUP_RST": {
+                    "description": "reg_timergroup_rst",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EFUSE_RST": {
+                    "description": "reg_efuse_rst",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIMERGROUP1_RST": {
+                    "description": "reg_timergroup1_rst",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI3_RST": {
+                    "description": "reg_spi3_rst",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PWM0_RST": {
+                    "description": "reg_pwm0_rst",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EXT1_RST": {
+                    "description": "reg_ext1_rst",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CAN_RST": {
+                    "description": "reg_can_rst",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PWM1_RST": {
+                    "description": "reg_pwm1_rst",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2S1_RST": {
+                    "description": "reg_i2s1_rst",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SPI2_DMA_RST": {
+                    "description": "reg_spi2_dma_rst",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USB_DEVICE_RST": {
+                    "description": "reg_usb_device_rst",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "UART_MEM_RST": {
+                    "description": "reg_uart_mem_rst",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PWM2_RST": {
+                    "description": "reg_pwm2_rst",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PWM3_RST": {
+                    "description": "reg_pwm3_rst",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SPI3_DMA_RST": {
+                    "description": "reg_spi3_dma_rst",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_RST": {
+                    "description": "reg_apb_saradc_rst",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "SYSTIMER_RST": {
+                    "description": "reg_systimer_rst",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ADC2_ARB_RST": {
+                    "description": "reg_adc2_arb_rst",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI4_RST": {
+                    "description": "reg_spi4_rst",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_RST_EN1": {
+              "description": "peripheral reset register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 510,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRYPTO_AES_RST": {
+                    "description": "reg_crypto_aes_rst",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CRYPTO_SHA_RST": {
+                    "description": "reg_crypto_sha_rst",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CRYPTO_RSA_RST": {
+                    "description": "reg_crypto_rsa_rst",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRYPTO_DS_RST": {
+                    "description": "reg_crypto_ds_rst",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRYPTO_HMAC_RST": {
+                    "description": "reg_crypto_hmac_rst",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMA_RST": {
+                    "description": "reg_dma_rst",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDIO_HOST_RST": {
+                    "description": "reg_sdio_host_rst",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCD_CAM_RST": {
+                    "description": "reg_lcd_cam_rst",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UART2_RST": {
+                    "description": "reg_uart2_rst",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TSENS_RST": {
+                    "description": "reg_tsens_rst",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BT_LPCK_DIV_INT": {
+              "description": "clock config register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_LPCK_DIV_NUM": {
+                    "description": "reg_bt_lpck_div_num",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "BT_LPCK_DIV_FRAC": {
+              "description": "clock config register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 33558529,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_LPCK_DIV_B": {
+                    "description": "reg_bt_lpck_div_b",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "BT_LPCK_DIV_A": {
+                    "description": "reg_bt_lpck_div_a",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "LPCLK_SEL_RTC_SLOW": {
+                    "description": "reg_lpclk_sel_rtc_slow",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_8M": {
+                    "description": "reg_lpclk_sel_8m",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_XTAL": {
+                    "description": "reg_lpclk_sel_xtal",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_XTAL32K": {
+                    "description": "reg_lpclk_sel_xtal32k",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "LPCLK_RTC_EN": {
+                    "description": "reg_lpclk_rtc_en",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_0": {
+              "description": "interrupt generate register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_0": {
+                    "description": "reg_cpu_intr_from_cpu_0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_1": {
+              "description": "interrupt generate register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_1": {
+                    "description": "reg_cpu_intr_from_cpu_1",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_2": {
+              "description": "interrupt generate register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_2": {
+                    "description": "reg_cpu_intr_from_cpu_2",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_3": {
+              "description": "interrupt generate register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_3": {
+                    "description": "reg_cpu_intr_from_cpu_3",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RSA_PD_CTRL": {
+              "description": "rsa memory power control register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSA_MEM_PD": {
+                    "description": "reg_rsa_mem_pd",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RSA_MEM_FORCE_PU": {
+                    "description": "reg_rsa_mem_force_pu",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RSA_MEM_FORCE_PD": {
+                    "description": "reg_rsa_mem_force_pd",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EDMA_CTRL": {
+              "description": "edma clcok and reset register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EDMA_CLK_ON": {
+                    "description": "reg_edma_clk_on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EDMA_RESET": {
+                    "description": "reg_edma_reset",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_CONTROL": {
+              "description": "cache control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_CLK_ON": {
+                    "description": "reg_icache_clk_on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_RESET": {
+                    "description": "reg_icache_reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DCACHE_CLK_ON": {
+                    "description": "reg_dcache_clk_on",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCACHE_RESET": {
+                    "description": "reg_dcache_reset",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL": {
+              "description": "SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_SPI_MANUAL_ENCRYPT": {
+                    "description": "reg_enable_spi_manual_encrypt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_DB_ENCRYPT": {
+                    "description": "reg_enable_download_db_encrypt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_G0CB_DECRYPT": {
+                    "description": "reg_enable_download_g0cb_decrypt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_MANUAL_ENCRYPT": {
+                    "description": "reg_enable_download_manual_encrypt",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTC_FASTMEM_CONFIG": {
+              "description": "fast memory config register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 2146435072,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_MEM_CRC_START": {
+                    "description": "reg_rtc_mem_crc_start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RTC_MEM_CRC_ADDR": {
+                    "description": "reg_rtc_mem_crc_addr",
+                    "offset": 9,
+                    "size": 11
+                  },
+                  "RTC_MEM_CRC_LEN": {
+                    "description": "reg_rtc_mem_crc_len",
+                    "offset": 20,
+                    "size": 11
+                  },
+                  "RTC_MEM_CRC_FINISH": {
+                    "description": "reg_rtc_mem_crc_finish",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RTC_FASTMEM_CRC": {
+              "description": "reserved",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_MEM_CRC_RES": {
+                    "description": "reg_rtc_mem_crc_res",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "REDUNDANT_ECO_CTRL": {
+              "description": "eco register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDUNDANT_ECO_DRIVE": {
+                    "description": "reg_redundant_eco_drive",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REDUNDANT_ECO_RESULT": {
+                    "description": "reg_redundant_eco_result",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "clock gating register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSCLK_CONF": {
+              "description": "system clock config register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_DIV_CNT": {
+                    "description": "reg_pre_div_cnt",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "SOC_CLK_SEL": {
+                    "description": "reg_soc_clk_sel",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CLK_XTAL_FREQ": {
+                    "description": "reg_clk_xtal_freq",
+                    "offset": 12,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "CLK_DIV_EN": {
+                    "description": "reg_clk_div_en",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MEM_PVT": {
+              "description": "mem pvt register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_PATH_LEN": {
+                    "description": "reg_mem_path_len",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "MEM_ERR_CNT_CLR": {
+                    "description": "reg_mem_err_cnt_clr",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MONITOR_EN": {
+                    "description": "reg_mem_pvt_monitor_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MEM_TIMING_ERR_CNT": {
+                    "description": "reg_mem_timing_err_cnt",
+                    "offset": 6,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "MEM_VT_SEL": {
+                    "description": "reg_mem_vt_sel",
+                    "offset": 22,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "COMB_PVT_LVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_LVT": {
+                    "description": "reg_comb_path_len_lvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_LVT": {
+                    "description": "reg_comb_err_cnt_clr_lvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_LVT": {
+                    "description": "reg_comb_pvt_monitor_en_lvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_NVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_NVT": {
+                    "description": "reg_comb_path_len_nvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_NVT": {
+                    "description": "reg_comb_err_cnt_clr_nvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_NVT": {
+                    "description": "reg_comb_pvt_monitor_en_nvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_HVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_HVT": {
+                    "description": "reg_comb_path_len_hvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_HVT": {
+                    "description": "reg_comb_err_cnt_clr_hvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_HVT": {
+                    "description": "reg_comb_pvt_monitor_en_hvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SYSTEM_REG_DATE": {
+              "description": "Version register",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 33583440,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTEM_REG_DATE": {
+                    "description": "reg_system_reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSTIMER": {
+        "description": "System Timer",
+        "children": {
+          "registers": {
+            "CONF": {
+              "description": "SYSTIMER_CONF.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1174405120,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_CLK_FO": {
+                    "description": "systimer clock force on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TARGET2_WORK_EN": {
+                    "description": "target2 work enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TARGET1_WORK_EN": {
+                    "description": "target1 work enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TARGET0_WORK_EN": {
+                    "description": "target0 work enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_CORE1_STALL_EN": {
+                    "description": "If timer unit1 is stalled when core1 stalled",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_CORE0_STALL_EN": {
+                    "description": "If timer unit1 is stalled when core0 stalled",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_CORE1_STALL_EN": {
+                    "description": "If timer unit0 is stalled when core1 stalled",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_CORE0_STALL_EN": {
+                    "description": "If timer unit0 is stalled when core0 stalled",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_WORK_EN": {
+                    "description": "timer unit1 work enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_WORK_EN": {
+                    "description": "timer unit0 work enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "register file clk gating",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UNIT0_OP": {
+              "description": "SYSTIMER_UNIT0_OP.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_VALID": {
+                    "description": "reg_timer_unit0_value_valid",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMER_UNIT0_UPDATE": {
+                    "description": "update timer_unit0",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_OP": {
+              "description": "SYSTIMER_UNIT1_OP.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_VALID": {
+                    "description": "timer value is sync and valid",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMER_UNIT1_UPDATE": {
+                    "description": "update timer unit1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD_HI": {
+              "description": "SYSTIMER_UNIT0_LOAD_HI.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD_HI": {
+                    "description": "timer unit0 load high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD_LO": {
+              "description": "SYSTIMER_UNIT0_LOAD_LO.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD_LO": {
+                    "description": "timer unit0 load low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD_HI": {
+              "description": "SYSTIMER_UNIT1_LOAD_HI.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD_HI": {
+                    "description": "timer unit1 load high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD_LO": {
+              "description": "SYSTIMER_UNIT1_LOAD_LO.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD_LO": {
+                    "description": "timer unit1 load low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET0_HI": {
+              "description": "SYSTIMER_TARGET0_HI.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET0_HI": {
+                    "description": "timer taget0 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET0_LO": {
+              "description": "SYSTIMER_TARGET0_LO.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET0_LO": {
+                    "description": "timer taget0 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET1_HI": {
+              "description": "SYSTIMER_TARGET1_HI.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET1_HI": {
+                    "description": "timer taget1 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET1_LO": {
+              "description": "SYSTIMER_TARGET1_LO.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET1_LO": {
+                    "description": "timer taget1 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET2_HI": {
+              "description": "SYSTIMER_TARGET2_HI.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET2_HI": {
+                    "description": "timer taget2 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET2_LO": {
+              "description": "SYSTIMER_TARGET2_LO.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET2_LO": {
+                    "description": "timer taget2 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET0_CONF": {
+              "description": "SYSTIMER_TARGET0_CONF.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_PERIOD": {
+                    "description": "target0 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET0_PERIOD_MODE": {
+                    "description": "Set target0 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET0_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TARGET1_CONF": {
+              "description": "SYSTIMER_TARGET1_CONF.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET1_PERIOD": {
+                    "description": "target1 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET1_PERIOD_MODE": {
+                    "description": "Set target1 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET1_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TARGET2_CONF": {
+              "description": "SYSTIMER_TARGET2_CONF.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET2_PERIOD": {
+                    "description": "target2 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET2_PERIOD_MODE": {
+                    "description": "Set target2 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET2_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UNIT0_VALUE_HI": {
+              "description": "SYSTIMER_UNIT0_VALUE_HI.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_HI": {
+                    "description": "timer read value high 32bit",
+                    "offset": 0,
+                    "size": 20,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_VALUE_LO": {
+              "description": "SYSTIMER_UNIT0_VALUE_LO.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_LO": {
+                    "description": "timer read value low 32bit",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_VALUE_HI": {
+              "description": "SYSTIMER_UNIT1_VALUE_HI.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_HI": {
+                    "description": "timer read value high 32bit",
+                    "offset": 0,
+                    "size": 20,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_VALUE_LO": {
+              "description": "SYSTIMER_UNIT1_VALUE_LO.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_LO": {
+                    "description": "timer read value low 32bit",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMP0_LOAD": {
+              "description": "SYSTIMER_COMP0_LOAD.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP0_LOAD": {
+                    "description": "timer comp0 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "COMP1_LOAD": {
+              "description": "SYSTIMER_COMP1_LOAD.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP1_LOAD": {
+                    "description": "timer comp1 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "COMP2_LOAD": {
+              "description": "SYSTIMER_COMP2_LOAD.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP2_LOAD": {
+                    "description": "timer comp2 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD": {
+              "description": "SYSTIMER_UNIT0_LOAD.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD": {
+                    "description": "timer unit0 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD": {
+              "description": "SYSTIMER_UNIT1_LOAD.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD": {
+                    "description": "timer unit1 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "SYSTIMER_INT_ENA.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_ENA": {
+                    "description": "interupt0 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TARGET1_INT_ENA": {
+                    "description": "interupt1 enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TARGET2_INT_ENA": {
+                    "description": "interupt2 enable",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "SYSTIMER_INT_RAW.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_RAW": {
+                    "description": "interupt0 raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET1_INT_RAW": {
+                    "description": "interupt1 raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET2_INT_RAW": {
+                    "description": "interupt2 raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "SYSTIMER_INT_CLR.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_CLR": {
+                    "description": "interupt0 clear",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TARGET1_INT_CLR": {
+                    "description": "interupt1 clear",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TARGET2_INT_CLR": {
+                    "description": "interupt2 clear",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "SYSTIMER_INT_ST.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_ST": {
+                    "description": "reg_target0_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET1_INT_ST": {
+                    "description": "reg_target1_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET2_INT_ST": {
+                    "description": "reg_target2_int_st",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "SYSTIMER_DATE.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 33579377,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMG0": {
+        "description": "Timer Group",
+        "children": {
+          "registers": {
+            "T0CONFIG": {
+              "description": "TIMG_T0CONFIG_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1610620928,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_USE_XTAL": {
+                    "description": "reg_t0_use_xtal.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "T0_ALARM_EN": {
+                    "description": "reg_t0_alarm_en.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "T0_DIVCNT_RST": {
+                    "description": "reg_t0_divcnt_rst.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "T0_DIVIDER": {
+                    "description": "reg_t0_divider.",
+                    "offset": 13,
+                    "size": 16
+                  },
+                  "T0_AUTORELOAD": {
+                    "description": "reg_t0_autoreload.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "T0_INCREASE": {
+                    "description": "reg_t0_increase.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "T0_EN": {
+                    "description": "reg_t0_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "T0LO": {
+              "description": "TIMG_T0LO_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LO": {
+                    "description": "t0_lo",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "T0HI": {
+              "description": "TIMG_T0HI_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_HI": {
+                    "description": "t0_hi",
+                    "offset": 0,
+                    "size": 22,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "T0UPDATE": {
+              "description": "TIMG_T0UPDATE_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_UPDATE": {
+                    "description": "t0_update",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "T0ALARMLO": {
+              "description": "TIMG_T0ALARMLO_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_ALARM_LO": {
+                    "description": "reg_t0_alarm_lo.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T0ALARMHI": {
+              "description": "TIMG_T0ALARMHI_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_ALARM_HI": {
+                    "description": "reg_t0_alarm_hi.",
+                    "offset": 0,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "T0LOADLO": {
+              "description": "TIMG_T0LOADLO_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD_LO": {
+                    "description": "reg_t0_load_lo.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T0LOADHI": {
+              "description": "TIMG_T0LOADHI_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD_HI": {
+                    "description": "reg_t0_load_hi.",
+                    "offset": 0,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "T0LOAD": {
+              "description": "TIMG_T0LOAD_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD": {
+                    "description": "t0_load",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTCONFIG0": {
+              "description": "TIMG_WDTCONFIG0_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 311296,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_APPCPU_RESET_EN": {
+                    "description": "reg_wdt_appcpu_reset_en.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WDT_PROCPU_RESET_EN": {
+                    "description": "reg_wdt_procpu_reset_en.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WDT_FLASHBOOT_MOD_EN": {
+                    "description": "reg_wdt_flashboot_mod_en.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WDT_SYS_RESET_LENGTH": {
+                    "description": "reg_wdt_sys_reset_length.",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "WDT_CPU_RESET_LENGTH": {
+                    "description": "reg_wdt_cpu_reset_length.",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "WDT_USE_XTAL": {
+                    "description": "reg_wdt_use_xtal.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "WDT_CONF_UPDATE_EN": {
+                    "description": "reg_wdt_conf_update_en.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_STG3": {
+                    "description": "reg_wdt_stg3.",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "WDT_STG2": {
+                    "description": "reg_wdt_stg2.",
+                    "offset": 25,
+                    "size": 2
+                  },
+                  "WDT_STG1": {
+                    "description": "reg_wdt_stg1.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "WDT_STG0": {
+                    "description": "reg_wdt_stg0.",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "WDT_EN": {
+                    "description": "reg_wdt_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG1": {
+              "description": "TIMG_WDTCONFIG1_REG.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 65536,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_DIVCNT_RST": {
+                    "description": "reg_wdt_divcnt_rst.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_CLK_PRESCALE": {
+                    "description": "reg_wdt_clk_prescale.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "WDTCONFIG2": {
+              "description": "TIMG_WDTCONFIG2_REG.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 26000000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG0_HOLD": {
+                    "description": "reg_wdt_stg0_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG3": {
+              "description": "TIMG_WDTCONFIG3_REG.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 134217727,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG1_HOLD": {
+                    "description": "reg_wdt_stg1_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG4": {
+              "description": "TIMG_WDTCONFIG4_REG.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1048575,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG2_HOLD": {
+                    "description": "reg_wdt_stg2_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG5": {
+              "description": "TIMG_WDTCONFIG5_REG.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1048575,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG3_HOLD": {
+                    "description": "reg_wdt_stg3_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTFEED": {
+              "description": "TIMG_WDTFEED_REG.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_FEED": {
+                    "description": "wdt_feed",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTWPROTECT": {
+              "description": "TIMG_WDTWPROTECT_REG.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 1356348065,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_WKEY": {
+                    "description": "reg_wdt_wkey.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RTCCALICFG": {
+              "description": "TIMG_RTCCALICFG_REG.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 77824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_START_CYCLING": {
+                    "description": "reg_rtc_cali_start_cycling.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTC_CALI_CLK_SEL": {
+                    "description": "reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "RTC_CALI_RDY": {
+                    "description": "rtc_cali_rdy",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_MAX": {
+                    "description": "reg_rtc_cali_max.",
+                    "offset": 16,
+                    "size": 15
+                  },
+                  "RTC_CALI_START": {
+                    "description": "reg_rtc_cali_start.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTCCALICFG1": {
+              "description": "TIMG_RTCCALICFG1_REG.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_CYCLING_DATA_VLD": {
+                    "description": "rtc_cali_cycling_data_vld",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_VALUE": {
+                    "description": "rtc_cali_value",
+                    "offset": 7,
+                    "size": 25,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_TIMERS": {
+              "description": "INT_ENA_TIMG_REG",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_ENA": {
+                    "description": "t0_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "WDT_INT_ENA": {
+                    "description": "wdt_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW_TIMERS": {
+              "description": "INT_RAW_TIMG_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_RAW": {
+                    "description": "t0_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WDT_INT_RAW": {
+                    "description": "wdt_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_TIMERS": {
+              "description": "INT_ST_TIMG_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_ST": {
+                    "description": "t0_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WDT_INT_ST": {
+                    "description": "wdt_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR_TIMERS": {
+              "description": "INT_CLR_TIMG_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_CLR": {
+                    "description": "t0_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_INT_CLR": {
+                    "description": "wdt_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RTCCALICFG2": {
+              "description": "TIMG_RTCCALICFG2_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 4294967192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_TIMEOUT": {
+                    "description": "timeoutindicator",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_TIMEOUT_RST_CNT": {
+                    "description": "reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset",
+                    "offset": 3,
+                    "size": 4
+                  },
+                  "RTC_CALI_TIMEOUT_THRES": {
+                    "description": "reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "NTIMG_DATE": {
+              "description": "TIMG_NTIMG_DATE_REG.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 33579409,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NTIMGS_DATE": {
+                    "description": "reg_ntimers_date.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "REGCLK": {
+              "description": "TIMG_REGCLK_REG.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 1610612736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_CLK_IS_ACTIVE": {
+                    "description": "reg_wdt_clk_is_active.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TIMER_CLK_IS_ACTIVE": {
+                    "description": "reg_timer_clk_is_active.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "XTS_AES": {
+        "description": "XTS-AES-128 Flash Encryption",
+        "children": {
+          "registers": {
+            "PLAIN_MEM": {
+              "description": "The memory that stores plaintext",
+              "offset": 0,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "LINESIZE": {
+              "description": "XTS-AES line-size register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINESIZE": {
+                    "description": "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DESTINATION": {
+              "description": "XTS-AES destination register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DESTINATION": {
+                    "description": "This bit stores the destination. 0: flash(default). 1: reserved.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PHYSICAL_ADDRESS": {
+              "description": "XTS-AES physical address register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PHYSICAL_ADDRESS": {
+                    "description": "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "TRIGGER": {
+              "description": "XTS-AES trigger register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGER": {
+                    "description": "Set this bit to start manual encryption calculation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RELEASE": {
+              "description": "XTS-AES release register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELEASE": {
+                    "description": "Set this bit to release the manual encrypted result, after that the result will be visible to spi",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DESTROY": {
+              "description": "XTS-AES destroy register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DESTROY": {
+                    "description": "Set this bit to destroy XTS-AES result.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "XTS-AES status register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "XTS-AES version control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 538969635,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Those bits stores the version information of XTS-AES.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWAI": {
+        "description": "Two-Wire Automotive Interface",
+        "children": {
+          "registers": {
+            "MODE": {
+              "description": "Mode Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_MODE": {
+                    "description": "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LISTEN_ONLY_MODE": {
+                    "description": "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SELF_TEST_MODE": {
+                    "description": "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_FILTER_MODE": {
+                    "description": "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "Command Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_REQ": {
+                    "description": "Set the bit to 1 to allow the driving nodes start transmission.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ABORT_TX": {
+                    "description": "Set the bit to 1 to cancel a pending transmission request.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RELEASE_BUF": {
+                    "description": "Set the bit to 1 to release the RX buffer.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CLR_OVERRUN": {
+                    "description": "Set the bit to 1 to clear the data overrun status bit.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SELF_RX_REQ": {
+                    "description": "Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_BUF_ST": {
+                    "description": "1: The data in the RX buffer is not empty, with at least one received data packet.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERRUN_ST": {
+                    "description": "1: The RX FIFO is full and data overrun has occurred.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BUF_ST": {
+                    "description": "1: The TX buffer is empty, the CPU may write a message into it.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_COMPLETE": {
+                    "description": "1: The TWAI controller has successfully received a packet from the bus.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_ST": {
+                    "description": "1: The TWAI Controller is receiving a message from the bus.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_ST": {
+                    "description": "1: The TWAI Controller is transmitting a message to the bus.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_ST": {
+                    "description": "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_OFF_ST": {
+                    "description": "1: In bus-off status, the TWAI Controller is no longer involved in bus activities.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MISS_ST": {
+                    "description": "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "Interrupt Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_INT_ST": {
+                    "description": "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_INT_ST": {
+                    "description": "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_WARN_INT_ST": {
+                    "description": "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERRUN_INT_ST": {
+                    "description": "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_PASSIVE_INT_ST": {
+                    "description": "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARB_LOST_INT_ST": {
+                    "description": "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_ERR_INT_ST": {
+                    "description": "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "Interrupt Enable Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_INT_ENA": {
+                    "description": "Set this bit to 1 to enable receive interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_INT_ENA": {
+                    "description": "Set this bit to 1 to enable transmit interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ERR_WARN_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error warning interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVERRUN_INT_ENA": {
+                    "description": "Set this bit to 1 to enable data overrun interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_PASSIVE_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error passive interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ARB_LOST_INT_ENA": {
+                    "description": "Set this bit to 1 to enable arbitration lost interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BUS_ERR_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BUS_TIMING_0": {
+              "description": "Bus Timing Register 0",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUD_PRESC": {
+                    "description": "Baud Rate Prescaler, determines the frequency dividing ratio.",
+                    "offset": 0,
+                    "size": 13
+                  },
+                  "SYNC_JUMP_WIDTH": {
+                    "description": "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide.",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BUS_TIMING_1": {
+              "description": "Bus Timing Register 1",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME_SEG1": {
+                    "description": "The width of PBS1.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "TIME_SEG2": {
+                    "description": "The width of PBS2.",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "TIME_SAMP": {
+                    "description": "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ARB_LOST_CAP": {
+              "description": "Arbitration Lost Capture Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARB_LOST_CAP": {
+                    "description": "This register contains information about the bit position of lost arbitration.",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ERR_CODE_CAP": {
+              "description": "Error Code Capture Register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECC_SEGMENT": {
+                    "description": "This register contains information about the location of errors, see Table 181 for details.",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "ECC_DIRECTION": {
+                    "description": "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ECC_TYPE": {
+                    "description": "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ERR_WARNING_LIMIT": {
+              "description": "Error Warning Limit Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 96,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERR_WARNING_LIMIT": {
+                    "description": "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RX_ERR_CNT": {
+              "description": "Receive Error Counter Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_ERR_CNT": {
+                    "description": "The RX error counter register, reflects value changes under reception status.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TX_ERR_CNT": {
+              "description": "Transmit Error Counter Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_ERR_CNT": {
+                    "description": "The TX error counter register, reflects value changes under transmission status.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DATA_0": {
+              "description": "Data register 0",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_0": {
+                    "description": "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_1": {
+              "description": "Data register 1",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_1": {
+                    "description": "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_2": {
+              "description": "Data register 2",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_2": {
+                    "description": "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_3": {
+              "description": "Data register 3",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_3": {
+                    "description": "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_4": {
+              "description": "Data register 4",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_4": {
+                    "description": "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_5": {
+              "description": "Data register 5",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_5": {
+                    "description": "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_6": {
+              "description": "Data register 6",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_6": {
+                    "description": "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_7": {
+              "description": "Data register 7",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_7": {
+                    "description": "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_8": {
+              "description": "Data register 8",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_8": {
+                    "description": "Stored the 8th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_9": {
+              "description": "Data register 9",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_9": {
+                    "description": "Stored the 9th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_10": {
+              "description": "Data register 10",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_10": {
+                    "description": "Stored the 10th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_11": {
+              "description": "Data register 11",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_11": {
+                    "description": "Stored the 11th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_12": {
+              "description": "Data register 12",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_12": {
+                    "description": "Stored the 12th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RX_MESSAGE_CNT": {
+              "description": "Receive Message Counter Register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_MESSAGE_COUNTER": {
+                    "description": "This register reflects the number of messages available within the RX FIFO.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_DIVIDER": {
+              "description": "Clock Divider register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CD": {
+                    "description": "These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLOCK_OFF": {
+                    "description": "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART0": {
+        "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+        "children": {
+          "registers": {
+            "FIFO": {
+              "description": "FIFO data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_RD_BYTE": {
+                    "description": "UART 0 accesses FIFO via this register.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "Raw interrupt status",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_EMPTY_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PARITY_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error in the data.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FRM_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error .",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSR_CHG_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTS_CHG_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRK_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_TOUT_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XON_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XOFF_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GLITCH_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_PARITY_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_FRM_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_CLASH_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WAKEUP_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "Masked interrupt status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_ST": {
+                    "description": "This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_EMPTY_INT_ST": {
+                    "description": "This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PARITY_ERR_INT_ST": {
+                    "description": "This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FRM_ERR_INT_ST": {
+                    "description": "This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_ST": {
+                    "description": "This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSR_CHG_INT_ST": {
+                    "description": "This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTS_CHG_INT_ST": {
+                    "description": "This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRK_DET_INT_ST": {
+                    "description": "This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_TOUT_INT_ST": {
+                    "description": "This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XON_INT_ST": {
+                    "description": "This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XOFF_INT_ST": {
+                    "description": "This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GLITCH_DET_INT_ST": {
+                    "description": "This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_DONE_INT_ST": {
+                    "description": "This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_ST": {
+                    "description": "This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_ST": {
+                    "description": "This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_PARITY_ERR_INT_ST": {
+                    "description": "This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_FRM_ERR_INT_ST": {
+                    "description": "This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_CLASH_INT_ST": {
+                    "description": "This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_ST": {
+                    "description": "This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WAKEUP_INT_ST": {
+                    "description": "This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "Interrupt enable bits",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_full_int_st register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFIFO_EMPTY_INT_ENA": {
+                    "description": "This is the enable bit for txfifo_empty_int_st register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PARITY_ERR_INT_ENA": {
+                    "description": "This is the enable bit for parity_err_int_st register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FRM_ERR_INT_ENA": {
+                    "description": "This is the enable bit for frm_err_int_st register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFIFO_OVF_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_ovf_int_st register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DSR_CHG_INT_ENA": {
+                    "description": "This is the enable bit for dsr_chg_int_st register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CTS_CHG_INT_ENA": {
+                    "description": "This is the enable bit for cts_chg_int_st register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BRK_DET_INT_ENA": {
+                    "description": "This is the enable bit for brk_det_int_st register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RXFIFO_TOUT_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_tout_int_st register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SW_XON_INT_ENA": {
+                    "description": "This is the enable bit for sw_xon_int_st register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SW_XOFF_INT_ENA": {
+                    "description": "This is the enable bit for sw_xoff_int_st register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GLITCH_DET_INT_ENA": {
+                    "description": "This is the enable bit for glitch_det_int_st register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_BRK_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_brk_done_int_st register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_BRK_IDLE_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_brk_idle_done_int_st register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_done_int_st register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RS485_PARITY_ERR_INT_ENA": {
+                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RS485_FRM_ERR_INT_ENA": {
+                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RS485_CLASH_INT_ENA": {
+                    "description": "This is the enable bit for rs485_clash_int_st register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AT_CMD_CHAR_DET_INT_ENA": {
+                    "description": "This is the enable bit for at_cmd_char_det_int_st register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "WAKEUP_INT_ENA": {
+                    "description": "This is the enable bit for uart_wakeup_int_st register.",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "Interrupt clear bits",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_CLR": {
+                    "description": "Set this bit to clear the rxfifo_full_int_raw interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_EMPTY_INT_CLR": {
+                    "description": "Set this bit to clear txfifo_empty_int_raw interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PARITY_ERR_INT_CLR": {
+                    "description": "Set this bit to clear parity_err_int_raw interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "FRM_ERR_INT_CLR": {
+                    "description": "Set this bit to clear frm_err_int_raw interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_OVF_INT_CLR": {
+                    "description": "Set this bit to clear rxfifo_ovf_int_raw interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DSR_CHG_INT_CLR": {
+                    "description": "Set this bit to clear the dsr_chg_int_raw interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CTS_CHG_INT_CLR": {
+                    "description": "Set this bit to clear the cts_chg_int_raw interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BRK_DET_INT_CLR": {
+                    "description": "Set this bit to clear the brk_det_int_raw interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_TOUT_INT_CLR": {
+                    "description": "Set this bit to clear the rxfifo_tout_int_raw interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_XON_INT_CLR": {
+                    "description": "Set this bit to clear the sw_xon_int_raw interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_XOFF_INT_CLR": {
+                    "description": "Set this bit to clear the sw_xoff_int_raw interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "GLITCH_DET_INT_CLR": {
+                    "description": "Set this bit to clear the glitch_det_int_raw interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_BRK_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_brk_done_int_raw interrupt..",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_brk_idle_done_int_raw interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_done_int_raw interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_PARITY_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_parity_err_int_raw interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_FRM_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_frm_err_int_raw interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_CLASH_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_clash_int_raw interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_CLR": {
+                    "description": "Set this bit to clear the at_cmd_char_det_int_raw interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WAKEUP_INT_CLR": {
+                    "description": "Set this bit to clear the uart_wakeup_int_raw interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLKDIV": {
+              "description": "Clock divider configuration",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 694,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKDIV": {
+                    "description": "The integral part of the frequency divider factor.",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "FRAG": {
+                    "description": "The decimal part of the frequency divider factor.",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RX_FILT": {
+              "description": "Rx Filter configuration",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GLITCH_FILT": {
+                    "description": "when input pulse width is lower than this value, the pulse is ignored.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "GLITCH_FILT_EN": {
+                    "description": "Set this bit to enable Rx signal filter.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "UART status register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 3758145536,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_CNT": {
+                    "description": "Stores the byte number of valid data in Rx-FIFO.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "DSRN": {
+                    "description": "The register represent the level value of the internal uart dsr signal.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTSN": {
+                    "description": "This register represent the level value of the internal uart cts signal.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXD": {
+                    "description": "This register represent the  level value of the internal uart rxd signal.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_CNT": {
+                    "description": "Stores the byte number of data in Tx-FIFO.",
+                    "offset": 16,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "DTRN": {
+                    "description": "This bit represents the level of the internal uart dtr signal.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTSN": {
+                    "description": "This bit represents the level of the internal uart rts signal.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXD": {
+                    "description": "This bit represents the  level of the internal uart txd signal.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CONF0": {
+              "description": "a",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 268435484,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PARITY": {
+                    "description": "This register is used to configure the parity check mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PARITY_EN": {
+                    "description": "Set this bit to enable uart parity check.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BIT_NUM": {
+                    "description": "This register is used to set the length of data.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "STOP_BIT_NUM": {
+                    "description": "This register is used to set the length of  stop bit.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "SW_RTS": {
+                    "description": "This register is used to configure the software rts signal which is used in software flow control.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SW_DTR": {
+                    "description": "This register is used to configure the software dtr signal which is used in software flow control.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TXD_BRK": {
+                    "description": "Set this bit to enbale transmitter to  send NULL when the process of sending data is done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IRDA_DPLX": {
+                    "description": "Set this bit to enable IrDA loopback mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IRDA_TX_EN": {
+                    "description": "This is the start enable bit for IrDA transmitter.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IRDA_WCTL": {
+                    "description": "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IRDA_TX_INV": {
+                    "description": "Set this bit to invert the level of  IrDA transmitter.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IRDA_RX_INV": {
+                    "description": "Set this bit to invert the level of IrDA receiver.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LOOPBACK": {
+                    "description": "Set this bit to enable uart loopback test mode.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TX_FLOW_EN": {
+                    "description": "Set this bit to enable flow control function for transmitter.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IRDA_EN": {
+                    "description": "Set this bit to enable IrDA protocol.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFO_RST": {
+                    "description": "Set this bit to reset the uart receive-FIFO.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFO_RST": {
+                    "description": "Set this bit to reset the uart transmit-FIFO.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXD_INV": {
+                    "description": "Set this bit to inverse the level value of uart rxd signal.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CTS_INV": {
+                    "description": "Set this bit to inverse the level value of uart cts signal.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "DSR_INV": {
+                    "description": "Set this bit to inverse the level value of uart dsr signal.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXD_INV": {
+                    "description": "Set this bit to inverse the level value of uart txd signal.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RTS_INV": {
+                    "description": "Set this bit to inverse the level value of uart rts signal.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DTR_INV": {
+                    "description": "Set this bit to inverse the level value of uart dtr signal.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ERR_WR_MASK": {
+                    "description": "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "AUTOBAUD_EN": {
+                    "description": "This is the enable bit for detecting baudrate.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "MEM_CLK_EN": {
+                    "description": "UART memory clock gate enable signal.",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CONF1": {
+              "description": "Configuration register 1",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 49248,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_THRHD": {
+                    "description": "It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "TXFIFO_EMPTY_THRHD": {
+                    "description": "It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "DIS_RX_DAT_OVF": {
+                    "description": "Disable UART Rx data overflow detect.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RX_TOUT_FLOW_DIS": {
+                    "description": "Set this bit to stop accumulating idle_cnt when hardware flow control works.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RX_FLOW_EN": {
+                    "description": "This is the flow enable bit for UART receiver.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RX_TOUT_EN": {
+                    "description": "This is the enble bit for uart receiver's timeout function.",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOWPULSE": {
+              "description": "Autobaud minimum low pulse duration register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_CNT": {
+                    "description": "This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HIGHPULSE": {
+              "description": "Autobaud minimum high pulse duration register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_CNT": {
+                    "description": "This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXD_CNT": {
+              "description": "Autobaud edge change count register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXD_EDGE_CNT": {
+                    "description": "This register stores the count of rxd edge change. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FLOW_CONF": {
+              "description": "Software flow-control configuration",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_FLOW_CON_EN": {
+                    "description": "Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "XONOFF_DEL": {
+                    "description": "Set this bit to remove flow control char from the received data.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCE_XON": {
+                    "description": "Set this bit to enable the transmitter to go on sending data.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FORCE_XOFF": {
+                    "description": "Set this bit to stop the  transmitter from sending data.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEND_XON": {
+                    "description": "Set this bit to send Xon char. It is cleared by hardware automatically.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SEND_XOFF": {
+                    "description": "Set this bit to send Xoff char. It is cleared by hardware automatically.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLEEP_CONF": {
+              "description": "Sleep-mode configuration",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 240,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACTIVE_THRESHOLD": {
+                    "description": "The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "SWFC_CONF0": {
+              "description": "Software flow-control character configuration",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 9952,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XOFF_THRESHOLD": {
+                    "description": "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "XOFF_CHAR": {
+                    "description": "This register stores the Xoff flow control char.",
+                    "offset": 9,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SWFC_CONF1": {
+              "description": "Software flow-control character configuration",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8704,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XON_THRESHOLD": {
+                    "description": "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "XON_CHAR": {
+                    "description": "This register stores the Xon flow control char.",
+                    "offset": 9,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXBRK_CONF": {
+              "description": "Tx Break character configuration",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BRK_NUM": {
+                    "description": "This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IDLE_CONF": {
+              "description": "Frame-end idle configuration",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 262400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_IDLE_THRHD": {
+                    "description": "It will produce frame end signal when receiver takes more time to receive one byte data than this register value.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "TX_IDLE_NUM": {
+                    "description": "This register is used to configure the duration time between transfers.",
+                    "offset": 10,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "RS485_CONF": {
+              "description": "RS485 mode configuration",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RS485_EN": {
+                    "description": "Set this bit to choose the rs485 mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DL0_EN": {
+                    "description": "Set this bit to delay the stop bit by 1 bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DL1_EN": {
+                    "description": "Set this bit to delay the stop bit by 1 bit.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RS485TX_RX_EN": {
+                    "description": "Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RS485RXBY_TX_EN": {
+                    "description": "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RS485_RX_DLY_NUM": {
+                    "description": "This register is used to delay the receiver's internal data signal.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RS485_TX_DLY_NUM": {
+                    "description": "This register is used to delay the transmitter's internal data signal.",
+                    "offset": 6,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AT_CMD_PRECNT": {
+              "description": "Pre-sequence timing configuration",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 2305,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_IDLE_NUM": {
+                    "description": "This register is used to configure the idle duration time before the first at_cmd is received by receiver.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_POSTCNT": {
+              "description": "Post-sequence timing configuration",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 2305,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POST_IDLE_NUM": {
+                    "description": "This register is used to configure the duration time between the last at_cmd and the next data.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_GAPTOUT": {
+              "description": "Timeout configuration",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 11,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_GAP_TOUT": {
+                    "description": "This register is used to configure the duration time between the at_cmd chars.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_CHAR": {
+              "description": "AT escape sequence detection configuration",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 811,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AT_CMD_CHAR": {
+                    "description": "This register is used to configure the content of at_cmd char.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CHAR_NUM": {
+                    "description": "This register is used to configure the num of continuous at_cmd chars received by receiver.",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MEM_CONF": {
+              "description": "UART threshold and allocation configuration",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 655378,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_SIZE": {
+                    "description": "This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.",
+                    "offset": 1,
+                    "size": 3
+                  },
+                  "TX_SIZE": {
+                    "description": "This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "RX_FLOW_THRHD": {
+                    "description": "This register is used to configure the maximum amount of data that can be received  when hardware flow control works.",
+                    "offset": 7,
+                    "size": 9
+                  },
+                  "RX_TOUT_THRHD": {
+                    "description": "This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "MEM_FORCE_PD": {
+                    "description": "Set this bit to force power down UART memory.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PU": {
+                    "description": "Set this bit to force power up UART memory.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MEM_TX_STATUS": {
+              "description": "Tx-FIFO write and read offset address.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_TX_WADDR": {
+                    "description": "This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "TX_RADDR": {
+                    "description": "This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.",
+                    "offset": 11,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MEM_RX_STATUS": {
+              "description": "Rx-FIFO write and read offset address.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_RX_RADDR": {
+                    "description": "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "RX_WADDR": {
+                    "description": "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.",
+                    "offset": 11,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FSM_STATUS": {
+              "description": "UART transmit and receive status.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ST_URX_OUT": {
+                    "description": "This is the status register of receiver.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "ST_UTX_OUT": {
+                    "description": "This is the status register of transmitter.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "POSPULSE": {
+              "description": "Autobaud high pulse register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POSEDGE_MIN_CNT": {
+                    "description": "This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "NEGPULSE": {
+              "description": "Autobaud low pulse register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NEGEDGE_MIN_CNT": {
+                    "description": "This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "UART core clock configuration",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 57675776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLK_DIV_B": {
+                    "description": "The  denominator of the frequency divider factor.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "The numerator of the frequency divider factor.",
+                    "offset": 6,
+                    "size": 6
+                  },
+                  "SCLK_DIV_NUM": {
+                    "description": "The integral part of the frequency divider factor.",
+                    "offset": 12,
+                    "size": 8
+                  },
+                  "SCLK_SEL": {
+                    "description": "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "SCLK_EN": {
+                    "description": "Set this bit to enable UART Tx/Rx clock.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Tx/Rx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TX_SCLK_EN": {
+                    "description": "Set this bit to enable UART Tx clock.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RX_SCLK_EN": {
+                    "description": "Set this bit to enable UART Rx clock.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "TX_RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Tx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RX_RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Rx.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "UART Version register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 33587824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "This is the version register.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ID": {
+              "description": "UART ID register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 1073743104,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ID": {
+                    "description": "This register is used to configure the uart_id.",
+                    "offset": 0,
+                    "size": 30
+                  },
+                  "HIGH_SPEED": {
+                    "description": "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "REG_UPDATE": {
+                    "description": "Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USB_DEVICE": {
+        "description": "Full-speed USB Serial/JTAG Controller",
+        "children": {
+          "registers": {
+            "EP1": {
+              "description": "USB_DEVICE_EP1_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RDWR_BYTE": {
+                    "description": "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "EP1_CONF": {
+              "description": "USB_DEVICE_EP1_CONF_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_DONE": {
+                    "description": "Set this bit to indicate writing byte data to UART Tx FIFO is done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_IN_EP_DATA_FREE": {
+                    "description": "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_EP_DATA_AVAIL": {
+                    "description": "1'b1: Indicate there is data in UART Rx FIFO.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "USB_DEVICE_INT_RAW_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when SOF frame is received.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PID_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when pid error is detected.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC5_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when CRC5 error is detected.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC16_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when CRC16 error is detected.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STUFF_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when stuff error is detected.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_BUS_RESET_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when usb bus reset is detected.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "USB_DEVICE_INT_ST_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PID_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC5_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC16_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STUFF_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_BUS_RESET_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "USB_DEVICE_INT_ENA_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOF_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SERIAL_IN_EMPTY_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PID_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRC5_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRC16_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "STUFF_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USB_BUS_RESET_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "USB_DEVICE_INT_CLR_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SOF_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PID_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRC5_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRC16_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STUFF_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "USB_BUS_RESET_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONF0": {
+              "description": "USB_DEVICE_CONF0_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 16896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PHY_SEL": {
+                    "description": "Select internal/external PHY",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EXCHG_PINS_OVERRIDE": {
+                    "description": "Enable software control USB D+ D- exchange",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXCHG_PINS": {
+                    "description": "USB D+ D- exchange",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VREFH": {
+                    "description": "Control single-end input high threshold,1.76V to 2V, step 80mV",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "VREFL": {
+                    "description": "Control single-end input low threshold,0.8V to 1.04V, step 80mV",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "VREF_OVERRIDE": {
+                    "description": "Enable software control input  threshold",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PAD_PULL_OVERRIDE": {
+                    "description": "Enable software control USB D+ D- pullup pulldown",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DP_PULLUP": {
+                    "description": "Control USB D+ pull up.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DP_PULLDOWN": {
+                    "description": "Control USB D+ pull down.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DM_PULLUP": {
+                    "description": "Control USB D- pull up.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DM_PULLDOWN": {
+                    "description": "Control USB D- pull down.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PULLUP_VALUE": {
+                    "description": "Control pull up value.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USB_PAD_ENABLE": {
+                    "description": "Enable USB pad function.",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TEST": {
+              "description": "USB_DEVICE_TEST_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable test of the USB pad",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USB_OE": {
+                    "description": "USB pad oen in test",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_DP": {
+                    "description": "USB D+ tx value in test",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_DM": {
+                    "description": "USB D- tx value in test",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "JFIFO_ST": {
+              "description": "USB_DEVICE_JFIFO_ST_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 68,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_FIFO_CNT": {
+                    "description": "JTAT in fifo counter.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_EMPTY": {
+                    "description": "1: JTAG in fifo is empty.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_FULL": {
+                    "description": "1: JTAG in fifo is full.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_CNT": {
+                    "description": "JTAT out fifo counter.",
+                    "offset": 4,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_EMPTY": {
+                    "description": "1: JTAG out fifo is empty.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_FULL": {
+                    "description": "1: JTAG out fifo is full.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_RESET": {
+                    "description": "Write 1 to reset JTAG in fifo.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OUT_FIFO_RESET": {
+                    "description": "Write 1 to reset JTAG out fifo.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FRAM_NUM": {
+              "description": "USB_DEVICE_FRAM_NUM_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOF_FRAME_INDEX": {
+                    "description": "Frame index of received SOF frame.",
+                    "offset": 0,
+                    "size": 11,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP0_ST": {
+              "description": "USB_DEVICE_IN_EP0_ST_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP0_STATE": {
+                    "description": "State of IN Endpoint 0.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP0_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 0.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP0_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 0.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP1_ST": {
+              "description": "USB_DEVICE_IN_EP1_ST_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP1_STATE": {
+                    "description": "State of IN Endpoint 1.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP1_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 1.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP1_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 1.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP2_ST": {
+              "description": "USB_DEVICE_IN_EP2_ST_REG.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP2_STATE": {
+                    "description": "State of IN Endpoint 2.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP2_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 2.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP2_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 2.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP3_ST": {
+              "description": "USB_DEVICE_IN_EP3_ST_REG.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP3_STATE": {
+                    "description": "State of IN Endpoint 3.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP3_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 3.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP3_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 3.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP0_ST": {
+              "description": "USB_DEVICE_OUT_EP0_ST_REG.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP0_STATE": {
+                    "description": "State of OUT Endpoint 0.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP0_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP0_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 0.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP1_ST": {
+              "description": "USB_DEVICE_OUT_EP1_ST_REG.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP1_STATE": {
+                    "description": "State of OUT Endpoint 1.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 1.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_REC_DATA_CNT": {
+                    "description": "Data count in OUT endpoint 1 when one packet is received.",
+                    "offset": 16,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP2_ST": {
+              "description": "USB_DEVICE_OUT_EP2_ST_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP2_STATE": {
+                    "description": "State of OUT Endpoint 2.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 2.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MISC_CONF": {
+              "description": "USB_DEVICE_MISC_CONF_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MEM_CONF": {
+              "description": "USB_DEVICE_MEM_CONF_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USB_MEM_PD": {
+                    "description": "1: power down usb memory.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USB_MEM_CLK_EN": {
+                    "description": "1: Force clock on for usb memory.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "USB_DEVICE_DATE_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 33583872,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "register version.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UHCI0": {
+        "description": "Universal Host Controller Interface",
+        "children": {
+          "registers": {
+            "CONF0": {
+              "description": "a",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1760,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_RST": {
+                    "description": "Write 1, then write 0 to this bit to reset decode state machine.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RX_RST": {
+                    "description": "Write 1, then write 0 to this bit to reset encode state machine.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART0_CE": {
+                    "description": "Set this bit to link up HCI and UART0.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UART1_CE": {
+                    "description": "Set this bit to link up HCI and UART1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEPER_EN": {
+                    "description": "Set this bit to separate the data frame using a special char.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HEAD_EN": {
+                    "description": "Set this bit to encode the data packet with a formatting header.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CRC_REC_EN": {
+                    "description": "Set this bit to enable UHCI to receive the 16 bit CRC.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UART_IDLE_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LEN_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ENCODE_CRC_EN": {
+                    "description": "Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UART_RX_BRK_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "a",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_RAW": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_START_INT_RAW": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_RAW": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_RAW": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_S_REG_Q_INT_RAW": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_A_REG_Q_INT_RAW": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_INT_RAW": {
+                    "description": "This is the interrupt raw bit. Triggered when there are some errors in EOF in the",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP_CTRL0_INT_RAW": {
+                    "description": "Soft control int raw bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "APP_CTRL1_INT_RAW": {
+                    "description": "Soft control int raw bit.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "a",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_ST": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_START_INT_ST": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_ST": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_ST": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_S_REG_Q_INT_ST": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_A_REG_Q_INT_ST": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTLINK_EOF_ERR_INT_ST": {
+                    "description": "a",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP_CTRL0_INT_ST": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP_CTRL1_INT_ST": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "a",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_ENA": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_START_INT_ENA": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RX_HUNG_INT_ENA": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_HUNG_INT_ENA": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEND_S_REG_Q_INT_ENA": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SEND_A_REG_Q_INT_ENA": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUTLINK_EOF_ERR_INT_ENA": {
+                    "description": "a",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "APP_CTRL0_INT_ENA": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "APP_CTRL1_INT_ENA": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "a",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_CLR": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_START_INT_CLR": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_HUNG_INT_CLR": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_HUNG_INT_CLR": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SEND_S_REG_Q_INT_CLR": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SEND_A_REG_Q_INT_CLR": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTLINK_EOF_ERR_INT_CLR": {
+                    "description": "a",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP_CTRL0_INT_CLR": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP_CTRL1_INT_CLR": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONF1": {
+              "description": "a",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 51,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHECK_SUM_EN": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHECK_SEQ_EN": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CRC_DISABLE": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SAVE_HEAD": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TX_CHECK_SUM_RE": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TX_ACK_NUM_RE": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WAIT_SW_START": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SW_START": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATE0": {
+              "description": "a",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_ERR_CAUSE": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DECODE_STATE": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STATE1": {
+              "description": "a",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENCODE_STATE": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ESCAPE_CONF": {
+              "description": "a",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 51,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_C0_ESC_EN": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_DB_ESC_EN": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_11_ESC_EN": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_13_ESC_EN": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_C0_ESC_EN": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_DB_ESC_EN": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RX_11_ESC_EN": {
+                    "description": "a",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RX_13_ESC_EN": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HUNG_CONF": {
+              "description": "a",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 8456208,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFIFO_TIMEOUT": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "TXFIFO_TIMEOUT_SHIFT": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "TXFIFO_TIMEOUT_ENA": {
+                    "description": "a",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXFIFO_TIMEOUT": {
+                    "description": "a",
+                    "offset": 12,
+                    "size": 8
+                  },
+                  "RXFIFO_TIMEOUT_SHIFT": {
+                    "description": "a",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "RXFIFO_TIMEOUT_ENA": {
+                    "description": "a",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ACK_NUM": {
+              "description": "a",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACK_NUM": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "LOAD": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RX_HEAD": {
+              "description": "a",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_HEAD": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUICK_SENT": {
+              "description": "a",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SINGLE_SEND_NUM": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SINGLE_SEND_EN": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALWAYS_SEND_NUM": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "ALWAYS_SEND_EN": {
+                    "description": "a",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REG_Q0_WORD0": {
+              "description": "a",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q0_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q0_WORD1": {
+              "description": "a",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q0_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q1_WORD0": {
+              "description": "a",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q1_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q1_WORD1": {
+              "description": "a",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q1_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q2_WORD0": {
+              "description": "a",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q2_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q2_WORD1": {
+              "description": "a",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q2_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q3_WORD0": {
+              "description": "a",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q3_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q3_WORD1": {
+              "description": "a",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q3_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q4_WORD0": {
+              "description": "a",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q4_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q4_WORD1": {
+              "description": "a",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q4_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q5_WORD0": {
+              "description": "a",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q5_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q5_WORD1": {
+              "description": "a",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q5_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q6_WORD0": {
+              "description": "a",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q6_WORD0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REG_Q6_WORD1": {
+              "description": "a",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEND_Q6_WORD1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ESC_CONF0": {
+              "description": "a",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 14474176,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEPER_CHAR": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SEPER_ESC_CHAR0": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SEPER_ESC_CHAR1": {
+                    "description": "a",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ESC_CONF1": {
+              "description": "a",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 14539739,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ESC_SEQ0": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "ESC_SEQ0_CHAR0": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ESC_SEQ0_CHAR1": {
+                    "description": "a",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ESC_CONF2": {
+              "description": "a",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 14605073,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ESC_SEQ1": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "ESC_SEQ1_CHAR0": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ESC_SEQ1_CHAR1": {
+                    "description": "a",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ESC_CONF3": {
+              "description": "a",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 14670611,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ESC_SEQ2": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "ESC_SEQ2_CHAR0": {
+                    "description": "a",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ESC_SEQ2_CHAR1": {
+                    "description": "a",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PKT_THRES": {
+              "description": "a",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PKT_THRS": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "a",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 33583472,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "ESP32-C3": {
+      "arch": "unknown",
+      "description": "32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)",
+      "properties": {
+        "cpu.mpuPresent": "false",
+        "cpu.nvicPrioBits": "4",
+        "cpu.vendorSystickConfig": "false",
+        "cpu.revision": "r0p0",
+        "cpu.endian": "little",
+        "license": "\n    Copyright 2022 Espressif Systems (Shanghai) PTE LTD\n\n    Licensed under the Apache License, Version 2.0 (the \"License\");\n    you may not use this file except in compliance with the License.\n    You may obtain a copy of the License at\n\n        http://www.apache.org/licenses/LICENSE-2.0\n\n    Unless required by applicable law or agreed to in writing, software\n    distributed under the License is distributed on an \"AS IS\" BASIS,\n    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n    See the License for the specific language governing permissions and\n    limitations under the License.\n",
+        "cpu.name": "RV32IMC",
+        "cpu.fpuPresent": "false"
+      },
+      "children": {
+        "interrupts": {
+          "AES": {
+            "index": 48
+          },
+          "APB_ADC": {
+            "index": 43
+          },
+          "ASSIST_DEBUG": {
+            "index": 54
+          },
+          "DMA_CH0": {
+            "index": 44
+          },
+          "DMA_CH1": {
+            "index": 45
+          },
+          "DMA_CH2": {
+            "index": 46
+          },
+          "EFUSE": {
+            "index": 24
+          },
+          "GPIO": {
+            "index": 16
+          },
+          "GPIO_NMI": {
+            "index": 17
+          },
+          "I2C_EXT0": {
+            "index": 29
+          },
+          "I2S": {
+            "index": 20
+          },
+          "LEDC": {
+            "index": 23
+          },
+          "RMT": {
+            "index": 28
+          },
+          "RSA": {
+            "index": 47
+          },
+          "RTC_CORE": {
+            "index": 27
+          },
+          "SHA": {
+            "index": 49
+          },
+          "SPI2": {
+            "index": 19
+          },
+          "SYSTIMER_TARGET0": {
+            "index": 37
+          },
+          "SYSTIMER_TARGET1": {
+            "index": 38
+          },
+          "SYSTIMER_TARGET2": {
+            "index": 39
+          },
+          "TG0_T0_LEVEL": {
+            "index": 32
+          },
+          "TG0_WDT_LEVEL": {
+            "index": 33
+          },
+          "TG1_T0_LEVEL": {
+            "index": 34
+          },
+          "TG1_WDT_LEVEL": {
+            "index": 35
+          },
+          "TWAI": {
+            "index": 25
+          },
+          "UART0": {
+            "index": 21
+          },
+          "UART1": {
+            "index": 22
+          },
+          "UHCI0": {
+            "index": 15
+          },
+          "USB_SERIAL_JTAG": {
+            "index": 26
+          }
+        },
+        "peripheral_instances": {
+          "AES": {
+            "description": "AES (Advanced Encryption Standard) Accelerator",
+            "offset": 1610850304,
+            "type": "types.peripherals.AES"
+          },
+          "APB_CTRL": {
+            "description": "Advanced Peripheral Bus Controller",
+            "offset": 1610768384,
+            "type": "types.peripherals.APB_CTRL"
+          },
+          "APB_SARADC": {
+            "description": "Successive Approximation Register Analog to Digital Converter",
+            "offset": 1610874880,
+            "type": "types.peripherals.APB_SARADC"
+          },
+          "ASSIST_DEBUG": {
+            "description": "Debug Assist",
+            "offset": 1611456512,
+            "type": "types.peripherals.ASSIST_DEBUG"
+          },
+          "DMA": {
+            "description": "DMA (Direct Memory Access) Controller",
+            "offset": 1610870784,
+            "type": "types.peripherals.DMA"
+          },
+          "DS": {
+            "description": "Digital Signature",
+            "offset": 1610862592,
+            "type": "types.peripherals.DS"
+          },
+          "EFUSE": {
+            "description": "eFuse Controller",
+            "offset": 1610647552,
+            "type": "types.peripherals.EFUSE"
+          },
+          "EXTMEM": {
+            "description": "External Memory",
+            "offset": 1611415552,
+            "type": "types.peripherals.EXTMEM"
+          },
+          "GPIO": {
+            "description": "General Purpose Input/Output",
+            "offset": 1610629120,
+            "type": "types.peripherals.GPIO"
+          },
+          "GPIOSD": {
+            "description": "Sigma-Delta Modulation",
+            "offset": 1610632960,
+            "type": "types.peripherals.GPIOSD"
+          },
+          "HMAC": {
+            "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
+            "offset": 1610866688,
+            "type": "types.peripherals.HMAC"
+          },
+          "I2C0": {
+            "description": "I2C (Inter-Integrated Circuit) Controller",
+            "offset": 1610690560,
+            "type": "types.peripherals.I2C0"
+          },
+          "I2S": {
+            "description": "I2S (Inter-IC Sound) Controller",
+            "offset": 1610797056,
+            "type": "types.peripherals.I2S"
+          },
+          "INTERRUPT_CORE0": {
+            "description": "Interrupt Core",
+            "offset": 1611407360,
+            "type": "types.peripherals.INTERRUPT_CORE0"
+          },
+          "IO_MUX": {
+            "description": "Input/Output Multiplexer",
+            "offset": 1610649600,
+            "type": "types.peripherals.IO_MUX"
+          },
+          "LEDC": {
+            "description": "LED Control PWM (Pulse Width Modulation)",
+            "offset": 1610715136,
+            "type": "types.peripherals.LEDC"
+          },
+          "RMT": {
+            "description": "Remote Control Peripheral",
+            "offset": 1610702848,
+            "type": "types.peripherals.RMT"
+          },
+          "RNG": {
+            "description": "Hardware random number generator",
+            "offset": 1610768384,
+            "type": "types.peripherals.RNG"
+          },
+          "RSA": {
+            "description": "RSA (Rivest Shamir Adleman) Accelerator",
+            "offset": 1610858496,
+            "type": "types.peripherals.RSA"
+          },
+          "RTC_CNTL": {
+            "description": "Real-Time Clock Control",
+            "offset": 1610645504,
+            "type": "types.peripherals.RTC_CNTL"
+          },
+          "SENSITIVE": {
+            "description": "Sensitive",
+            "offset": 1611403264,
+            "type": "types.peripherals.SENSITIVE"
+          },
+          "SHA": {
+            "description": "SHA (Secure Hash Algorithm) Accelerator",
+            "offset": 1610854400,
+            "type": "types.peripherals.SHA"
+          },
+          "SPI0": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610625024,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPI1": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610620928,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610760192,
+            "type": "types.peripherals.SPI2"
+          },
+          "SYSTEM": {
+            "description": "System",
+            "offset": 1611399168,
+            "type": "types.peripherals.SYSTEM"
+          },
+          "SYSTIMER": {
+            "description": "System Timer",
+            "offset": 1610756096,
+            "type": "types.peripherals.SYSTIMER"
+          },
+          "TIMG0": {
+            "description": "Timer Group",
+            "offset": 1610739712,
+            "type": "types.peripherals.TIMG0"
+          },
+          "TIMG1": {
+            "description": "Timer Group",
+            "offset": 1610743808,
+            "type": "types.peripherals.TIMG0"
+          },
+          "TWAI": {
+            "description": "Two-Wire Automotive Interface",
+            "offset": 1610788864,
+            "type": "types.peripherals.TWAI"
+          },
+          "UART0": {
+            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+            "offset": 1610612736,
+            "type": "types.peripherals.UART0"
+          },
+          "UART1": {
+            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+            "offset": 1610678272,
+            "type": "types.peripherals.UART0"
+          },
+          "UHCI0": {
+            "description": "Universal Host Controller Interface",
+            "offset": 1610694656,
+            "type": "types.peripherals.UHCI0"
+          },
+          "UHCI1": {
+            "description": "Universal Host Controller Interface",
+            "offset": 1610661888,
+            "type": "types.peripherals.UHCI0"
+          },
+          "USB_DEVICE": {
+            "description": "Full-speed USB Serial/JTAG Controller",
+            "offset": 1610887168,
+            "type": "types.peripherals.USB_DEVICE"
+          },
+          "XTS_AES": {
+            "description": "XTS-AES-128 Flash Encryption",
+            "offset": 1611448320,
+            "type": "types.peripherals.XTS_AES"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
new file mode 100644
index 0000000..50a3263
--- /dev/null
+++ b/src/chips/ESP32_C3.zig
@@ -0,0 +1,12378 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
+    pub const @"ESP32-C3" = struct {
+        pub const properties = struct {
+            pub const @"cpu.mpuPresent" = "false";
+            pub const @"cpu.nvicPrioBits" = "4";
+            pub const @"cpu.vendorSystickConfig" = "false";
+            pub const @"cpu.revision" = "r0p0";
+            pub const @"cpu.endian" = "little";
+            pub const license =
+                \\
+                \\    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+                \\
+                \\    Licensed under the Apache License, Version 2.0 (the "License");
+                \\    you may not use this file except in compliance with the License.
+                \\    You may obtain a copy of the License at
+                \\
+                \\        http://www.apache.org/licenses/LICENSE-2.0
+                \\
+                \\    Unless required by applicable law or agreed to in writing, software
+                \\    distributed under the License is distributed on an "AS IS" BASIS,
+                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+                \\    See the License for the specific language governing permissions and
+                \\    limitations under the License.
+                \\
+            ;
+            pub const @"cpu.name" = "RV32IMC";
+            pub const @"cpu.fpuPresent" = "false";
+        };
+
+        pub const peripherals = struct {
+            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x60000000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI1, 0x60002000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x60003000);
+            ///  General Purpose Input/Output
+            pub const GPIO = @intToPtr(*volatile types.peripherals.GPIO, 0x60004000);
+            ///  Sigma-Delta Modulation
+            pub const GPIOSD = @intToPtr(*volatile types.peripherals.GPIOSD, 0x60004f00);
+            ///  Real-Time Clock Control
+            pub const RTC_CNTL = @intToPtr(*volatile types.peripherals.RTC_CNTL, 0x60008000);
+            ///  eFuse Controller
+            pub const EFUSE = @intToPtr(*volatile types.peripherals.EFUSE, 0x60008800);
+            ///  Input/Output Multiplexer
+            pub const IO_MUX = @intToPtr(*volatile types.peripherals.IO_MUX, 0x60009000);
+            ///  Universal Host Controller Interface
+            pub const UHCI1 = @intToPtr(*volatile types.peripherals.UHCI0, 0x6000c000);
+            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x60010000);
+            ///  I2C (Inter-Integrated Circuit) Controller
+            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x60013000);
+            ///  Universal Host Controller Interface
+            pub const UHCI0 = @intToPtr(*volatile types.peripherals.UHCI0, 0x60014000);
+            ///  Remote Control Peripheral
+            pub const RMT = @intToPtr(*volatile types.peripherals.RMT, 0x60016000);
+            ///  LED Control PWM (Pulse Width Modulation)
+            pub const LEDC = @intToPtr(*volatile types.peripherals.LEDC, 0x60019000);
+            ///  Timer Group
+            pub const TIMG0 = @intToPtr(*volatile types.peripherals.TIMG0, 0x6001f000);
+            ///  Timer Group
+            pub const TIMG1 = @intToPtr(*volatile types.peripherals.TIMG0, 0x60020000);
+            ///  System Timer
+            pub const SYSTIMER = @intToPtr(*volatile types.peripherals.SYSTIMER, 0x60023000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI2, 0x60024000);
+            ///  Advanced Peripheral Bus Controller
+            pub const APB_CTRL = @intToPtr(*volatile types.peripherals.APB_CTRL, 0x60026000);
+            ///  Hardware random number generator
+            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x60026000);
+            ///  Two-Wire Automotive Interface
+            pub const TWAI = @intToPtr(*volatile types.peripherals.TWAI, 0x6002b000);
+            ///  I2S (Inter-IC Sound) Controller
+            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x6002d000);
+            ///  AES (Advanced Encryption Standard) Accelerator
+            pub const AES = @intToPtr(*volatile types.peripherals.AES, 0x6003a000);
+            ///  SHA (Secure Hash Algorithm) Accelerator
+            pub const SHA = @intToPtr(*volatile types.peripherals.SHA, 0x6003b000);
+            ///  RSA (Rivest Shamir Adleman) Accelerator
+            pub const RSA = @intToPtr(*volatile types.peripherals.RSA, 0x6003c000);
+            ///  Digital Signature
+            pub const DS = @intToPtr(*volatile types.peripherals.DS, 0x6003d000);
+            ///  HMAC (Hash-based Message Authentication Code) Accelerator
+            pub const HMAC = @intToPtr(*volatile types.peripherals.HMAC, 0x6003e000);
+            ///  DMA (Direct Memory Access) Controller
+            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x6003f000);
+            ///  Successive Approximation Register Analog to Digital Converter
+            pub const APB_SARADC = @intToPtr(*volatile types.peripherals.APB_SARADC, 0x60040000);
+            ///  Full-speed USB Serial/JTAG Controller
+            pub const USB_DEVICE = @intToPtr(*volatile types.peripherals.USB_DEVICE, 0x60043000);
+            ///  System
+            pub const SYSTEM = @intToPtr(*volatile types.peripherals.SYSTEM, 0x600c0000);
+            ///  Sensitive
+            pub const SENSITIVE = @intToPtr(*volatile types.peripherals.SENSITIVE, 0x600c1000);
+            ///  Interrupt Core
+            pub const INTERRUPT_CORE0 = @intToPtr(*volatile types.peripherals.INTERRUPT_CORE0, 0x600c2000);
+            ///  External Memory
+            pub const EXTMEM = @intToPtr(*volatile types.peripherals.EXTMEM, 0x600c4000);
+            ///  XTS-AES-128 Flash Encryption
+            pub const XTS_AES = @intToPtr(*volatile types.peripherals.XTS_AES, 0x600cc000);
+            ///  Debug Assist
+            pub const ASSIST_DEBUG = @intToPtr(*volatile types.peripherals.ASSIST_DEBUG, 0x600ce000);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  AES (Advanced Encryption Standard) Accelerator
+        pub const AES = extern struct {
+            ///  Key material key_0 configure register
+            KEY_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_0 that is a part of key material.
+                KEY_0: u32,
+            }),
+            ///  Key material key_1 configure register
+            KEY_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_1 that is a part of key material.
+                KEY_1: u32,
+            }),
+            ///  Key material key_2 configure register
+            KEY_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_2 that is a part of key material.
+                KEY_2: u32,
+            }),
+            ///  Key material key_3 configure register
+            KEY_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_3 that is a part of key material.
+                KEY_3: u32,
+            }),
+            ///  Key material key_4 configure register
+            KEY_4: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_4 that is a part of key material.
+                KEY_4: u32,
+            }),
+            ///  Key material key_5 configure register
+            KEY_5: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_5 that is a part of key material.
+                KEY_5: u32,
+            }),
+            ///  Key material key_6 configure register
+            KEY_6: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_6 that is a part of key material.
+                KEY_6: u32,
+            }),
+            ///  Key material key_7 configure register
+            KEY_7: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_7 that is a part of key material.
+                KEY_7: u32,
+            }),
+            ///  source text material text_in_0 configure register
+            TEXT_IN_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_0 that is a part of source text material.
+                TEXT_IN_0: u32,
+            }),
+            ///  source text material text_in_1 configure register
+            TEXT_IN_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_1 that is a part of source text material.
+                TEXT_IN_1: u32,
+            }),
+            ///  source text material text_in_2 configure register
+            TEXT_IN_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_2 that is a part of source text material.
+                TEXT_IN_2: u32,
+            }),
+            ///  source text material text_in_3 configure register
+            TEXT_IN_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_3 that is a part of source text material.
+                TEXT_IN_3: u32,
+            }),
+            ///  result text material text_out_0 configure register
+            TEXT_OUT_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_0 that is a part of result text material.
+                TEXT_OUT_0: u32,
+            }),
+            ///  result text material text_out_1 configure register
+            TEXT_OUT_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_1 that is a part of result text material.
+                TEXT_OUT_1: u32,
+            }),
+            ///  result text material text_out_2 configure register
+            TEXT_OUT_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_2 that is a part of result text material.
+                TEXT_OUT_2: u32,
+            }),
+            ///  result text material text_out_3 configure register
+            TEXT_OUT_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_3 that is a part of result text material.
+                TEXT_OUT_3: u32,
+            }),
+            ///  AES Mode register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+                MODE: u3,
+                padding: u29,
+            }),
+            ///  AES Endian configure register
+            ENDIAN: mmio.Mmio(packed struct(u32) {
+                ///  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian
+                ENDIAN: u6,
+                padding: u26,
+            }),
+            ///  AES trigger register
+            TRIGGER: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to start AES calculation.
+                TRIGGER: u1,
+                padding: u31,
+            }),
+            ///  AES state register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
+                STATE: u2,
+                padding: u30,
+            }),
+            ///  The memory that stores initialization vector
+            IV_MEM: [16]u8,
+            ///  The memory that stores GCM hash subkey
+            H_MEM: [16]u8,
+            ///  The memory that stores J0
+            J0_MEM: [16]u8,
+            ///  The memory that stores T0
+            T0_MEM: [16]u8,
+            ///  DMA-AES working mode register
+            DMA_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+                DMA_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  AES cipher block mode register
+            BLOCK_MODE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+                BLOCK_MODE: u3,
+                padding: u29,
+            }),
+            ///  AES block number register
+            BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of Plaintext/ciphertext block.
+                BLOCK_NUM: u32,
+            }),
+            ///  Standard incrementing function configure register
+            INC_SEL: mmio.Mmio(packed struct(u32) {
+                ///  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+                INC_SEL: u1,
+                padding: u31,
+            }),
+            ///  Additional Authential Data block number register
+            AAD_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of AAD block.
+                AAD_BLOCK_NUM: u32,
+            }),
+            ///  AES remainder bit number register
+            REMAINDER_BIT_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of remainder bit.
+                REMAINDER_BIT_NUM: u7,
+                padding: u25,
+            }),
+            ///  AES continue register
+            CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to continue GCM operation.
+                CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  AES Interrupt clear register
+            INT_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the AES interrupt.
+                INT_CLEAR: u1,
+                padding: u31,
+            }),
+            ///  AES Interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+                INT_ENA: u1,
+                padding: u31,
+            }),
+            ///  AES version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores the version information of AES.
+                DATE: u30,
+                padding: u2,
+            }),
+            ///  AES-DMA exit config
+            DMA_EXIT: mmio.Mmio(packed struct(u32) {
+                ///  Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
+                DMA_EXIT: u1,
+                padding: u31,
+            }),
+        };
+
+        ///  Advanced Peripheral Bus Controller
+        pub const APB_CTRL = extern struct {
+            ///  APB_CTRL_SYSCLK_CONF_REG
+            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_pre_div_cnt
+                PRE_DIV_CNT: u10,
+                ///  reg_clk_320m_en
+                CLK_320M_EN: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                ///  reg_rst_tick_cnt
+                RST_TICK_CNT: u1,
+                padding: u19,
+            }),
+            ///  APB_CTRL_TICK_CONF_REG
+            TICK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_xtal_tick_num
+                XTAL_TICK_NUM: u8,
+                ///  reg_ck8m_tick_num
+                CK8M_TICK_NUM: u8,
+                ///  reg_tick_enable
+                TICK_ENABLE: u1,
+                padding: u15,
+            }),
+            ///  APB_CTRL_CLK_OUT_EN_REG
+            CLK_OUT_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_clk20_oen
+                CLK20_OEN: u1,
+                ///  reg_clk22_oen
+                CLK22_OEN: u1,
+                ///  reg_clk44_oen
+                CLK44_OEN: u1,
+                ///  reg_clk_bb_oen
+                CLK_BB_OEN: u1,
+                ///  reg_clk80_oen
+                CLK80_OEN: u1,
+                ///  reg_clk160_oen
+                CLK160_OEN: u1,
+                ///  reg_clk_320m_oen
+                CLK_320M_OEN: u1,
+                ///  reg_clk_adc_inf_oen
+                CLK_ADC_INF_OEN: u1,
+                ///  reg_clk_dac_cpu_oen
+                CLK_DAC_CPU_OEN: u1,
+                ///  reg_clk40x_bb_oen
+                CLK40X_BB_OEN: u1,
+                ///  reg_clk_xtal_oen
+                CLK_XTAL_OEN: u1,
+                padding: u21,
+            }),
+            ///  APB_CTRL_WIFI_BB_CFG_REG
+            WIFI_BB_CFG: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_bb_cfg
+                WIFI_BB_CFG: u32,
+            }),
+            ///  APB_CTRL_WIFI_BB_CFG_2_REG
+            WIFI_BB_CFG_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_bb_cfg_2
+                WIFI_BB_CFG_2: u32,
+            }),
+            ///  APB_CTRL_WIFI_CLK_EN_REG
+            WIFI_CLK_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_clk_en
+                WIFI_CLK_EN: u32,
+            }),
+            ///  APB_CTRL_WIFI_RST_EN_REG
+            WIFI_RST_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_rst
+                WIFI_RST: u32,
+            }),
+            ///  APB_CTRL_HOST_INF_SEL_REG
+            HOST_INF_SEL: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_io_swap
+                PERI_IO_SWAP: u8,
+                padding: u24,
+            }),
+            ///  APB_CTRL_EXT_MEM_PMS_LOCK_REG
+            EXT_MEM_PMS_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  reg_ext_mem_pms_lock
+                EXT_MEM_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            reserved40: [4]u8,
+            ///  APB_CTRL_FLASH_ACE0_ATTR_REG
+            FLASH_ACE0_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_attr
+                FLASH_ACE0_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_ATTR_REG
+            FLASH_ACE1_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_attr
+                FLASH_ACE1_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_ATTR_REG
+            FLASH_ACE2_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_attr
+                FLASH_ACE2_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_ATTR_REG
+            FLASH_ACE3_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_attr
+                FLASH_ACE3_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE0_ADDR_REG
+            FLASH_ACE0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_ADDR_REG
+            FLASH_ACE1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_ADDR_REG
+            FLASH_ACE2_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_ADDR_REG
+            FLASH_ACE3_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE0_SIZE_REG
+            FLASH_ACE0_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_size
+                FLASH_ACE0_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_SIZE_REG
+            FLASH_ACE1_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_size
+                FLASH_ACE1_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_SIZE_REG
+            FLASH_ACE2_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_size
+                FLASH_ACE2_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_SIZE_REG
+            FLASH_ACE3_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_size
+                FLASH_ACE3_SIZE: u13,
+                padding: u19,
+            }),
+            reserved136: [48]u8,
+            ///  APB_CTRL_SPI_MEM_PMS_CTRL_REG
+            SPI_MEM_PMS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_spi_mem_reject_int
+                SPI_MEM_REJECT_INT: u1,
+                ///  reg_spi_mem_reject_clr
+                SPI_MEM_REJECT_CLR: u1,
+                ///  reg_spi_mem_reject_cde
+                SPI_MEM_REJECT_CDE: u5,
+                padding: u25,
+            }),
+            ///  APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+            SPI_MEM_REJECT_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_spi_mem_reject_addr
+                SPI_MEM_REJECT_ADDR: u32,
+            }),
+            ///  APB_CTRL_SDIO_CTRL_REG
+            SDIO_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_sdio_win_access_en
+                SDIO_WIN_ACCESS_EN: u1,
+                padding: u31,
+            }),
+            ///  APB_CTRL_REDCY_SIG0_REG
+            REDCY_SIG0: mmio.Mmio(packed struct(u32) {
+                ///  reg_redcy_sig0
+                REDCY_SIG0: u31,
+                ///  reg_redcy_andor
+                REDCY_ANDOR: u1,
+            }),
+            ///  APB_CTRL_REDCY_SIG1_REG
+            REDCY_SIG1: mmio.Mmio(packed struct(u32) {
+                ///  reg_redcy_sig1
+                REDCY_SIG1: u31,
+                ///  reg_redcy_nandor
+                REDCY_NANDOR: u1,
+            }),
+            ///  APB_CTRL_FRONT_END_MEM_PD_REG
+            FRONT_END_MEM_PD: mmio.Mmio(packed struct(u32) {
+                ///  reg_agc_mem_force_pu
+                AGC_MEM_FORCE_PU: u1,
+                ///  reg_agc_mem_force_pd
+                AGC_MEM_FORCE_PD: u1,
+                ///  reg_pbus_mem_force_pu
+                PBUS_MEM_FORCE_PU: u1,
+                ///  reg_pbus_mem_force_pd
+                PBUS_MEM_FORCE_PD: u1,
+                ///  reg_dc_mem_force_pu
+                DC_MEM_FORCE_PU: u1,
+                ///  reg_dc_mem_force_pd
+                DC_MEM_FORCE_PD: u1,
+                padding: u26,
+            }),
+            ///  APB_CTRL_RETENTION_CTRL_REG
+            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_retention_link_addr
+                RETENTION_LINK_ADDR: u27,
+                ///  reg_nobypass_cpu_iso_rst
+                NOBYPASS_CPU_ISO_RST: u1,
+                padding: u4,
+            }),
+            ///  APB_CTRL_CLKGATE_FORCE_ON_REG
+            CLKGATE_FORCE_ON: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_clkgate_force_on
+                ROM_CLKGATE_FORCE_ON: u2,
+                ///  reg_sram_clkgate_force_on
+                SRAM_CLKGATE_FORCE_ON: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_MEM_POWER_DOWN_REG
+            MEM_POWER_DOWN: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_power_down
+                ROM_POWER_DOWN: u2,
+                ///  reg_sram_power_down
+                SRAM_POWER_DOWN: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_MEM_POWER_UP_REG
+            MEM_POWER_UP: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_power_up
+                ROM_POWER_UP: u2,
+                ///  reg_sram_power_up
+                SRAM_POWER_UP: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_RND_DATA_REG
+            RND_DATA: mmio.Mmio(packed struct(u32) {
+                ///  reg_rnd_data
+                RND_DATA: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_CONFIG_REG
+            PERI_BACKUP_CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_peri_backup_flow_err
+                PERI_BACKUP_FLOW_ERR: u2,
+                reserved4: u1,
+                ///  reg_peri_backup_burst_limit
+                PERI_BACKUP_BURST_LIMIT: u5,
+                ///  reg_peri_backup_tout_thres
+                PERI_BACKUP_TOUT_THRES: u10,
+                ///  reg_peri_backup_size
+                PERI_BACKUP_SIZE: u10,
+                ///  reg_peri_backup_start
+                PERI_BACKUP_START: u1,
+                ///  reg_peri_backup_to_mem
+                PERI_BACKUP_TO_MEM: u1,
+                ///  reg_peri_backup_ena
+                PERI_BACKUP_ENA: u1,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+            PERI_BACKUP_APB_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_backup_apb_start_addr
+                BACKUP_APB_START_ADDR: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+            PERI_BACKUP_MEM_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_backup_mem_start_addr
+                BACKUP_MEM_START_ADDR: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_RAW_REG
+            PERI_BACKUP_INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_raw
+                PERI_BACKUP_DONE_INT_RAW: u1,
+                ///  reg_peri_backup_err_int_raw
+                PERI_BACKUP_ERR_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_ST_REG
+            PERI_BACKUP_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_st
+                PERI_BACKUP_DONE_INT_ST: u1,
+                ///  reg_peri_backup_err_int_st
+                PERI_BACKUP_ERR_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_ENA_REG
+            PERI_BACKUP_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_ena
+                PERI_BACKUP_DONE_INT_ENA: u1,
+                ///  reg_peri_backup_err_int_ena
+                PERI_BACKUP_ERR_INT_ENA: u1,
+                padding: u30,
+            }),
+            reserved208: [4]u8,
+            ///  APB_CTRL_PERI_BACKUP_INT_CLR_REG
+            PERI_BACKUP_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_clr
+                PERI_BACKUP_DONE_INT_CLR: u1,
+                ///  reg_peri_backup_err_int_clr
+                PERI_BACKUP_ERR_INT_CLR: u1,
+                padding: u30,
+            }),
+            reserved1020: [808]u8,
+            ///  APB_CTRL_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_dateVersion control
+                DATE: u32,
+            }),
+        };
+
+        ///  Successive Approximation Register Analog to Digital Converter
+        pub const APB_SARADC = extern struct {
+            ///  digital saradc configure register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  select software enable saradc sample
+                SARADC_START_FORCE: u1,
+                ///  software enable saradc sample
+                SARADC_START: u1,
+                reserved6: u4,
+                ///  SAR clock gated
+                SARADC_SAR_CLK_GATED: u1,
+                ///  SAR clock divider
+                SARADC_SAR_CLK_DIV: u8,
+                ///  0 ~ 15 means length 1 ~ 16
+                SARADC_SAR_PATT_LEN: u3,
+                reserved23: u5,
+                ///  clear the pointer of pattern table for DIG ADC1 CTRL
+                SARADC_SAR_PATT_P_CLEAR: u1,
+                reserved27: u3,
+                ///  force option to xpd sar blocks
+                SARADC_XPD_SAR_FORCE: u2,
+                reserved30: u1,
+                ///  wait arbit signal stable after sar_done
+                SARADC_WAIT_ARB_CYCLE: u2,
+            }),
+            ///  digital saradc configure register
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  enable max meas num
+                SARADC_MEAS_NUM_LIMIT: u1,
+                ///  max conversion number
+                SARADC_MAX_MEAS_NUM: u8,
+                ///  1: data to DIG ADC1 CTRL is inverted, otherwise not
+                SARADC_SAR1_INV: u1,
+                ///  1: data to DIG ADC2 CTRL is inverted, otherwise not
+                SARADC_SAR2_INV: u1,
+                reserved12: u1,
+                ///  to set saradc timer target
+                SARADC_TIMER_TARGET: u12,
+                ///  to enable saradc timer trigger
+                SARADC_TIMER_EN: u1,
+                padding: u7,
+            }),
+            ///  digital saradc configure register
+            FILTER_CTRL1: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  Factor of saradc filter1
+                APB_SARADC_FILTER_FACTOR1: u3,
+                ///  Factor of saradc filter0
+                APB_SARADC_FILTER_FACTOR0: u3,
+            }),
+            ///  digital saradc configure register
+            FSM_WAIT: mmio.Mmio(packed struct(u32) {
+                ///  saradc_xpd_wait
+                SARADC_XPD_WAIT: u8,
+                ///  saradc_rstb_wait
+                SARADC_RSTB_WAIT: u8,
+                ///  saradc_standby_wait
+                SARADC_STANDBY_WAIT: u8,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            SAR1_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc1 status about data and channel
+                SARADC_SAR1_STATUS: u32,
+            }),
+            ///  digital saradc configure register
+            SAR2_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc2 status about data and channel
+                SARADC_SAR2_STATUS: u32,
+            }),
+            ///  digital saradc configure register
+            SAR_PATT_TAB1: mmio.Mmio(packed struct(u32) {
+                ///  item 0 ~ 3 for pattern table 1 (each item one byte)
+                SARADC_SAR_PATT_TAB1: u24,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            SAR_PATT_TAB2: mmio.Mmio(packed struct(u32) {
+                ///  Item 4 ~ 7 for pattern table 1 (each item one byte)
+                SARADC_SAR_PATT_TAB2: u24,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            ONETIME_SAMPLE: mmio.Mmio(packed struct(u32) {
+                reserved23: u23,
+                ///  configure onetime atten
+                SARADC_ONETIME_ATTEN: u2,
+                ///  configure onetime channel
+                SARADC_ONETIME_CHANNEL: u4,
+                ///  trigger adc onetime sample
+                SARADC_ONETIME_START: u1,
+                ///  enable adc2 onetime sample
+                SARADC2_ONETIME_SAMPLE: u1,
+                ///  enable adc1 onetime sample
+                SARADC1_ONETIME_SAMPLE: u1,
+            }),
+            ///  digital saradc configure register
+            ARB_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  adc2 arbiter force to enableapb controller
+                ADC_ARB_APB_FORCE: u1,
+                ///  adc2 arbiter force to enable rtc controller
+                ADC_ARB_RTC_FORCE: u1,
+                ///  adc2 arbiter force to enable wifi controller
+                ADC_ARB_WIFI_FORCE: u1,
+                ///  adc2 arbiter force grant
+                ADC_ARB_GRANT_FORCE: u1,
+                ///  Set adc2 arbiterapb priority
+                ADC_ARB_APB_PRIORITY: u2,
+                ///  Set adc2 arbiter rtc priority
+                ADC_ARB_RTC_PRIORITY: u2,
+                ///  Set adc2 arbiter wifi priority
+                ADC_ARB_WIFI_PRIORITY: u2,
+                ///  adc2 arbiter uses fixed priority
+                ADC_ARB_FIX_PRIORITY: u1,
+                padding: u19,
+            }),
+            ///  digital saradc configure register
+            FILTER_CTRL0: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  configure filter1 to adc channel
+                APB_SARADC_FILTER_CHANNEL1: u4,
+                ///  configure filter0 to adc channel
+                APB_SARADC_FILTER_CHANNEL0: u4,
+                reserved31: u5,
+                ///  enable apb_adc1_filter
+                APB_SARADC_FILTER_RESET: u1,
+            }),
+            ///  digital saradc configure register
+            SAR1DATA_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc1 data
+                APB_SARADC1_DATA: u17,
+                padding: u15,
+            }),
+            ///  digital saradc configure register
+            SAR2DATA_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc2 data
+                APB_SARADC2_DATA: u17,
+                padding: u15,
+            }),
+            ///  digital saradc configure register
+            THRES0_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  configure thres0 to adc channel
+                APB_SARADC_THRES0_CHANNEL: u4,
+                reserved5: u1,
+                ///  saradc thres0 monitor thres
+                APB_SARADC_THRES0_HIGH: u13,
+                ///  saradc thres0 monitor thres
+                APB_SARADC_THRES0_LOW: u13,
+                padding: u1,
+            }),
+            ///  digital saradc configure register
+            THRES1_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  configure thres1 to adc channel
+                APB_SARADC_THRES1_CHANNEL: u4,
+                reserved5: u1,
+                ///  saradc thres1 monitor thres
+                APB_SARADC_THRES1_HIGH: u13,
+                ///  saradc thres1 monitor thres
+                APB_SARADC_THRES1_LOW: u13,
+                padding: u1,
+            }),
+            ///  digital saradc configure register
+            THRES_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  enable thres to all channel
+                APB_SARADC_THRES_ALL_EN: u1,
+                reserved30: u2,
+                ///  enable thres1
+                APB_SARADC_THRES1_EN: u1,
+                ///  enable thres0
+                APB_SARADC_THRES0_EN: u1,
+            }),
+            ///  digital saradc int register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt enable
+                APB_SARADC_THRES1_LOW_INT_ENA: u1,
+                ///  saradc thres0 low interrupt enable
+                APB_SARADC_THRES0_LOW_INT_ENA: u1,
+                ///  saradc thres1 high interrupt enable
+                APB_SARADC_THRES1_HIGH_INT_ENA: u1,
+                ///  saradc thres0 high interrupt enable
+                APB_SARADC_THRES0_HIGH_INT_ENA: u1,
+                ///  saradc2 done interrupt enable
+                APB_SARADC2_DONE_INT_ENA: u1,
+                ///  saradc1 done interrupt enable
+                APB_SARADC1_DONE_INT_ENA: u1,
+            }),
+            ///  digital saradc int register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt raw
+                APB_SARADC_THRES1_LOW_INT_RAW: u1,
+                ///  saradc thres0 low interrupt raw
+                APB_SARADC_THRES0_LOW_INT_RAW: u1,
+                ///  saradc thres1 high interrupt raw
+                APB_SARADC_THRES1_HIGH_INT_RAW: u1,
+                ///  saradc thres0 high interrupt raw
+                APB_SARADC_THRES0_HIGH_INT_RAW: u1,
+                ///  saradc2 done interrupt raw
+                APB_SARADC2_DONE_INT_RAW: u1,
+                ///  saradc1 done interrupt raw
+                APB_SARADC1_DONE_INT_RAW: u1,
+            }),
+            ///  digital saradc int register
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt state
+                APB_SARADC_THRES1_LOW_INT_ST: u1,
+                ///  saradc thres0 low interrupt state
+                APB_SARADC_THRES0_LOW_INT_ST: u1,
+                ///  saradc thres1 high interrupt state
+                APB_SARADC_THRES1_HIGH_INT_ST: u1,
+                ///  saradc thres0 high interrupt state
+                APB_SARADC_THRES0_HIGH_INT_ST: u1,
+                ///  saradc2 done interrupt state
+                APB_SARADC2_DONE_INT_ST: u1,
+                ///  saradc1 done interrupt state
+                APB_SARADC1_DONE_INT_ST: u1,
+            }),
+            ///  digital saradc int register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt clear
+                APB_SARADC_THRES1_LOW_INT_CLR: u1,
+                ///  saradc thres0 low interrupt clear
+                APB_SARADC_THRES0_LOW_INT_CLR: u1,
+                ///  saradc thres1 high interrupt clear
+                APB_SARADC_THRES1_HIGH_INT_CLR: u1,
+                ///  saradc thres0 high interrupt clear
+                APB_SARADC_THRES0_HIGH_INT_CLR: u1,
+                ///  saradc2 done interrupt clear
+                APB_SARADC2_DONE_INT_CLR: u1,
+                ///  saradc1 done interrupt clear
+                APB_SARADC1_DONE_INT_CLR: u1,
+            }),
+            ///  digital saradc configure register
+            DMA_CONF: mmio.Mmio(packed struct(u32) {
+                ///  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+                APB_ADC_EOF_NUM: u16,
+                reserved30: u14,
+                ///  reset_apb_adc_state
+                APB_ADC_RESET_FSM: u1,
+                ///  enable apb_adc use spi_dma
+                APB_ADC_TRANS: u1,
+            }),
+            ///  digital saradc configure register
+            CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S clock divider value
+                CLKM_DIV_NUM: u8,
+                ///  Fractional clock divider numerator value
+                CLKM_DIV_B: u6,
+                ///  Fractional clock divider denominator value
+                CLKM_DIV_A: u6,
+                ///  reg clk en
+                CLK_EN: u1,
+                ///  Set this bit to enable clk_apll
+                CLK_SEL: u2,
+                padding: u9,
+            }),
+            ///  digital tsens configure register
+            APB_TSENS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  temperature sensor data out
+                TSENS_OUT: u8,
+                reserved13: u5,
+                ///  invert temperature sensor data
+                TSENS_IN_INV: u1,
+                ///  temperature sensor clock divider
+                TSENS_CLK_DIV: u8,
+                ///  temperature sensor power up
+                TSENS_PU: u1,
+                padding: u9,
+            }),
+            ///  digital tsens configure register
+            TSENS_CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  the time that power up tsens need wait
+                TSENS_XPD_WAIT: u12,
+                ///  force power up tsens
+                TSENS_XPD_FORCE: u2,
+                ///  inv tsens clk
+                TSENS_CLK_INV: u1,
+                ///  tsens clk select
+                TSENS_CLK_SEL: u1,
+                padding: u16,
+            }),
+            ///  digital saradc configure register
+            CALI: mmio.Mmio(packed struct(u32) {
+                ///  saradc cali factor
+                APB_SARADC_CALI_CFG: u17,
+                padding: u15,
+            }),
+            reserved1020: [920]u8,
+            ///  version
+            CTRL_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version
+                DATE: u32,
+            }),
+        };
+
+        ///  Debug Assist
+        pub const ASSIST_DEBUG = extern struct {
+            ///  ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+            C0RE_0_MONTR_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_ena
+                CORE_0_AREA_DRAM0_0_RD_ENA: u1,
+                ///  reg_core_0_area_dram0_0_wr_ena
+                CORE_0_AREA_DRAM0_0_WR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_rd_ena
+                CORE_0_AREA_DRAM0_1_RD_ENA: u1,
+                ///  reg_core_0_area_dram0_1_wr_ena
+                CORE_0_AREA_DRAM0_1_WR_ENA: u1,
+                ///  reg_core_0_area_pif_0_rd_ena
+                CORE_0_AREA_PIF_0_RD_ENA: u1,
+                ///  reg_core_0_area_pif_0_wr_ena
+                CORE_0_AREA_PIF_0_WR_ENA: u1,
+                ///  reg_core_0_area_pif_1_rd_ena
+                CORE_0_AREA_PIF_1_RD_ENA: u1,
+                ///  reg_core_0_area_pif_1_wr_ena
+                CORE_0_AREA_PIF_1_WR_ENA: u1,
+                ///  reg_core_0_sp_spill_min_ena
+                CORE_0_SP_SPILL_MIN_ENA: u1,
+                ///  reg_core_0_sp_spill_max_ena
+                CORE_0_SP_SPILL_MAX_ENA: u1,
+                ///  reg_core_0_iram0_exception_monitor_ena
+                CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
+                ///  reg_core_0_dram0_exception_monitor_ena
+                CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+            CORE_0_INTR_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_raw
+                CORE_0_AREA_DRAM0_0_RD_RAW: u1,
+                ///  reg_core_0_area_dram0_0_wr_raw
+                CORE_0_AREA_DRAM0_0_WR_RAW: u1,
+                ///  reg_core_0_area_dram0_1_rd_raw
+                CORE_0_AREA_DRAM0_1_RD_RAW: u1,
+                ///  reg_core_0_area_dram0_1_wr_raw
+                CORE_0_AREA_DRAM0_1_WR_RAW: u1,
+                ///  reg_core_0_area_pif_0_rd_raw
+                CORE_0_AREA_PIF_0_RD_RAW: u1,
+                ///  reg_core_0_area_pif_0_wr_raw
+                CORE_0_AREA_PIF_0_WR_RAW: u1,
+                ///  reg_core_0_area_pif_1_rd_raw
+                CORE_0_AREA_PIF_1_RD_RAW: u1,
+                ///  reg_core_0_area_pif_1_wr_raw
+                CORE_0_AREA_PIF_1_WR_RAW: u1,
+                ///  reg_core_0_sp_spill_min_raw
+                CORE_0_SP_SPILL_MIN_RAW: u1,
+                ///  reg_core_0_sp_spill_max_raw
+                CORE_0_SP_SPILL_MAX_RAW: u1,
+                ///  reg_core_0_iram0_exception_monitor_raw
+                CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
+                ///  reg_core_0_dram0_exception_monitor_raw
+                CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+            CORE_0_INTR_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_intr_ena
+                CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_0_wr_intr_ena
+                CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_rd_intr_ena
+                CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_wr_intr_ena
+                CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_0_rd_intr_ena
+                CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_0_wr_intr_ena
+                CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_1_rd_intr_ena
+                CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_1_wr_intr_ena
+                CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
+                ///  reg_core_0_sp_spill_min_intr_ena
+                CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
+                ///  reg_core_0_sp_spill_max_intr_ena
+                CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
+                ///  reg_core_0_iram0_exception_monitor_ena
+                CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
+                ///  reg_core_0_dram0_exception_monitor_ena
+                CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+            CORE_0_INTR_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_clr
+                CORE_0_AREA_DRAM0_0_RD_CLR: u1,
+                ///  reg_core_0_area_dram0_0_wr_clr
+                CORE_0_AREA_DRAM0_0_WR_CLR: u1,
+                ///  reg_core_0_area_dram0_1_rd_clr
+                CORE_0_AREA_DRAM0_1_RD_CLR: u1,
+                ///  reg_core_0_area_dram0_1_wr_clr
+                CORE_0_AREA_DRAM0_1_WR_CLR: u1,
+                ///  reg_core_0_area_pif_0_rd_clr
+                CORE_0_AREA_PIF_0_RD_CLR: u1,
+                ///  reg_core_0_area_pif_0_wr_clr
+                CORE_0_AREA_PIF_0_WR_CLR: u1,
+                ///  reg_core_0_area_pif_1_rd_clr
+                CORE_0_AREA_PIF_1_RD_CLR: u1,
+                ///  reg_core_0_area_pif_1_wr_clr
+                CORE_0_AREA_PIF_1_WR_CLR: u1,
+                ///  reg_core_0_sp_spill_min_clr
+                CORE_0_SP_SPILL_MIN_CLR: u1,
+                ///  reg_core_0_sp_spill_max_clr
+                CORE_0_SP_SPILL_MAX_CLR: u1,
+                ///  reg_core_0_iram0_exception_monitor_clr
+                CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
+                ///  reg_core_0_dram0_exception_monitor_clr
+                CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+            CORE_0_AREA_DRAM0_0_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_min
+                CORE_0_AREA_DRAM0_0_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+            CORE_0_AREA_DRAM0_0_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_max
+                CORE_0_AREA_DRAM0_0_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+            CORE_0_AREA_DRAM0_1_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_1_min
+                CORE_0_AREA_DRAM0_1_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+            CORE_0_AREA_DRAM0_1_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_1_max
+                CORE_0_AREA_DRAM0_1_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+            CORE_0_AREA_PIF_0_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_0_min
+                CORE_0_AREA_PIF_0_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+            CORE_0_AREA_PIF_0_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_0_max
+                CORE_0_AREA_PIF_0_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+            CORE_0_AREA_PIF_1_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_1_min
+                CORE_0_AREA_PIF_1_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+            CORE_0_AREA_PIF_1_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_1_max
+                CORE_0_AREA_PIF_1_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PC_REG
+            CORE_0_AREA_PC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pc
+                CORE_0_AREA_PC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_SP_REG
+            CORE_0_AREA_SP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_sp
+                CORE_0_AREA_SP: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_MIN_REG
+            CORE_0_SP_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_min
+                CORE_0_SP_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_MAX_REG
+            CORE_0_SP_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_max
+                CORE_0_SP_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_PC_REG
+            CORE_0_SP_PC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_pc
+                CORE_0_SP_PC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_EN_REG
+            CORE_0_RCD_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_recorden
+                CORE_0_RCD_RECORDEN: u1,
+                ///  reg_core_0_rcd_pdebugen
+                CORE_0_RCD_PDEBUGEN: u1,
+                padding: u30,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+            CORE_0_RCD_PDEBUGPC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_pdebugpc
+                CORE_0_RCD_PDEBUGPC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+            CORE_0_RCD_PDEBUGSP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_pdebugsp
+                CORE_0_RCD_PDEBUGSP: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+            CORE_0_IRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_iram0_recording_addr_0
+                CORE_0_IRAM0_RECORDING_ADDR_0: u24,
+                ///  reg_core_0_iram0_recording_wr_0
+                CORE_0_IRAM0_RECORDING_WR_0: u1,
+                ///  reg_core_0_iram0_recording_loadstore_0
+                CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
+                padding: u6,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_IRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_iram0_recording_addr_1
+                CORE_0_IRAM0_RECORDING_ADDR_1: u24,
+                ///  reg_core_0_iram0_recording_wr_1
+                CORE_0_IRAM0_RECORDING_WR_1: u1,
+                ///  reg_core_0_iram0_recording_loadstore_1
+                CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
+                padding: u6,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_addr_0
+                CORE_0_DRAM0_RECORDING_ADDR_0: u24,
+                ///  reg_core_0_dram0_recording_wr_0
+                CORE_0_DRAM0_RECORDING_WR_0: u1,
+                ///  reg_core_0_dram0_recording_byteen_0
+                CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
+                padding: u3,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_pc_0
+                CORE_0_DRAM0_RECORDING_PC_0: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_addr_1
+                CORE_0_DRAM0_RECORDING_ADDR_1: u24,
+                ///  reg_core_0_dram0_recording_wr_1
+                CORE_0_DRAM0_RECORDING_WR_1: u1,
+                ///  reg_core_0_dram0_recording_byteen_1
+                CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
+                padding: u3,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_pc_1
+                CORE_0_DRAM0_RECORDING_PC_1: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_x_iram0_dram0_limit_cycle_0
+                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
+                padding: u12,
+            }),
+            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_x_iram0_dram0_limit_cycle_1
+                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
+                padding: u12,
+            }),
+            ///  ASSIST_DEBUG_LOG_SETTING
+            LOG_SETTING: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_ena
+                LOG_ENA: u3,
+                ///  reg_log_mode
+                LOG_MODE: u4,
+                ///  reg_log_mem_loop_enable
+                LOG_MEM_LOOP_ENABLE: u1,
+                padding: u24,
+            }),
+            ///  ASSIST_DEBUG_LOG_DATA_0_REG
+            LOG_DATA_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_data_0
+                LOG_DATA_0: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_DATA_MASK_REG
+            LOG_DATA_MASK: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_data_size
+                LOG_DATA_SIZE: u16,
+                padding: u16,
+            }),
+            ///  ASSIST_DEBUG_LOG_MIN_REG
+            LOG_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_min
+                LOG_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MAX_REG
+            LOG_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_max
+                LOG_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_START_REG
+            LOG_MEM_START: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_start
+                LOG_MEM_START: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_END_REG
+            LOG_MEM_END: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_end
+                LOG_MEM_END: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+            LOG_MEM_WRITING_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_writing_addr
+                LOG_MEM_WRITING_ADDR: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+            LOG_MEM_FULL_FLAG: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_full_flag
+                LOG_MEM_FULL_FLAG: u1,
+                ///  reg_clr_log_mem_full_flag
+                CLR_LOG_MEM_FULL_FLAG: u1,
+                padding: u30,
+            }),
+            ///  ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+            C0RE_0_LASTPC_BEFORE_EXCEPTION: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_lastpc_before_exc
+                CORE_0_LASTPC_BEFORE_EXC: u32,
+            }),
+            ///  ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+            C0RE_0_DEBUG_MODE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_debug_mode
+                CORE_0_DEBUG_MODE: u1,
+                ///  reg_core_0_debug_module_active
+                CORE_0_DEBUG_MODULE_ACTIVE: u1,
+                padding: u30,
+            }),
+            reserved508: [352]u8,
+            ///  ASSIST_DEBUG_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_assist_debug_date
+                ASSIST_DEBUG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  DMA (Direct Memory Access) Controller
+        pub const DMA = extern struct {
+            ///  DMA_INT_RAW_CH0_REG.
+            INT_RAW_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
+                IN_DONE_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
+                IN_SUC_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
+                OUT_DONE_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
+                OUT_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
+                IN_DSCR_ERR_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
+                OUT_DSCR_ERR_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
+                IN_DSCR_EMPTY_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
+                OUT_TOTAL_EOF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
+                INFIFO_OVF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
+                INFIFO_UDF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
+                OUTFIFO_OVF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
+                OUTFIFO_UDF_CH0_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH0_REG.
+            INT_ST_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH0_REG.
+            INT_ENA_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH0_REG.
+            INT_CLR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_CLR: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_RAW_CH1_REG.
+            INT_RAW_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
+                IN_DONE_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
+                IN_SUC_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
+                OUT_DONE_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
+                OUT_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
+                IN_DSCR_ERR_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
+                OUT_DSCR_ERR_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
+                IN_DSCR_EMPTY_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
+                OUT_TOTAL_EOF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
+                INFIFO_OVF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
+                INFIFO_UDF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
+                OUTFIFO_OVF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
+                OUTFIFO_UDF_CH1_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH1_REG.
+            INT_ST_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH1_REG.
+            INT_ENA_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH1_REG.
+            INT_CLR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_CLR: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_RAW_CH2_REG.
+            INT_RAW_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
+                IN_DONE_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
+                IN_SUC_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
+                OUT_DONE_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
+                OUT_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
+                IN_DSCR_ERR_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
+                OUT_DSCR_ERR_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
+                IN_DSCR_EMPTY_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
+                OUT_TOTAL_EOF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
+                INFIFO_OVF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
+                INFIFO_UDF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
+                OUTFIFO_OVF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
+                OUTFIFO_UDF_CH2_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH2_REG.
+            INT_ST_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH2_REG.
+            INT_ENA_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH2_REG.
+            INT_CLR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_CLR: u1,
+                padding: u19,
+            }),
+            reserved64: [16]u8,
+            ///  DMA_AHB_TEST_REG.
+            AHB_TEST: mmio.Mmio(packed struct(u32) {
+                ///  reserved
+                AHB_TESTMODE: u3,
+                reserved4: u1,
+                ///  reserved
+                AHB_TESTADDR: u2,
+                padding: u26,
+            }),
+            ///  DMA_MISC_CONF_REG.
+            MISC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit, then clear this bit to reset the internal ahb FSM.
+                AHBM_RST_INTER: u1,
+                reserved2: u1,
+                ///  Set this bit to disable priority arbitration function.
+                ARB_PRI_DIS: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                padding: u28,
+            }),
+            ///  DMA_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  register version.
+                DATE: u32,
+            }),
+            reserved112: [36]u8,
+            ///  DMA_IN_CONF0_CH0_REG.
+            IN_CONF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH0: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH0: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH0: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH0_REG.
+            IN_CONF1_CH0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH0_REG.
+            INFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 0.
+                INFIFO_FULL_CH0: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 0.
+                INFIFO_EMPTY_CH0: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+                INFIFO_CNT_CH0: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH0: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH0: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH0_REG.
+            IN_POP_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH0: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH0_REG.
+            IN_LINK_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH0: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH0: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH0: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH0: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH0: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH0: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH0_REG.
+            IN_STATE_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH0: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH0: u2,
+                ///  reserved
+                IN_STATE_CH0: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+            IN_SUC_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+            IN_ERR_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_CH0_REG.
+            IN_DSCR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH0_REG.
+            IN_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH0_REG.
+            IN_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH0: u32,
+            }),
+            ///  DMA_IN_PRI_CH0_REG.
+            IN_PRI_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 0. The larger of the value, the higher of the priority.
+                RX_PRI_CH0: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH0_REG.
+            IN_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH0: u6,
+                padding: u26,
+            }),
+            reserved208: [44]u8,
+            ///  DMA_OUT_CONF0_CH0_REG.
+            OUT_CONF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH0: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH0: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH0: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH0: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH0_REG.
+            OUT_CONF1_CH0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH0_REG.
+            OUTFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 0.
+                OUTFIFO_FULL_CH0: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 0.
+                OUTFIFO_EMPTY_CH0: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+                OUTFIFO_CNT_CH0: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH0: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH0_REG.
+            OUT_PUSH_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH0: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH0: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH0_REG.
+            OUT_LINK_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH0: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH0: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH0: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH0: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH0: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH0_REG.
+            OUT_STATE_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH0: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH0: u2,
+                ///  reserved
+                OUT_STATE_CH0: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH0_REG.
+            OUT_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+            OUT_EOF_BFR_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH0_REG.
+            OUT_DSCR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH0_REG.
+            OUT_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH0_REG.
+            OUT_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH0: u32,
+            }),
+            ///  DMA_OUT_PRI_CH0_REG.
+            OUT_PRI_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 0. The larger of the value, the higher of the priority.
+                TX_PRI_CH0: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH0_REG.
+            OUT_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH0: u6,
+                padding: u26,
+            }),
+            reserved304: [44]u8,
+            ///  DMA_IN_CONF0_CH1_REG.
+            IN_CONF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH1: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH1: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH1: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH1_REG.
+            IN_CONF1_CH1: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH1_REG.
+            INFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 1.
+                INFIFO_FULL_CH1: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 1.
+                INFIFO_EMPTY_CH1: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+                INFIFO_CNT_CH1: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH1: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH1: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH1_REG.
+            IN_POP_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH1: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH1_REG.
+            IN_LINK_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH1: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH1: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH1: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH1: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH1: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH1: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH1_REG.
+            IN_STATE_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH1: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH1: u2,
+                ///  reserved
+                IN_STATE_CH1: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+            IN_SUC_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+            IN_ERR_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_CH1_REG.
+            IN_DSCR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH1_REG.
+            IN_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH1_REG.
+            IN_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH1: u32,
+            }),
+            ///  DMA_IN_PRI_CH1_REG.
+            IN_PRI_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 1. The larger of the value, the higher of the priority.
+                RX_PRI_CH1: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH1_REG.
+            IN_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH1: u6,
+                padding: u26,
+            }),
+            reserved400: [44]u8,
+            ///  DMA_OUT_CONF0_CH1_REG.
+            OUT_CONF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH1: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH1: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH1: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH1: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH1_REG.
+            OUT_CONF1_CH1: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH1_REG.
+            OUTFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 1.
+                OUTFIFO_FULL_CH1: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 1.
+                OUTFIFO_EMPTY_CH1: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+                OUTFIFO_CNT_CH1: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH1: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH1_REG.
+            OUT_PUSH_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH1: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH1: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH1_REG.
+            OUT_LINK_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH1: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH1: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH1: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH1: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH1: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH1_REG.
+            OUT_STATE_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH1: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH1: u2,
+                ///  reserved
+                OUT_STATE_CH1: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH1_REG.
+            OUT_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+            OUT_EOF_BFR_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH1_REG.
+            OUT_DSCR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH1_REG.
+            OUT_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH1_REG.
+            OUT_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH1: u32,
+            }),
+            ///  DMA_OUT_PRI_CH1_REG.
+            OUT_PRI_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 1. The larger of the value, the higher of the priority.
+                TX_PRI_CH1: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH1_REG.
+            OUT_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH1: u6,
+                padding: u26,
+            }),
+            reserved496: [44]u8,
+            ///  DMA_IN_CONF0_CH2_REG.
+            IN_CONF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH2: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH2: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH2: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH2_REG.
+            IN_CONF1_CH2: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH2_REG.
+            INFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 2.
+                INFIFO_FULL_CH2: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 2.
+                INFIFO_EMPTY_CH2: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+                INFIFO_CNT_CH2: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH2: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH2: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH2_REG.
+            IN_POP_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH2: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH2_REG.
+            IN_LINK_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH2: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH2: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH2: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH2: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH2: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH2: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH2_REG.
+            IN_STATE_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH2: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH2: u2,
+                ///  reserved
+                IN_STATE_CH2: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+            IN_SUC_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+            IN_ERR_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_CH2_REG.
+            IN_DSCR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH2_REG.
+            IN_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH2_REG.
+            IN_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH2: u32,
+            }),
+            ///  DMA_IN_PRI_CH2_REG.
+            IN_PRI_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 2. The larger of the value, the higher of the priority.
+                RX_PRI_CH2: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH2_REG.
+            IN_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH2: u6,
+                padding: u26,
+            }),
+            reserved592: [44]u8,
+            ///  DMA_OUT_CONF0_CH2_REG.
+            OUT_CONF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH2: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH2: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH2: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH2: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH2_REG.
+            OUT_CONF1_CH2: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH2_REG.
+            OUTFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 2.
+                OUTFIFO_FULL_CH2: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 2.
+                OUTFIFO_EMPTY_CH2: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+                OUTFIFO_CNT_CH2: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH2: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH2_REG.
+            OUT_PUSH_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH2: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH2: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH2_REG.
+            OUT_LINK_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH2: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH2: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH2: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH2: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH2: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH2_REG.
+            OUT_STATE_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH2: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH2: u2,
+                ///  reserved
+                OUT_STATE_CH2: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH2_REG.
+            OUT_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+            OUT_EOF_BFR_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH2_REG.
+            OUT_DSCR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH2_REG.
+            OUT_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH2_REG.
+            OUT_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH2: u32,
+            }),
+            ///  DMA_OUT_PRI_CH2_REG.
+            OUT_PRI_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 2. The larger of the value, the higher of the priority.
+                TX_PRI_CH2: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH2_REG.
+            OUT_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH2: u6,
+                padding: u26,
+            }),
+        };
+
+        ///  Digital Signature
+        pub const DS = extern struct {
+            ///  memory that stores Y
+            Y_MEM: [512]u8,
+            ///  memory that stores M
+            M_MEM: [512]u8,
+            ///  memory that stores Rb
+            RB_MEM: [512]u8,
+            ///  memory that stores BOX
+            BOX_MEM: [48]u8,
+            reserved2048: [464]u8,
+            ///  memory that stores X
+            X_MEM: [512]u8,
+            ///  memory that stores Z
+            Z_MEM: [512]u8,
+            reserved3584: [512]u8,
+            ///  DS start control register
+            SET_START: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to start DS operation.
+                SET_START: u1,
+                padding: u31,
+            }),
+            ///  DS continue control register
+            SET_CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to continue DS operation.
+                SET_CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  DS finish control register
+            SET_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to finish DS process.
+                SET_FINISH: u1,
+                padding: u31,
+            }),
+            ///  DS query busy register
+            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
+                ///  digital signature state. 1'b0: idle, 1'b1: busy
+                QUERY_BUSY: u1,
+                padding: u31,
+            }),
+            ///  DS query key-wrong counter register
+            QUERY_KEY_WRONG: mmio.Mmio(packed struct(u32) {
+                ///  digital signature key wrong counter
+                QUERY_KEY_WRONG: u4,
+                padding: u28,
+            }),
+            ///  DS query check result register
+            QUERY_CHECK: mmio.Mmio(packed struct(u32) {
+                ///  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+                MD_ERROR: u1,
+                ///  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+                PADDING_BAD: u1,
+                padding: u30,
+            }),
+            reserved3616: [8]u8,
+            ///  DS version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  ds version information
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  eFuse Controller
+        pub const EFUSE = extern struct {
+            ///  Register 0 that stores data to be programmed.
+            PGM_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 0th 32-bit data to be programmed.
+                PGM_DATA_0: u32,
+            }),
+            ///  Register 1 that stores data to be programmed.
+            PGM_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 1st 32-bit data to be programmed.
+                PGM_DATA_1: u32,
+            }),
+            ///  Register 2 that stores data to be programmed.
+            PGM_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 2nd 32-bit data to be programmed.
+                PGM_DATA_2: u32,
+            }),
+            ///  Register 3 that stores data to be programmed.
+            PGM_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 3rd 32-bit data to be programmed.
+                PGM_DATA_3: u32,
+            }),
+            ///  Register 4 that stores data to be programmed.
+            PGM_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 4th 32-bit data to be programmed.
+                PGM_DATA_4: u32,
+            }),
+            ///  Register 5 that stores data to be programmed.
+            PGM_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 5th 32-bit data to be programmed.
+                PGM_DATA_5: u32,
+            }),
+            ///  Register 6 that stores data to be programmed.
+            PGM_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 6th 32-bit data to be programmed.
+                PGM_DATA_6: u32,
+            }),
+            ///  Register 7 that stores data to be programmed.
+            PGM_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 7th 32-bit data to be programmed.
+                PGM_DATA_7: u32,
+            }),
+            ///  Register 0 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE0: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 0th 32-bit RS code to be programmed.
+                PGM_RS_DATA_0: u32,
+            }),
+            ///  Register 1 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE1: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 1st 32-bit RS code to be programmed.
+                PGM_RS_DATA_1: u32,
+            }),
+            ///  Register 2 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE2: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 2nd 32-bit RS code to be programmed.
+                PGM_RS_DATA_2: u32,
+            }),
+            ///  BLOCK0 data register 0.
+            RD_WR_DIS: mmio.Mmio(packed struct(u32) {
+                ///  Disable programming of individual eFuses.
+                WR_DIS: u32,
+            }),
+            ///  BLOCK0 data register 1.
+            RD_REPEAT_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to disable reading from BlOCK4-10.
+                RD_DIS: u7,
+                ///  Set this bit to disable boot from RTC RAM.
+                DIS_RTC_RAM_BOOT: u1,
+                ///  Set this bit to disable Icache.
+                DIS_ICACHE: u1,
+                ///  Set this bit to disable function of usb switch to jtag in module of usb device.
+                DIS_USB_JTAG: u1,
+                ///  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
+                DIS_DOWNLOAD_ICACHE: u1,
+                ///  Set this bit to disable usb device.
+                DIS_USB_DEVICE: u1,
+                ///  Set this bit to disable the function that forces chip into download mode.
+                DIS_FORCE_DOWNLOAD: u1,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED6: u1,
+                ///  Set this bit to disable CAN function.
+                DIS_CAN: u1,
+                ///  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+                JTAG_SEL_ENABLE: u1,
+                ///  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
+                SOFT_DIS_JTAG: u3,
+                ///  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+                DIS_PAD_JTAG: u1,
+                ///  Set this bit to disable flash encryption when in download boot modes.
+                DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
+                ///  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
+                USB_DREFH: u2,
+                ///  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
+                USB_DREFL: u2,
+                ///  Set this bit to exchange USB D+ and D- pins.
+                USB_EXCHG_PINS: u1,
+                ///  Set this bit to vdd spi pin function as gpio.
+                VDD_SPI_AS_GPIO: u1,
+                ///  Enable btlc gpio.
+                BTLC_GPIO_ENABLE: u2,
+                ///  Set this bit to enable power glitch function.
+                POWERGLITCH_EN: u1,
+                ///  Sample delay configuration of power glitch.
+                POWER_GLITCH_DSENSE: u2,
+            }),
+            ///  BLOCK0 data register 2.
+            RD_REPEAT_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED2: u16,
+                ///  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
+                WDT_DELAY_SEL: u2,
+                ///  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
+                SPI_BOOT_CRYPT_CNT: u3,
+                ///  Set this bit to enable revoking first secure boot key.
+                SECURE_BOOT_KEY_REVOKE0: u1,
+                ///  Set this bit to enable revoking second secure boot key.
+                SECURE_BOOT_KEY_REVOKE1: u1,
+                ///  Set this bit to enable revoking third secure boot key.
+                SECURE_BOOT_KEY_REVOKE2: u1,
+                ///  Purpose of Key0.
+                KEY_PURPOSE_0: u4,
+                ///  Purpose of Key1.
+                KEY_PURPOSE_1: u4,
+            }),
+            ///  BLOCK0 data register 3.
+            RD_REPEAT_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Purpose of Key2.
+                KEY_PURPOSE_2: u4,
+                ///  Purpose of Key3.
+                KEY_PURPOSE_3: u4,
+                ///  Purpose of Key4.
+                KEY_PURPOSE_4: u4,
+                ///  Purpose of Key5.
+                KEY_PURPOSE_5: u4,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED3: u4,
+                ///  Set this bit to enable secure boot.
+                SECURE_BOOT_EN: u1,
+                ///  Set this bit to enable revoking aggressive secure boot.
+                SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED0: u6,
+                ///  Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
+                FLASH_TPUW: u4,
+            }),
+            ///  BLOCK0 data register 4.
+            RD_REPEAT_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+                DIS_DOWNLOAD_MODE: u1,
+                ///  Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+                DIS_LEGACY_SPI_BOOT: u1,
+                ///  Selectes the default UART print channel. 0: UART0. 1: UART1.
+                UART_PRINT_CHANNEL: u1,
+                ///  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
+                FLASH_ECC_MODE: u1,
+                ///  Set this bit to disable UART download mode through USB.
+                DIS_USB_DOWNLOAD_MODE: u1,
+                ///  Set this bit to enable secure UART download mode.
+                ENABLE_SECURITY_DOWNLOAD: u1,
+                ///  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+                UART_PRINT_CONTROL: u2,
+                ///  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+                PIN_POWER_SELECTION: u1,
+                ///  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+                FLASH_TYPE: u1,
+                ///  Set Flash page size.
+                FLASH_PAGE_SIZE: u2,
+                ///  Set 1 to enable ECC for flash boot.
+                FLASH_ECC_EN: u1,
+                ///  Set this bit to force ROM code to send a resume command during SPI boot.
+                FORCE_SEND_RESUME: u1,
+                ///  Secure version (used by ESP-IDF anti-rollback feature).
+                SECURE_VERSION: u16,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED1: u2,
+            }),
+            ///  BLOCK0 data register 5.
+            RD_REPEAT_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED4: u24,
+                padding: u8,
+            }),
+            ///  BLOCK1 data register 0.
+            RD_MAC_SPI_SYS_0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the low 32 bits of MAC address.
+                MAC_0: u32,
+            }),
+            ///  BLOCK1 data register 1.
+            RD_MAC_SPI_SYS_1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the high 16 bits of MAC address.
+                MAC_1: u16,
+                ///  Stores the zeroth part of SPI_PAD_CONF.
+                SPI_PAD_CONF_0: u16,
+            }),
+            ///  BLOCK1 data register 2.
+            RD_MAC_SPI_SYS_2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first part of SPI_PAD_CONF.
+                SPI_PAD_CONF_1: u32,
+            }),
+            ///  BLOCK1 data register 3.
+            RD_MAC_SPI_SYS_3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second part of SPI_PAD_CONF.
+                SPI_PAD_CONF_2: u18,
+                ///  Stores the fist 14 bits of the zeroth part of system data.
+                SYS_DATA_PART0_0: u14,
+            }),
+            ///  BLOCK1 data register 4.
+            RD_MAC_SPI_SYS_4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fist 32 bits of the zeroth part of system data.
+                SYS_DATA_PART0_1: u32,
+            }),
+            ///  BLOCK1 data register 5.
+            RD_MAC_SPI_SYS_5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of the zeroth part of system data.
+                SYS_DATA_PART0_2: u32,
+            }),
+            ///  Register 0 of BLOCK2 (system).
+            RD_SYS_PART1_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of the first part of system data.
+                SYS_DATA_PART1_0: u32,
+            }),
+            ///  Register 1 of BLOCK2 (system).
+            RD_SYS_PART1_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of the first part of system data.
+                SYS_DATA_PART1_1: u32,
+            }),
+            ///  Register 2 of BLOCK2 (system).
+            RD_SYS_PART1_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of the first part of system data.
+                SYS_DATA_PART1_2: u32,
+            }),
+            ///  Register 3 of BLOCK2 (system).
+            RD_SYS_PART1_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of the first part of system data.
+                SYS_DATA_PART1_3: u32,
+            }),
+            ///  Register 4 of BLOCK2 (system).
+            RD_SYS_PART1_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of the first part of system data.
+                SYS_DATA_PART1_4: u32,
+            }),
+            ///  Register 5 of BLOCK2 (system).
+            RD_SYS_PART1_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of the first part of system data.
+                SYS_DATA_PART1_5: u32,
+            }),
+            ///  Register 6 of BLOCK2 (system).
+            RD_SYS_PART1_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of the first part of system data.
+                SYS_DATA_PART1_6: u32,
+            }),
+            ///  Register 7 of BLOCK2 (system).
+            RD_SYS_PART1_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of the first part of system data.
+                SYS_DATA_PART1_7: u32,
+            }),
+            ///  Register 0 of BLOCK3 (user).
+            RD_USR_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of BLOCK3 (user).
+                USR_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK3 (user).
+            RD_USR_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of BLOCK3 (user).
+                USR_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK3 (user).
+            RD_USR_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of BLOCK3 (user).
+                USR_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK3 (user).
+            RD_USR_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of BLOCK3 (user).
+                USR_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK3 (user).
+            RD_USR_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of BLOCK3 (user).
+                USR_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK3 (user).
+            RD_USR_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of BLOCK3 (user).
+                USR_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK3 (user).
+            RD_USR_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of BLOCK3 (user).
+                USR_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK3 (user).
+            RD_USR_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of BLOCK3 (user).
+                USR_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK4 (KEY0).
+            RD_KEY0_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY0.
+                KEY0_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK4 (KEY0).
+            RD_KEY0_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY0.
+                KEY0_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK4 (KEY0).
+            RD_KEY0_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY0.
+                KEY0_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK4 (KEY0).
+            RD_KEY0_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY0.
+                KEY0_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK4 (KEY0).
+            RD_KEY0_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY0.
+                KEY0_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK4 (KEY0).
+            RD_KEY0_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY0.
+                KEY0_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK4 (KEY0).
+            RD_KEY0_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY0.
+                KEY0_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK4 (KEY0).
+            RD_KEY0_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY0.
+                KEY0_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK5 (KEY1).
+            RD_KEY1_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY1.
+                KEY1_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK5 (KEY1).
+            RD_KEY1_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY1.
+                KEY1_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK5 (KEY1).
+            RD_KEY1_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY1.
+                KEY1_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK5 (KEY1).
+            RD_KEY1_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY1.
+                KEY1_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK5 (KEY1).
+            RD_KEY1_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY1.
+                KEY1_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK5 (KEY1).
+            RD_KEY1_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY1.
+                KEY1_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK5 (KEY1).
+            RD_KEY1_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY1.
+                KEY1_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK5 (KEY1).
+            RD_KEY1_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY1.
+                KEY1_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK6 (KEY2).
+            RD_KEY2_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY2.
+                KEY2_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK6 (KEY2).
+            RD_KEY2_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY2.
+                KEY2_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK6 (KEY2).
+            RD_KEY2_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY2.
+                KEY2_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK6 (KEY2).
+            RD_KEY2_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY2.
+                KEY2_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK6 (KEY2).
+            RD_KEY2_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY2.
+                KEY2_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK6 (KEY2).
+            RD_KEY2_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY2.
+                KEY2_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK6 (KEY2).
+            RD_KEY2_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY2.
+                KEY2_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK6 (KEY2).
+            RD_KEY2_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY2.
+                KEY2_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK7 (KEY3).
+            RD_KEY3_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY3.
+                KEY3_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK7 (KEY3).
+            RD_KEY3_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY3.
+                KEY3_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK7 (KEY3).
+            RD_KEY3_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY3.
+                KEY3_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK7 (KEY3).
+            RD_KEY3_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY3.
+                KEY3_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK7 (KEY3).
+            RD_KEY3_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY3.
+                KEY3_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK7 (KEY3).
+            RD_KEY3_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY3.
+                KEY3_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK7 (KEY3).
+            RD_KEY3_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY3.
+                KEY3_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK7 (KEY3).
+            RD_KEY3_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY3.
+                KEY3_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK8 (KEY4).
+            RD_KEY4_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY4.
+                KEY4_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK8 (KEY4).
+            RD_KEY4_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY4.
+                KEY4_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK8 (KEY4).
+            RD_KEY4_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY4.
+                KEY4_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK8 (KEY4).
+            RD_KEY4_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY4.
+                KEY4_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK8 (KEY4).
+            RD_KEY4_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY4.
+                KEY4_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK8 (KEY4).
+            RD_KEY4_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY4.
+                KEY4_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK8 (KEY4).
+            RD_KEY4_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY4.
+                KEY4_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK8 (KEY4).
+            RD_KEY4_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY4.
+                KEY4_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK9 (KEY5).
+            RD_KEY5_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY5.
+                KEY5_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK9 (KEY5).
+            RD_KEY5_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY5.
+                KEY5_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK9 (KEY5).
+            RD_KEY5_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY5.
+                KEY5_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK9 (KEY5).
+            RD_KEY5_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY5.
+                KEY5_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK9 (KEY5).
+            RD_KEY5_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY5.
+                KEY5_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK9 (KEY5).
+            RD_KEY5_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY5.
+                KEY5_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK9 (KEY5).
+            RD_KEY5_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY5.
+                KEY5_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK9 (KEY5).
+            RD_KEY5_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY5.
+                KEY5_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK10 (system).
+            RD_SYS_PART2_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 0th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_0: u32,
+            }),
+            ///  Register 1 of BLOCK9 (KEY5).
+            RD_SYS_PART2_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 1st 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_1: u32,
+            }),
+            ///  Register 2 of BLOCK10 (system).
+            RD_SYS_PART2_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 2nd 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_2: u32,
+            }),
+            ///  Register 3 of BLOCK10 (system).
+            RD_SYS_PART2_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 3rd 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_3: u32,
+            }),
+            ///  Register 4 of BLOCK10 (system).
+            RD_SYS_PART2_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 4th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_4: u32,
+            }),
+            ///  Register 5 of BLOCK10 (system).
+            RD_SYS_PART2_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 5th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_5: u32,
+            }),
+            ///  Register 6 of BLOCK10 (system).
+            RD_SYS_PART2_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 6th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_6: u32,
+            }),
+            ///  Register 7 of BLOCK10 (system).
+            RD_SYS_PART2_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 7th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_7: u32,
+            }),
+            ///  Programming error record register 0 of BLOCK0.
+            RD_REPEAT_ERR0: mmio.Mmio(packed struct(u32) {
+                ///  If any bit in RD_DIS is 1, then it indicates a programming error.
+                RD_DIS_ERR: u7,
+                ///  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+                DIS_RTC_RAM_BOOT_ERR: u1,
+                ///  If DIS_ICACHE is 1, then it indicates a programming error.
+                DIS_ICACHE_ERR: u1,
+                ///  If DIS_USB_JTAG is 1, then it indicates a programming error.
+                DIS_USB_JTAG_ERR: u1,
+                ///  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_ICACHE_ERR: u1,
+                ///  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+                DIS_USB_DEVICE_ERR: u1,
+                ///  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+                DIS_FORCE_DOWNLOAD_ERR: u1,
+                ///  Reserved.
+                RPT4_RESERVED6_ERR: u1,
+                ///  If DIS_CAN is 1, then it indicates a programming error.
+                DIS_CAN_ERR: u1,
+                ///  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+                JTAG_SEL_ENABLE_ERR: u1,
+                ///  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+                SOFT_DIS_JTAG_ERR: u3,
+                ///  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+                DIS_PAD_JTAG_ERR: u1,
+                ///  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
+                ///  If any bit in USB_DREFH is 1, then it indicates a programming error.
+                USB_DREFH_ERR: u2,
+                ///  If any bit in USB_DREFL is 1, then it indicates a programming error.
+                USB_DREFL_ERR: u2,
+                ///  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+                USB_EXCHG_PINS_ERR: u1,
+                ///  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+                VDD_SPI_AS_GPIO_ERR: u1,
+                ///  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+                BTLC_GPIO_ENABLE_ERR: u2,
+                ///  If POWERGLITCH_EN is 1, then it indicates a programming error.
+                POWERGLITCH_EN_ERR: u1,
+                ///  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+                POWER_GLITCH_DSENSE_ERR: u2,
+            }),
+            ///  Programming error record register 1 of BLOCK0.
+            RD_REPEAT_ERR1: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RPT4_RESERVED2_ERR: u16,
+                ///  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+                WDT_DELAY_SEL_ERR: u2,
+                ///  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+                SPI_BOOT_CRYPT_CNT_ERR: u3,
+                ///  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE0_ERR: u1,
+                ///  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE1_ERR: u1,
+                ///  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE2_ERR: u1,
+                ///  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+                KEY_PURPOSE_0_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+                KEY_PURPOSE_1_ERR: u4,
+            }),
+            ///  Programming error record register 2 of BLOCK0.
+            RD_REPEAT_ERR2: mmio.Mmio(packed struct(u32) {
+                ///  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+                KEY_PURPOSE_2_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+                KEY_PURPOSE_3_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+                KEY_PURPOSE_4_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+                KEY_PURPOSE_5_ERR: u4,
+                ///  Reserved.
+                RPT4_RESERVED3_ERR: u4,
+                ///  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+                SECURE_BOOT_EN_ERR: u1,
+                ///  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+                SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
+                ///  Reserved.
+                RPT4_RESERVED0_ERR: u6,
+                ///  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+                FLASH_TPUW_ERR: u4,
+            }),
+            ///  Programming error record register 3 of BLOCK0.
+            RD_REPEAT_ERR3: mmio.Mmio(packed struct(u32) {
+                ///  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_MODE_ERR: u1,
+                ///  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+                DIS_LEGACY_SPI_BOOT_ERR: u1,
+                ///  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+                UART_PRINT_CHANNEL_ERR: u1,
+                ///  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+                FLASH_ECC_MODE_ERR: u1,
+                ///  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+                DIS_USB_DOWNLOAD_MODE_ERR: u1,
+                ///  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+                ENABLE_SECURITY_DOWNLOAD_ERR: u1,
+                ///  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+                UART_PRINT_CONTROL_ERR: u2,
+                ///  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+                PIN_POWER_SELECTION_ERR: u1,
+                ///  If FLASH_TYPE is 1, then it indicates a programming error.
+                FLASH_TYPE_ERR: u1,
+                ///  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+                FLASH_PAGE_SIZE_ERR: u2,
+                ///  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+                FLASH_ECC_EN_ERR: u1,
+                ///  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+                FORCE_SEND_RESUME_ERR: u1,
+                ///  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+                SECURE_VERSION_ERR: u16,
+                ///  Reserved.
+                RPT4_RESERVED1_ERR: u2,
+            }),
+            reserved400: [4]u8,
+            ///  Programming error record register 4 of BLOCK0.
+            RD_REPEAT_ERR4: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RPT4_RESERVED4_ERR: u24,
+                padding: u8,
+            }),
+            reserved448: [44]u8,
+            ///  Programming error record register 0 of BLOCK1-10.
+            RD_RS_ERR0: mmio.Mmio(packed struct(u32) {
+                ///  The value of this signal means the number of error bytes.
+                MAC_SPI_8M_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                MAC_SPI_8M_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                SYS_PART1_NUM: u3,
+                ///  0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                SYS_PART1_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                USR_DATA_ERR_NUM: u3,
+                ///  0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                USR_DATA_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY0_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
+                KEY0_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY1_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
+                KEY1_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY2_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
+                KEY2_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY3_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
+                KEY3_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY4_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
+                KEY4_FAIL: u1,
+            }),
+            ///  Programming error record register 1 of BLOCK1-10.
+            RD_RS_ERR1: mmio.Mmio(packed struct(u32) {
+                ///  The value of this signal means the number of error bytes.
+                KEY5_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                KEY5_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                SYS_PART2_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                SYS_PART2_FAIL: u1,
+                padding: u24,
+            }),
+            ///  eFuse clcok configuration register.
+            CLK: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to force eFuse SRAM into power-saving mode.
+                EFUSE_MEM_FORCE_PD: u1,
+                ///  Set this bit and force to activate clock signal of eFuse SRAM.
+                MEM_CLK_FORCE_ON: u1,
+                ///  Set this bit to force eFuse SRAM into working mode.
+                EFUSE_MEM_FORCE_PU: u1,
+                reserved16: u13,
+                ///  Set this bit and force to enable clock signal of eFuse memory.
+                EN: u1,
+                padding: u15,
+            }),
+            ///  eFuse operation mode configuraiton register;
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+                OP_CODE: u16,
+                padding: u16,
+            }),
+            ///  eFuse status register.
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the state of the eFuse state machine.
+                STATE: u4,
+                ///  The value of OTP_LOAD_SW.
+                OTP_LOAD_SW: u1,
+                ///  The value of OTP_VDDQ_C_SYNC2.
+                OTP_VDDQ_C_SYNC2: u1,
+                ///  The value of OTP_STROBE_SW.
+                OTP_STROBE_SW: u1,
+                ///  The value of OTP_CSB_SW.
+                OTP_CSB_SW: u1,
+                ///  The value of OTP_PGENB_SW.
+                OTP_PGENB_SW: u1,
+                ///  The value of OTP_VDDQ_IS_SW.
+                OTP_VDDQ_IS_SW: u1,
+                ///  Indicates the number of error bits during programming BLOCK0.
+                REPEAT_ERR_CNT: u8,
+                padding: u14,
+            }),
+            ///  eFuse command register.
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to send read command.
+                READ_CMD: u1,
+                ///  Set this bit to send programming command.
+                PGM_CMD: u1,
+                ///  The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
+                BLK_NUM: u4,
+                padding: u26,
+            }),
+            ///  eFuse raw interrupt register.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw bit signal for read_done interrupt.
+                READ_DONE_INT_RAW: u1,
+                ///  The raw bit signal for pgm_done interrupt.
+                PGM_DONE_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt status register.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status signal for read_done interrupt.
+                READ_DONE_INT_ST: u1,
+                ///  The status signal for pgm_done interrupt.
+                PGM_DONE_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt enable register.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable signal for read_done interrupt.
+                READ_DONE_INT_ENA: u1,
+                ///  The enable signal for pgm_done interrupt.
+                PGM_DONE_INT_ENA: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt clear register.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear signal for read_done interrupt.
+                READ_DONE_INT_CLR: u1,
+                ///  The clear signal for pgm_done interrupt.
+                PGM_DONE_INT_CLR: u1,
+                padding: u30,
+            }),
+            ///  Controls the eFuse programming voltage.
+            DAC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Controls the division factor of the rising clock of the programming voltage.
+                DAC_CLK_DIV: u8,
+                ///  Don't care.
+                DAC_CLK_PAD_SEL: u1,
+                ///  Controls the rising period of the programming voltage.
+                DAC_NUM: u8,
+                ///  Reduces the power supply of the programming voltage.
+                OE_CLR: u1,
+                padding: u14,
+            }),
+            ///  Configures read timing parameters.
+            RD_TIM_CONF: mmio.Mmio(packed struct(u32) {
+                reserved24: u24,
+                ///  Configures the initial read time of eFuse.
+                READ_INIT_NUM: u8,
+            }),
+            ///  Configurarion register 1 of eFuse programming timing parameters.
+            WR_TIM_CONF1: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Configures the power up time for VDDQ.
+                PWR_ON_NUM: u16,
+                padding: u8,
+            }),
+            ///  Configurarion register 2 of eFuse programming timing parameters.
+            WR_TIM_CONF2: mmio.Mmio(packed struct(u32) {
+                ///  Configures the power outage time for VDDQ.
+                PWR_OFF_NUM: u16,
+                padding: u16,
+            }),
+            reserved508: [4]u8,
+            ///  eFuse version register.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Stores eFuse version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  External Memory
+        pub const EXTMEM = extern struct {
+            ///  This description will be updated in the near future.
+            ICACHE_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to activate the data cache. 0: disable, 1: enable
+                ICACHE_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable core0 ibus, 0: enable, 1: disable
+                ICACHE_SHUT_IBUS: u1,
+                ///  The bit is used to disable core1 ibus, 0: enable, 1: disable
+                ICACHE_SHUT_DBUS: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_TAG_POWER_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.
+                ICACHE_TAG_MEM_FORCE_ON: u1,
+                ///  The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down
+                ICACHE_TAG_MEM_FORCE_PD: u1,
+                ///  The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
+                ICACHE_TAG_MEM_FORCE_PU: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable the first section of prelock function.
+                ICACHE_PRELOCK_SCT0_EN: u1,
+                ///  The bit is used to enable the second section of prelock function.
+                ICACHE_PRELOCK_SCT1_EN: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
+                ICACHE_PRELOCK_SCT0_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
+                ICACHE_PRELOCK_SCT1_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+                ICACHE_PRELOCK_SCT1_SIZE: u16,
+                ///  The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+                ICACHE_PRELOCK_SCT0_SIZE: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
+                ICACHE_LOCK_ENA: u1,
+                ///  The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
+                ICACHE_UNLOCK_ENA: u1,
+                ///  The bit is used to indicate unlock/lock operation is finished.
+                ICACHE_LOCK_DONE: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
+                ICACHE_LOCK_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
+                ICACHE_LOCK_SIZE: u16,
+                padding: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
+                ICACHE_INVALIDATE_ENA: u1,
+                ///  The bit is used to indicate invalidate operation is finished.
+                ICACHE_SYNC_DONE: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
+                ICACHE_SYNC_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
+                ICACHE_SYNC_SIZE: u23,
+                padding: u9,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
+                ICACHE_PRELOAD_ENA: u1,
+                ///  The bit is used to indicate preload operation is finished.
+                ICACHE_PRELOAD_DONE: u1,
+                ///  The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
+                ICACHE_PRELOAD_ORDER: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
+                ICACHE_PRELOAD_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
+                ICACHE_PRELOAD_SIZE: u16,
+                padding: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to enable the first section for autoload operation.
+                ICACHE_AUTOLOAD_SCT0_ENA: u1,
+                ///  The bits are used to enable the second section for autoload operation.
+                ICACHE_AUTOLOAD_SCT1_ENA: u1,
+                ///  The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
+                ICACHE_AUTOLOAD_ENA: u1,
+                ///  The bit is used to indicate autoload operation is finished.
+                ICACHE_AUTOLOAD_DONE: u1,
+                ///  The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
+                ICACHE_AUTOLOAD_ORDER: u1,
+                ///  The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
+                ICACHE_AUTOLOAD_RQST: u2,
+                padding: u25,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+                ICACHE_AUTOLOAD_SCT0_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT0_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+                ICACHE_AUTOLOAD_SCT0_SIZE: u27,
+                padding: u5,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+                ICACHE_AUTOLOAD_SCT1_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT1_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+                ICACHE_AUTOLOAD_SCT1_SIZE: u27,
+                padding: u5,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+                IBUS_TO_FLASH_START_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+                IBUS_TO_FLASH_END_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+                DBUS_TO_FLASH_START_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+                DBUS_TO_FLASH_END_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ACS_CNT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear ibus counter.
+                IBUS_ACS_CNT_CLR: u1,
+                ///  The bit is used to clear dbus counter.
+                DBUS_ACS_CNT_CLR: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_ACS_MISS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of the cache miss caused by ibus access flash.
+                IBUS_ACS_MISS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of ibus access flash through icache.
+                IBUS_ACS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_ACS_FLASH_MISS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of the cache miss caused by dbus access flash.
+                DBUS_ACS_FLASH_MISS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of dbus access flash through icache.
+                DBUS_ACS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
+                reserved5: u3,
+                ///  The bit is used to enable interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_INT_ENA: u1,
+                reserved7: u1,
+                ///  The bit is used to enable interrupt by ibus counter overflow.
+                IBUS_CNT_OVF_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by dbus counter overflow.
+                DBUS_CNT_OVF_INT_ENA: u1,
+                padding: u23,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
+                reserved5: u3,
+                ///  The bit is used to clear interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_INT_CLR: u1,
+                reserved7: u1,
+                ///  The bit is used to clear interrupt by ibus counter overflow.
+                IBUS_CNT_OVF_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by dbus counter overflow.
+                DBUS_CNT_OVF_INT_CLR: u1,
+                padding: u23,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_ST: u1,
+                ///  The bit is used to indicate interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_ST: u1,
+                reserved5: u3,
+                ///  The bit is used to indicate interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_ST: u1,
+                reserved7: u1,
+                ///  The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
+                IBUS_ACS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
+                IBUS_ACS_MISS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
+                DBUS_ACS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus access flash miss counter overflow.
+                DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
+                padding: u21,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by authentication fail.
+                CORE0_IBUS_REJECT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by authentication fail.
+                CORE0_DBUS_REJECT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_IC_INT_ENA: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by authentication fail.
+                CORE0_IBUS_REJECT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by authentication fail.
+                CORE0_DBUS_REJECT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_IC_INT_CLR: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by authentication fail.
+                CORE0_IBUS_REJECT_ST: u1,
+                ///  The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by authentication fail.
+                CORE0_DBUS_REJECT_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_ICACHE_ST: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_DBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
+                CORE0_DBUS_ATTR: u3,
+                ///  The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
+                CORE0_DBUS_WORLD: u1,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_DBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
+                CORE0_DBUS_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_IBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+                CORE0_IBUS_ATTR: u3,
+                ///  The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
+                CORE0_IBUS_WORLD: u1,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_IBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address of CPU access ibus when authentication fail.
+                CORE0_IBUS_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_FAULT_CONTENT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the content of mmu entry which cause mmu fault..
+                CACHE_MMU_FAULT_CONTENT: u10,
+                ///  The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
+                CACHE_MMU_FAULT_CODE: u4,
+                padding: u18,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_FAULT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address which cause mmu fault..
+                CACHE_MMU_FAULT_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_WRAP_AROUND_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable wrap around mode when read data from flash.
+                CACHE_FLASH_WRAP_AROUND: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_POWER_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
+                CACHE_MMU_MEM_FORCE_ON: u1,
+                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+                CACHE_MMU_MEM_FORCE_PD: u1,
+                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+                CACHE_MMU_MEM_FORCE_PU: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_STATE: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
+                ICACHE_STATE: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RECORD_DISABLE_DB_ENCRYPT: u1,
+                ///  Reserved.
+                RECORD_DISABLE_G0CB_DECRYPT: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_MANUAL_CRYPT: u1,
+                ///  The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_AUTO_CRYPT: u1,
+                ///  The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_CRYPT: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_PRELOAD_INT_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_ST: u1,
+                ///  The bit is used to enable the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_ENA: u1,
+                ///  The bit is used to clear the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_SYNC_INT_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate the interrupt by icache sync done.
+                ICACHE_SYNC_INT_ST: u1,
+                ///  The bit is used to enable the interrupt by icache sync done.
+                ICACHE_SYNC_INT_ENA: u1,
+                ///  The bit is used to clear the interrupt by icache sync done.
+                ICACHE_SYNC_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_OWNER: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
+                CACHE_MMU_OWNER: u4,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_CONF_MISC: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable checking mmu entry fault by preload operation.
+                CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
+                ///  The bit is used to disable checking mmu entry fault by sync operation.
+                CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
+                ///  The bit is used to enable cache trace function.
+                CACHE_TRACE_ENA: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_FREEZE: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable icache freeze mode
+                ENA: u1,
+                ///  The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
+                MODE: u1,
+                ///  The bit is used to indicate icache freeze success
+                DONE: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_ATOMIC_OPERATE_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
+                ICACHE_ATOMIC_OPERATE_ENA: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_REQUEST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable request recording which could cause performance issue
+                BYPASS: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                IBUS_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                IBUS_PMS_BOUNDARY0: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary1
+                IBUS_PMS_BOUNDARY1: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary2
+                IBUS_PMS_BOUNDARY2: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+                IBUS_PMS_SCT1_ATTR: u4,
+                ///  The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+                IBUS_PMS_SCT2_ATTR: u4,
+                padding: u24,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                DBUS_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary0
+                DBUS_PMS_BOUNDARY0: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary1
+                DBUS_PMS_BOUNDARY1: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary2
+                DBUS_PMS_BOUNDARY2: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
+                DBUS_PMS_SCT1_ATTR: u2,
+                ///  The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
+                DBUS_PMS_SCT2_ATTR: u2,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  clock gate enable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1020: [760]u8,
+            ///  This description will be updated in the near future.
+            REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version information
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  General Purpose Input/Output
+        pub const GPIO = extern struct {
+            ///  GPIO bit select register
+            BT_SELECT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO bit select register
+                BT_SEL: u32,
+            }),
+            ///  GPIO output register
+            OUT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output register for GPIO0-25
+                DATA_ORIG: u26,
+                padding: u6,
+            }),
+            ///  GPIO output set register
+            OUT_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output set register for GPIO0-25
+                OUT_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO output clear register
+            OUT_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output clear register for GPIO0-25
+                OUT_W1TC: u26,
+                padding: u6,
+            }),
+            reserved28: [12]u8,
+            ///  GPIO sdio select register
+            SDIO_SELECT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO sdio select register
+                SDIO_SEL: u8,
+                padding: u24,
+            }),
+            ///  GPIO output enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable register for GPIO0-25
+                DATA: u26,
+                padding: u6,
+            }),
+            ///  GPIO output enable set register
+            ENABLE_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable set register for GPIO0-25
+                ENABLE_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO output enable clear register
+            ENABLE_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable clear register for GPIO0-25
+                ENABLE_W1TC: u26,
+                padding: u6,
+            }),
+            reserved56: [12]u8,
+            ///  pad strapping register
+            STRAP: mmio.Mmio(packed struct(u32) {
+                ///  pad strapping register
+                STRAPPING: u16,
+                padding: u16,
+            }),
+            ///  GPIO input register
+            IN: mmio.Mmio(packed struct(u32) {
+                ///  GPIO input register for GPIO0-25
+                DATA_NEXT: u26,
+                padding: u6,
+            }),
+            reserved68: [4]u8,
+            ///  GPIO interrupt status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status register for GPIO0-25
+                INTERRUPT: u26,
+                padding: u6,
+            }),
+            ///  GPIO interrupt status set register
+            STATUS_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status set register for GPIO0-25
+                STATUS_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO interrupt status clear register
+            STATUS_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status clear register for GPIO0-25
+                STATUS_W1TC: u26,
+                padding: u6,
+            }),
+            reserved92: [12]u8,
+            ///  GPIO PRO_CPU interrupt status register
+            PCPU_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO PRO_CPU interrupt status register for GPIO0-25
+                PROCPU_INT: u26,
+                padding: u6,
+            }),
+            ///  GPIO PRO_CPU(not shielded) interrupt status register
+            PCPU_NMI_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+                PROCPU_NMI_INT: u26,
+                padding: u6,
+            }),
+            ///  GPIO CPUSDIO interrupt status register
+            CPUSDIO_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO CPUSDIO interrupt status register for GPIO0-25
+                SDIO_INT: u26,
+                padding: u6,
+            }),
+            reserved116: [12]u8,
+            ///  GPIO pin configuration register
+            PIN: [26]mmio.Mmio(packed struct(u32) {
+                ///  set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+                PIN_SYNC2_BYPASS: u2,
+                ///  set this bit to select pad driver. 1:open-drain. :normal.
+                PIN_PAD_DRIVER: u1,
+                ///  set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+                PIN_SYNC1_BYPASS: u2,
+                reserved7: u2,
+                ///  set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
+                PIN_INT_TYPE: u3,
+                ///  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+                PIN_WAKEUP_ENABLE: u1,
+                ///  reserved
+                PIN_CONFIG: u2,
+                ///  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
+                PIN_INT_ENA: u5,
+                padding: u14,
+            }),
+            reserved332: [112]u8,
+            ///  GPIO interrupt source register
+            STATUS_NEXT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt source register for GPIO0-25
+                STATUS_INTERRUPT_NEXT: u26,
+                padding: u6,
+            }),
+            reserved340: [4]u8,
+            ///  GPIO input function configuration register
+            FUNC_IN_SEL_CFG: [128]mmio.Mmio(packed struct(u32) {
+                ///  set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
+                IN_SEL: u5,
+                ///  set this bit to invert input signal. 1:invert. :not invert.
+                IN_INV_SEL: u1,
+                ///  set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+                SEL: u1,
+                padding: u25,
+            }),
+            reserved1364: [512]u8,
+            ///  GPIO output function select register
+            FUNC_OUT_SEL_CFG: [26]mmio.Mmio(packed struct(u32) {
+                ///  The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
+                OUT_SEL: u8,
+                ///  set this bit to invert output signal.1:invert.:not invert.
+                INV_SEL: u1,
+                ///  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
+                OEN_SEL: u1,
+                ///  set this bit to invert output enable signal.1:invert.:not invert.
+                OEN_INV_SEL: u1,
+                padding: u21,
+            }),
+            reserved1580: [112]u8,
+            ///  GPIO clock gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to enable GPIO clock gate
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1788: [204]u8,
+            ///  GPIO version register
+            REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version register
+                REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Sigma-Delta Modulation
+        pub const GPIOSD = extern struct {
+            ///  Duty Cycle Configure Register of SDM%s
+            SIGMADELTA: [4]mmio.Mmio(packed struct(u32) {
+                ///  This field is used to configure the duty cycle of sigma delta modulation output.
+                SD0_IN: u8,
+                ///  This field is used to set a divider value to divide APB clock.
+                SD0_PRESCALE: u8,
+                padding: u16,
+            }),
+            reserved32: [16]u8,
+            ///  Clock Gating Configure Register
+            SIGMADELTA_CG: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  Clock enable bit of configuration registers for sigma delta modulation.
+                CLK_EN: u1,
+            }),
+            ///  MISC Register
+            SIGMADELTA_MISC: mmio.Mmio(packed struct(u32) {
+                reserved30: u30,
+                ///  Clock enable bit of sigma delta modulation.
+                FUNCTION_CLK_EN: u1,
+                ///  Reserved.
+                SPI_SWAP: u1,
+            }),
+            ///  Version Control Register
+            SIGMADELTA_VERSION: mmio.Mmio(packed struct(u32) {
+                ///  Version control register.
+                GPIO_SD_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  HMAC (Hash-based Message Authentication Code) Accelerator
+        pub const HMAC = extern struct {
+            reserved64: [64]u8,
+            ///  Process control register 0.
+            SET_START: mmio.Mmio(packed struct(u32) {
+                ///  Start hmac operation.
+                SET_START: u1,
+                padding: u31,
+            }),
+            ///  Configure purpose.
+            SET_PARA_PURPOSE: mmio.Mmio(packed struct(u32) {
+                ///  Set hmac parameter purpose.
+                PURPOSE_SET: u4,
+                padding: u28,
+            }),
+            ///  Configure key.
+            SET_PARA_KEY: mmio.Mmio(packed struct(u32) {
+                ///  Set hmac parameter key.
+                KEY_SET: u3,
+                padding: u29,
+            }),
+            ///  Finish initial configuration.
+            SET_PARA_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  Finish hmac configuration.
+                SET_PARA_END: u1,
+                padding: u31,
+            }),
+            ///  Process control register 1.
+            SET_MESSAGE_ONE: mmio.Mmio(packed struct(u32) {
+                ///  Call SHA to calculate one message block.
+                SET_TEXT_ONE: u1,
+                padding: u31,
+            }),
+            ///  Process control register 2.
+            SET_MESSAGE_ING: mmio.Mmio(packed struct(u32) {
+                ///  Continue typical hmac.
+                SET_TEXT_ING: u1,
+                padding: u31,
+            }),
+            ///  Process control register 3.
+            SET_MESSAGE_END: mmio.Mmio(packed struct(u32) {
+                ///  Start hardware padding.
+                SET_TEXT_END: u1,
+                padding: u31,
+            }),
+            ///  Process control register 4.
+            SET_RESULT_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  After read result from upstream, then let hmac back to idle.
+                SET_RESULT_END: u1,
+                padding: u31,
+            }),
+            ///  Invalidate register 0.
+            SET_INVALIDATE_JTAG: mmio.Mmio(packed struct(u32) {
+                ///  Clear result from hmac downstream JTAG.
+                SET_INVALIDATE_JTAG: u1,
+                padding: u31,
+            }),
+            ///  Invalidate register 1.
+            SET_INVALIDATE_DS: mmio.Mmio(packed struct(u32) {
+                ///  Clear result from hmac downstream DS.
+                SET_INVALIDATE_DS: u1,
+                padding: u31,
+            }),
+            ///  Error register.
+            QUERY_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  Hmac configuration state. 0: key are agree with purpose. 1: error
+                QUREY_CHECK: u1,
+                padding: u31,
+            }),
+            ///  Busy register.
+            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
+                ///  Hmac state. 1'b0: idle. 1'b1: busy
+                BUSY_STATE: u1,
+                padding: u31,
+            }),
+            reserved128: [16]u8,
+            ///  Message block memory.
+            WR_MESSAGE_MEM: [64]u8,
+            ///  Result from upstream.
+            RD_RESULT_MEM: [32]u8,
+            reserved240: [16]u8,
+            ///  Process control register 5.
+            SET_MESSAGE_PAD: mmio.Mmio(packed struct(u32) {
+                ///  Start software padding.
+                SET_TEXT_PAD: u1,
+                padding: u31,
+            }),
+            ///  Process control register 6.
+            ONE_BLOCK: mmio.Mmio(packed struct(u32) {
+                ///  Don't have to do padding.
+                SET_ONE_BLOCK: u1,
+                padding: u31,
+            }),
+            ///  Jtag register 0.
+            SOFT_JTAG_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Turn on JTAG verification.
+                SOFT_JTAG_CTRL: u1,
+                padding: u31,
+            }),
+            ///  Jtag register 1.
+            WR_JTAG: mmio.Mmio(packed struct(u32) {
+                ///  32-bit of key to be compared.
+                WR_JTAG: u32,
+            }),
+        };
+
+        ///  I2C (Inter-Integrated Circuit) Controller
+        pub const I2C0 = extern struct {
+            ///  I2C_SCL_LOW_PERIOD_REG
+            SCL_LOW_PERIOD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_low_period
+                SCL_LOW_PERIOD: u9,
+                padding: u23,
+            }),
+            ///  I2C_CTR_REG
+            CTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_force_out
+                SDA_FORCE_OUT: u1,
+                ///  reg_scl_force_out
+                SCL_FORCE_OUT: u1,
+                ///  reg_sample_scl_level
+                SAMPLE_SCL_LEVEL: u1,
+                ///  reg_rx_full_ack_level
+                RX_FULL_ACK_LEVEL: u1,
+                ///  reg_ms_mode
+                MS_MODE: u1,
+                ///  reg_trans_start
+                TRANS_START: u1,
+                ///  reg_tx_lsb_first
+                TX_LSB_FIRST: u1,
+                ///  reg_rx_lsb_first
+                RX_LSB_FIRST: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                ///  reg_arbitration_en
+                ARBITRATION_EN: u1,
+                ///  reg_fsm_rst
+                FSM_RST: u1,
+                ///  reg_conf_upgate
+                CONF_UPGATE: u1,
+                ///  reg_slv_tx_auto_start_en
+                SLV_TX_AUTO_START_EN: u1,
+                ///  reg_addr_10bit_rw_check_en
+                ADDR_10BIT_RW_CHECK_EN: u1,
+                ///  reg_addr_broadcasting_en
+                ADDR_BROADCASTING_EN: u1,
+                padding: u17,
+            }),
+            ///  I2C_SR_REG
+            SR: mmio.Mmio(packed struct(u32) {
+                ///  reg_resp_rec
+                RESP_REC: u1,
+                ///  reg_slave_rw
+                SLAVE_RW: u1,
+                reserved3: u1,
+                ///  reg_arb_lost
+                ARB_LOST: u1,
+                ///  reg_bus_busy
+                BUS_BUSY: u1,
+                ///  reg_slave_addressed
+                SLAVE_ADDRESSED: u1,
+                reserved8: u2,
+                ///  reg_rxfifo_cnt
+                RXFIFO_CNT: u6,
+                ///  reg_stretch_cause
+                STRETCH_CAUSE: u2,
+                reserved18: u2,
+                ///  reg_txfifo_cnt
+                TXFIFO_CNT: u6,
+                ///  reg_scl_main_state_last
+                SCL_MAIN_STATE_LAST: u3,
+                reserved28: u1,
+                ///  reg_scl_state_last
+                SCL_STATE_LAST: u3,
+                padding: u1,
+            }),
+            ///  I2C_TO_REG
+            TO: mmio.Mmio(packed struct(u32) {
+                ///  reg_time_out_value
+                TIME_OUT_VALUE: u5,
+                ///  reg_time_out_en
+                TIME_OUT_EN: u1,
+                padding: u26,
+            }),
+            ///  I2C_SLAVE_ADDR_REG
+            SLAVE_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_slave_addr
+                SLAVE_ADDR: u15,
+                reserved31: u16,
+                ///  reg_addr_10bit_en
+                ADDR_10BIT_EN: u1,
+            }),
+            ///  I2C_FIFO_ST_REG
+            FIFO_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_raddr
+                RXFIFO_RADDR: u5,
+                ///  reg_rxfifo_waddr
+                RXFIFO_WADDR: u5,
+                ///  reg_txfifo_raddr
+                TXFIFO_RADDR: u5,
+                ///  reg_txfifo_waddr
+                TXFIFO_WADDR: u5,
+                reserved22: u2,
+                ///  reg_slave_rw_point
+                SLAVE_RW_POINT: u8,
+                padding: u2,
+            }),
+            ///  I2C_FIFO_CONF_REG
+            FIFO_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_thrhd
+                RXFIFO_WM_THRHD: u5,
+                ///  reg_txfifo_wm_thrhd
+                TXFIFO_WM_THRHD: u5,
+                ///  reg_nonfifo_en
+                NONFIFO_EN: u1,
+                ///  reg_fifo_addr_cfg_en
+                FIFO_ADDR_CFG_EN: u1,
+                ///  reg_rx_fifo_rst
+                RX_FIFO_RST: u1,
+                ///  reg_tx_fifo_rst
+                TX_FIFO_RST: u1,
+                ///  reg_fifo_prt_en
+                FIFO_PRT_EN: u1,
+                padding: u17,
+            }),
+            ///  I2C_FIFO_DATA_REG
+            DATA: mmio.Mmio(packed struct(u32) {
+                ///  reg_fifo_rdata
+                FIFO_RDATA: u8,
+                padding: u24,
+            }),
+            ///  I2C_INT_RAW_REG
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_raw
+                RXFIFO_WM_INT_RAW: u1,
+                ///  reg_txfifo_wm_int_raw
+                TXFIFO_WM_INT_RAW: u1,
+                ///  reg_rxfifo_ovf_int_raw
+                RXFIFO_OVF_INT_RAW: u1,
+                ///  reg_end_detect_int_raw
+                END_DETECT_INT_RAW: u1,
+                ///  reg_byte_trans_done_int_raw
+                BYTE_TRANS_DONE_INT_RAW: u1,
+                ///  reg_arbitration_lost_int_raw
+                ARBITRATION_LOST_INT_RAW: u1,
+                ///  reg_mst_txfifo_udf_int_raw
+                MST_TXFIFO_UDF_INT_RAW: u1,
+                ///  reg_trans_complete_int_raw
+                TRANS_COMPLETE_INT_RAW: u1,
+                ///  reg_time_out_int_raw
+                TIME_OUT_INT_RAW: u1,
+                ///  reg_trans_start_int_raw
+                TRANS_START_INT_RAW: u1,
+                ///  reg_nack_int_raw
+                NACK_INT_RAW: u1,
+                ///  reg_txfifo_ovf_int_raw
+                TXFIFO_OVF_INT_RAW: u1,
+                ///  reg_rxfifo_udf_int_raw
+                RXFIFO_UDF_INT_RAW: u1,
+                ///  reg_scl_st_to_int_raw
+                SCL_ST_TO_INT_RAW: u1,
+                ///  reg_scl_main_st_to_int_raw
+                SCL_MAIN_ST_TO_INT_RAW: u1,
+                ///  reg_det_start_int_raw
+                DET_START_INT_RAW: u1,
+                ///  reg_slave_stretch_int_raw
+                SLAVE_STRETCH_INT_RAW: u1,
+                ///  reg_general_call_int_raw
+                GENERAL_CALL_INT_RAW: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_CLR_REG
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_clr
+                RXFIFO_WM_INT_CLR: u1,
+                ///  reg_txfifo_wm_int_clr
+                TXFIFO_WM_INT_CLR: u1,
+                ///  reg_rxfifo_ovf_int_clr
+                RXFIFO_OVF_INT_CLR: u1,
+                ///  reg_end_detect_int_clr
+                END_DETECT_INT_CLR: u1,
+                ///  reg_byte_trans_done_int_clr
+                BYTE_TRANS_DONE_INT_CLR: u1,
+                ///  reg_arbitration_lost_int_clr
+                ARBITRATION_LOST_INT_CLR: u1,
+                ///  reg_mst_txfifo_udf_int_clr
+                MST_TXFIFO_UDF_INT_CLR: u1,
+                ///  reg_trans_complete_int_clr
+                TRANS_COMPLETE_INT_CLR: u1,
+                ///  reg_time_out_int_clr
+                TIME_OUT_INT_CLR: u1,
+                ///  reg_trans_start_int_clr
+                TRANS_START_INT_CLR: u1,
+                ///  reg_nack_int_clr
+                NACK_INT_CLR: u1,
+                ///  reg_txfifo_ovf_int_clr
+                TXFIFO_OVF_INT_CLR: u1,
+                ///  reg_rxfifo_udf_int_clr
+                RXFIFO_UDF_INT_CLR: u1,
+                ///  reg_scl_st_to_int_clr
+                SCL_ST_TO_INT_CLR: u1,
+                ///  reg_scl_main_st_to_int_clr
+                SCL_MAIN_ST_TO_INT_CLR: u1,
+                ///  reg_det_start_int_clr
+                DET_START_INT_CLR: u1,
+                ///  reg_slave_stretch_int_clr
+                SLAVE_STRETCH_INT_CLR: u1,
+                ///  reg_general_call_int_clr
+                GENERAL_CALL_INT_CLR: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_ENA_REG
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_ena
+                RXFIFO_WM_INT_ENA: u1,
+                ///  reg_txfifo_wm_int_ena
+                TXFIFO_WM_INT_ENA: u1,
+                ///  reg_rxfifo_ovf_int_ena
+                RXFIFO_OVF_INT_ENA: u1,
+                ///  reg_end_detect_int_ena
+                END_DETECT_INT_ENA: u1,
+                ///  reg_byte_trans_done_int_ena
+                BYTE_TRANS_DONE_INT_ENA: u1,
+                ///  reg_arbitration_lost_int_ena
+                ARBITRATION_LOST_INT_ENA: u1,
+                ///  reg_mst_txfifo_udf_int_ena
+                MST_TXFIFO_UDF_INT_ENA: u1,
+                ///  reg_trans_complete_int_ena
+                TRANS_COMPLETE_INT_ENA: u1,
+                ///  reg_time_out_int_ena
+                TIME_OUT_INT_ENA: u1,
+                ///  reg_trans_start_int_ena
+                TRANS_START_INT_ENA: u1,
+                ///  reg_nack_int_ena
+                NACK_INT_ENA: u1,
+                ///  reg_txfifo_ovf_int_ena
+                TXFIFO_OVF_INT_ENA: u1,
+                ///  reg_rxfifo_udf_int_ena
+                RXFIFO_UDF_INT_ENA: u1,
+                ///  reg_scl_st_to_int_ena
+                SCL_ST_TO_INT_ENA: u1,
+                ///  reg_scl_main_st_to_int_ena
+                SCL_MAIN_ST_TO_INT_ENA: u1,
+                ///  reg_det_start_int_ena
+                DET_START_INT_ENA: u1,
+                ///  reg_slave_stretch_int_ena
+                SLAVE_STRETCH_INT_ENA: u1,
+                ///  reg_general_call_int_ena
+                GENERAL_CALL_INT_ENA: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_STATUS_REG
+            INT_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_st
+                RXFIFO_WM_INT_ST: u1,
+                ///  reg_txfifo_wm_int_st
+                TXFIFO_WM_INT_ST: u1,
+                ///  reg_rxfifo_ovf_int_st
+                RXFIFO_OVF_INT_ST: u1,
+                ///  reg_end_detect_int_st
+                END_DETECT_INT_ST: u1,
+                ///  reg_byte_trans_done_int_st
+                BYTE_TRANS_DONE_INT_ST: u1,
+                ///  reg_arbitration_lost_int_st
+                ARBITRATION_LOST_INT_ST: u1,
+                ///  reg_mst_txfifo_udf_int_st
+                MST_TXFIFO_UDF_INT_ST: u1,
+                ///  reg_trans_complete_int_st
+                TRANS_COMPLETE_INT_ST: u1,
+                ///  reg_time_out_int_st
+                TIME_OUT_INT_ST: u1,
+                ///  reg_trans_start_int_st
+                TRANS_START_INT_ST: u1,
+                ///  reg_nack_int_st
+                NACK_INT_ST: u1,
+                ///  reg_txfifo_ovf_int_st
+                TXFIFO_OVF_INT_ST: u1,
+                ///  reg_rxfifo_udf_int_st
+                RXFIFO_UDF_INT_ST: u1,
+                ///  reg_scl_st_to_int_st
+                SCL_ST_TO_INT_ST: u1,
+                ///  reg_scl_main_st_to_int_st
+                SCL_MAIN_ST_TO_INT_ST: u1,
+                ///  reg_det_start_int_st
+                DET_START_INT_ST: u1,
+                ///  reg_slave_stretch_int_st
+                SLAVE_STRETCH_INT_ST: u1,
+                ///  reg_general_call_int_st
+                GENERAL_CALL_INT_ST: u1,
+                padding: u14,
+            }),
+            ///  I2C_SDA_HOLD_REG
+            SDA_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SDA_SAMPLE_REG
+            SDA_SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_sample_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_HIGH_PERIOD_REG
+            SCL_HIGH_PERIOD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_high_period
+                SCL_HIGH_PERIOD: u9,
+                ///  reg_scl_wait_high_period
+                SCL_WAIT_HIGH_PERIOD: u7,
+                padding: u16,
+            }),
+            reserved64: [4]u8,
+            ///  I2C_SCL_START_HOLD_REG
+            SCL_START_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_start_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_RSTART_SETUP_REG
+            SCL_RSTART_SETUP: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_rstart_setup_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_STOP_HOLD_REG
+            SCL_STOP_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_stop_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_STOP_SETUP_REG
+            SCL_STOP_SETUP: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_stop_setup_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_FILTER_CFG_REG
+            FILTER_CFG: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_filter_thres
+                SCL_FILTER_THRES: u4,
+                ///  reg_sda_filter_thres
+                SDA_FILTER_THRES: u4,
+                ///  reg_scl_filter_en
+                SCL_FILTER_EN: u1,
+                ///  reg_sda_filter_en
+                SDA_FILTER_EN: u1,
+                padding: u22,
+            }),
+            ///  I2C_CLK_CONF_REG
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_sclk_div_num
+                SCLK_DIV_NUM: u8,
+                ///  reg_sclk_div_a
+                SCLK_DIV_A: u6,
+                ///  reg_sclk_div_b
+                SCLK_DIV_B: u6,
+                ///  reg_sclk_sel
+                SCLK_SEL: u1,
+                ///  reg_sclk_active
+                SCLK_ACTIVE: u1,
+                padding: u10,
+            }),
+            ///  I2C_COMD%s_REG
+            COMD: [8]mmio.Mmio(packed struct(u32) {
+                ///  reg_command
+                COMMAND: u14,
+                reserved31: u17,
+                ///  reg_command_done
+                COMMAND_DONE: u1,
+            }),
+            ///  I2C_SCL_ST_TIME_OUT_REG
+            SCL_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_st_to_regno more than 23
+                SCL_ST_TO_I2C: u5,
+                padding: u27,
+            }),
+            ///  I2C_SCL_MAIN_ST_TIME_OUT_REG
+            SCL_MAIN_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_main_st_to_regno more than 23
+                SCL_MAIN_ST_TO_I2C: u5,
+                padding: u27,
+            }),
+            ///  I2C_SCL_SP_CONF_REG
+            SCL_SP_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_rst_slv_en
+                SCL_RST_SLV_EN: u1,
+                ///  reg_scl_rst_slv_num
+                SCL_RST_SLV_NUM: u5,
+                ///  reg_scl_pd_en
+                SCL_PD_EN: u1,
+                ///  reg_sda_pd_en
+                SDA_PD_EN: u1,
+                padding: u24,
+            }),
+            ///  I2C_SCL_STRETCH_CONF_REG
+            SCL_STRETCH_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_stretch_protect_num
+                STRETCH_PROTECT_NUM: u10,
+                ///  reg_slave_scl_stretch_en
+                SLAVE_SCL_STRETCH_EN: u1,
+                ///  reg_slave_scl_stretch_clr
+                SLAVE_SCL_STRETCH_CLR: u1,
+                ///  reg_slave_byte_ack_ctl_en
+                SLAVE_BYTE_ACK_CTL_EN: u1,
+                ///  reg_slave_byte_ack_lvl
+                SLAVE_BYTE_ACK_LVL: u1,
+                padding: u18,
+            }),
+            reserved248: [112]u8,
+            ///  I2C_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u32,
+            }),
+            reserved256: [4]u8,
+            ///  I2C_TXFIFO_START_ADDR_REG
+            TXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_txfifo_start_addr.
+                TXFIFO_START_ADDR: u32,
+            }),
+            reserved384: [124]u8,
+            ///  I2C_RXFIFO_START_ADDR_REG
+            RXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_start_addr.
+                RXFIFO_START_ADDR: u32,
+            }),
+        };
+
+        ///  I2S (Inter-IC Sound) Controller
+        pub const I2S = extern struct {
+            reserved12: [12]u8,
+            ///  I2S interrupt raw register, valid in level.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_RAW: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt status register.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The masked interrupt status bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_ST: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt enable register.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_ENA: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt clear register.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the i2s_rx_done_int interrupt
+                RX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_tx_done_int interrupt
+                TX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_CLR: u1,
+                padding: u28,
+            }),
+            reserved32: [4]u8,
+            ///  I2S RX configure register
+            RX_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to reset receiver
+                RX_RESET: u1,
+                ///  Set this bit to reset Rx AFIFO
+                RX_FIFO_RESET: u1,
+                ///  Set this bit to start receiving data
+                RX_START: u1,
+                ///  Set this bit to enable slave receiver mode
+                RX_SLAVE_MOD: u1,
+                reserved5: u1,
+                ///  Set this bit to enable receiver in mono mode
+                RX_MONO: u1,
+                reserved7: u1,
+                ///  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+                RX_BIG_ENDIAN: u1,
+                ///  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
+                RX_UPDATE: u1,
+                ///  1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
+                RX_MONO_FST_VLD: u1,
+                ///  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+                RX_PCM_CONF: u2,
+                ///  Set this bit to bypass Compress/Decompress module for received data.
+                RX_PCM_BYPASS: u1,
+                ///  0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+                RX_STOP_MODE: u2,
+                ///  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+                RX_LEFT_ALIGN: u1,
+                ///  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+                RX_24_FILL_EN: u1,
+                ///  0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+                RX_WS_IDLE_POL: u1,
+                ///  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
+                RX_BIT_ORDER: u1,
+                ///  1: Enable I2S TDM Rx mode . 0: Disable.
+                RX_TDM_EN: u1,
+                ///  1: Enable I2S PDM Rx mode . 0: Disable.
+                RX_PDM_EN: u1,
+                padding: u11,
+            }),
+            ///  I2S TX configure register
+            TX_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to reset transmitter
+                TX_RESET: u1,
+                ///  Set this bit to reset Tx AFIFO
+                TX_FIFO_RESET: u1,
+                ///  Set this bit to start transmitting data
+                TX_START: u1,
+                ///  Set this bit to enable slave transmitter mode
+                TX_SLAVE_MOD: u1,
+                reserved5: u1,
+                ///  Set this bit to enable transmitter in mono mode
+                TX_MONO: u1,
+                ///  1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+                TX_CHAN_EQUAL: u1,
+                ///  I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+                TX_BIG_ENDIAN: u1,
+                ///  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
+                TX_UPDATE: u1,
+                ///  1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
+                TX_MONO_FST_VLD: u1,
+                ///  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+                TX_PCM_CONF: u2,
+                ///  Set this bit to bypass Compress/Decompress module for transmitted data.
+                TX_PCM_BYPASS: u1,
+                ///  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+                TX_STOP_EN: u1,
+                reserved15: u1,
+                ///  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+                TX_LEFT_ALIGN: u1,
+                ///  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+                TX_24_FILL_EN: u1,
+                ///  0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+                TX_WS_IDLE_POL: u1,
+                ///  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
+                TX_BIT_ORDER: u1,
+                ///  1: Enable I2S TDM Tx mode . 0: Disable.
+                TX_TDM_EN: u1,
+                ///  1: Enable I2S PDM Tx mode . 0: Disable.
+                TX_PDM_EN: u1,
+                reserved24: u3,
+                ///  I2S transmitter channel mode configuration bits.
+                TX_CHAN_MOD: u3,
+                ///  Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
+                SIG_LOOPBACK: u1,
+                padding: u4,
+            }),
+            ///  I2S RX configure register 1
+            RX_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+                RX_TDM_WS_WIDTH: u7,
+                ///  Bit clock configuration bits in receiver mode.
+                RX_BCK_DIV_NUM: u6,
+                ///  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+                RX_BITS_MOD: u5,
+                ///  I2S Rx half sample bits -1.
+                RX_HALF_SAMPLE_BITS: u6,
+                ///  The Rx bit number for each channel minus 1in TDM mode.
+                RX_TDM_CHAN_BITS: u5,
+                ///  Set this bit to enable receiver in Phillips standard mode
+                RX_MSB_SHIFT: u1,
+                padding: u2,
+            }),
+            ///  I2S TX configure register 1
+            TX_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+                TX_TDM_WS_WIDTH: u7,
+                ///  Bit clock configuration bits in transmitter mode.
+                TX_BCK_DIV_NUM: u6,
+                ///  Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+                TX_BITS_MOD: u5,
+                ///  I2S Tx half sample bits -1.
+                TX_HALF_SAMPLE_BITS: u6,
+                ///  The Tx bit number for each channel minus 1in TDM mode.
+                TX_TDM_CHAN_BITS: u5,
+                ///  Set this bit to enable transmitter in Phillips standard mode
+                TX_MSB_SHIFT: u1,
+                ///  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
+                TX_BCK_NO_DLY: u1,
+                padding: u1,
+            }),
+            ///  I2S RX clock configure register
+            RX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S clock divider value
+                RX_CLKM_DIV_NUM: u8,
+                reserved26: u18,
+                ///  I2S Rx module clock enable signal.
+                RX_CLK_ACTIVE: u1,
+                ///  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+                RX_CLK_SEL: u2,
+                ///  0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.
+                MCLK_SEL: u1,
+                padding: u2,
+            }),
+            ///  I2S TX clock configure register
+            TX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
+                TX_CLKM_DIV_NUM: u8,
+                reserved26: u18,
+                ///  I2S Tx module clock enable signal.
+                TX_CLK_ACTIVE: u1,
+                ///  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+                TX_CLK_SEL: u2,
+                ///  Set this bit to enable clk gate
+                CLK_EN: u1,
+                padding: u2,
+            }),
+            ///  I2S RX module clock divider configure register
+            RX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
+                RX_CLKM_DIV_Z: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+                RX_CLKM_DIV_Y: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+                RX_CLKM_DIV_X: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
+                RX_CLKM_DIV_YN1: u1,
+                padding: u4,
+            }),
+            ///  I2S TX module clock divider configure register
+            TX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
+                TX_CLKM_DIV_Z: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+                TX_CLKM_DIV_Y: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+                TX_CLKM_DIV_X: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
+                TX_CLKM_DIV_YN1: u1,
+                padding: u4,
+            }),
+            ///  I2S TX PCM2PDM configuration register
+            TX_PCM2PDM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  I2S TX PDM bypass hp filter or not. The option has been removed.
+                TX_PDM_HP_BYPASS: u1,
+                ///  I2S TX PDM OSR2 value
+                TX_PDM_SINC_OSR2: u4,
+                ///  I2S TX PDM prescale for sigmadelta
+                TX_PDM_PRESCALE: u8,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_HP_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_LP_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_SINC_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_SIGMADELTA_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta dither2 value
+                TX_PDM_SIGMADELTA_DITHER2: u1,
+                ///  I2S TX PDM sigmadelta dither value
+                TX_PDM_SIGMADELTA_DITHER: u1,
+                ///  I2S TX PDM dac mode enable
+                TX_PDM_DAC_2OUT_EN: u1,
+                ///  I2S TX PDM dac 2channel enable
+                TX_PDM_DAC_MODE_EN: u1,
+                ///  I2S TX PDM Converter enable
+                PCM2PDM_CONV_EN: u1,
+                padding: u6,
+            }),
+            ///  I2S TX PCM2PDM configuration register
+            TX_PCM2PDM_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  I2S TX PDM Fp
+                TX_PDM_FP: u10,
+                ///  I2S TX PDM Fs
+                TX_PDM_FS: u10,
+                ///  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
+                TX_IIR_HP_MULT12_5: u3,
+                ///  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
+                TX_IIR_HP_MULT12_0: u3,
+                padding: u6,
+            }),
+            reserved80: [8]u8,
+            ///  I2S TX TDM mode control register
+            RX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN0_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN1_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN2_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN3_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN4_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN5_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN6_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN7_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN8_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN9_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN10_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN11_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN12_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN13_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN14_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN15_EN: u1,
+                ///  The total channel number of I2S TX TDM mode.
+                RX_TDM_TOT_CHAN_NUM: u4,
+                padding: u12,
+            }),
+            ///  I2S TX TDM mode control register
+            TX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN0_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN1_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN2_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN3_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN4_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN5_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN6_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN7_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN8_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN9_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN10_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN11_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN12_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN13_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN14_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN15_EN: u1,
+                ///  The total channel number of I2S TX TDM mode.
+                TX_TDM_TOT_CHAN_NUM: u4,
+                ///  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
+                TX_TDM_SKIP_MSK_EN: u1,
+                padding: u11,
+            }),
+            ///  I2S RX timing control register
+            RX_TIMING: mmio.Mmio(packed struct(u32) {
+                ///  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_SD_IN_DM: u2,
+                reserved16: u14,
+                ///  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_WS_OUT_DM: u2,
+                reserved20: u2,
+                ///  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_BCK_OUT_DM: u2,
+                reserved24: u2,
+                ///  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_WS_IN_DM: u2,
+                reserved28: u2,
+                ///  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_BCK_IN_DM: u2,
+                padding: u2,
+            }),
+            ///  I2S TX timing control register
+            TX_TIMING: mmio.Mmio(packed struct(u32) {
+                ///  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_SD_OUT_DM: u2,
+                reserved4: u2,
+                ///  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_SD1_OUT_DM: u2,
+                reserved16: u10,
+                ///  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_WS_OUT_DM: u2,
+                reserved20: u2,
+                ///  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_BCK_OUT_DM: u2,
+                reserved24: u2,
+                ///  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_WS_IN_DM: u2,
+                reserved28: u2,
+                ///  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_BCK_IN_DM: u2,
+                padding: u2,
+            }),
+            ///  I2S HUNG configure register.
+            LC_HUNG_CONF: mmio.Mmio(packed struct(u32) {
+                ///  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
+                LC_FIFO_TIMEOUT: u8,
+                ///  The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+                LC_FIFO_TIMEOUT_SHIFT: u3,
+                ///  The enable bit for FIFO timeout
+                LC_FIFO_TIMEOUT_ENA: u1,
+                padding: u20,
+            }),
+            ///  I2S RX data number control register.
+            RXEOF_NUM: mmio.Mmio(packed struct(u32) {
+                ///  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+                RX_EOF_NUM: u12,
+                padding: u20,
+            }),
+            ///  I2S signal data register
+            CONF_SIGLE_DATA: mmio.Mmio(packed struct(u32) {
+                ///  The configured constant channel data to be sent out.
+                SINGLE_DATA: u32,
+            }),
+            ///  I2S TX status register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  1: i2s_tx is idle state. 0: i2s_tx is working.
+                TX_IDLE: u1,
+                padding: u31,
+            }),
+            reserved128: [16]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  I2S version control register
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Interrupt Core
+        pub const INTERRUPT_CORE0 = extern struct {
+            ///  mac intr map register
+            MAC_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  core0_mac_intr_map
+                MAC_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac nmi_intr map register
+            MAC_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_mac_nmi_map
+                MAC_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  pwr intr map register
+            PWR_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_pwr_intr_map
+                PWR_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb intr map register
+            BB_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bb_int_map
+                BB_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bt intr map register
+            BT_MAC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_mac_int_map
+                BT_MAC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb_bt intr map register
+            BT_BB_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_bb_int_map
+                BT_BB_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb_bt_nmi intr map register
+            BT_BB_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_bb_nmi_map
+                BT_BB_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwbt intr map register
+            RWBT_IRQ_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwbt_irq_map
+                RWBT_IRQ_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwble intr map register
+            RWBLE_IRQ_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwble_irq_map
+                RWBLE_IRQ_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwbt_nmi intr map register
+            RWBT_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwbt_nmi_map
+                RWBT_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwble_nmi intr map register
+            RWBLE_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwble_nmi_map
+                RWBLE_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2c intr map register
+            I2C_MST_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2c_mst_int_map
+                I2C_MST_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  slc0 intr map register
+            SLC0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_slc0_intr_map
+                SLC0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  slc1 intr map register
+            SLC1_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_slc1_intr_map
+                SLC1_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  apb_ctrl intr map register
+            APB_CTRL_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_apb_ctrl_intr_map
+                APB_CTRL_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  uchi0 intr map register
+            UHCI0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uhci0_intr_map
+                UHCI0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio intr map register
+            GPIO_INTERRUPT_PRO_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_gpio_interrupt_pro_map
+                GPIO_INTERRUPT_PRO_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio_pro intr map register
+            GPIO_INTERRUPT_PRO_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_gpio_interrupt_pro_nmi_map
+                GPIO_INTERRUPT_PRO_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio_pro_nmi intr map register
+            SPI_INTR_1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_intr_1_map
+                SPI_INTR_1_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi1 intr map register
+            SPI_INTR_2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_intr_2_map
+                SPI_INTR_2_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi2 intr map register
+            I2S1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2s1_int_map
+                I2S1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2s1 intr map register
+            UART_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uart_intr_map
+                UART_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  uart1 intr map register
+            UART1_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uart1_intr_map
+                UART1_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  ledc intr map register
+            LEDC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_ledc_int_map
+                LEDC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  efuse intr map register
+            EFUSE_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_efuse_int_map
+                EFUSE_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  can intr map register
+            CAN_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_can_int_map
+                CAN_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  usb intr map register
+            USB_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_usb_intr_map
+                USB_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  rtc intr map register
+            RTC_CORE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rtc_core_intr_map
+                RTC_CORE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  rmt intr map register
+            RMT_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rmt_intr_map
+                RMT_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2c intr map register
+            I2C_EXT0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2c_ext0_intr_map
+                I2C_EXT0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  timer1 intr map register
+            TIMER_INT1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_timer_int1_map
+                TIMER_INT1_MAP: u5,
+                padding: u27,
+            }),
+            ///  timer2 intr map register
+            TIMER_INT2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_timer_int2_map
+                TIMER_INT2_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg to intr map register
+            TG_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg_t0_int_map
+                TG_T0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg wdt intr map register
+            TG_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg_wdt_int_map
+                TG_WDT_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg1 to intr map register
+            TG1_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg1_t0_int_map
+                TG1_T0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg1 wdt intr map register
+            TG1_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg1_wdt_int_map
+                TG1_WDT_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  cache ia intr map register
+            CACHE_IA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cache_ia_int_map
+                CACHE_IA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer intr map register
+            SYSTIMER_TARGET0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target0_int_map
+                SYSTIMER_TARGET0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer target1 intr map register
+            SYSTIMER_TARGET1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target1_int_map
+                SYSTIMER_TARGET1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer target2 intr map register
+            SYSTIMER_TARGET2_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target2_int_map
+                SYSTIMER_TARGET2_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi mem reject intr map register
+            SPI_MEM_REJECT_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_mem_reject_intr_map
+                SPI_MEM_REJECT_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  icache perload intr map register
+            ICACHE_PRELOAD_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_icache_preload_int_map
+                ICACHE_PRELOAD_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  icache sync intr map register
+            ICACHE_SYNC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_icache_sync_int_map
+                ICACHE_SYNC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  adc intr map register
+            APB_ADC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_apb_adc_int_map
+                APB_ADC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch0 intr map register
+            DMA_CH0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch0_int_map
+                DMA_CH0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch1 intr map register
+            DMA_CH1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch1_int_map
+                DMA_CH1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch2 intr map register
+            DMA_CH2_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch2_int_map
+                DMA_CH2_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  rsa intr map register
+            RSA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rsa_int_map
+                RSA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  aes intr map register
+            AES_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_aes_int_map
+                AES_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  sha intr map register
+            SHA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_sha_int_map
+                SHA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 0 intr map register
+            CPU_INTR_FROM_CPU_0_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_0_map
+                CPU_INTR_FROM_CPU_0_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 0 intr map register
+            CPU_INTR_FROM_CPU_1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_1_map
+                CPU_INTR_FROM_CPU_1_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 1 intr map register
+            CPU_INTR_FROM_CPU_2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_2_map
+                CPU_INTR_FROM_CPU_2_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 3 intr map register
+            CPU_INTR_FROM_CPU_3_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_3_map
+                CPU_INTR_FROM_CPU_3_MAP: u5,
+                padding: u27,
+            }),
+            ///  assist debug intr map register
+            ASSIST_DEBUG_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_assist_debug_intr_map
+                ASSIST_DEBUG_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma pms violatile intr map register
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_apbperi_pms_monitor_violate_intr_map
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  iram0 pms violatile intr map register
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_iram0_pms_monitor_violate_intr_map
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_dram0_pms_monitor_violate_intr_map
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_pif_pms_monitor_violate_intr_map
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            BACKUP_PMS_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_backup_pms_violate_intr_map
+                BACKUP_PMS_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CACHE_CORE0_ACS_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cache_core0_acs_int_map
+                CACHE_CORE0_ACS_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            INTR_STATUS_REG_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_intr_status_0
+                INTR_STATUS_0: u32,
+            }),
+            ///  mac intr map register
+            INTR_STATUS_REG_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_intr_status_1
+                INTR_STATUS_1: u32,
+            }),
+            ///  mac intr map register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_reg_clk_en
+                REG_CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  mac intr map register
+            CPU_INT_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_enable
+                CPU_INT_ENABLE: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_TYPE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_type
+                CPU_INT_TYPE: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_clear
+                CPU_INT_CLEAR: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_EIP_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_eip_status
+                CPU_INT_EIP_STATUS: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_0_map
+                CPU_PRI_0_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_1_map
+                CPU_PRI_1_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_2_map
+                CPU_PRI_2_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_3_map
+                CPU_PRI_3_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_4: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_4_map
+                CPU_PRI_4_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_5: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_5_map
+                CPU_PRI_5_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_6: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_6_map
+                CPU_PRI_6_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_7: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_7_map
+                CPU_PRI_7_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_8: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_8_map
+                CPU_PRI_8_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_9: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_9_map
+                CPU_PRI_9_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_10: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_10_map
+                CPU_PRI_10_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_11: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_11_map
+                CPU_PRI_11_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_12: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_12_map
+                CPU_PRI_12_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_13: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_13_map
+                CPU_PRI_13_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_14: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_14_map
+                CPU_PRI_14_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_15: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_15_map
+                CPU_PRI_15_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_16: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_16_map
+                CPU_PRI_16_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_17: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_17_map
+                CPU_PRI_17_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_18: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_18_map
+                CPU_PRI_18_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_19: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_19_map
+                CPU_PRI_19_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_20: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_20_map
+                CPU_PRI_20_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_21: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_21_map
+                CPU_PRI_21_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_22: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_22_map
+                CPU_PRI_22_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_23: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_23_map
+                CPU_PRI_23_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_24: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_24_map
+                CPU_PRI_24_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_25: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_25_map
+                CPU_PRI_25_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_26: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_26_map
+                CPU_PRI_26_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_27: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_27_map
+                CPU_PRI_27_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_28: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_28_map
+                CPU_PRI_28_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_29: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_29_map
+                CPU_PRI_29_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_30: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_30_map
+                CPU_PRI_30_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_31: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_31_map
+                CPU_PRI_31_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_THRESH: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_thresh
+                CPU_INT_THRESH: u4,
+                padding: u28,
+            }),
+            reserved2044: [1636]u8,
+            ///  mac intr map register
+            INTERRUPT_REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_interrupt_reg_date
+                INTERRUPT_REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Input/Output Multiplexer
+        pub const IO_MUX = extern struct {
+            ///  Clock Output Configuration Register
+            PIN_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
+                CLK_OUT1: u4,
+                ///  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
+                CLK_OUT2: u4,
+                ///  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
+                CLK_OUT3: u4,
+                padding: u20,
+            }),
+            ///  IO MUX Configure Register for pad XTAL_32K_P
+            GPIO: [22]mmio.Mmio(packed struct(u32) {
+                ///  Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+                MCU_OE: u1,
+                ///  Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+                SLP_SEL: u1,
+                ///  Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
+                MCU_WPD: u1,
+                ///  Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
+                MCU_WPU: u1,
+                ///  Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+                MCU_IE: u1,
+                reserved7: u2,
+                ///  Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
+                FUN_WPD: u1,
+                ///  Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
+                FUN_WPU: u1,
+                ///  Input enable of the pad. 1: input enabled; 0: input disabled.
+                FUN_IE: u1,
+                ///  Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+                FUN_DRV: u2,
+                ///  Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
+                MCU_SEL: u3,
+                ///  Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+                FILTER_EN: u1,
+                padding: u16,
+            }),
+            reserved252: [160]u8,
+            ///  IO MUX Version Control Register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Version control register
+                REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  LED Control PWM (Pulse Width Modulation)
+        pub const LEDC = extern struct {
+            ///  LEDC_LSCH0_CONF0.
+            LSCH0_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch0.
+                TIMER_SEL_LSCH0: u2,
+                ///  reg_sig_out_en_lsch0.
+                SIG_OUT_EN_LSCH0: u1,
+                ///  reg_idle_lv_lsch0.
+                IDLE_LV_LSCH0: u1,
+                ///  reg_para_up_lsch0.
+                PARA_UP_LSCH0: u1,
+                ///  reg_ovf_num_lsch0.
+                OVF_NUM_LSCH0: u10,
+                ///  reg_ovf_cnt_en_lsch0.
+                OVF_CNT_EN_LSCH0: u1,
+                ///  reg_ovf_cnt_reset_lsch0.
+                OVF_CNT_RESET_LSCH0: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH0_HPOINT.
+            LSCH0_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch0.
+                HPOINT_LSCH0: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH0_DUTY.
+            LSCH0_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch0.
+                DUTY_LSCH0: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH0_CONF1.
+            LSCH0_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch0.
+                DUTY_SCALE_LSCH0: u10,
+                ///  reg_duty_cycle_lsch0.
+                DUTY_CYCLE_LSCH0: u10,
+                ///  reg_duty_num_lsch0.
+                DUTY_NUM_LSCH0: u10,
+                ///  reg_duty_inc_lsch0.
+                DUTY_INC_LSCH0: u1,
+                ///  reg_duty_start_lsch0.
+                DUTY_START_LSCH0: u1,
+            }),
+            ///  LEDC_LSCH0_DUTY_R.
+            LSCH0_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch0_r.
+                DUTY_LSCH0_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH1_CONF0.
+            LSCH1_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch1.
+                TIMER_SEL_LSCH1: u2,
+                ///  reg_sig_out_en_lsch1.
+                SIG_OUT_EN_LSCH1: u1,
+                ///  reg_idle_lv_lsch1.
+                IDLE_LV_LSCH1: u1,
+                ///  reg_para_up_lsch1.
+                PARA_UP_LSCH1: u1,
+                ///  reg_ovf_num_lsch1.
+                OVF_NUM_LSCH1: u10,
+                ///  reg_ovf_cnt_en_lsch1.
+                OVF_CNT_EN_LSCH1: u1,
+                ///  reg_ovf_cnt_reset_lsch1.
+                OVF_CNT_RESET_LSCH1: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH1_HPOINT.
+            LSCH1_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch1.
+                HPOINT_LSCH1: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH1_DUTY.
+            LSCH1_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch1.
+                DUTY_LSCH1: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH1_CONF1.
+            LSCH1_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch1.
+                DUTY_SCALE_LSCH1: u10,
+                ///  reg_duty_cycle_lsch1.
+                DUTY_CYCLE_LSCH1: u10,
+                ///  reg_duty_num_lsch1.
+                DUTY_NUM_LSCH1: u10,
+                ///  reg_duty_inc_lsch1.
+                DUTY_INC_LSCH1: u1,
+                ///  reg_duty_start_lsch1.
+                DUTY_START_LSCH1: u1,
+            }),
+            ///  LEDC_LSCH1_DUTY_R.
+            LSCH1_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch1_r.
+                DUTY_LSCH1_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH2_CONF0.
+            LSCH2_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch2.
+                TIMER_SEL_LSCH2: u2,
+                ///  reg_sig_out_en_lsch2.
+                SIG_OUT_EN_LSCH2: u1,
+                ///  reg_idle_lv_lsch2.
+                IDLE_LV_LSCH2: u1,
+                ///  reg_para_up_lsch2.
+                PARA_UP_LSCH2: u1,
+                ///  reg_ovf_num_lsch2.
+                OVF_NUM_LSCH2: u10,
+                ///  reg_ovf_cnt_en_lsch2.
+                OVF_CNT_EN_LSCH2: u1,
+                ///  reg_ovf_cnt_reset_lsch2.
+                OVF_CNT_RESET_LSCH2: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH2_HPOINT.
+            LSCH2_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch2.
+                HPOINT_LSCH2: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH2_DUTY.
+            LSCH2_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch2.
+                DUTY_LSCH2: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH2_CONF1.
+            LSCH2_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch2.
+                DUTY_SCALE_LSCH2: u10,
+                ///  reg_duty_cycle_lsch2.
+                DUTY_CYCLE_LSCH2: u10,
+                ///  reg_duty_num_lsch2.
+                DUTY_NUM_LSCH2: u10,
+                ///  reg_duty_inc_lsch2.
+                DUTY_INC_LSCH2: u1,
+                ///  reg_duty_start_lsch2.
+                DUTY_START_LSCH2: u1,
+            }),
+            ///  LEDC_LSCH2_DUTY_R.
+            LSCH2_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch2_r.
+                DUTY_LSCH2_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH3_CONF0.
+            LSCH3_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch3.
+                TIMER_SEL_LSCH3: u2,
+                ///  reg_sig_out_en_lsch3.
+                SIG_OUT_EN_LSCH3: u1,
+                ///  reg_idle_lv_lsch3.
+                IDLE_LV_LSCH3: u1,
+                ///  reg_para_up_lsch3.
+                PARA_UP_LSCH3: u1,
+                ///  reg_ovf_num_lsch3.
+                OVF_NUM_LSCH3: u10,
+                ///  reg_ovf_cnt_en_lsch3.
+                OVF_CNT_EN_LSCH3: u1,
+                ///  reg_ovf_cnt_reset_lsch3.
+                OVF_CNT_RESET_LSCH3: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH3_HPOINT.
+            LSCH3_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch3.
+                HPOINT_LSCH3: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH3_DUTY.
+            LSCH3_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch3.
+                DUTY_LSCH3: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH3_CONF1.
+            LSCH3_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch3.
+                DUTY_SCALE_LSCH3: u10,
+                ///  reg_duty_cycle_lsch3.
+                DUTY_CYCLE_LSCH3: u10,
+                ///  reg_duty_num_lsch3.
+                DUTY_NUM_LSCH3: u10,
+                ///  reg_duty_inc_lsch3.
+                DUTY_INC_LSCH3: u1,
+                ///  reg_duty_start_lsch3.
+                DUTY_START_LSCH3: u1,
+            }),
+            ///  LEDC_LSCH3_DUTY_R.
+            LSCH3_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch3_r.
+                DUTY_LSCH3_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH4_CONF0.
+            LSCH4_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch4.
+                TIMER_SEL_LSCH4: u2,
+                ///  reg_sig_out_en_lsch4.
+                SIG_OUT_EN_LSCH4: u1,
+                ///  reg_idle_lv_lsch4.
+                IDLE_LV_LSCH4: u1,
+                ///  reg_para_up_lsch4.
+                PARA_UP_LSCH4: u1,
+                ///  reg_ovf_num_lsch4.
+                OVF_NUM_LSCH4: u10,
+                ///  reg_ovf_cnt_en_lsch4.
+                OVF_CNT_EN_LSCH4: u1,
+                ///  reg_ovf_cnt_reset_lsch4.
+                OVF_CNT_RESET_LSCH4: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH4_HPOINT.
+            LSCH4_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch4.
+                HPOINT_LSCH4: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH4_DUTY.
+            LSCH4_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch4.
+                DUTY_LSCH4: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH4_CONF1.
+            LSCH4_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch4.
+                DUTY_SCALE_LSCH4: u10,
+                ///  reg_duty_cycle_lsch4.
+                DUTY_CYCLE_LSCH4: u10,
+                ///  reg_duty_num_lsch4.
+                DUTY_NUM_LSCH4: u10,
+                ///  reg_duty_inc_lsch4.
+                DUTY_INC_LSCH4: u1,
+                ///  reg_duty_start_lsch4.
+                DUTY_START_LSCH4: u1,
+            }),
+            ///  LEDC_LSCH4_DUTY_R.
+            LSCH4_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch4_r.
+                DUTY_LSCH4_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH5_CONF0.
+            LSCH5_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch5.
+                TIMER_SEL_LSCH5: u2,
+                ///  reg_sig_out_en_lsch5.
+                SIG_OUT_EN_LSCH5: u1,
+                ///  reg_idle_lv_lsch5.
+                IDLE_LV_LSCH5: u1,
+                ///  reg_para_up_lsch5.
+                PARA_UP_LSCH5: u1,
+                ///  reg_ovf_num_lsch5.
+                OVF_NUM_LSCH5: u10,
+                ///  reg_ovf_cnt_en_lsch5.
+                OVF_CNT_EN_LSCH5: u1,
+                ///  reg_ovf_cnt_reset_lsch5.
+                OVF_CNT_RESET_LSCH5: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH5_HPOINT.
+            LSCH5_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch5.
+                HPOINT_LSCH5: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH5_DUTY.
+            LSCH5_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch5.
+                DUTY_LSCH5: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH5_CONF1.
+            LSCH5_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch5.
+                DUTY_SCALE_LSCH5: u10,
+                ///  reg_duty_cycle_lsch5.
+                DUTY_CYCLE_LSCH5: u10,
+                ///  reg_duty_num_lsch5.
+                DUTY_NUM_LSCH5: u10,
+                ///  reg_duty_inc_lsch5.
+                DUTY_INC_LSCH5: u1,
+                ///  reg_duty_start_lsch5.
+                DUTY_START_LSCH5: u1,
+            }),
+            ///  LEDC_LSCH5_DUTY_R.
+            LSCH5_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch5_r.
+                DUTY_LSCH5_R: u19,
+                padding: u13,
+            }),
+            reserved160: [40]u8,
+            ///  LEDC_LSTIMER0_CONF.
+            LSTIMER0_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_duty_res.
+                LSTIMER0_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer0.
+                CLK_DIV_LSTIMER0: u18,
+                ///  reg_lstimer0_pause.
+                LSTIMER0_PAUSE: u1,
+                ///  reg_lstimer0_rst.
+                LSTIMER0_RST: u1,
+                ///  reg_tick_sel_lstimer0.
+                TICK_SEL_LSTIMER0: u1,
+                ///  reg_lstimer0_para_up.
+                LSTIMER0_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER0_VALUE.
+            LSTIMER0_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_cnt.
+                LSTIMER0_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER1_CONF.
+            LSTIMER1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer1_duty_res.
+                LSTIMER1_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer1.
+                CLK_DIV_LSTIMER1: u18,
+                ///  reg_lstimer1_pause.
+                LSTIMER1_PAUSE: u1,
+                ///  reg_lstimer1_rst.
+                LSTIMER1_RST: u1,
+                ///  reg_tick_sel_lstimer1.
+                TICK_SEL_LSTIMER1: u1,
+                ///  reg_lstimer1_para_up.
+                LSTIMER1_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER1_VALUE.
+            LSTIMER1_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer1_cnt.
+                LSTIMER1_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER2_CONF.
+            LSTIMER2_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer2_duty_res.
+                LSTIMER2_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer2.
+                CLK_DIV_LSTIMER2: u18,
+                ///  reg_lstimer2_pause.
+                LSTIMER2_PAUSE: u1,
+                ///  reg_lstimer2_rst.
+                LSTIMER2_RST: u1,
+                ///  reg_tick_sel_lstimer2.
+                TICK_SEL_LSTIMER2: u1,
+                ///  reg_lstimer2_para_up.
+                LSTIMER2_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER2_VALUE.
+            LSTIMER2_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer2_cnt.
+                LSTIMER2_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER3_CONF.
+            LSTIMER3_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer3_duty_res.
+                LSTIMER3_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer3.
+                CLK_DIV_LSTIMER3: u18,
+                ///  reg_lstimer3_pause.
+                LSTIMER3_PAUSE: u1,
+                ///  reg_lstimer3_rst.
+                LSTIMER3_RST: u1,
+                ///  reg_tick_sel_lstimer3.
+                TICK_SEL_LSTIMER3: u1,
+                ///  reg_lstimer3_para_up.
+                LSTIMER3_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER3_VALUE.
+            LSTIMER3_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer3_cnt.
+                LSTIMER3_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_INT_RAW.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_raw.
+                LSTIMER0_OVF_INT_RAW: u1,
+                ///  reg_lstimer1_ovf_int_raw.
+                LSTIMER1_OVF_INT_RAW: u1,
+                ///  reg_lstimer2_ovf_int_raw.
+                LSTIMER2_OVF_INT_RAW: u1,
+                ///  reg_lstimer3_ovf_int_raw.
+                LSTIMER3_OVF_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch0_int_raw.
+                DUTY_CHNG_END_LSCH0_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch1_int_raw.
+                DUTY_CHNG_END_LSCH1_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch2_int_raw.
+                DUTY_CHNG_END_LSCH2_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch3_int_raw.
+                DUTY_CHNG_END_LSCH3_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch4_int_raw.
+                DUTY_CHNG_END_LSCH4_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch5_int_raw.
+                DUTY_CHNG_END_LSCH5_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch0_int_raw.
+                OVF_CNT_LSCH0_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch1_int_raw.
+                OVF_CNT_LSCH1_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch2_int_raw.
+                OVF_CNT_LSCH2_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch3_int_raw.
+                OVF_CNT_LSCH3_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch4_int_raw.
+                OVF_CNT_LSCH4_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch5_int_raw.
+                OVF_CNT_LSCH5_INT_RAW: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_ST.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_st.
+                LSTIMER0_OVF_INT_ST: u1,
+                ///  reg_lstimer1_ovf_int_st.
+                LSTIMER1_OVF_INT_ST: u1,
+                ///  reg_lstimer2_ovf_int_st.
+                LSTIMER2_OVF_INT_ST: u1,
+                ///  reg_lstimer3_ovf_int_st.
+                LSTIMER3_OVF_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch0_int_st.
+                DUTY_CHNG_END_LSCH0_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch1_int_st.
+                DUTY_CHNG_END_LSCH1_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch2_int_st.
+                DUTY_CHNG_END_LSCH2_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch3_int_st.
+                DUTY_CHNG_END_LSCH3_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch4_int_st.
+                DUTY_CHNG_END_LSCH4_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch5_int_st.
+                DUTY_CHNG_END_LSCH5_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch0_int_st.
+                OVF_CNT_LSCH0_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch1_int_st.
+                OVF_CNT_LSCH1_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch2_int_st.
+                OVF_CNT_LSCH2_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch3_int_st.
+                OVF_CNT_LSCH3_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch4_int_st.
+                OVF_CNT_LSCH4_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch5_int_st.
+                OVF_CNT_LSCH5_INT_ST: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_ENA.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_ena.
+                LSTIMER0_OVF_INT_ENA: u1,
+                ///  reg_lstimer1_ovf_int_ena.
+                LSTIMER1_OVF_INT_ENA: u1,
+                ///  reg_lstimer2_ovf_int_ena.
+                LSTIMER2_OVF_INT_ENA: u1,
+                ///  reg_lstimer3_ovf_int_ena.
+                LSTIMER3_OVF_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch0_int_ena.
+                DUTY_CHNG_END_LSCH0_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch1_int_ena.
+                DUTY_CHNG_END_LSCH1_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch2_int_ena.
+                DUTY_CHNG_END_LSCH2_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch3_int_ena.
+                DUTY_CHNG_END_LSCH3_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch4_int_ena.
+                DUTY_CHNG_END_LSCH4_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch5_int_ena.
+                DUTY_CHNG_END_LSCH5_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch0_int_ena.
+                OVF_CNT_LSCH0_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch1_int_ena.
+                OVF_CNT_LSCH1_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch2_int_ena.
+                OVF_CNT_LSCH2_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch3_int_ena.
+                OVF_CNT_LSCH3_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch4_int_ena.
+                OVF_CNT_LSCH4_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch5_int_ena.
+                OVF_CNT_LSCH5_INT_ENA: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_CLR.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_clr.
+                LSTIMER0_OVF_INT_CLR: u1,
+                ///  reg_lstimer1_ovf_int_clr.
+                LSTIMER1_OVF_INT_CLR: u1,
+                ///  reg_lstimer2_ovf_int_clr.
+                LSTIMER2_OVF_INT_CLR: u1,
+                ///  reg_lstimer3_ovf_int_clr.
+                LSTIMER3_OVF_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch0_int_clr.
+                DUTY_CHNG_END_LSCH0_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch1_int_clr.
+                DUTY_CHNG_END_LSCH1_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch2_int_clr.
+                DUTY_CHNG_END_LSCH2_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch3_int_clr.
+                DUTY_CHNG_END_LSCH3_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch4_int_clr.
+                DUTY_CHNG_END_LSCH4_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch5_int_clr.
+                DUTY_CHNG_END_LSCH5_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch0_int_clr.
+                OVF_CNT_LSCH0_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch1_int_clr.
+                OVF_CNT_LSCH1_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch2_int_clr.
+                OVF_CNT_LSCH2_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch3_int_clr.
+                OVF_CNT_LSCH3_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch4_int_clr.
+                OVF_CNT_LSCH4_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch5_int_clr.
+                OVF_CNT_LSCH5_INT_CLR: u1,
+                padding: u16,
+            }),
+            ///  LEDC_CONF.
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_apb_clk_sel.
+                APB_CLK_SEL: u2,
+                reserved31: u29,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+            reserved252: [40]u8,
+            ///  LEDC_DATE.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_ledc_date.
+                LEDC_DATE: u32,
+            }),
+        };
+
+        ///  Remote Control Peripheral
+        pub const RMT = extern struct {
+            ///  RMT_CH0DATA_REG.
+            CH0DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH1DATA_REG.
+            CH1DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH2DATA_REG.
+            CH2DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH3DATA_REG.
+            CH3DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            reserved28: [12]u8,
+            ///  RMT_CH2CONF1_REG.
+            CH2CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_rx_en_ch2.
+                RX_EN: u1,
+                ///  reg_mem_wr_rst_ch2.
+                MEM_WR_RST: u1,
+                ///  reg_apb_mem_rst_ch2.
+                APB_MEM_RST: u1,
+                ///  reg_mem_owner_ch2.
+                MEM_OWNER: u1,
+                ///  reg_rx_filter_en_ch2.
+                RX_FILTER_EN: u1,
+                ///  reg_rx_filter_thres_ch2.
+                RX_FILTER_THRES: u8,
+                ///  reg_mem_rx_wrap_en_ch2.
+                MEM_RX_WRAP_EN: u1,
+                ///  reg_afifo_rst_ch2.
+                AFIFO_RST: u1,
+                ///  reg_conf_update_ch2.
+                CONF_UPDATE: u1,
+                padding: u16,
+            }),
+            reserved36: [4]u8,
+            ///  RMT_CH3CONF1_REG.
+            CH3CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_rx_en_ch3.
+                RX_EN: u1,
+                ///  reg_mem_wr_rst_ch3.
+                MEM_WR_RST: u1,
+                ///  reg_apb_mem_rst_ch3.
+                APB_MEM_RST: u1,
+                ///  reg_mem_owner_ch3.
+                MEM_OWNER: u1,
+                ///  reg_rx_filter_en_ch3.
+                RX_FILTER_EN: u1,
+                ///  reg_rx_filter_thres_ch3.
+                RX_FILTER_THRES: u8,
+                ///  reg_mem_rx_wrap_en_ch3.
+                MEM_RX_WRAP_EN: u1,
+                ///  reg_afifo_rst_ch3.
+                AFIFO_RST: u1,
+                ///  reg_conf_update_ch3.
+                CONF_UPDATE: u1,
+                padding: u16,
+            }),
+            ///  RMT_CH0STATUS_REG.
+            CH0STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_raddr_ex_ch0.
+                MEM_RADDR_EX: u9,
+                ///  reg_state_ch0.
+                STATE: u3,
+                ///  reg_apb_mem_waddr_ch0.
+                APB_MEM_WADDR: u9,
+                ///  reg_apb_mem_rd_err_ch0.
+                APB_MEM_RD_ERR: u1,
+                ///  reg_mem_empty_ch0.
+                MEM_EMPTY: u1,
+                ///  reg_apb_mem_wr_err_ch0.
+                APB_MEM_WR_ERR: u1,
+                ///  reg_apb_mem_raddr_ch0.
+                APB_MEM_RADDR: u8,
+            }),
+            ///  RMT_CH1STATUS_REG.
+            CH1STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_raddr_ex_ch1.
+                MEM_RADDR_EX: u9,
+                ///  reg_state_ch1.
+                STATE: u3,
+                ///  reg_apb_mem_waddr_ch1.
+                APB_MEM_WADDR: u9,
+                ///  reg_apb_mem_rd_err_ch1.
+                APB_MEM_RD_ERR: u1,
+                ///  reg_mem_empty_ch1.
+                MEM_EMPTY: u1,
+                ///  reg_apb_mem_wr_err_ch1.
+                APB_MEM_WR_ERR: u1,
+                ///  reg_apb_mem_raddr_ch1.
+                APB_MEM_RADDR: u8,
+            }),
+            ///  RMT_CH2STATUS_REG.
+            CH2STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_waddr_ex_ch2.
+                MEM_WADDR_EX: u9,
+                reserved12: u3,
+                ///  reg_apb_mem_raddr_ch2.
+                APB_MEM_RADDR: u9,
+                reserved22: u1,
+                ///  reg_state_ch2.
+                STATE: u3,
+                ///  reg_mem_owner_err_ch2.
+                MEM_OWNER_ERR: u1,
+                ///  reg_mem_full_ch2.
+                MEM_FULL: u1,
+                ///  reg_apb_mem_rd_err_ch2.
+                APB_MEM_RD_ERR: u1,
+                padding: u4,
+            }),
+            ///  RMT_CH3STATUS_REG.
+            CH3STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_waddr_ex_ch3.
+                MEM_WADDR_EX: u9,
+                reserved12: u3,
+                ///  reg_apb_mem_raddr_ch3.
+                APB_MEM_RADDR: u9,
+                reserved22: u1,
+                ///  reg_state_ch3.
+                STATE: u3,
+                ///  reg_mem_owner_err_ch3.
+                MEM_OWNER_ERR: u1,
+                ///  reg_mem_full_ch3.
+                MEM_FULL: u1,
+                ///  reg_apb_mem_rd_err_ch3.
+                APB_MEM_RD_ERR: u1,
+                padding: u4,
+            }),
+            ///  RMT_INT_RAW_REG.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_raw.
+                CH2_RX_THR_EVENT_INT_RAW: u1,
+                ///  reg_ch3_rx_thr_event_int_raw.
+                CH3_RX_THR_EVENT_INT_RAW: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_ST_REG.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_st.
+                CH2_RX_THR_EVENT_INT_ST: u1,
+                ///  reg_ch3_rx_thr_event_int_st.
+                CH3_RX_THR_EVENT_INT_ST: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_ENA_REG.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_ena.
+                CH2_RX_THR_EVENT_INT_ENA: u1,
+                ///  reg_ch3_rx_thr_event_int_ena.
+                CH3_RX_THR_EVENT_INT_ENA: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_CLR_REG.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_clr.
+                CH2_RX_THR_EVENT_INT_CLR: u1,
+                ///  reg_ch3_rx_thr_event_int_clr.
+                CH3_RX_THR_EVENT_INT_CLR: u1,
+                padding: u20,
+            }),
+            ///  RMT_CH0CARRIER_DUTY_REG.
+            CH0CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_ch0.
+                CARRIER_LOW: u16,
+                ///  reg_carrier_high_ch0.
+                CARRIER_HIGH: u16,
+            }),
+            ///  RMT_CH1CARRIER_DUTY_REG.
+            CH1CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_ch1.
+                CARRIER_LOW: u16,
+                ///  reg_carrier_high_ch1.
+                CARRIER_HIGH: u16,
+            }),
+            ///  RMT_CH2_RX_CARRIER_RM_REG.
+            CH2_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_thres_ch2.
+                CARRIER_LOW_THRES: u16,
+                ///  reg_carrier_high_thres_ch2.
+                CARRIER_HIGH_THRES: u16,
+            }),
+            ///  RMT_CH3_RX_CARRIER_RM_REG.
+            CH3_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_thres_ch3.
+                CARRIER_LOW_THRES: u16,
+                ///  reg_carrier_high_thres_ch3.
+                CARRIER_HIGH_THRES: u16,
+            }),
+            reserved104: [16]u8,
+            ///  RMT_SYS_CONF_REG.
+            SYS_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_apb_fifo_mask.
+                APB_FIFO_MASK: u1,
+                ///  reg_mem_clk_force_on.
+                MEM_CLK_FORCE_ON: u1,
+                ///  reg_rmt_mem_force_pd.
+                MEM_FORCE_PD: u1,
+                ///  reg_rmt_mem_force_pu.
+                MEM_FORCE_PU: u1,
+                ///  reg_rmt_sclk_div_num.
+                SCLK_DIV_NUM: u8,
+                ///  reg_rmt_sclk_div_a.
+                SCLK_DIV_A: u6,
+                ///  reg_rmt_sclk_div_b.
+                SCLK_DIV_B: u6,
+                ///  reg_rmt_sclk_sel.
+                SCLK_SEL: u2,
+                ///  reg_rmt_sclk_active.
+                SCLK_ACTIVE: u1,
+                reserved31: u4,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+            ///  RMT_TX_SIM_REG.
+            TX_SIM: mmio.Mmio(packed struct(u32) {
+                ///  reg_rmt_tx_sim_ch0.
+                TX_SIM_CH0: u1,
+                ///  reg_rmt_tx_sim_ch1.
+                TX_SIM_CH1: u1,
+                ///  reg_rmt_tx_sim_en.
+                TX_SIM_EN: u1,
+                padding: u29,
+            }),
+            ///  RMT_REF_CNT_RST_REG.
+            REF_CNT_RST: mmio.Mmio(packed struct(u32) {
+                ///  reg_ref_cnt_rst_ch0.
+                CH0: u1,
+                ///  reg_ref_cnt_rst_ch1.
+                CH1: u1,
+                ///  reg_ref_cnt_rst_ch2.
+                CH2: u1,
+                ///  reg_ref_cnt_rst_ch3.
+                CH3: u1,
+                padding: u28,
+            }),
+            reserved204: [88]u8,
+            ///  RMT_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_rmt_date.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Hardware random number generator
+        pub const RNG = extern struct {
+            reserved176: [176]u8,
+            ///  Random number data
+            DATA: u32,
+        };
+
+        ///  RSA (Rivest Shamir Adleman) Accelerator
+        pub const RSA = extern struct {
+            ///  The memory that stores M
+            M_MEM: [16]u8,
+            reserved512: [496]u8,
+            ///  The memory that stores Z
+            Z_MEM: [16]u8,
+            reserved1024: [496]u8,
+            ///  The memory that stores Y
+            Y_MEM: [16]u8,
+            reserved1536: [496]u8,
+            ///  The memory that stores X
+            X_MEM: [16]u8,
+            reserved2048: [496]u8,
+            ///  RSA M_prime register
+            M_PRIME: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores m'
+                M_PRIME: u32,
+            }),
+            ///  RSA mode register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  rsa mode (rsa length).
+                MODE: u7,
+                padding: u25,
+            }),
+            ///  RSA query clean register
+            QUERY_CLEAN: mmio.Mmio(packed struct(u32) {
+                ///  query clean
+                QUERY_CLEAN: u1,
+                padding: u31,
+            }),
+            ///  RSA modular exponentiation trigger register.
+            SET_START_MODEXP: mmio.Mmio(packed struct(u32) {
+                ///  start modular exponentiation
+                SET_START_MODEXP: u1,
+                padding: u31,
+            }),
+            ///  RSA modular multiplication trigger register.
+            SET_START_MODMULT: mmio.Mmio(packed struct(u32) {
+                ///  start modular multiplication
+                SET_START_MODMULT: u1,
+                padding: u31,
+            }),
+            ///  RSA normal multiplication trigger register.
+            SET_START_MULT: mmio.Mmio(packed struct(u32) {
+                ///  start multiplicaiton
+                SET_START_MULT: u1,
+                padding: u31,
+            }),
+            ///  RSA query idle register
+            QUERY_IDLE: mmio.Mmio(packed struct(u32) {
+                ///  query rsa idle. 1'b0: busy, 1'b1: idle
+                QUERY_IDLE: u1,
+                padding: u31,
+            }),
+            ///  RSA interrupt clear register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to clear RSA interrupt.
+                CLEAR_INTERRUPT: u1,
+                padding: u31,
+            }),
+            ///  RSA constant time option register
+            CONSTANT_TIME: mmio.Mmio(packed struct(u32) {
+                ///  Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
+                CONSTANT_TIME: u1,
+                padding: u31,
+            }),
+            ///  RSA search option
+            SEARCH_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
+                SEARCH_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  RSA search position configure register
+            SEARCH_POS: mmio.Mmio(packed struct(u32) {
+                ///  Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
+                SEARCH_POS: u12,
+                padding: u20,
+            }),
+            ///  RSA interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
+                INT_ENA: u1,
+                padding: u31,
+            }),
+            ///  RSA version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  rsa version information
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  Real-Time Clock Control
+        pub const RTC_CNTL = extern struct {
+            ///  rtc configure register
+            OPTIONS0: mmio.Mmio(packed struct(u32) {
+                ///  {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
+                SW_STALL_APPCPU_C0: u2,
+                ///  {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
+                SW_STALL_PROCPU_C0: u2,
+                ///  APP CPU SW reset
+                SW_APPCPU_RST: u1,
+                ///  PRO CPU SW reset
+                SW_PROCPU_RST: u1,
+                ///  BB_I2C force power down
+                BB_I2C_FORCE_PD: u1,
+                ///  BB_I2C force power up
+                BB_I2C_FORCE_PU: u1,
+                ///  BB_PLL _I2C force power down
+                BBPLL_I2C_FORCE_PD: u1,
+                ///  BB_PLL_I2C force power up
+                BBPLL_I2C_FORCE_PU: u1,
+                ///  BB_PLL force power down
+                BBPLL_FORCE_PD: u1,
+                ///  BB_PLL force power up
+                BBPLL_FORCE_PU: u1,
+                ///  crystall force power down
+                XTL_FORCE_PD: u1,
+                ///  crystall force power up
+                XTL_FORCE_PU: u1,
+                ///  wait bias_sleep and current source wakeup
+                XTL_EN_WAIT: u4,
+                reserved20: u2,
+                ///  analog configure
+                XTL_EXT_CTR_SEL: u3,
+                ///  analog configure
+                XTL_FORCE_ISO: u1,
+                ///  analog configure
+                PLL_FORCE_ISO: u1,
+                ///  analog configure
+                ANALOG_FORCE_ISO: u1,
+                ///  analog configure
+                XTL_FORCE_NOISO: u1,
+                ///  analog configure
+                PLL_FORCE_NOISO: u1,
+                ///  analog configure
+                ANALOG_FORCE_NOISO: u1,
+                ///  digital wrap force reset in deep sleep
+                DG_WRAP_FORCE_RST: u1,
+                ///  digital core force no reset in deep sleep
+                DG_WRAP_FORCE_NORST: u1,
+                ///  SW system reset
+                SW_SYS_RST: u1,
+            }),
+            ///  rtc configure register
+            SLP_TIMER0: mmio.Mmio(packed struct(u32) {
+                ///  configure the sleep time
+                SLP_VAL_LO: u32,
+            }),
+            ///  rtc configure register
+            SLP_TIMER1: mmio.Mmio(packed struct(u32) {
+                ///  RTC sleep timer high 16 bits
+                SLP_VAL_HI: u16,
+                ///  timer alarm enable bit
+                RTC_MAIN_TIMER_ALARM_EN: u1,
+                padding: u15,
+            }),
+            ///  rtc configure register
+            TIME_UPDATE: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  Enable to record system stall time
+                TIMER_SYS_STALL: u1,
+                ///  Enable to record 40M XTAL OFF time
+                TIMER_XTL_OFF: u1,
+                ///  enable to record system reset time
+                TIMER_SYS_RST: u1,
+                reserved31: u1,
+                ///  Set 1: to update register with RTC timer
+                RTC_TIME_UPDATE: u1,
+            }),
+            ///  rtc configure register
+            TIME_LOW0: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer low 32 bits
+                RTC_TIMER_VALUE0_LOW: u32,
+            }),
+            ///  rtc configure register
+            TIME_HIGH0: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer high 16 bits
+                RTC_TIMER_VALUE0_HIGH: u16,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            STATE0: mmio.Mmio(packed struct(u32) {
+                ///  rtc software interrupt to main cpu
+                RTC_SW_CPU_INT: u1,
+                ///  clear rtc sleep reject cause
+                RTC_SLP_REJECT_CAUSE_CLR: u1,
+                reserved22: u20,
+                ///  1: APB to RTC using bridge
+                APB2RTC_BRIDGE_SEL: u1,
+                reserved28: u5,
+                ///  SDIO active indication
+                SDIO_ACTIVE_IND: u1,
+                ///  leep wakeup bit
+                SLP_WAKEUP: u1,
+                ///  leep reject bit
+                SLP_REJECT: u1,
+                ///  sleep enable bit
+                SLEEP_EN: u1,
+            }),
+            ///  rtc configure register
+            TIMER1: mmio.Mmio(packed struct(u32) {
+                ///  CPU stall enable bit
+                CPU_STALL_EN: u1,
+                ///  CPU stall wait cycles in fast_clk_rtc
+                CPU_STALL_WAIT: u5,
+                ///  CK8M wait cycles in slow_clk_rtc
+                CK8M_WAIT: u8,
+                ///  XTAL wait cycles in slow_clk_rtc
+                XTL_BUF_WAIT: u10,
+                ///  PLL wait cycles in slow_clk_rtc
+                PLL_BUF_WAIT: u8,
+            }),
+            ///  rtc configure register
+            TIMER2: mmio.Mmio(packed struct(u32) {
+                reserved24: u24,
+                ///  minimal cycles in slow_clk_rtc for CK8M in power down state
+                MIN_TIME_CK8M_OFF: u8,
+            }),
+            ///  rtc configure register
+            TIMER3: mmio.Mmio(packed struct(u32) {
+                ///  wifi power domain wakeup time
+                WIFI_WAIT_TIMER: u9,
+                ///  wifi power domain power on time
+                WIFI_POWERUP_TIMER: u7,
+                ///  bt power domain wakeup time
+                BT_WAIT_TIMER: u9,
+                ///  bt power domain power on time
+                BT_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            TIMER4: mmio.Mmio(packed struct(u32) {
+                ///  cpu top power domain wakeup time
+                CPU_TOP_WAIT_TIMER: u9,
+                ///  cpu top power domain power on time
+                CPU_TOP_POWERUP_TIMER: u7,
+                ///  digital wrap power domain wakeup time
+                DG_WRAP_WAIT_TIMER: u9,
+                ///  digital wrap power domain power on time
+                DG_WRAP_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            TIMER5: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  minimal sleep cycles in slow_clk_rtc
+                MIN_SLP_VAL: u8,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            TIMER6: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  digital peri power domain wakeup time
+                DG_PERI_WAIT_TIMER: u9,
+                ///  digital peri power domain power on time
+                DG_PERI_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            ANA_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  force no bypass i2c power on reset
+                RESET_POR_FORCE_PD: u1,
+                ///  force bypass i2c power on reset
+                RESET_POR_FORCE_PU: u1,
+                ///  enable glitch reset
+                GLITCH_RST_EN: u1,
+                reserved22: u1,
+                ///  PLLA force power up
+                SAR_I2C_PU: u1,
+                ///  PLLA force power down
+                PLLA_FORCE_PD: u1,
+                ///  PLLA force power up
+                PLLA_FORCE_PU: u1,
+                ///  start BBPLL calibration during sleep
+                BBPLL_CAL_SLP_START: u1,
+                ///  1: PVTMON power up
+                PVTMON_PU: u1,
+                ///  1: TXRF_I2C power up
+                TXRF_I2C_PU: u1,
+                ///  1: RFRX_PBUS power up
+                RFRX_PBUS_PU: u1,
+                reserved30: u1,
+                ///  1: CKGEN_I2C power up
+                CKGEN_I2C_PU: u1,
+                ///  power up pll i2c
+                PLL_I2C_PU: u1,
+            }),
+            ///  rtc configure register
+            RESET_STATE: mmio.Mmio(packed struct(u32) {
+                ///  reset cause of PRO CPU
+                RESET_CAUSE_PROCPU: u6,
+                ///  reset cause of APP CPU
+                RESET_CAUSE_APPCPU: u6,
+                ///  APP CPU state vector sel
+                STAT_VECTOR_SEL_APPCPU: u1,
+                ///  PRO CPU state vector sel
+                STAT_VECTOR_SEL_PROCPU: u1,
+                ///  PRO CPU reset_flag
+                ALL_RESET_FLAG_PROCPU: u1,
+                ///  APP CPU reset flag
+                ALL_RESET_FLAG_APPCPU: u1,
+                ///  clear PRO CPU reset_flag
+                ALL_RESET_FLAG_CLR_PROCPU: u1,
+                ///  clear APP CPU reset flag
+                ALL_RESET_FLAG_CLR_APPCPU: u1,
+                ///  APPCPU OcdHaltOnReset
+                OCD_HALT_ON_RESET_APPCPU: u1,
+                ///  PROCPU OcdHaltOnReset
+                OCD_HALT_ON_RESET_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_APPCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_CLR_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_CLR_APPCPU: u1,
+                ///  configure dreset configure
+                RTC_DRESET_MASK_APPCPU: u1,
+                ///  configure dreset configure
+                RTC_DRESET_MASK_PROCPU: u1,
+                padding: u6,
+            }),
+            ///  rtc configure register
+            WAKEUP_STATE: mmio.Mmio(packed struct(u32) {
+                reserved15: u15,
+                ///  wakeup enable bitmap
+                RTC_WAKEUP_ENA: u17,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC: mmio.Mmio(packed struct(u32) {
+                ///  enable sleep wakeup interrupt
+                SLP_WAKEUP_INT_ENA: u1,
+                ///  enable sleep reject interrupt
+                SLP_REJECT_INT_ENA: u1,
+                reserved3: u1,
+                ///  enable RTC WDT interrupt
+                RTC_WDT_INT_ENA: u1,
+                reserved9: u5,
+                ///  enable brown out interrupt
+                RTC_BROWN_OUT_INT_ENA: u1,
+                ///  enable RTC main timer interrupt
+                RTC_MAIN_TIMER_INT_ENA: u1,
+                reserved15: u4,
+                ///  enable super watch dog interrupt
+                RTC_SWD_INT_ENA: u1,
+                ///  enable xtal32k_dead interrupt
+                RTC_XTAL32K_DEAD_INT_ENA: u1,
+                reserved19: u2,
+                ///  enbale gitch det interrupt
+                RTC_GLITCH_DET_INT_ENA: u1,
+                ///  enbale bbpll cal end interrupt
+                RTC_BBPLL_CAL_INT_ENA: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_RAW_RTC: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup interrupt raw
+                SLP_WAKEUP_INT_RAW: u1,
+                ///  sleep reject interrupt raw
+                SLP_REJECT_INT_RAW: u1,
+                reserved3: u1,
+                ///  RTC WDT interrupt raw
+                RTC_WDT_INT_RAW: u1,
+                reserved9: u5,
+                ///  brown out interrupt raw
+                RTC_BROWN_OUT_INT_RAW: u1,
+                ///  RTC main timer interrupt raw
+                RTC_MAIN_TIMER_INT_RAW: u1,
+                reserved15: u4,
+                ///  super watch dog interrupt raw
+                RTC_SWD_INT_RAW: u1,
+                ///  xtal32k dead detection interrupt raw
+                RTC_XTAL32K_DEAD_INT_RAW: u1,
+                reserved19: u2,
+                ///  glitch_det_interrupt_raw
+                RTC_GLITCH_DET_INT_RAW: u1,
+                ///  bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_RAW: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_ST_RTC: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup interrupt state
+                SLP_WAKEUP_INT_ST: u1,
+                ///  sleep reject interrupt state
+                SLP_REJECT_INT_ST: u1,
+                reserved3: u1,
+                ///  RTC WDT interrupt state
+                RTC_WDT_INT_ST: u1,
+                reserved9: u5,
+                ///  brown out interrupt state
+                RTC_BROWN_OUT_INT_ST: u1,
+                ///  RTC main timer interrupt state
+                RTC_MAIN_TIMER_INT_ST: u1,
+                reserved15: u4,
+                ///  super watch dog interrupt state
+                RTC_SWD_INT_ST: u1,
+                ///  xtal32k dead detection interrupt state
+                RTC_XTAL32K_DEAD_INT_ST: u1,
+                reserved19: u2,
+                ///  glitch_det_interrupt state
+                RTC_GLITCH_DET_INT_ST: u1,
+                ///  bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_ST: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_CLR_RTC: mmio.Mmio(packed struct(u32) {
+                ///  Clear sleep wakeup interrupt state
+                SLP_WAKEUP_INT_CLR: u1,
+                ///  Clear sleep reject interrupt state
+                SLP_REJECT_INT_CLR: u1,
+                reserved3: u1,
+                ///  Clear RTC WDT interrupt state
+                RTC_WDT_INT_CLR: u1,
+                reserved9: u5,
+                ///  Clear brown out interrupt state
+                RTC_BROWN_OUT_INT_CLR: u1,
+                ///  Clear RTC main timer interrupt state
+                RTC_MAIN_TIMER_INT_CLR: u1,
+                reserved15: u4,
+                ///  Clear super watch dog interrupt state
+                RTC_SWD_INT_CLR: u1,
+                ///  Clear RTC WDT interrupt state
+                RTC_XTAL32K_DEAD_INT_CLR: u1,
+                reserved19: u2,
+                ///  Clear glitch det interrupt state
+                RTC_GLITCH_DET_INT_CLR: u1,
+                ///  clear bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_CLR: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            STORE0: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH0: u32,
+            }),
+            ///  rtc configure register
+            STORE1: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH1: u32,
+            }),
+            ///  rtc configure register
+            STORE2: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH2: u32,
+            }),
+            ///  rtc configure register
+            STORE3: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH3: u32,
+            }),
+            ///  rtc configure register
+            EXT_XTL_CONF: mmio.Mmio(packed struct(u32) {
+                ///  xtal 32k watch dog enable
+                XTAL32K_WDT_EN: u1,
+                ///  xtal 32k watch dog clock force on
+                XTAL32K_WDT_CLK_FO: u1,
+                ///  xtal 32k watch dog sw reset
+                XTAL32K_WDT_RESET: u1,
+                ///  xtal 32k external xtal clock force on
+                XTAL32K_EXT_CLK_FO: u1,
+                ///  xtal 32k switch to back up clock when xtal is dead
+                XTAL32K_AUTO_BACKUP: u1,
+                ///  xtal 32k restart xtal when xtal is dead
+                XTAL32K_AUTO_RESTART: u1,
+                ///  xtal 32k switch back xtal when xtal is restarted
+                XTAL32K_AUTO_RETURN: u1,
+                ///  Xtal 32k xpd control by sw or fsm
+                XTAL32K_XPD_FORCE: u1,
+                ///  apply an internal clock to help xtal 32k to start
+                ENCKINIT_XTAL_32K: u1,
+                ///  0: single-end buffer 1: differential buffer
+                DBUF_XTAL_32K: u1,
+                ///  xtal_32k gm control
+                DGM_XTAL_32K: u3,
+                ///  DRES_XTAL_32K
+                DRES_XTAL_32K: u3,
+                ///  XPD_XTAL_32K
+                XPD_XTAL_32K: u1,
+                ///  DAC_XTAL_32K
+                DAC_XTAL_32K: u3,
+                ///  state of 32k_wdt
+                RTC_WDT_STATE: u3,
+                ///  XTAL_32K sel. 0: external XTAL_32K
+                RTC_XTAL32K_GPIO_SEL: u1,
+                reserved30: u6,
+                ///  0: power down XTAL at high level
+                XTL_EXT_CTR_LV: u1,
+                ///  enable gpio configure xtal power on
+                XTL_EXT_CTR_EN: u1,
+            }),
+            ///  rtc configure register
+            EXT_WAKEUP_CONF: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  enable filter for gpio wakeup event
+                GPIO_WAKEUP_FILTER: u1,
+            }),
+            ///  rtc configure register
+            SLP_REJECT_CONF: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  sleep reject enable
+                RTC_SLEEP_REJECT_ENA: u18,
+                ///  enable reject for light sleep
+                LIGHT_SLP_REJECT_EN: u1,
+                ///  enable reject for deep sleep
+                DEEP_SLP_REJECT_EN: u1,
+            }),
+            ///  rtc configure register
+            CPU_PERIOD_CONF: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  CPU sel option
+                RTC_CPUSEL_CONF: u1,
+                ///  CPU clk sel option
+                RTC_CPUPERIOD_SEL: u2,
+            }),
+            ///  rtc configure register
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  efuse_clk_force_gating
+                EFUSE_CLK_FORCE_GATING: u1,
+                ///  efuse_clk_force_nogating
+                EFUSE_CLK_FORCE_NOGATING: u1,
+                ///  used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+                CK8M_DIV_SEL_VLD: u1,
+                ///  CK8M_D256_OUT divider. 00: div128
+                CK8M_DIV: u2,
+                ///  disable CK8M and CK8M_D256_OUT
+                ENB_CK8M: u1,
+                ///  1: CK8M_D256_OUT is actually CK8M
+                ENB_CK8M_DIV: u1,
+                ///  enable CK_XTAL_32K for digital core (no relationship with RTC core)
+                DIG_XTAL32K_EN: u1,
+                ///  enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+                DIG_CLK8M_D256_EN: u1,
+                ///  enable CK8M for digital core (no relationship with RTC core)
+                DIG_CLK8M_EN: u1,
+                reserved12: u1,
+                ///  divider = reg_ck8m_div_sel + 1
+                CK8M_DIV_SEL: u3,
+                ///  XTAL force no gating during sleep
+                XTAL_FORCE_NOGATING: u1,
+                ///  CK8M force no gating during sleep
+                CK8M_FORCE_NOGATING: u1,
+                ///  CK8M_DFREQ
+                CK8M_DFREQ: u8,
+                ///  CK8M force power down
+                CK8M_FORCE_PD: u1,
+                ///  CK8M force power up
+                CK8M_FORCE_PU: u1,
+                ///  force enable xtal clk gating
+                XTAL_GLOBAL_FORCE_GATING: u1,
+                ///  force bypass xtal clk gating
+                XTAL_GLOBAL_FORCE_NOGATING: u1,
+                ///  fast_clk_rtc sel. 0: XTAL div 4
+                FAST_CLK_RTC_SEL: u1,
+                ///  slelect rtc slow clk
+                ANA_CLK_RTC_SEL: u2,
+            }),
+            ///  rtc configure register
+            SLOW_CLK_CONF: mmio.Mmio(packed struct(u32) {
+                reserved22: u22,
+                ///  used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+                RTC_ANA_CLK_DIV_VLD: u1,
+                ///  the clk divider num of RTC_CLK
+                RTC_ANA_CLK_DIV: u8,
+                ///  flag rtc_slow_clk_next_edge
+                RTC_SLOW_CLK_NEXT_EDGE: u1,
+            }),
+            ///  rtc configure register
+            SDIO_CONF: mmio.Mmio(packed struct(u32) {
+                ///  timer count to apply reg_sdio_dcap after sdio power on
+                SDIO_TIMER_TARGET: u8,
+                reserved9: u1,
+                ///  Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+                SDIO_DTHDRV: u2,
+                ///  ability to prevent LDO from overshoot
+                SDIO_DCAP: u2,
+                ///  add resistor from ldo output to ground. 0: no res
+                SDIO_INITI: u2,
+                ///  0 to set init[1:0]=0
+                SDIO_EN_INITI: u1,
+                ///  tune current limit threshold when tieh = 0. About 800mA/(8+d)
+                SDIO_DCURLIM: u3,
+                ///  select current limit mode
+                SDIO_MODECURLIM: u1,
+                ///  enable current limit
+                SDIO_ENCURLIM: u1,
+                ///  power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+                SDIO_REG_PD_EN: u1,
+                ///  1: use SW option to control SDIO_REG
+                SDIO_FORCE: u1,
+                ///  SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+                SDIO_TIEH: u1,
+                ///  read only register for REG1P8_READY
+                _1P8_READY: u1,
+                ///  SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+                DREFL_SDIO: u2,
+                ///  SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+                DREFM_SDIO: u2,
+                ///  SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+                DREFH_SDIO: u2,
+                XPD_SDIO: u1,
+            }),
+            ///  rtc configure register
+            BIAS_CONF: mmio.Mmio(packed struct(u32) {
+                DG_VDD_DRV_B_SLP: u8,
+                DG_VDD_DRV_B_SLP_EN: u1,
+                reserved10: u1,
+                ///  bias buf when rtc in normal work state
+                BIAS_BUF_IDLE: u1,
+                ///  bias buf when rtc in wakeup state
+                BIAS_BUF_WAKE: u1,
+                ///  bias buf when rtc in sleep state
+                BIAS_BUF_DEEP_SLP: u1,
+                ///  bias buf when rtc in monitor state
+                BIAS_BUF_MONITOR: u1,
+                ///  xpd cur when rtc in sleep_state
+                PD_CUR_DEEP_SLP: u1,
+                ///  xpd cur when rtc in monitor state
+                PD_CUR_MONITOR: u1,
+                ///  bias_sleep when rtc in sleep_state
+                BIAS_SLEEP_DEEP_SLP: u1,
+                ///  bias_sleep when rtc in monitor state
+                BIAS_SLEEP_MONITOR: u1,
+                ///  DBG_ATTEN when rtc in sleep state
+                DBG_ATTEN_DEEP_SLP: u4,
+                ///  DBG_ATTEN when rtc in monitor state
+                DBG_ATTEN_MONITOR: u4,
+                padding: u6,
+            }),
+            ///  rtc configure register
+            RTC_CNTL: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  software enable digital regulator cali
+                DIG_REG_CAL_EN: u1,
+                reserved14: u6,
+                ///  SCK_DCAP
+                SCK_DCAP: u8,
+                reserved28: u6,
+                ///  RTC_DBOOST force power down
+                DBOOST_FORCE_PD: u1,
+                ///  RTC_DBOOST force power up
+                DBOOST_FORCE_PU: u1,
+                ///  RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
+                REGULATOR_FORCE_PD: u1,
+                ///  RTC_REG force power up
+                REGULATOR_FORCE_PU: u1,
+            }),
+            ///  rtc configure register
+            PWC: mmio.Mmio(packed struct(u32) {
+                reserved21: u21,
+                ///  rtc pad force hold
+                RTC_PAD_FORCE_HOLD: u1,
+                padding: u10,
+            }),
+            ///  rtc configure register
+            DIG_PWC: mmio.Mmio(packed struct(u32) {
+                ///  vdd_spi drv's software value
+                VDD_SPI_PWR_DRV: u2,
+                ///  vdd_spi drv use software value
+                VDD_SPI_PWR_FORCE: u1,
+                ///  memories in digital core force PD in sleep
+                LSLP_MEM_FORCE_PD: u1,
+                ///  memories in digital core force PU in sleep
+                LSLP_MEM_FORCE_PU: u1,
+                reserved11: u6,
+                ///  bt force power down
+                BT_FORCE_PD: u1,
+                ///  bt force power up
+                BT_FORCE_PU: u1,
+                ///  digital peri force power down
+                DG_PERI_FORCE_PD: u1,
+                ///  digital peri force power up
+                DG_PERI_FORCE_PU: u1,
+                ///  fastmemory retention mode in sleep
+                RTC_FASTMEM_FORCE_LPD: u1,
+                ///  fastmemory donlt entry retention mode in sleep
+                RTC_FASTMEM_FORCE_LPU: u1,
+                ///  wifi force power down
+                WIFI_FORCE_PD: u1,
+                ///  wifi force power up
+                WIFI_FORCE_PU: u1,
+                ///  digital core force power down
+                DG_WRAP_FORCE_PD: u1,
+                ///  digital core force power up
+                DG_WRAP_FORCE_PU: u1,
+                ///  cpu core force power down
+                CPU_TOP_FORCE_PD: u1,
+                ///  cpu force power up
+                CPU_TOP_FORCE_PU: u1,
+                reserved27: u4,
+                ///  enable power down bt in sleep
+                BT_PD_EN: u1,
+                ///  enable power down digital peri in sleep
+                DG_PERI_PD_EN: u1,
+                ///  enable power down cpu in sleep
+                CPU_TOP_PD_EN: u1,
+                ///  enable power down wifi in sleep
+                WIFI_PD_EN: u1,
+                ///  enable power down digital wrap in sleep
+                DG_WRAP_PD_EN: u1,
+            }),
+            ///  rtc configure register
+            DIG_ISO: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  DIG_ISO force off
+                FORCE_OFF: u1,
+                ///  DIG_ISO force on
+                FORCE_ON: u1,
+                ///  read only register to indicate digital pad auto-hold status
+                DG_PAD_AUTOHOLD: u1,
+                ///  wtite only register to clear digital pad auto-hold
+                CLR_DG_PAD_AUTOHOLD: u1,
+                ///  digital pad enable auto-hold
+                DG_PAD_AUTOHOLD_EN: u1,
+                ///  digital pad force no ISO
+                DG_PAD_FORCE_NOISO: u1,
+                ///  digital pad force ISO
+                DG_PAD_FORCE_ISO: u1,
+                ///  digital pad force un-hold
+                DG_PAD_FORCE_UNHOLD: u1,
+                ///  digital pad force hold
+                DG_PAD_FORCE_HOLD: u1,
+                reserved22: u6,
+                ///  bt force ISO
+                BT_FORCE_ISO: u1,
+                ///  bt force no ISO
+                BT_FORCE_NOISO: u1,
+                ///  Digital peri force ISO
+                DG_PERI_FORCE_ISO: u1,
+                ///  digital peri force no ISO
+                DG_PERI_FORCE_NOISO: u1,
+                ///  cpu force ISO
+                CPU_TOP_FORCE_ISO: u1,
+                ///  cpu force no ISO
+                CPU_TOP_FORCE_NOISO: u1,
+                ///  wifi force ISO
+                WIFI_FORCE_ISO: u1,
+                ///  wifi force no ISO
+                WIFI_FORCE_NOISO: u1,
+                ///  digital core force ISO
+                DG_WRAP_FORCE_ISO: u1,
+                ///  digital core force no ISO
+                DG_WRAP_FORCE_NOISO: u1,
+            }),
+            ///  rtc configure register
+            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
+                ///  chip reset siginal pulse width
+                WDT_CHIP_RESET_WIDTH: u8,
+                ///  wdt reset whole chip enable
+                WDT_CHIP_RESET_EN: u1,
+                ///  pause WDT in sleep
+                WDT_PAUSE_IN_SLP: u1,
+                ///  enable WDT reset APP CPU
+                WDT_APPCPU_RESET_EN: u1,
+                ///  enable WDT reset PRO CPU
+                WDT_PROCPU_RESET_EN: u1,
+                ///  enable WDT in flash boot
+                WDT_FLASHBOOT_MOD_EN: u1,
+                ///  system reset counter length
+                WDT_SYS_RESET_LENGTH: u3,
+                ///  CPU reset counter length
+                WDT_CPU_RESET_LENGTH: u3,
+                ///  1: interrupt stage en
+                WDT_STG3: u3,
+                ///  1: interrupt stage en
+                WDT_STG2: u3,
+                ///  1: interrupt stage en
+                WDT_STG1: u3,
+                ///  1: interrupt stage en
+                WDT_STG0: u3,
+                ///  enable rtc wdt
+                WDT_EN: u1,
+            }),
+            ///  rtc configure register
+            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage0
+                WDT_STG0_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage1
+                WDT_STG1_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage2
+                WDT_STG2_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage3
+                WDT_STG3_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTFEED: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  sw feed rtc wdt
+                RTC_WDT_FEED: u1,
+            }),
+            ///  rtc configure register
+            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  the key of rtc wdt
+                WDT_WKEY: u32,
+            }),
+            ///  rtc configure register
+            SWD_CONF: mmio.Mmio(packed struct(u32) {
+                ///  swd reset flag
+                SWD_RESET_FLAG: u1,
+                ///  swd interrupt for feeding
+                SWD_FEED_INT: u1,
+                reserved17: u15,
+                ///  Bypass swd rst
+                SWD_BYPASS_RST: u1,
+                ///  adjust signal width send to swd
+                SWD_SIGNAL_WIDTH: u10,
+                ///  reset swd reset flag
+                SWD_RST_FLAG_CLR: u1,
+                ///  Sw feed swd
+                SWD_FEED: u1,
+                ///  disabel SWD
+                SWD_DISABLE: u1,
+                ///  automatically feed swd when int comes
+                SWD_AUTO_FEED_EN: u1,
+            }),
+            ///  rtc configure register
+            SWD_WPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  the key of super wdt
+                SWD_WKEY: u32,
+            }),
+            ///  rtc configure register
+            SW_CPU_STALL: mmio.Mmio(packed struct(u32) {
+                reserved20: u20,
+                ///  {reg_sw_stall_appcpu_c1[5:0]
+                SW_STALL_APPCPU_C1: u6,
+                ///  stall cpu by software
+                SW_STALL_PROCPU_C1: u6,
+            }),
+            ///  rtc configure register
+            STORE4: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH4: u32,
+            }),
+            ///  rtc configure register
+            STORE5: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH5: u32,
+            }),
+            ///  rtc configure register
+            STORE6: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH6: u32,
+            }),
+            ///  rtc configure register
+            STORE7: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH7: u32,
+            }),
+            ///  rtc configure register
+            LOW_POWER_ST: mmio.Mmio(packed struct(u32) {
+                ///  rom0 power down
+                XPD_ROM0: u1,
+                reserved2: u1,
+                ///  External DCDC power down
+                XPD_DIG_DCDC: u1,
+                ///  rtc peripheral iso
+                RTC_PERI_ISO: u1,
+                ///  rtc peripheral power down
+                XPD_RTC_PERI: u1,
+                ///  wifi iso
+                WIFI_ISO: u1,
+                ///  wifi wrap power down
+                XPD_WIFI: u1,
+                ///  digital wrap iso
+                DIG_ISO: u1,
+                ///  digital wrap power down
+                XPD_DIG: u1,
+                ///  touch should start to work
+                RTC_TOUCH_STATE_START: u1,
+                ///  touch is about to working. Switch rtc main state
+                RTC_TOUCH_STATE_SWITCH: u1,
+                ///  touch is in sleep state
+                RTC_TOUCH_STATE_SLP: u1,
+                ///  touch is done
+                RTC_TOUCH_STATE_DONE: u1,
+                ///  ulp/cocpu should start to work
+                RTC_COCPU_STATE_START: u1,
+                ///  ulp/cocpu is about to working. Switch rtc main state
+                RTC_COCPU_STATE_SWITCH: u1,
+                ///  ulp/cocpu is in sleep state
+                RTC_COCPU_STATE_SLP: u1,
+                ///  ulp/cocpu is done
+                RTC_COCPU_STATE_DONE: u1,
+                ///  no use any more
+                RTC_MAIN_STATE_XTAL_ISO: u1,
+                ///  rtc main state machine is in states that pll should be running
+                RTC_MAIN_STATE_PLL_ON: u1,
+                ///  rtc is ready to receive wake up trigger from wake up source
+                RTC_RDY_FOR_WAKEUP: u1,
+                ///  rtc main state machine has been waited for some cycles
+                RTC_MAIN_STATE_WAIT_END: u1,
+                ///  rtc main state machine is in the states of wakeup process
+                RTC_IN_WAKEUP_STATE: u1,
+                ///  rtc main state machine is in the states of low power
+                RTC_IN_LOW_POWER_STATE: u1,
+                ///  rtc main state machine is in wait 8m state
+                RTC_MAIN_STATE_IN_WAIT_8M: u1,
+                ///  rtc main state machine is in wait pll state
+                RTC_MAIN_STATE_IN_WAIT_PLL: u1,
+                ///  rtc main state machine is in wait xtal state
+                RTC_MAIN_STATE_IN_WAIT_XTL: u1,
+                ///  rtc main state machine is in sleep state
+                RTC_MAIN_STATE_IN_SLP: u1,
+                ///  rtc main state machine is in idle state
+                RTC_MAIN_STATE_IN_IDLE: u1,
+                ///  rtc main state machine status
+                RTC_MAIN_STATE: u4,
+            }),
+            ///  rtc configure register
+            DIAG0: mmio.Mmio(packed struct(u32) {
+                RTC_LOW_POWER_DIAG1: u32,
+            }),
+            ///  rtc configure register
+            PAD_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  the hold configure of rtc gpio0
+                RTC_GPIO_PIN0_HOLD: u1,
+                ///  the hold configure of rtc gpio1
+                RTC_GPIO_PIN1_HOLD: u1,
+                ///  the hold configure of rtc gpio2
+                RTC_GPIO_PIN2_HOLD: u1,
+                ///  the hold configure of rtc gpio3
+                RTC_GPIO_PIN3_HOLD: u1,
+                ///  the hold configure of rtc gpio4
+                RTC_GPIO_PIN4_HOLD: u1,
+                ///  the hold configure of rtc gpio5
+                RTC_GPIO_PIN5_HOLD: u1,
+                padding: u26,
+            }),
+            ///  rtc configure register
+            DIG_PAD_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  the configure of digital pad
+                DIG_PAD_HOLD: u32,
+            }),
+            ///  rtc configure register
+            BROWN_OUT: mmio.Mmio(packed struct(u32) {
+                reserved4: u4,
+                ///  brown out interrupt wait cycles
+                INT_WAIT: u10,
+                ///  enable close flash when brown out happens
+                CLOSE_FLASH_ENA: u1,
+                ///  enable power down RF when brown out happens
+                PD_RF_ENA: u1,
+                ///  brown out reset wait cycles
+                RST_WAIT: u10,
+                ///  enable brown out reset
+                RST_ENA: u1,
+                ///  1: 4-pos reset
+                RST_SEL: u1,
+                ///  brown_out origin reset enable
+                ANA_RST_EN: u1,
+                ///  clear brown out counter
+                CNT_CLR: u1,
+                ///  enable brown out
+                ENA: u1,
+                ///  the flag of brown det from analog
+                DET: u1,
+            }),
+            ///  rtc configure register
+            TIME_LOW1: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer low 32 bits
+                RTC_TIMER_VALUE1_LOW: u32,
+            }),
+            ///  rtc configure register
+            TIME_HIGH1: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer high 16 bits
+                RTC_TIMER_VALUE1_HIGH: u16,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            XTAL32K_CLK_FACTOR: mmio.Mmio(packed struct(u32) {
+                ///  xtal 32k watch dog backup clock factor
+                XTAL32K_CLK_FACTOR: u32,
+            }),
+            ///  rtc configure register
+            XTAL32K_CONF: mmio.Mmio(packed struct(u32) {
+                ///  cycles to wait to return noral xtal 32k
+                XTAL32K_RETURN_WAIT: u4,
+                ///  cycles to wait to repower on xtal 32k
+                XTAL32K_RESTART_WAIT: u16,
+                ///  If no clock detected for this amount of time
+                XTAL32K_WDT_TIMEOUT: u8,
+                ///  if restarted xtal32k period is smaller than this
+                XTAL32K_STABLE_THRES: u4,
+            }),
+            ///  rtc configure register
+            USB_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  disable io_mux reset
+                IO_MUX_RESET_DISABLE: u1,
+                padding: u13,
+            }),
+            ///  RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+            SLP_REJECT_CAUSE: mmio.Mmio(packed struct(u32) {
+                ///  sleep reject cause
+                REJECT_CAUSE: u18,
+                padding: u14,
+            }),
+            ///  rtc configure register
+            OPTION1: mmio.Mmio(packed struct(u32) {
+                ///  force chip entry download mode
+                FORCE_DOWNLOAD_BOOT: u1,
+                padding: u31,
+            }),
+            ///  RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+            SLP_WAKEUP_CAUSE: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup cause
+                WAKEUP_CAUSE: u17,
+                padding: u15,
+            }),
+            ///  rtc configure register
+            ULP_CP_TIMER_1: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  sleep cycles for ULP-coprocessor timer
+                ULP_CP_TIMER_SLP_CYCLE: u24,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  enable sleep wakeup interrupt
+                SLP_WAKEUP_INT_ENA_W1TS: u1,
+                ///  enable sleep reject interrupt
+                SLP_REJECT_INT_ENA_W1TS: u1,
+                reserved3: u1,
+                ///  enable RTC WDT interrupt
+                RTC_WDT_INT_ENA_W1TS: u1,
+                reserved9: u5,
+                ///  enable brown out interrupt
+                RTC_BROWN_OUT_INT_ENA_W1TS: u1,
+                ///  enable RTC main timer interrupt
+                RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
+                reserved15: u4,
+                ///  enable super watch dog interrupt
+                RTC_SWD_INT_ENA_W1TS: u1,
+                ///  enable xtal32k_dead interrupt
+                RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
+                reserved19: u2,
+                ///  enbale gitch det interrupt
+                RTC_GLITCH_DET_INT_ENA_W1TS: u1,
+                ///  enbale bbpll cal interrupt
+                RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  clear sleep wakeup interrupt enable
+                SLP_WAKEUP_INT_ENA_W1TC: u1,
+                ///  clear sleep reject interrupt enable
+                SLP_REJECT_INT_ENA_W1TC: u1,
+                reserved3: u1,
+                ///  clear RTC WDT interrupt enable
+                RTC_WDT_INT_ENA_W1TC: u1,
+                reserved9: u5,
+                ///  clear brown out interrupt enable
+                RTC_BROWN_OUT_INT_ENA_W1TC: u1,
+                ///  Clear RTC main timer interrupt enable
+                RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
+                reserved15: u4,
+                ///  clear super watch dog interrupt enable
+                RTC_SWD_INT_ENA_W1TC: u1,
+                ///  clear xtal32k_dead interrupt enable
+                RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
+                reserved19: u2,
+                ///  clear gitch det interrupt enable
+                RTC_GLITCH_DET_INT_ENA_W1TC: u1,
+                ///  clear bbpll cal interrupt enable
+                RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  Retention clk sel
+                RETENTION_CLK_SEL: u1,
+                ///  Retention done wait time
+                RETENTION_DONE_WAIT: u3,
+                ///  Retention clkoff wait time
+                RETENTION_CLKOFF_WAIT: u4,
+                ///  enable cpu retention when light sleep
+                RETENTION_EN: u1,
+                ///  wait cycles for rention operation
+                RETENTION_WAIT: u5,
+            }),
+            ///  rtc configure register
+            FIB_SEL: mmio.Mmio(packed struct(u32) {
+                ///  select use analog fib signal
+                RTC_FIB_SEL: u3,
+                padding: u29,
+            }),
+            ///  rtc configure register
+            GPIO_WAKEUP: mmio.Mmio(packed struct(u32) {
+                ///  rtc gpio wakeup flag
+                RTC_GPIO_WAKEUP_STATUS: u6,
+                ///  clear rtc gpio wakeup flag
+                RTC_GPIO_WAKEUP_STATUS_CLR: u1,
+                ///  enable rtc io clk gate
+                RTC_GPIO_PIN_CLK_GATE: u1,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN5_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN4_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN3_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN2_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN1_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN0_INT_TYPE: u3,
+                ///  enable wakeup from rtc gpio5
+                RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio4
+                RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio3
+                RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio2
+                RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio1
+                RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio0
+                RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
+            }),
+            ///  rtc configure register
+            DBG_SEL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  use for debug
+                RTC_DEBUG_12M_NO_GATING: u1,
+                ///  use for debug
+                RTC_DEBUG_BIT_SEL: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL0: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL1: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL2: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL3: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL4: u5,
+            }),
+            ///  rtc configure register
+            DBG_MAP: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  use for debug
+                RTC_GPIO_PIN5_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN4_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN3_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN2_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN1_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN0_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN5_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN4_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN3_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN2_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN1_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN0_FUN_SEL: u4,
+            }),
+            ///  rtc configure register
+            SENSOR_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  reg_sar2_pwdet_cct
+                SAR2_PWDET_CCT: u3,
+                ///  force power up SAR
+                FORCE_XPD_SAR: u2,
+            }),
+            ///  rtc configure register
+            DBG_SAR_SEL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  use for debug
+                SAR_DEBUG_SEL: u5,
+            }),
+            ///  rtc configure register
+            PG_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  power glitch desense
+                POWER_GLITCH_DSENSE: u2,
+                ///  force disable power glitch
+                POWER_GLITCH_FORCE_PD: u1,
+                ///  force enable power glitch
+                POWER_GLITCH_FORCE_PU: u1,
+                ///  use efuse value control power glitch enable
+                POWER_GLITCH_EFUSE_SEL: u1,
+                ///  enable power glitch
+                POWER_GLITCH_EN: u1,
+            }),
+            reserved508: [212]u8,
+            ///  rtc configure register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  verision
+                RTC_CNTL_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Sensitive
+        pub const SENSITIVE = extern struct {
+            ///  SENSITIVE_ROM_TABLE_LOCK_REG
+            ROM_TABLE_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  rom_table_lock
+                ROM_TABLE_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_ROM_TABLE_REG
+            ROM_TABLE: mmio.Mmio(packed struct(u32) {
+                ///  rom_table
+                ROM_TABLE: u32,
+            }),
+            ///  SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+            PRIVILEGE_MODE_SEL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  privilege_mode_sel_lock
+                PRIVILEGE_MODE_SEL_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_PRIVILEGE_MODE_SEL_REG
+            PRIVILEGE_MODE_SEL: mmio.Mmio(packed struct(u32) {
+                ///  privilege_mode_sel
+                PRIVILEGE_MODE_SEL: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+            APB_PERIPHERAL_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  apb_peripheral_access_lock
+                APB_PERIPHERAL_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+            APB_PERIPHERAL_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  apb_peripheral_access_split_burst
+                APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+            INTERNAL_SRAM_USAGE_0: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_lock
+                INTERNAL_SRAM_USAGE_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+            INTERNAL_SRAM_USAGE_1: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_cpu_cache
+                INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
+                ///  internal_sram_usage_cpu_sram
+                INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
+                padding: u28,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+            INTERNAL_SRAM_USAGE_3: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_mac_dump_sram
+                INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
+                ///  internal_sram_alloc_mac_dump
+                INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
+                padding: u28,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+            INTERNAL_SRAM_USAGE_4: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_log_sram
+                INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_TAG_ACCESS_0_REG
+            CACHE_TAG_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  cache_tag_access_lock
+                CACHE_TAG_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_TAG_ACCESS_1_REG
+            CACHE_TAG_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  pro_i_tag_rd_acs
+                PRO_I_TAG_RD_ACS: u1,
+                ///  pro_i_tag_wr_acs
+                PRO_I_TAG_WR_ACS: u1,
+                ///  pro_d_tag_rd_acs
+                PRO_D_TAG_RD_ACS: u1,
+                ///  pro_d_tag_wr_acs
+                PRO_D_TAG_WR_ACS: u1,
+                padding: u28,
+            }),
+            ///  SENSITIVE_CACHE_MMU_ACCESS_0_REG
+            CACHE_MMU_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  cache_mmu_access_lock
+                CACHE_MMU_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_MMU_ACCESS_1_REG
+            CACHE_MMU_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  pro_mmu_rd_acs
+                PRO_MMU_RD_ACS: u1,
+                ///  pro_mmu_wr_acs
+                PRO_MMU_WR_ACS: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_spi2_pms_constrain_lock
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_uchi0_pms_constrain_lock
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_i2s0_pms_constrain_lock
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_mac_pms_constrain_lock
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_backup_pms_constrain_lock
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_LC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_lc_pms_constrain_lock
+                DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_LC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_AES_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_aes_pms_constrain_lock
+                DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_AES_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_sha_pms_constrain_lock
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_adc_dac_pms_constrain_lock
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+            DMA_APBPERI_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_lock
+                DMA_APBPERI_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+            DMA_APBPERI_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_clr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  dma_apbperi_pms_monitor_violate_en
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+            DMA_APBPERI_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_intr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  dma_apbperi_pms_monitor_violate_status_world
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  dma_apbperi_pms_monitor_violate_status_addr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u5,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+            DMA_APBPERI_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_status_wr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  dma_apbperi_pms_monitor_violate_status_byteen
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_dram0_dma_split_line_constrain_lock
+                CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_dram0_dma_sram_category_0
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
+                ///  core_x_iram0_dram0_dma_sram_category_1
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
+                ///  core_x_iram0_dram0_dma_sram_category_2
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_dram0_dma_sram_splitaddr
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_sram_line_0_category_0
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
+                ///  core_x_iram0_sram_line_0_category_1
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
+                ///  core_x_iram0_sram_line_0_category_2
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_sram_line_0_splitaddr
+                CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_sram_line_1_category_0
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
+                ///  core_x_iram0_sram_line_1_category_1
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
+                ///  core_x_iram0_sram_line_1_category_2
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_sram_line_1_splitaddr
+                CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_dma_sram_line_0_category_0
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
+                ///  core_x_dram0_dma_sram_line_0_category_1
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
+                ///  core_x_dram0_dma_sram_line_0_category_2
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_dram0_dma_sram_line_0_splitaddr
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_dma_sram_line_1_category_0
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
+                ///  core_x_dram0_dma_sram_line_1_category_1
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
+                ///  core_x_dram0_dma_sram_line_1_category_2
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_dram0_dma_sram_line_1_splitaddr
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_lock
+                CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_1
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_2
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_3
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
+                reserved18: u3,
+                ///  core_x_iram0_pms_constrain_rom_world_1_pms
+                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
+                padding: u11,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_1
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_2
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_3
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
+                reserved18: u3,
+                ///  core_x_iram0_pms_constrain_rom_world_0_pms
+                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
+                padding: u11,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+            CORE_0_IRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_lock
+                CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+            CORE_0_IRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_violate_clr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_iram0_pms_monitor_violate_en
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+            CORE_0_IRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_violate_intr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_wr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_loadstore
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_world
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  core_0_iram0_pms_monitor_violate_status_addr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u3,
+            }),
+            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+            CORE_X_DRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_pms_constrain_lock
+                CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+            CORE_X_DRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_0
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_1
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_2
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_3
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_0
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_1
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_2
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_3
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                reserved24: u4,
+                ///  core_x_dram0_pms_constrain_rom_world_0_pms
+                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
+                ///  core_x_dram0_pms_constrain_rom_world_1_pms
+                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
+                padding: u4,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+            CORE_0_DRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_lock
+                CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+            CORE_0_DRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_clr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_dram0_pms_monitor_violate_en
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+            CORE_0_DRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_intr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_lock
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_world
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  core_0_dram0_pms_monitor_violate_status_addr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u4,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+            CORE_0_DRAM0_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_status_wr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_byteen
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+            CORE_0_PIF_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_lock
+                CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+            CORE_0_PIF_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_uart
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
+                ///  core_0_pif_pms_constrain_world_0_g0spi_1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
+                ///  core_0_pif_pms_constrain_world_0_g0spi_0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
+                ///  core_0_pif_pms_constrain_world_0_gpio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
+                ///  core_0_pif_pms_constrain_world_0_fe2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
+                ///  core_0_pif_pms_constrain_world_0_fe
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
+                ///  core_0_pif_pms_constrain_world_0_timer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
+                ///  core_0_pif_pms_constrain_world_0_rtc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
+                ///  core_0_pif_pms_constrain_world_0_io_mux
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
+                ///  core_0_pif_pms_constrain_world_0_wdg
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
+                reserved24: u4,
+                ///  core_0_pif_pms_constrain_world_0_misc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2c
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
+                reserved30: u2,
+                ///  core_0_pif_pms_constrain_world_0_uart1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+            CORE_0_PIF_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_bt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2c_ext0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
+                ///  core_0_pif_pms_constrain_world_0_uhci0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
+                reserved10: u2,
+                ///  core_0_pif_pms_constrain_world_0_rmt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
+                reserved16: u4,
+                ///  core_0_pif_pms_constrain_world_0_ledc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
+                reserved22: u4,
+                ///  core_0_pif_pms_constrain_world_0_bb
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_0_timergroup
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
+                ///  core_0_pif_pms_constrain_world_0_timergroup1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
+                ///  core_0_pif_pms_constrain_world_0_systimer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+            CORE_0_PIF_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_spi_2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_0_apb_ctrl
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
+                reserved10: u4,
+                ///  core_0_pif_pms_constrain_world_0_can
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
+                reserved14: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2s1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
+                reserved22: u6,
+                ///  core_0_pif_pms_constrain_world_0_rwbt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_0_wifimac
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
+                ///  core_0_pif_pms_constrain_world_0_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+            CORE_0_PIF_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  core_0_pif_pms_constrain_world_0_usb_wrap
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
+                ///  core_0_pif_pms_constrain_world_0_crypto_peri
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
+                ///  core_0_pif_pms_constrain_world_0_crypto_dma
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
+                ///  core_0_pif_pms_constrain_world_0_apb_adc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
+                reserved12: u2,
+                ///  core_0_pif_pms_constrain_world_0_bt_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
+                ///  core_0_pif_pms_constrain_world_0_usb_device
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
+                ///  core_0_pif_pms_constrain_world_0_system
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
+                ///  core_0_pif_pms_constrain_world_0_sensitive
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
+                ///  core_0_pif_pms_constrain_world_0_interrupt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
+                ///  core_0_pif_pms_constrain_world_0_dma_copy
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
+                ///  core_0_pif_pms_constrain_world_0_cache_config
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
+                ///  core_0_pif_pms_constrain_world_0_ad
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
+                ///  core_0_pif_pms_constrain_world_0_dio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
+                ///  core_0_pif_pms_constrain_world_0_world_controller
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+            CORE_0_PIF_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_uart
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
+                ///  core_0_pif_pms_constrain_world_1_g0spi_1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
+                ///  core_0_pif_pms_constrain_world_1_g0spi_0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
+                ///  core_0_pif_pms_constrain_world_1_gpio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
+                ///  core_0_pif_pms_constrain_world_1_fe2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
+                ///  core_0_pif_pms_constrain_world_1_fe
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
+                ///  core_0_pif_pms_constrain_world_1_timer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
+                ///  core_0_pif_pms_constrain_world_1_rtc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
+                ///  core_0_pif_pms_constrain_world_1_io_mux
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
+                ///  core_0_pif_pms_constrain_world_1_wdg
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
+                reserved24: u4,
+                ///  core_0_pif_pms_constrain_world_1_misc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2c
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
+                reserved30: u2,
+                ///  core_0_pif_pms_constrain_world_1_uart1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+            CORE_0_PIF_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_bt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2c_ext0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
+                ///  core_0_pif_pms_constrain_world_1_uhci0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
+                reserved10: u2,
+                ///  core_0_pif_pms_constrain_world_1_rmt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
+                reserved16: u4,
+                ///  core_0_pif_pms_constrain_world_1_ledc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
+                reserved22: u4,
+                ///  core_0_pif_pms_constrain_world_1_bb
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_1_timergroup
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
+                ///  core_0_pif_pms_constrain_world_1_timergroup1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
+                ///  core_0_pif_pms_constrain_world_1_systimer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+            CORE_0_PIF_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_spi_2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_1_apb_ctrl
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
+                reserved10: u4,
+                ///  core_0_pif_pms_constrain_world_1_can
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
+                reserved14: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2s1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
+                reserved22: u6,
+                ///  core_0_pif_pms_constrain_world_1_rwbt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_1_wifimac
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
+                ///  core_0_pif_pms_constrain_world_1_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+            CORE_0_PIF_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  core_0_pif_pms_constrain_world_1_usb_wrap
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
+                ///  core_0_pif_pms_constrain_world_1_crypto_peri
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
+                ///  core_0_pif_pms_constrain_world_1_crypto_dma
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
+                ///  core_0_pif_pms_constrain_world_1_apb_adc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
+                reserved12: u2,
+                ///  core_0_pif_pms_constrain_world_1_bt_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
+                ///  core_0_pif_pms_constrain_world_1_usb_device
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
+                ///  core_0_pif_pms_constrain_world_1_system
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
+                ///  core_0_pif_pms_constrain_world_1_sensitive
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
+                ///  core_0_pif_pms_constrain_world_1_interrupt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
+                ///  core_0_pif_pms_constrain_world_1_dma_copy
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
+                ///  core_0_pif_pms_constrain_world_1_cache_config
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
+                ///  core_0_pif_pms_constrain_world_1_ad
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
+                ///  core_0_pif_pms_constrain_world_1_dio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
+                ///  core_0_pif_pms_constrain_world_1_world_controller
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+            CORE_0_PIF_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
+                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+            CORE_0_PIF_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_rtcfast_world_0_l
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_0_h
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_1_l
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_1_h
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
+                padding: u20,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+            REGION_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_lock
+                REGION_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+            REGION_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_world_0_area_0
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
+                ///  region_pms_constrain_world_0_area_1
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
+                ///  region_pms_constrain_world_0_area_2
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
+                ///  region_pms_constrain_world_0_area_3
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
+                ///  region_pms_constrain_world_0_area_4
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
+                ///  region_pms_constrain_world_0_area_5
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
+                ///  region_pms_constrain_world_0_area_6
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
+                padding: u18,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+            REGION_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_world_1_area_0
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
+                ///  region_pms_constrain_world_1_area_1
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
+                ///  region_pms_constrain_world_1_area_2
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
+                ///  region_pms_constrain_world_1_area_3
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
+                ///  region_pms_constrain_world_1_area_4
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
+                ///  region_pms_constrain_world_1_area_5
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
+                ///  region_pms_constrain_world_1_area_6
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
+                padding: u18,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+            REGION_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_0
+                REGION_PMS_CONSTRAIN_ADDR_0: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+            REGION_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_1
+                REGION_PMS_CONSTRAIN_ADDR_1: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+            REGION_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_2
+                REGION_PMS_CONSTRAIN_ADDR_2: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+            REGION_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_3
+                REGION_PMS_CONSTRAIN_ADDR_3: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+            REGION_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_4
+                REGION_PMS_CONSTRAIN_ADDR_4: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+            REGION_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_5
+                REGION_PMS_CONSTRAIN_ADDR_5: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+            REGION_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_6
+                REGION_PMS_CONSTRAIN_ADDR_6: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+            REGION_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_7
+                REGION_PMS_CONSTRAIN_ADDR_7: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+            CORE_0_PIF_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_lock
+                CORE_0_PIF_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+            CORE_0_PIF_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_clr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_pif_pms_monitor_violate_en
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+            CORE_0_PIF_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_intr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hport_0
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hsize
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+                ///  core_0_pif_pms_monitor_violate_status_hwrite
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hworld
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
+                padding: u24,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+            CORE_0_PIF_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_status_haddr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+            CORE_0_PIF_PMS_MONITOR_4: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_clr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
+                ///  core_0_pif_pms_monitor_nonword_violate_en
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+            CORE_0_PIF_PMS_MONITOR_5: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_intr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
+                ///  core_0_pif_pms_monitor_nonword_violate_status_hsize
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
+                ///  core_0_pif_pms_monitor_nonword_violate_status_hworld
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+            CORE_0_PIF_PMS_MONITOR_6: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_status_haddr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+            BACKUP_BUS_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_lock
+                BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+            BACKUP_BUS_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_uart
+                BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
+                ///  backup_bus_pms_constrain_g0spi_1
+                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
+                ///  backup_bus_pms_constrain_g0spi_0
+                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
+                ///  backup_bus_pms_constrain_gpio
+                BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
+                ///  backup_bus_pms_constrain_fe2
+                BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
+                ///  backup_bus_pms_constrain_fe
+                BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
+                ///  backup_bus_pms_constrain_timer
+                BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
+                ///  backup_bus_pms_constrain_rtc
+                BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
+                ///  backup_bus_pms_constrain_io_mux
+                BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
+                ///  backup_bus_pms_constrain_wdg
+                BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
+                reserved24: u4,
+                ///  backup_bus_pms_constrain_misc
+                BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
+                ///  backup_bus_pms_constrain_i2c
+                BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
+                reserved30: u2,
+                ///  backup_bus_pms_constrain_uart1
+                BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+            BACKUP_BUS_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_bt
+                BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
+                reserved4: u2,
+                ///  backup_bus_pms_constrain_i2c_ext0
+                BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
+                ///  backup_bus_pms_constrain_uhci0
+                BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
+                reserved10: u2,
+                ///  backup_bus_pms_constrain_rmt
+                BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
+                reserved16: u4,
+                ///  backup_bus_pms_constrain_ledc
+                BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
+                reserved22: u4,
+                ///  backup_bus_pms_constrain_bb
+                BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
+                reserved26: u2,
+                ///  backup_bus_pms_constrain_timergroup
+                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
+                ///  backup_bus_pms_constrain_timergroup1
+                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
+                ///  backup_bus_pms_constrain_systimer
+                BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+            BACKUP_BUS_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_spi_2
+                BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
+                reserved4: u2,
+                ///  backup_bus_pms_constrain_apb_ctrl
+                BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
+                reserved10: u4,
+                ///  backup_bus_pms_constrain_can
+                BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
+                reserved14: u2,
+                ///  backup_bus_pms_constrain_i2s1
+                BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
+                reserved22: u6,
+                ///  backup_bus_pms_constrain_rwbt
+                BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
+                reserved26: u2,
+                ///  backup_bus_pms_constrain_wifimac
+                BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
+                ///  backup_bus_pms_constrain_pwr
+                BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+            BACKUP_BUS_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  backup_bus_pms_constrain_usb_wrap
+                BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
+                ///  backup_bus_pms_constrain_crypto_peri
+                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
+                ///  backup_bus_pms_constrain_crypto_dma
+                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
+                ///  backup_bus_pms_constrain_apb_adc
+                BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
+                reserved12: u2,
+                ///  backup_bus_pms_constrain_bt_pwr
+                BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
+                ///  backup_bus_pms_constrain_usb_device
+                BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
+                padding: u16,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+            BACKUP_BUS_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_lock
+                BACKUP_BUS_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+            BACKUP_BUS_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_clr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  backup_bus_pms_monitor_violate_en
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+            BACKUP_BUS_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_intr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  backup_bus_pms_monitor_violate_status_htrans
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
+                ///  backup_bus_pms_monitor_violate_status_hsize
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+                ///  backup_bus_pms_monitor_violate_status_hwrite
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+                padding: u25,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+            BACKUP_BUS_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_haddr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
+            }),
+            ///  SENSITIVE_CLOCK_GATE_REG
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  clk_en
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved4092: [3720]u8,
+            ///  SENSITIVE_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SHA (Secure Hash Algorithm) Accelerator
+        pub const SHA = extern struct {
+            ///  Initial configuration register.
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Sha mode.
+                MODE: u3,
+                padding: u29,
+            }),
+            ///  SHA 512/t configuration register 0.
+            T_STRING: mmio.Mmio(packed struct(u32) {
+                ///  Sha t_string (used if and only if mode == SHA_512/t).
+                T_STRING: u32,
+            }),
+            ///  SHA 512/t configuration register 1.
+            T_LENGTH: mmio.Mmio(packed struct(u32) {
+                ///  Sha t_length (used if and only if mode == SHA_512/t).
+                T_LENGTH: u6,
+                padding: u26,
+            }),
+            ///  DMA configuration register 0.
+            DMA_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Dma-sha block number.
+                DMA_BLOCK_NUM: u6,
+                padding: u26,
+            }),
+            ///  Typical SHA configuration register 0.
+            START: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Reserved.
+                START: u31,
+            }),
+            ///  Typical SHA configuration register 1.
+            CONTINUE: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Reserved.
+                CONTINUE: u31,
+            }),
+            ///  Busy register.
+            BUSY: mmio.Mmio(packed struct(u32) {
+                ///  Sha busy state. 1'b0: idle. 1'b1: busy.
+                STATE: u1,
+                padding: u31,
+            }),
+            ///  DMA configuration register 1.
+            DMA_START: mmio.Mmio(packed struct(u32) {
+                ///  Start dma-sha.
+                DMA_START: u1,
+                padding: u31,
+            }),
+            ///  DMA configuration register 2.
+            DMA_CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  Continue dma-sha.
+                DMA_CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  Interrupt clear register.
+            CLEAR_IRQ: mmio.Mmio(packed struct(u32) {
+                ///  Clear sha interrupt.
+                CLEAR_INTERRUPT: u1,
+                padding: u31,
+            }),
+            ///  Interrupt enable register.
+            IRQ_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+                INTERRUPT_ENA: u1,
+                padding: u31,
+            }),
+            ///  Date register.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Sha date information/ sha version information.
+                DATE: u30,
+                padding: u2,
+            }),
+            reserved64: [16]u8,
+            ///  Sha H memory which contains intermediate hash or finial hash.
+            H_MEM: [64]u8,
+            ///  Sha M memory which contains message.
+            M_MEM: [64]u8,
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI0 = extern struct {
+            reserved8: [8]u8,
+            ///  SPI0 control register.
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller.
+                FDUMMY_OUT: u1,
+                reserved7: u3,
+                ///  Apply 2 signals during command phase 1:enable 0: disable
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable
+                FCMD_QUAD: u1,
+                reserved13: u4,
+                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+                FASTRD_MODE: u1,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DUAL: u1,
+                reserved18: u3,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low
+                D_POL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QUAD: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
+                WP: u1,
+                reserved23: u1,
+                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DIO: u1,
+                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QIO: u1,
+                padding: u7,
+            }),
+            ///  SPI0 control1 register.
+            CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+                CLK_MODE: u2,
+                reserved30: u28,
+                ///  SPI0 RX FIFO reset signal.
+                RXFIFO_RST: u1,
+                padding: u1,
+            }),
+            ///  SPI0 control2 register.
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
+                CS_SETUP_TIME: u5,
+                ///  Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
+                CS_HOLD_TIME: u5,
+                reserved25: u15,
+                ///  These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
+                CS_HOLD_DELAY: u6,
+                ///  The FSM will be reset.
+                SYNC_RESET: u1,
+            }),
+            ///  SPI clock division control register.
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
+                CLKCNT_L: u8,
+                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+                CLKCNT_H: u8,
+                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+                CLKCNT_N: u8,
+                reserved31: u7,
+                ///  Set this bit in 1-division mode.
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI0 user register.
+            USER: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable.
+                CS_HOLD: u1,
+                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
+                CS_SETUP: u1,
+                reserved9: u1,
+                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+                CK_OUT_EDGE: u1,
+                reserved26: u16,
+                ///  spi clock is disable in dummy phase when the bit is enable.
+                USR_DUMMY_IDLE: u1,
+                reserved29: u2,
+                ///  This bit enable the dummy phase of an operation.
+                USR_DUMMY: u1,
+                padding: u2,
+            }),
+            ///  SPI0 user1 register.
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+                USR_DUMMY_CYCLELEN: u6,
+                reserved26: u20,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1).
+                USR_ADDR_BITLEN: u6,
+            }),
+            ///  SPI0 user2 register.
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command.
+                USR_COMMAND_VALUE: u16,
+                reserved28: u12,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1)
+                USR_COMMAND_BITLEN: u4,
+            }),
+            reserved44: [8]u8,
+            ///  SPI0 read control register.
+            RD_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
+                WB_MODE: u8,
+                padding: u8,
+            }),
+            reserved52: [4]u8,
+            ///  SPI0 misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  The bit is used to indicate the spi0_mst_st controlled transmitting is done.
+                TRANS_END: u1,
+                ///  The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
+                TRANS_END_INT_ENA: u1,
+                ///  The bit is used to indicate the spi0_slv_st controlled transmitting is done.
+                CSPI_ST_TRANS_END: u1,
+                ///  The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
+                CSPI_ST_TRANS_END_INT_ENA: u1,
+                reserved9: u2,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set.
+                CS_KEEP_ACTIVE: u1,
+                padding: u21,
+            }),
+            reserved60: [4]u8,
+            ///  SPI0 bit mode control register.
+            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
+                ///  For SPI0, Cache access enable, 1: enable, 0:disable.
+                CACHE_REQ_EN: u1,
+                ///  For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
+                CACHE_USR_ADDR_4BYTE: u1,
+                ///  For SPI0, cache read flash for user define command, 1: enable, 0:disable.
+                CACHE_FLASH_USR_CMD: u1,
+                ///  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDIN_DUAL: u1,
+                ///  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDOUT_DUAL: u1,
+                ///  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FADDR_DUAL: u1,
+                ///  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDIN_QUAD: u1,
+                ///  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDOUT_QUAD: u1,
+                ///  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FADDR_QUAD: u1,
+                padding: u23,
+            }),
+            reserved84: [20]u8,
+            ///  SPI0 FSM status register
+            FSM: mmio.Mmio(packed struct(u32) {
+                ///  The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+                CSPI_ST: u4,
+                ///  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+                EM_ST: u3,
+                ///  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+                CSPI_LOCK_DELAY_TIME: u5,
+                padding: u20,
+            }),
+            reserved168: [80]u8,
+            ///  SPI0 timing calibration register
+            TIMING_CALI: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable timing adjust clock for all reading operations.
+                TIMING_CLK_ENA: u1,
+                ///  The bit is used to enable timing auto-calibration for all reading operations.
+                TIMING_CALI: u1,
+                ///  add extra dummy spi clock cycle length for spi clock calibration.
+                EXTRA_DUMMY_CYCLELEN: u3,
+                padding: u27,
+            }),
+            ///  SPI0 input delay mode control register
+            DIN_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN0_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN1_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN2_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN3_MODE: u2,
+                padding: u24,
+            }),
+            ///  SPI0 input delay number control register
+            DIN_NUM: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN0_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN1_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN2_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN3_NUM: u2,
+                padding: u24,
+            }),
+            ///  SPI0 output delay mode control register
+            DOUT_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT0_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT1_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT2_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT3_MODE: u1,
+                padding: u28,
+            }),
+            reserved220: [36]u8,
+            ///  SPI0 clk_gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  SPI0 module clock select register
+            CORE_CLK_SEL: mmio.Mmio(packed struct(u32) {
+                ///  When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
+                SPI01_CLK_SEL: u2,
+                padding: u30,
+            }),
+            reserved1020: [792]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  SPI register version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI1 = extern struct {
+            ///  SPI1 memory command register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  The current status of SPI1 master FSM.
+                SPI1_MST_ST: u4,
+                ///  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+                MSPI_ST: u4,
+                reserved17: u9,
+                ///  In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PE: u1,
+                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                USR: u1,
+                ///  Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_HPM: u1,
+                ///  This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_RES: u1,
+                ///  Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_DP: u1,
+                ///  Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_CE: u1,
+                ///  Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_BE: u1,
+                ///  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_SE: u1,
+                ///  Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
+                FLASH_PP: u1,
+                ///  Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_WRSR: u1,
+                ///  Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_RDSR: u1,
+                ///  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_RDID: u1,
+                ///  Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_WRDI: u1,
+                ///  Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_WREN: u1,
+                ///  Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_READ: u1,
+            }),
+            ///  SPI1 address register
+            ADDR: mmio.Mmio(packed struct(u32) {
+                ///  In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
+                USR_ADDR_VALUE: u32,
+            }),
+            ///  SPI1 control register.
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller.
+                FDUMMY_OUT: u1,
+                reserved7: u3,
+                ///  Apply 2 signals during command phase 1:enable 0: disable
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable
+                FCMD_QUAD: u1,
+                reserved10: u1,
+                ///  For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
+                FCS_CRC_EN: u1,
+                ///  For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+                TX_CRC_EN: u1,
+                reserved13: u1,
+                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+                FASTRD_MODE: u1,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DUAL: u1,
+                ///  The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
+                RESANDRES: u1,
+                reserved18: u2,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low
+                D_POL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QUAD: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
+                WP: u1,
+                ///  two bytes data will be written to status register when it is set. 1: enable 0: disable.
+                WRSR_2B: u1,
+                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DIO: u1,
+                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QIO: u1,
+                padding: u7,
+            }),
+            ///  SPI1 control1 register.
+            CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+                CLK_MODE: u2,
+                ///  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
+                CS_HOLD_DLY_RES: u10,
+                padding: u20,
+            }),
+            ///  SPI1 control2 register.
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  The FSM will be reset.
+                SYNC_RESET: u1,
+            }),
+            ///  SPI1 clock division control register.
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
+                CLKCNT_L: u8,
+                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+                CLKCNT_H: u8,
+                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+                CLKCNT_N: u8,
+                reserved31: u7,
+                ///  reserved
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI1 user register.
+            USER: mmio.Mmio(packed struct(u32) {
+                reserved9: u9,
+                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+                CK_OUT_EDGE: u1,
+                reserved12: u2,
+                ///  In the write operations read-data phase apply 2 signals
+                FWRITE_DUAL: u1,
+                ///  In the write operations read-data phase apply 4 signals
+                FWRITE_QUAD: u1,
+                ///  In the write operations address phase and read-data phase apply 2 signals.
+                FWRITE_DIO: u1,
+                ///  In the write operations address phase and read-data phase apply 4 signals.
+                FWRITE_QIO: u1,
+                reserved24: u8,
+                ///  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+                USR_MISO_HIGHPART: u1,
+                ///  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+                USR_MOSI_HIGHPART: u1,
+                ///  SPI clock is disable in dummy phase when the bit is enable.
+                USR_DUMMY_IDLE: u1,
+                ///  This bit enable the write-data phase of an operation.
+                USR_MOSI: u1,
+                ///  This bit enable the read-data phase of an operation.
+                USR_MISO: u1,
+                ///  This bit enable the dummy phase of an operation.
+                USR_DUMMY: u1,
+                ///  This bit enable the address phase of an operation.
+                USR_ADDR: u1,
+                ///  This bit enable the command phase of an operation.
+                USR_COMMAND: u1,
+            }),
+            ///  SPI1 user1 register.
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+                USR_DUMMY_CYCLELEN: u6,
+                reserved26: u20,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1).
+                USR_ADDR_BITLEN: u6,
+            }),
+            ///  SPI1 user2 register.
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command.
+                USR_COMMAND_VALUE: u16,
+                reserved28: u12,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1)
+                USR_COMMAND_BITLEN: u4,
+            }),
+            ///  SPI1 send data bit length control register.
+            MOSI_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The length in bits of write-data. The register value shall be (bit_num-1).
+                USR_MOSI_DBITLEN: u10,
+                padding: u22,
+            }),
+            ///  SPI1 receive data bit length control register.
+            MISO_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The length in bits of read-data. The register value shall be (bit_num-1).
+                USR_MISO_DBITLEN: u10,
+                padding: u22,
+            }),
+            ///  SPI1 status register.
+            RD_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+                STATUS: u16,
+                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
+                WB_MODE: u8,
+                padding: u8,
+            }),
+            reserved52: [4]u8,
+            ///  SPI1 misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                ///  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
+                CS0_DIS: u1,
+                ///  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
+                CS1_DIS: u1,
+                reserved9: u7,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set.
+                CS_KEEP_ACTIVE: u1,
+                padding: u21,
+            }),
+            ///  SPI1 TX CRC data register.
+            TX_CRC: mmio.Mmio(packed struct(u32) {
+                ///  For SPI1, the value of crc32.
+                DATA: u32,
+            }),
+            ///  SPI1 bit mode control register.
+            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
+                CACHE_USR_ADDR_4BYTE: u1,
+                reserved3: u1,
+                ///  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDIN_DUAL: u1,
+                ///  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDOUT_DUAL: u1,
+                ///  For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FADDR_DUAL: u1,
+                ///  For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDIN_QUAD: u1,
+                ///  For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDOUT_QUAD: u1,
+                ///  For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FADDR_QUAD: u1,
+                padding: u23,
+            }),
+            reserved88: [24]u8,
+            ///  SPI1 memory data buffer0
+            W0: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF0: u32,
+            }),
+            ///  SPI1 memory data buffer1
+            W1: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF1: u32,
+            }),
+            ///  SPI1 memory data buffer2
+            W2: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF2: u32,
+            }),
+            ///  SPI1 memory data buffer3
+            W3: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF3: u32,
+            }),
+            ///  SPI1 memory data buffer4
+            W4: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF4: u32,
+            }),
+            ///  SPI1 memory data buffer5
+            W5: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF5: u32,
+            }),
+            ///  SPI1 memory data buffer6
+            W6: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF6: u32,
+            }),
+            ///  SPI1 memory data buffer7
+            W7: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF7: u32,
+            }),
+            ///  SPI1 memory data buffer8
+            W8: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF8: u32,
+            }),
+            ///  SPI1 memory data buffer9
+            W9: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF9: u32,
+            }),
+            ///  SPI1 memory data buffer10
+            W10: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF10: u32,
+            }),
+            ///  SPI1 memory data buffer11
+            W11: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF11: u32,
+            }),
+            ///  SPI1 memory data buffer12
+            W12: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF12: u32,
+            }),
+            ///  SPI1 memory data buffer13
+            W13: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF13: u32,
+            }),
+            ///  SPI1 memory data buffer14
+            W14: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF14: u32,
+            }),
+            ///  SPI1 memory data buffer15
+            W15: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF15: u32,
+            }),
+            ///  SPI1 wait idle control register
+            FLASH_WAITI_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  The dummy phase enable when wait flash idle (RDSR)
+                WAITI_DUMMY: u1,
+                ///  The command to wait flash idle(RDSR).
+                WAITI_CMD: u8,
+                ///  The dummy cycle length when wait flash idle(RDSR).
+                WAITI_DUMMY_CYCLELEN: u6,
+                padding: u16,
+            }),
+            ///  SPI1 flash suspend control register
+            FLASH_SUS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PER: u1,
+                ///  program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PES: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
+                FLASH_PER_WAIT_EN: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
+                FLASH_PES_WAIT_EN: u1,
+                ///  Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
+                PES_PER_EN: u1,
+                ///  Set this bit to enable Auto-suspending function.
+                FLASH_PES_EN: u1,
+                ///  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+                PESR_END_MSK: u16,
+                ///  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit
+                RD_SUS_2B: u1,
+                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
+                PER_END_EN: u1,
+                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
+                PES_END_EN: u1,
+                ///  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
+                SUS_TIMEOUT_CNT: u7,
+            }),
+            ///  SPI1 flash suspend command register
+            FLASH_SUS_CMD: mmio.Mmio(packed struct(u32) {
+                ///  Program/Erase resume command.
+                FLASH_PER_COMMAND: u8,
+                ///  Program/Erase suspend command.
+                FLASH_PES_COMMAND: u8,
+                ///  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+                WAIT_PESR_COMMAND: u16,
+            }),
+            ///  SPI1 flash suspend status register
+            SUS_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The status of flash suspend, only used in SPI1.
+                FLASH_SUS: u1,
+                ///  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+                WAIT_PESR_CMD_2B: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
+                FLASH_HPM_DLY_128: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
+                FLASH_RES_DLY_128: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
+                FLASH_DP_DLY_128: u1,
+                ///  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
+                FLASH_PER_DLY_128: u1,
+                ///  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
+                FLASH_PES_DLY_128: u1,
+                ///  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+                SPI0_LOCK_EN: u1,
+                padding: u24,
+            }),
+            ///  SPI1 timing control register
+            TIMING_CALI: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  The bit is used to enable timing auto-calibration for all reading operations.
+                TIMING_CALI: u1,
+                ///  add extra dummy spi clock cycle length for spi clock calibration.
+                EXTRA_DUMMY_CYCLELEN: u3,
+                padding: u27,
+            }),
+            reserved192: [20]u8,
+            ///  SPI1 interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_ENA: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt clear register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_CLR: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt raw register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
+                PER_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
+                PES_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+                WPE_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
+                SLV_ST_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
+                MST_ST_END_INT_RAW: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt status register
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_ST: u1,
+                padding: u27,
+            }),
+            reserved220: [12]u8,
+            ///  SPI1 clk_gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1020: [796]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Version control register
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI2 = extern struct {
+            ///  Command control register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
+                CONF_BITLEN: u18,
+                reserved23: u5,
+                ///  Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
+                UPDATE: u1,
+                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
+                USR: u1,
+                padding: u7,
+            }),
+            ///  Address value register
+            ADDR: mmio.Mmio(packed struct(u32) {
+                ///  Address to slave. Can be configured in CONF state.
+                USR_ADDR_VALUE: u32,
+            }),
+            ///  SPI control register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
+                DUMMY_OUT: u1,
+                reserved5: u1,
+                ///  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+                FADDR_DUAL: u1,
+                ///  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+                FADDR_QUAD: u1,
+                reserved8: u1,
+                ///  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+                FCMD_QUAD: u1,
+                reserved14: u4,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
+                FREAD_DUAL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
+                FREAD_QUAD: u1,
+                reserved18: u2,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
+                D_POL: u1,
+                ///  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+                HOLD_POL: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+                WP_POL: u1,
+                reserved25: u3,
+                ///  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
+                RD_BIT_ORDER: u1,
+                ///  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
+                WR_BIT_ORDER: u1,
+                padding: u5,
+            }),
+            ///  SPI clock control register
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
+                CLKCNT_L: u6,
+                ///  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
+                CLKCNT_H: u6,
+                ///  In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+                CLKCNT_N: u6,
+                ///  In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
+                CLKDIV_PRE: u4,
+                reserved31: u9,
+                ///  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI USER control register
+            USER: mmio.Mmio(packed struct(u32) {
+                ///  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
+                DOUTDIN: u1,
+                reserved3: u2,
+                ///  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
+                QPI_MODE: u1,
+                reserved5: u1,
+                ///  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
+                TSCK_I_EDGE: u1,
+                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
+                CS_HOLD: u1,
+                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
+                CS_SETUP: u1,
+                ///  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
+                RSCK_I_EDGE: u1,
+                ///  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
+                CK_OUT_EDGE: u1,
+                reserved12: u2,
+                ///  In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
+                FWRITE_DUAL: u1,
+                ///  In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
+                FWRITE_QUAD: u1,
+                reserved15: u1,
+                ///  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
+                USR_CONF_NXT: u1,
+                reserved17: u1,
+                ///  Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+                SIO: u1,
+                reserved24: u6,
+                ///  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+                USR_MISO_HIGHPART: u1,
+                ///  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+                USR_MOSI_HIGHPART: u1,
+                ///  spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
+                USR_DUMMY_IDLE: u1,
+                ///  This bit enable the write-data phase of an operation. Can be configured in CONF state.
+                USR_MOSI: u1,
+                ///  This bit enable the read-data phase of an operation. Can be configured in CONF state.
+                USR_MISO: u1,
+                ///  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+                USR_DUMMY: u1,
+                ///  This bit enable the address phase of an operation. Can be configured in CONF state.
+                USR_ADDR: u1,
+                ///  This bit enable the command phase of an operation. Can be configured in CONF state.
+                USR_COMMAND: u1,
+            }),
+            ///  SPI USER control register 1
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
+                USR_DUMMY_CYCLELEN: u8,
+                reserved16: u8,
+                ///  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
+                MST_WFULL_ERR_END_EN: u1,
+                ///  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
+                CS_SETUP_TIME: u5,
+                ///  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
+                CS_HOLD_TIME: u5,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+                USR_ADDR_BITLEN: u5,
+            }),
+            ///  SPI USER control register 2
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command. Can be configured in CONF state.
+                USR_COMMAND_VALUE: u16,
+                reserved27: u11,
+                ///  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
+                MST_REMPTY_ERR_END_EN: u1,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+                USR_COMMAND_BITLEN: u4,
+            }),
+            ///  SPI data bit length control register
+            MS_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
+                MS_DATA_BITLEN: u18,
+                padding: u14,
+            }),
+            ///  SPI misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                ///  SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
+                CS0_DIS: u1,
+                ///  SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
+                CS1_DIS: u1,
+                ///  SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
+                CS2_DIS: u1,
+                ///  SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
+                CS3_DIS: u1,
+                ///  SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
+                CS4_DIS: u1,
+                ///  SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
+                CS5_DIS: u1,
+                ///  1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
+                CK_DIS: u1,
+                ///  In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+                MASTER_CS_POL: u6,
+                reserved23: u10,
+                ///  spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.
+                SLAVE_CS_POL: u1,
+                reserved29: u5,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set. Can be configured in CONF state.
+                CS_KEEP_ACTIVE: u1,
+                ///  1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.
+                QUAD_DIN_PIN_SWAP: u1,
+            }),
+            ///  SPI input delay mode configuration
+            DIN_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN0_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN1_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN2_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN3_MODE: u2,
+                reserved16: u8,
+                ///  1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
+                TIMING_HCLK_ACTIVE: u1,
+                padding: u15,
+            }),
+            ///  SPI input delay number configuration
+            DIN_NUM: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN0_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN1_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN2_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN3_NUM: u2,
+                padding: u24,
+            }),
+            ///  SPI output delay mode configuration
+            DOUT_MODE: mmio.Mmio(packed struct(u32) {
+                ///  The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT0_MODE: u1,
+                ///  The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT1_MODE: u1,
+                ///  The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT2_MODE: u1,
+                ///  The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT3_MODE: u1,
+                padding: u28,
+            }),
+            ///  SPI DMA control register
+            DMA_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+                DMA_SLV_SEG_TRANS_EN: u1,
+                ///  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
+                SLV_RX_SEG_TRANS_CLR_EN: u1,
+                ///  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+                SLV_TX_SEG_TRANS_CLR_EN: u1,
+                ///  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
+                RX_EOF_EN: u1,
+                reserved27: u5,
+                ///  Set this bit to enable SPI DMA controlled receive data mode.
+                DMA_RX_ENA: u1,
+                ///  Set this bit to enable SPI DMA controlled send data mode.
+                DMA_TX_ENA: u1,
+                ///  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
+                RX_AFIFO_RST: u1,
+                ///  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
+                BUF_AFIFO_RST: u1,
+                ///  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
+                DMA_AFIFO_RST: u1,
+            }),
+            ///  SPI DMA interrupt enable register
+            DMA_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_ENA: u1,
+                ///  The enable bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_APP2_INT interrupt.
+                APP2_INT_ENA: u1,
+                ///  The enable bit for SPI_APP1_INT interrupt.
+                APP1_INT_ENA: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt clear register
+            DMA_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_CLR: u1,
+                ///  The clear bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_APP2_INT interrupt.
+                APP2_INT_CLR: u1,
+                ///  The clear bit for SPI_APP1_INT interrupt.
+                APP1_INT_CLR: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt raw register
+            DMA_INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.
+                DMA_INFIFO_FULL_ERR_INT_RAW: u1,
+                ///  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.
+                DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
+                SLV_EX_QPI_INT_RAW: u1,
+                ///  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
+                SLV_EN_QPI_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
+                SLV_CMD7_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
+                SLV_CMD8_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
+                SLV_CMD9_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
+                SLV_CMDA_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
+                SLV_RD_DMA_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
+                SLV_WR_DMA_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
+                SLV_RD_BUF_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
+                SLV_WR_BUF_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
+                TRANS_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.
+                DMA_SEG_TRANS_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
+                SEG_MAGIC_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
+                SLV_BUF_ADDR_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
+                SLV_CMD_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
+                MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+                MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+                APP2_INT_RAW: u1,
+                ///  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+                APP1_INT_RAW: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt status register
+            DMA_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_ST: u1,
+                ///  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
+                ///  The status bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_ST: u1,
+                ///  The status bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_ST: u1,
+                ///  The status bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_ST: u1,
+                ///  The status bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_ST: u1,
+                ///  The status bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_ST: u1,
+                ///  The status bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_ST: u1,
+                ///  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_ST: u1,
+                ///  The status bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_ST: u1,
+                ///  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_ST: u1,
+                ///  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_ST: u1,
+                ///  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_ST: u1,
+                ///  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
+                ///  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
+                ///  The status bit for SPI_APP2_INT interrupt.
+                APP2_INT_ST: u1,
+                ///  The status bit for SPI_APP1_INT interrupt.
+                APP1_INT_ST: u1,
+                padding: u11,
+            }),
+            reserved152: [84]u8,
+            ///  SPI CPU-controlled buffer0
+            W0: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF0: u32,
+            }),
+            ///  SPI CPU-controlled buffer1
+            W1: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF1: u32,
+            }),
+            ///  SPI CPU-controlled buffer2
+            W2: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF2: u32,
+            }),
+            ///  SPI CPU-controlled buffer3
+            W3: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF3: u32,
+            }),
+            ///  SPI CPU-controlled buffer4
+            W4: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF4: u32,
+            }),
+            ///  SPI CPU-controlled buffer5
+            W5: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF5: u32,
+            }),
+            ///  SPI CPU-controlled buffer6
+            W6: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF6: u32,
+            }),
+            ///  SPI CPU-controlled buffer7
+            W7: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF7: u32,
+            }),
+            ///  SPI CPU-controlled buffer8
+            W8: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF8: u32,
+            }),
+            ///  SPI CPU-controlled buffer9
+            W9: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF9: u32,
+            }),
+            ///  SPI CPU-controlled buffer10
+            W10: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF10: u32,
+            }),
+            ///  SPI CPU-controlled buffer11
+            W11: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF11: u32,
+            }),
+            ///  SPI CPU-controlled buffer12
+            W12: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF12: u32,
+            }),
+            ///  SPI CPU-controlled buffer13
+            W13: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF13: u32,
+            }),
+            ///  SPI CPU-controlled buffer14
+            W14: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF14: u32,
+            }),
+            ///  SPI CPU-controlled buffer15
+            W15: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF15: u32,
+            }),
+            reserved224: [8]u8,
+            ///  SPI slave control register
+            SLAVE: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+                CLK_MODE: u2,
+                ///  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+                CLK_MODE_13: u1,
+                ///  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge
+                RSCK_DATA_OUT: u1,
+                reserved8: u4,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
+                SLV_RDDMA_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
+                SLV_WRDMA_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
+                SLV_RDBUF_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
+                SLV_WRBUF_BITLEN_EN: u1,
+                reserved22: u10,
+                ///  The magic value of BM table in master DMA seg-trans.
+                DMA_SEG_MAGIC_VALUE: u4,
+                ///  Set SPI work mode. 1: slave mode 0: master mode.
+                MODE: u1,
+                ///  Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
+                SOFT_RESET: u1,
+                ///  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
+                USR_CONF: u1,
+                padding: u3,
+            }),
+            ///  SPI slave control register 1
+            SLAVE1: mmio.Mmio(packed struct(u32) {
+                ///  The transferred data bit length in SPI slave FD and HD mode.
+                SLV_DATA_BITLEN: u18,
+                ///  In the slave mode it is the value of command.
+                SLV_LAST_COMMAND: u8,
+                ///  In the slave mode it is the value of address.
+                SLV_LAST_ADDR: u6,
+            }),
+            ///  SPI module clock and register clock control
+            CLK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable clk gate
+                CLK_EN: u1,
+                ///  Set this bit to power on the SPI module clock.
+                MST_CLK_ACTIVE: u1,
+                ///  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
+                MST_CLK_SEL: u1,
+                padding: u29,
+            }),
+            reserved240: [4]u8,
+            ///  Version control
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  SPI register version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  System
+        pub const SYSTEM = extern struct {
+            ///  cpu_peripheral clock gating register
+            CPU_PERI_CLK_EN: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  reg_clk_en_assist_debug
+                CLK_EN_ASSIST_DEBUG: u1,
+                ///  reg_clk_en_dedicated_gpio
+                CLK_EN_DEDICATED_GPIO: u1,
+                padding: u24,
+            }),
+            ///  cpu_peripheral reset register
+            CPU_PERI_RST_EN: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  reg_rst_en_assist_debug
+                RST_EN_ASSIST_DEBUG: u1,
+                ///  reg_rst_en_dedicated_gpio
+                RST_EN_DEDICATED_GPIO: u1,
+                padding: u24,
+            }),
+            ///  cpu clock config register
+            CPU_PER_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpuperiod_sel
+                CPUPERIOD_SEL: u2,
+                ///  reg_pll_freq_sel
+                PLL_FREQ_SEL: u1,
+                ///  reg_cpu_wait_mode_force_on
+                CPU_WAIT_MODE_FORCE_ON: u1,
+                ///  reg_cpu_waiti_delay_num
+                CPU_WAITI_DELAY_NUM: u4,
+                padding: u24,
+            }),
+            ///  memory power down mask register
+            MEM_PD_MASK: mmio.Mmio(packed struct(u32) {
+                ///  reg_lslp_mem_pd_mask
+                LSLP_MEM_PD_MASK: u1,
+                padding: u31,
+            }),
+            ///  peripheral clock gating register
+            PERIP_CLK_EN0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timers_clk_en
+                TIMERS_CLK_EN: u1,
+                ///  reg_spi01_clk_en
+                SPI01_CLK_EN: u1,
+                ///  reg_uart_clk_en
+                UART_CLK_EN: u1,
+                ///  reg_wdg_clk_en
+                WDG_CLK_EN: u1,
+                ///  reg_i2s0_clk_en
+                I2S0_CLK_EN: u1,
+                ///  reg_uart1_clk_en
+                UART1_CLK_EN: u1,
+                ///  reg_spi2_clk_en
+                SPI2_CLK_EN: u1,
+                ///  reg_ext0_clk_en
+                I2C_EXT0_CLK_EN: u1,
+                ///  reg_uhci0_clk_en
+                UHCI0_CLK_EN: u1,
+                ///  reg_rmt_clk_en
+                RMT_CLK_EN: u1,
+                ///  reg_pcnt_clk_en
+                PCNT_CLK_EN: u1,
+                ///  reg_ledc_clk_en
+                LEDC_CLK_EN: u1,
+                ///  reg_uhci1_clk_en
+                UHCI1_CLK_EN: u1,
+                ///  reg_timergroup_clk_en
+                TIMERGROUP_CLK_EN: u1,
+                ///  reg_efuse_clk_en
+                EFUSE_CLK_EN: u1,
+                ///  reg_timergroup1_clk_en
+                TIMERGROUP1_CLK_EN: u1,
+                ///  reg_spi3_clk_en
+                SPI3_CLK_EN: u1,
+                ///  reg_pwm0_clk_en
+                PWM0_CLK_EN: u1,
+                ///  reg_ext1_clk_en
+                EXT1_CLK_EN: u1,
+                ///  reg_can_clk_en
+                CAN_CLK_EN: u1,
+                ///  reg_pwm1_clk_en
+                PWM1_CLK_EN: u1,
+                ///  reg_i2s1_clk_en
+                I2S1_CLK_EN: u1,
+                ///  reg_spi2_dma_clk_en
+                SPI2_DMA_CLK_EN: u1,
+                ///  reg_usb_device_clk_en
+                USB_DEVICE_CLK_EN: u1,
+                ///  reg_uart_mem_clk_en
+                UART_MEM_CLK_EN: u1,
+                ///  reg_pwm2_clk_en
+                PWM2_CLK_EN: u1,
+                ///  reg_pwm3_clk_en
+                PWM3_CLK_EN: u1,
+                ///  reg_spi3_dma_clk_en
+                SPI3_DMA_CLK_EN: u1,
+                ///  reg_apb_saradc_clk_en
+                APB_SARADC_CLK_EN: u1,
+                ///  reg_systimer_clk_en
+                SYSTIMER_CLK_EN: u1,
+                ///  reg_adc2_arb_clk_en
+                ADC2_ARB_CLK_EN: u1,
+                ///  reg_spi4_clk_en
+                SPI4_CLK_EN: u1,
+            }),
+            ///  peripheral clock gating register
+            PERIP_CLK_EN1: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_crypto_aes_clk_en
+                CRYPTO_AES_CLK_EN: u1,
+                ///  reg_crypto_sha_clk_en
+                CRYPTO_SHA_CLK_EN: u1,
+                ///  reg_crypto_rsa_clk_en
+                CRYPTO_RSA_CLK_EN: u1,
+                ///  reg_crypto_ds_clk_en
+                CRYPTO_DS_CLK_EN: u1,
+                ///  reg_crypto_hmac_clk_en
+                CRYPTO_HMAC_CLK_EN: u1,
+                ///  reg_dma_clk_en
+                DMA_CLK_EN: u1,
+                ///  reg_sdio_host_clk_en
+                SDIO_HOST_CLK_EN: u1,
+                ///  reg_lcd_cam_clk_en
+                LCD_CAM_CLK_EN: u1,
+                ///  reg_uart2_clk_en
+                UART2_CLK_EN: u1,
+                ///  reg_tsens_clk_en
+                TSENS_CLK_EN: u1,
+                padding: u21,
+            }),
+            ///  reserved
+            PERIP_RST_EN0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timers_rst
+                TIMERS_RST: u1,
+                ///  reg_spi01_rst
+                SPI01_RST: u1,
+                ///  reg_uart_rst
+                UART_RST: u1,
+                ///  reg_wdg_rst
+                WDG_RST: u1,
+                ///  reg_i2s0_rst
+                I2S0_RST: u1,
+                ///  reg_uart1_rst
+                UART1_RST: u1,
+                ///  reg_spi2_rst
+                SPI2_RST: u1,
+                ///  reg_ext0_rst
+                I2C_EXT0_RST: u1,
+                ///  reg_uhci0_rst
+                UHCI0_RST: u1,
+                ///  reg_rmt_rst
+                RMT_RST: u1,
+                ///  reg_pcnt_rst
+                PCNT_RST: u1,
+                ///  reg_ledc_rst
+                LEDC_RST: u1,
+                ///  reg_uhci1_rst
+                UHCI1_RST: u1,
+                ///  reg_timergroup_rst
+                TIMERGROUP_RST: u1,
+                ///  reg_efuse_rst
+                EFUSE_RST: u1,
+                ///  reg_timergroup1_rst
+                TIMERGROUP1_RST: u1,
+                ///  reg_spi3_rst
+                SPI3_RST: u1,
+                ///  reg_pwm0_rst
+                PWM0_RST: u1,
+                ///  reg_ext1_rst
+                EXT1_RST: u1,
+                ///  reg_can_rst
+                CAN_RST: u1,
+                ///  reg_pwm1_rst
+                PWM1_RST: u1,
+                ///  reg_i2s1_rst
+                I2S1_RST: u1,
+                ///  reg_spi2_dma_rst
+                SPI2_DMA_RST: u1,
+                ///  reg_usb_device_rst
+                USB_DEVICE_RST: u1,
+                ///  reg_uart_mem_rst
+                UART_MEM_RST: u1,
+                ///  reg_pwm2_rst
+                PWM2_RST: u1,
+                ///  reg_pwm3_rst
+                PWM3_RST: u1,
+                ///  reg_spi3_dma_rst
+                SPI3_DMA_RST: u1,
+                ///  reg_apb_saradc_rst
+                APB_SARADC_RST: u1,
+                ///  reg_systimer_rst
+                SYSTIMER_RST: u1,
+                ///  reg_adc2_arb_rst
+                ADC2_ARB_RST: u1,
+                ///  reg_spi4_rst
+                SPI4_RST: u1,
+            }),
+            ///  peripheral reset register
+            PERIP_RST_EN1: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_crypto_aes_rst
+                CRYPTO_AES_RST: u1,
+                ///  reg_crypto_sha_rst
+                CRYPTO_SHA_RST: u1,
+                ///  reg_crypto_rsa_rst
+                CRYPTO_RSA_RST: u1,
+                ///  reg_crypto_ds_rst
+                CRYPTO_DS_RST: u1,
+                ///  reg_crypto_hmac_rst
+                CRYPTO_HMAC_RST: u1,
+                ///  reg_dma_rst
+                DMA_RST: u1,
+                ///  reg_sdio_host_rst
+                SDIO_HOST_RST: u1,
+                ///  reg_lcd_cam_rst
+                LCD_CAM_RST: u1,
+                ///  reg_uart2_rst
+                UART2_RST: u1,
+                ///  reg_tsens_rst
+                TSENS_RST: u1,
+                padding: u21,
+            }),
+            ///  clock config register
+            BT_LPCK_DIV_INT: mmio.Mmio(packed struct(u32) {
+                ///  reg_bt_lpck_div_num
+                BT_LPCK_DIV_NUM: u12,
+                padding: u20,
+            }),
+            ///  clock config register
+            BT_LPCK_DIV_FRAC: mmio.Mmio(packed struct(u32) {
+                ///  reg_bt_lpck_div_b
+                BT_LPCK_DIV_B: u12,
+                ///  reg_bt_lpck_div_a
+                BT_LPCK_DIV_A: u12,
+                ///  reg_lpclk_sel_rtc_slow
+                LPCLK_SEL_RTC_SLOW: u1,
+                ///  reg_lpclk_sel_8m
+                LPCLK_SEL_8M: u1,
+                ///  reg_lpclk_sel_xtal
+                LPCLK_SEL_XTAL: u1,
+                ///  reg_lpclk_sel_xtal32k
+                LPCLK_SEL_XTAL32K: u1,
+                ///  reg_lpclk_rtc_en
+                LPCLK_RTC_EN: u1,
+                padding: u3,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_0
+                CPU_INTR_FROM_CPU_0: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_1
+                CPU_INTR_FROM_CPU_1: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_2
+                CPU_INTR_FROM_CPU_2: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_3
+                CPU_INTR_FROM_CPU_3: u1,
+                padding: u31,
+            }),
+            ///  rsa memory power control register
+            RSA_PD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_rsa_mem_pd
+                RSA_MEM_PD: u1,
+                ///  reg_rsa_mem_force_pu
+                RSA_MEM_FORCE_PU: u1,
+                ///  reg_rsa_mem_force_pd
+                RSA_MEM_FORCE_PD: u1,
+                padding: u29,
+            }),
+            ///  edma clcok and reset register
+            EDMA_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_edma_clk_on
+                EDMA_CLK_ON: u1,
+                ///  reg_edma_reset
+                EDMA_RESET: u1,
+                padding: u30,
+            }),
+            ///  cache control register
+            CACHE_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  reg_icache_clk_on
+                ICACHE_CLK_ON: u1,
+                ///  reg_icache_reset
+                ICACHE_RESET: u1,
+                ///  reg_dcache_clk_on
+                DCACHE_CLK_ON: u1,
+                ///  reg_dcache_reset
+                DCACHE_RESET: u1,
+                padding: u28,
+            }),
+            ///  SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+            EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  reg_enable_spi_manual_encrypt
+                ENABLE_SPI_MANUAL_ENCRYPT: u1,
+                ///  reg_enable_download_db_encrypt
+                ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
+                ///  reg_enable_download_g0cb_decrypt
+                ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
+                ///  reg_enable_download_manual_encrypt
+                ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
+                padding: u28,
+            }),
+            ///  fast memory config register
+            RTC_FASTMEM_CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  reg_rtc_mem_crc_start
+                RTC_MEM_CRC_START: u1,
+                ///  reg_rtc_mem_crc_addr
+                RTC_MEM_CRC_ADDR: u11,
+                ///  reg_rtc_mem_crc_len
+                RTC_MEM_CRC_LEN: u11,
+                ///  reg_rtc_mem_crc_finish
+                RTC_MEM_CRC_FINISH: u1,
+            }),
+            ///  reserved
+            RTC_FASTMEM_CRC: mmio.Mmio(packed struct(u32) {
+                ///  reg_rtc_mem_crc_res
+                RTC_MEM_CRC_RES: u32,
+            }),
+            ///  eco register
+            REDUNDANT_ECO_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_redundant_eco_drive
+                REDUNDANT_ECO_DRIVE: u1,
+                ///  reg_redundant_eco_result
+                REDUNDANT_ECO_RESULT: u1,
+                padding: u30,
+            }),
+            ///  clock gating register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_clk_en
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  system clock config register
+            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_pre_div_cnt
+                PRE_DIV_CNT: u10,
+                ///  reg_soc_clk_sel
+                SOC_CLK_SEL: u2,
+                ///  reg_clk_xtal_freq
+                CLK_XTAL_FREQ: u7,
+                ///  reg_clk_div_en
+                CLK_DIV_EN: u1,
+                padding: u12,
+            }),
+            ///  mem pvt register
+            MEM_PVT: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_path_len
+                MEM_PATH_LEN: u4,
+                ///  reg_mem_err_cnt_clr
+                MEM_ERR_CNT_CLR: u1,
+                ///  reg_mem_pvt_monitor_en
+                MONITOR_EN: u1,
+                ///  reg_mem_timing_err_cnt
+                MEM_TIMING_ERR_CNT: u16,
+                ///  reg_mem_vt_sel
+                MEM_VT_SEL: u2,
+                padding: u8,
+            }),
+            ///  mem pvt register
+            COMB_PVT_LVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_lvt
+                COMB_PATH_LEN_LVT: u5,
+                ///  reg_comb_err_cnt_clr_lvt
+                COMB_ERR_CNT_CLR_LVT: u1,
+                ///  reg_comb_pvt_monitor_en_lvt
+                COMB_PVT_MONITOR_EN_LVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_NVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_nvt
+                COMB_PATH_LEN_NVT: u5,
+                ///  reg_comb_err_cnt_clr_nvt
+                COMB_ERR_CNT_CLR_NVT: u1,
+                ///  reg_comb_pvt_monitor_en_nvt
+                COMB_PVT_MONITOR_EN_NVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_HVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_hvt
+                COMB_PATH_LEN_HVT: u5,
+                ///  reg_comb_err_cnt_clr_hvt
+                COMB_ERR_CNT_CLR_HVT: u1,
+                ///  reg_comb_pvt_monitor_en_hvt
+                COMB_PVT_MONITOR_EN_HVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site0
+                COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site0
+                COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site0
+                COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site1
+                COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site1
+                COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site1
+                COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site2
+                COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site2
+                COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site2
+                COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site3
+                COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site3
+                COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site3
+                COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
+                padding: u16,
+            }),
+            reserved4092: [3936]u8,
+            ///  Version register
+            SYSTEM_REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_system_reg_date
+                SYSTEM_REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  System Timer
+        pub const SYSTIMER = extern struct {
+            ///  SYSTIMER_CONF.
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  systimer clock force on
+                SYSTIMER_CLK_FO: u1,
+                reserved22: u21,
+                ///  target2 work enable
+                TARGET2_WORK_EN: u1,
+                ///  target1 work enable
+                TARGET1_WORK_EN: u1,
+                ///  target0 work enable
+                TARGET0_WORK_EN: u1,
+                ///  If timer unit1 is stalled when core1 stalled
+                TIMER_UNIT1_CORE1_STALL_EN: u1,
+                ///  If timer unit1 is stalled when core0 stalled
+                TIMER_UNIT1_CORE0_STALL_EN: u1,
+                ///  If timer unit0 is stalled when core1 stalled
+                TIMER_UNIT0_CORE1_STALL_EN: u1,
+                ///  If timer unit0 is stalled when core0 stalled
+                TIMER_UNIT0_CORE0_STALL_EN: u1,
+                ///  timer unit1 work enable
+                TIMER_UNIT1_WORK_EN: u1,
+                ///  timer unit0 work enable
+                TIMER_UNIT0_WORK_EN: u1,
+                ///  register file clk gating
+                CLK_EN: u1,
+            }),
+            ///  SYSTIMER_UNIT0_OP.
+            UNIT0_OP: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  reg_timer_unit0_value_valid
+                TIMER_UNIT0_VALUE_VALID: u1,
+                ///  update timer_unit0
+                TIMER_UNIT0_UPDATE: u1,
+                padding: u1,
+            }),
+            ///  SYSTIMER_UNIT1_OP.
+            UNIT1_OP: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  timer value is sync and valid
+                TIMER_UNIT1_VALUE_VALID: u1,
+                ///  update timer unit1
+                TIMER_UNIT1_UPDATE: u1,
+                padding: u1,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD_HI.
+            UNIT0_LOAD_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load high 32 bit
+                TIMER_UNIT0_LOAD_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD_LO.
+            UNIT0_LOAD_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load low 32 bit
+                TIMER_UNIT0_LOAD_LO: u32,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD_HI.
+            UNIT1_LOAD_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load high 32 bit
+                TIMER_UNIT1_LOAD_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD_LO.
+            UNIT1_LOAD_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load low 32 bit
+                TIMER_UNIT1_LOAD_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET0_HI.
+            TARGET0_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget0 high 32 bit
+                TIMER_TARGET0_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET0_LO.
+            TARGET0_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget0 low 32 bit
+                TIMER_TARGET0_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET1_HI.
+            TARGET1_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget1 high 32 bit
+                TIMER_TARGET1_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET1_LO.
+            TARGET1_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget1 low 32 bit
+                TIMER_TARGET1_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET2_HI.
+            TARGET2_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget2 high 32 bit
+                TIMER_TARGET2_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET2_LO.
+            TARGET2_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget2 low 32 bit
+                TIMER_TARGET2_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET0_CONF.
+            TARGET0_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target0 period
+                TARGET0_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target0 to period mode
+                TARGET0_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET0_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_TARGET1_CONF.
+            TARGET1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target1 period
+                TARGET1_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target1 to period mode
+                TARGET1_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET1_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_TARGET2_CONF.
+            TARGET2_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target2 period
+                TARGET2_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target2 to period mode
+                TARGET2_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET2_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_UNIT0_VALUE_HI.
+            UNIT0_VALUE_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer read value high 32bit
+                TIMER_UNIT0_VALUE_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT0_VALUE_LO.
+            UNIT0_VALUE_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer read value low 32bit
+                TIMER_UNIT0_VALUE_LO: u32,
+            }),
+            ///  SYSTIMER_UNIT1_VALUE_HI.
+            UNIT1_VALUE_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer read value high 32bit
+                TIMER_UNIT1_VALUE_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT1_VALUE_LO.
+            UNIT1_VALUE_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer read value low 32bit
+                TIMER_UNIT1_VALUE_LO: u32,
+            }),
+            ///  SYSTIMER_COMP0_LOAD.
+            COMP0_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp0 load value
+                TIMER_COMP0_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_COMP1_LOAD.
+            COMP1_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp1 load value
+                TIMER_COMP1_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_COMP2_LOAD.
+            COMP2_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp2 load value
+                TIMER_COMP2_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD.
+            UNIT0_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load value
+                TIMER_UNIT0_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD.
+            UNIT1_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load value
+                TIMER_UNIT1_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_INT_ENA.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 enable
+                TARGET0_INT_ENA: u1,
+                ///  interupt1 enable
+                TARGET1_INT_ENA: u1,
+                ///  interupt2 enable
+                TARGET2_INT_ENA: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_RAW.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 raw
+                TARGET0_INT_RAW: u1,
+                ///  interupt1 raw
+                TARGET1_INT_RAW: u1,
+                ///  interupt2 raw
+                TARGET2_INT_RAW: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_CLR.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 clear
+                TARGET0_INT_CLR: u1,
+                ///  interupt1 clear
+                TARGET1_INT_CLR: u1,
+                ///  interupt2 clear
+                TARGET2_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_ST.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_target0_int_st
+                TARGET0_INT_ST: u1,
+                ///  reg_target1_int_st
+                TARGET1_INT_ST: u1,
+                ///  reg_target2_int_st
+                TARGET2_INT_ST: u1,
+                padding: u29,
+            }),
+            reserved252: [136]u8,
+            ///  SYSTIMER_DATE.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u32,
+            }),
+        };
+
+        ///  Timer Group
+        pub const TIMG0 = extern struct {
+            ///  TIMG_T0CONFIG_REG.
+            T0CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved9: u9,
+                ///  reg_t0_use_xtal.
+                T0_USE_XTAL: u1,
+                ///  reg_t0_alarm_en.
+                T0_ALARM_EN: u1,
+                reserved12: u1,
+                ///  reg_t0_divcnt_rst.
+                T0_DIVCNT_RST: u1,
+                ///  reg_t0_divider.
+                T0_DIVIDER: u16,
+                ///  reg_t0_autoreload.
+                T0_AUTORELOAD: u1,
+                ///  reg_t0_increase.
+                T0_INCREASE: u1,
+                ///  reg_t0_en.
+                T0_EN: u1,
+            }),
+            ///  TIMG_T0LO_REG.
+            T0LO: mmio.Mmio(packed struct(u32) {
+                ///  t0_lo
+                T0_LO: u32,
+            }),
+            ///  TIMG_T0HI_REG.
+            T0HI: mmio.Mmio(packed struct(u32) {
+                ///  t0_hi
+                T0_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0UPDATE_REG.
+            T0UPDATE: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  t0_update
+                T0_UPDATE: u1,
+            }),
+            ///  TIMG_T0ALARMLO_REG.
+            T0ALARMLO: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_alarm_lo.
+                T0_ALARM_LO: u32,
+            }),
+            ///  TIMG_T0ALARMHI_REG.
+            T0ALARMHI: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_alarm_hi.
+                T0_ALARM_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0LOADLO_REG.
+            T0LOADLO: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_load_lo.
+                T0_LOAD_LO: u32,
+            }),
+            ///  TIMG_T0LOADHI_REG.
+            T0LOADHI: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_load_hi.
+                T0_LOAD_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0LOAD_REG.
+            T0LOAD: mmio.Mmio(packed struct(u32) {
+                ///  t0_load
+                T0_LOAD: u32,
+            }),
+            reserved72: [36]u8,
+            ///  TIMG_WDTCONFIG0_REG.
+            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  reg_wdt_appcpu_reset_en.
+                WDT_APPCPU_RESET_EN: u1,
+                ///  reg_wdt_procpu_reset_en.
+                WDT_PROCPU_RESET_EN: u1,
+                ///  reg_wdt_flashboot_mod_en.
+                WDT_FLASHBOOT_MOD_EN: u1,
+                ///  reg_wdt_sys_reset_length.
+                WDT_SYS_RESET_LENGTH: u3,
+                ///  reg_wdt_cpu_reset_length.
+                WDT_CPU_RESET_LENGTH: u3,
+                ///  reg_wdt_use_xtal.
+                WDT_USE_XTAL: u1,
+                ///  reg_wdt_conf_update_en.
+                WDT_CONF_UPDATE_EN: u1,
+                ///  reg_wdt_stg3.
+                WDT_STG3: u2,
+                ///  reg_wdt_stg2.
+                WDT_STG2: u2,
+                ///  reg_wdt_stg1.
+                WDT_STG1: u2,
+                ///  reg_wdt_stg0.
+                WDT_STG0: u2,
+                ///  reg_wdt_en.
+                WDT_EN: u1,
+            }),
+            ///  TIMG_WDTCONFIG1_REG.
+            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_divcnt_rst.
+                WDT_DIVCNT_RST: u1,
+                reserved16: u15,
+                ///  reg_wdt_clk_prescale.
+                WDT_CLK_PRESCALE: u16,
+            }),
+            ///  TIMG_WDTCONFIG2_REG.
+            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg0_hold.
+                WDT_STG0_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG3_REG.
+            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg1_hold.
+                WDT_STG1_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG4_REG.
+            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg2_hold.
+                WDT_STG2_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG5_REG.
+            WDTCONFIG5: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg3_hold.
+                WDT_STG3_HOLD: u32,
+            }),
+            ///  TIMG_WDTFEED_REG.
+            WDTFEED: mmio.Mmio(packed struct(u32) {
+                ///  wdt_feed
+                WDT_FEED: u32,
+            }),
+            ///  TIMG_WDTWPROTECT_REG.
+            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_wkey.
+                WDT_WKEY: u32,
+            }),
+            ///  TIMG_RTCCALICFG_REG.
+            RTCCALICFG: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  reg_rtc_cali_start_cycling.
+                RTC_CALI_START_CYCLING: u1,
+                ///  reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+                RTC_CALI_CLK_SEL: u2,
+                ///  rtc_cali_rdy
+                RTC_CALI_RDY: u1,
+                ///  reg_rtc_cali_max.
+                RTC_CALI_MAX: u15,
+                ///  reg_rtc_cali_start.
+                RTC_CALI_START: u1,
+            }),
+            ///  TIMG_RTCCALICFG1_REG.
+            RTCCALICFG1: mmio.Mmio(packed struct(u32) {
+                ///  rtc_cali_cycling_data_vld
+                RTC_CALI_CYCLING_DATA_VLD: u1,
+                reserved7: u6,
+                ///  rtc_cali_value
+                RTC_CALI_VALUE: u25,
+            }),
+            ///  INT_ENA_TIMG_REG
+            INT_ENA_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_ena
+                T0_INT_ENA: u1,
+                ///  wdt_int_ena
+                WDT_INT_ENA: u1,
+                padding: u30,
+            }),
+            ///  INT_RAW_TIMG_REG
+            INT_RAW_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_raw
+                T0_INT_RAW: u1,
+                ///  wdt_int_raw
+                WDT_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  INT_ST_TIMG_REG
+            INT_ST_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_st
+                T0_INT_ST: u1,
+                ///  wdt_int_st
+                WDT_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  INT_CLR_TIMG_REG
+            INT_CLR_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_clr
+                T0_INT_CLR: u1,
+                ///  wdt_int_clr
+                WDT_INT_CLR: u1,
+                padding: u30,
+            }),
+            ///  TIMG_RTCCALICFG2_REG.
+            RTCCALICFG2: mmio.Mmio(packed struct(u32) {
+                ///  timeoutindicator
+                RTC_CALI_TIMEOUT: u1,
+                reserved3: u2,
+                ///  reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+                RTC_CALI_TIMEOUT_RST_CNT: u4,
+                ///  reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+                RTC_CALI_TIMEOUT_THRES: u25,
+            }),
+            reserved248: [116]u8,
+            ///  TIMG_NTIMG_DATE_REG.
+            NTIMG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_ntimers_date.
+                NTIMGS_DATE: u28,
+                padding: u4,
+            }),
+            ///  TIMG_REGCLK_REG.
+            REGCLK: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  reg_wdt_clk_is_active.
+                WDT_CLK_IS_ACTIVE: u1,
+                ///  reg_timer_clk_is_active.
+                TIMER_CLK_IS_ACTIVE: u1,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+        };
+
+        ///  XTS-AES-128 Flash Encryption
+        pub const XTS_AES = extern struct {
+            ///  The memory that stores plaintext
+            PLAIN_MEM: [16]u8,
+            reserved64: [48]u8,
+            ///  XTS-AES line-size register
+            LINESIZE: mmio.Mmio(packed struct(u32) {
+                ///  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+                LINESIZE: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES destination register
+            DESTINATION: mmio.Mmio(packed struct(u32) {
+                ///  This bit stores the destination. 0: flash(default). 1: reserved.
+                DESTINATION: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES physical address register
+            PHYSICAL_ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
+                PHYSICAL_ADDRESS: u30,
+                padding: u2,
+            }),
+            ///  XTS-AES trigger register
+            TRIGGER: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to start manual encryption calculation
+                TRIGGER: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES release register
+            RELEASE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to release the manual encrypted result, after that the result will be visible to spi
+                RELEASE: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES destroy register
+            DESTROY: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to destroy XTS-AES result.
+                DESTROY: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES status register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
+                STATE: u2,
+                padding: u30,
+            }),
+            ///  XTS-AES version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the version information of XTS-AES.
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  Two-Wire Automotive Interface
+        pub const TWAI = extern struct {
+            ///  Mode Register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
+                RESET_MODE: u1,
+                ///  1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
+                LISTEN_ONLY_MODE: u1,
+                ///  1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
+                SELF_TEST_MODE: u1,
+                ///  This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
+                RX_FILTER_MODE: u1,
+                padding: u28,
+            }),
+            ///  Command Register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Set the bit to 1 to allow the driving nodes start transmission.
+                TX_REQ: u1,
+                ///  Set the bit to 1 to cancel a pending transmission request.
+                ABORT_TX: u1,
+                ///  Set the bit to 1 to release the RX buffer.
+                RELEASE_BUF: u1,
+                ///  Set the bit to 1 to clear the data overrun status bit.
+                CLR_OVERRUN: u1,
+                ///  Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
+                SELF_RX_REQ: u1,
+                padding: u27,
+            }),
+            ///  Status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  1: The data in the RX buffer is not empty, with at least one received data packet.
+                RX_BUF_ST: u1,
+                ///  1: The RX FIFO is full and data overrun has occurred.
+                OVERRUN_ST: u1,
+                ///  1: The TX buffer is empty, the CPU may write a message into it.
+                TX_BUF_ST: u1,
+                ///  1: The TWAI controller has successfully received a packet from the bus.
+                TX_COMPLETE: u1,
+                ///  1: The TWAI Controller is receiving a message from the bus.
+                RX_ST: u1,
+                ///  1: The TWAI Controller is transmitting a message to the bus.
+                TX_ST: u1,
+                ///  1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
+                ERR_ST: u1,
+                ///  1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
+                BUS_OFF_ST: u1,
+                ///  This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
+                MISS_ST: u1,
+                padding: u23,
+            }),
+            ///  Interrupt Register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
+                RX_INT_ST: u1,
+                ///  Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
+                TX_INT_ST: u1,
+                ///  Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
+                ERR_WARN_INT_ST: u1,
+                ///  Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
+                OVERRUN_INT_ST: u1,
+                reserved5: u1,
+                ///  Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
+                ERR_PASSIVE_INT_ST: u1,
+                ///  Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
+                ARB_LOST_INT_ST: u1,
+                ///  Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
+                BUS_ERR_INT_ST: u1,
+                padding: u24,
+            }),
+            ///  Interrupt Enable Register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to 1 to enable receive interrupt.
+                RX_INT_ENA: u1,
+                ///  Set this bit to 1 to enable transmit interrupt.
+                TX_INT_ENA: u1,
+                ///  Set this bit to 1 to enable error warning interrupt.
+                ERR_WARN_INT_ENA: u1,
+                ///  Set this bit to 1 to enable data overrun interrupt.
+                OVERRUN_INT_ENA: u1,
+                reserved5: u1,
+                ///  Set this bit to 1 to enable error passive interrupt.
+                ERR_PASSIVE_INT_ENA: u1,
+                ///  Set this bit to 1 to enable arbitration lost interrupt.
+                ARB_LOST_INT_ENA: u1,
+                ///  Set this bit to 1 to enable error interrupt.
+                BUS_ERR_INT_ENA: u1,
+                padding: u24,
+            }),
+            reserved24: [4]u8,
+            ///  Bus Timing Register 0
+            BUS_TIMING_0: mmio.Mmio(packed struct(u32) {
+                ///  Baud Rate Prescaler, determines the frequency dividing ratio.
+                BAUD_PRESC: u13,
+                reserved14: u1,
+                ///  Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+                SYNC_JUMP_WIDTH: u2,
+                padding: u16,
+            }),
+            ///  Bus Timing Register 1
+            BUS_TIMING_1: mmio.Mmio(packed struct(u32) {
+                ///  The width of PBS1.
+                TIME_SEG1: u4,
+                ///  The width of PBS2.
+                TIME_SEG2: u3,
+                ///  The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
+                TIME_SAMP: u1,
+                padding: u24,
+            }),
+            reserved44: [12]u8,
+            ///  Arbitration Lost Capture Register
+            ARB_LOST_CAP: mmio.Mmio(packed struct(u32) {
+                ///  This register contains information about the bit position of lost arbitration.
+                ARB_LOST_CAP: u5,
+                padding: u27,
+            }),
+            ///  Error Code Capture Register
+            ERR_CODE_CAP: mmio.Mmio(packed struct(u32) {
+                ///  This register contains information about the location of errors, see Table 181 for details.
+                ECC_SEGMENT: u5,
+                ///  This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
+                ECC_DIRECTION: u1,
+                ///  This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
+                ECC_TYPE: u2,
+                padding: u24,
+            }),
+            ///  Error Warning Limit Register
+            ERR_WARNING_LIMIT: mmio.Mmio(packed struct(u32) {
+                ///  Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
+                ERR_WARNING_LIMIT: u8,
+                padding: u24,
+            }),
+            ///  Receive Error Counter Register
+            RX_ERR_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The RX error counter register, reflects value changes under reception status.
+                RX_ERR_CNT: u8,
+                padding: u24,
+            }),
+            ///  Transmit Error Counter Register
+            TX_ERR_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The TX error counter register, reflects value changes under transmission status.
+                TX_ERR_CNT: u8,
+                padding: u24,
+            }),
+            ///  Data register 0
+            DATA_0: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_0: u8,
+                padding: u24,
+            }),
+            ///  Data register 1
+            DATA_1: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
+                TX_BYTE_1: u8,
+                padding: u24,
+            }),
+            ///  Data register 2
+            DATA_2: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
+                TX_BYTE_2: u8,
+                padding: u24,
+            }),
+            ///  Data register 3
+            DATA_3: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
+                TX_BYTE_3: u8,
+                padding: u24,
+            }),
+            ///  Data register 4
+            DATA_4: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_4: u8,
+                padding: u24,
+            }),
+            ///  Data register 5
+            DATA_5: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_5: u8,
+                padding: u24,
+            }),
+            ///  Data register 6
+            DATA_6: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_6: u8,
+                padding: u24,
+            }),
+            ///  Data register 7
+            DATA_7: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_7: u8,
+                padding: u24,
+            }),
+            ///  Data register 8
+            DATA_8: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 8th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_8: u8,
+                padding: u24,
+            }),
+            ///  Data register 9
+            DATA_9: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 9th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_9: u8,
+                padding: u24,
+            }),
+            ///  Data register 10
+            DATA_10: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 10th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_10: u8,
+                padding: u24,
+            }),
+            ///  Data register 11
+            DATA_11: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 11th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_11: u8,
+                padding: u24,
+            }),
+            ///  Data register 12
+            DATA_12: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 12th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_12: u8,
+                padding: u24,
+            }),
+            ///  Receive Message Counter Register
+            RX_MESSAGE_CNT: mmio.Mmio(packed struct(u32) {
+                ///  This register reflects the number of messages available within the RX FIFO.
+                RX_MESSAGE_COUNTER: u7,
+                padding: u25,
+            }),
+            reserved124: [4]u8,
+            ///  Clock Divider register
+            CLOCK_DIVIDER: mmio.Mmio(packed struct(u32) {
+                ///  These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
+                CD: u8,
+                ///  This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
+                CLOCK_OFF: u1,
+                padding: u23,
+            }),
+        };
+
+        ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+        pub const UART0 = extern struct {
+            ///  FIFO data register
+            FIFO: mmio.Mmio(packed struct(u32) {
+                ///  UART 0 accesses FIFO via this register.
+                RXFIFO_RD_BYTE: u8,
+                padding: u24,
+            }),
+            ///  Raw interrupt status
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
+                RXFIFO_FULL_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
+                TXFIFO_EMPTY_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a parity error in the data.
+                PARITY_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a data frame error .
+                FRM_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
+                RXFIFO_OVF_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
+                DSR_CHG_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
+                CTS_CHG_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
+                BRK_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
+                RXFIFO_TOUT_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
+                SW_XON_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
+                SW_XOFF_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
+                GLITCH_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.
+                TX_BRK_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.
+                TX_BRK_IDLE_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
+                TX_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
+                RS485_PARITY_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
+                RS485_FRM_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
+                RS485_CLASH_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
+                AT_CMD_CHAR_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
+                WAKEUP_INT_RAW: u1,
+                padding: u12,
+            }),
+            ///  Masked interrupt status
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+                RXFIFO_FULL_INT_ST: u1,
+                ///  This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.
+                TXFIFO_EMPTY_INT_ST: u1,
+                ///  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+                PARITY_ERR_INT_ST: u1,
+                ///  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+                FRM_ERR_INT_ST: u1,
+                ///  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+                RXFIFO_OVF_INT_ST: u1,
+                ///  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+                DSR_CHG_INT_ST: u1,
+                ///  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+                CTS_CHG_INT_ST: u1,
+                ///  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+                BRK_DET_INT_ST: u1,
+                ///  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+                RXFIFO_TOUT_INT_ST: u1,
+                ///  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+                SW_XON_INT_ST: u1,
+                ///  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+                SW_XOFF_INT_ST: u1,
+                ///  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+                GLITCH_DET_INT_ST: u1,
+                ///  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+                TX_BRK_DONE_INT_ST: u1,
+                ///  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
+                TX_BRK_IDLE_DONE_INT_ST: u1,
+                ///  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+                TX_DONE_INT_ST: u1,
+                ///  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
+                RS485_PARITY_ERR_INT_ST: u1,
+                ///  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
+                RS485_FRM_ERR_INT_ST: u1,
+                ///  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+                RS485_CLASH_INT_ST: u1,
+                ///  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
+                AT_CMD_CHAR_DET_INT_ST: u1,
+                ///  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+                WAKEUP_INT_ST: u1,
+                padding: u12,
+            }),
+            ///  Interrupt enable bits
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  This is the enable bit for rxfifo_full_int_st register.
+                RXFIFO_FULL_INT_ENA: u1,
+                ///  This is the enable bit for txfifo_empty_int_st register.
+                TXFIFO_EMPTY_INT_ENA: u1,
+                ///  This is the enable bit for parity_err_int_st register.
+                PARITY_ERR_INT_ENA: u1,
+                ///  This is the enable bit for frm_err_int_st register.
+                FRM_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rxfifo_ovf_int_st register.
+                RXFIFO_OVF_INT_ENA: u1,
+                ///  This is the enable bit for dsr_chg_int_st register.
+                DSR_CHG_INT_ENA: u1,
+                ///  This is the enable bit for cts_chg_int_st register.
+                CTS_CHG_INT_ENA: u1,
+                ///  This is the enable bit for brk_det_int_st register.
+                BRK_DET_INT_ENA: u1,
+                ///  This is the enable bit for rxfifo_tout_int_st register.
+                RXFIFO_TOUT_INT_ENA: u1,
+                ///  This is the enable bit for sw_xon_int_st register.
+                SW_XON_INT_ENA: u1,
+                ///  This is the enable bit for sw_xoff_int_st register.
+                SW_XOFF_INT_ENA: u1,
+                ///  This is the enable bit for glitch_det_int_st register.
+                GLITCH_DET_INT_ENA: u1,
+                ///  This is the enable bit for tx_brk_done_int_st register.
+                TX_BRK_DONE_INT_ENA: u1,
+                ///  This is the enable bit for tx_brk_idle_done_int_st register.
+                TX_BRK_IDLE_DONE_INT_ENA: u1,
+                ///  This is the enable bit for tx_done_int_st register.
+                TX_DONE_INT_ENA: u1,
+                ///  This is the enable bit for rs485_parity_err_int_st register.
+                RS485_PARITY_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rs485_parity_err_int_st register.
+                RS485_FRM_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rs485_clash_int_st register.
+                RS485_CLASH_INT_ENA: u1,
+                ///  This is the enable bit for at_cmd_char_det_int_st register.
+                AT_CMD_CHAR_DET_INT_ENA: u1,
+                ///  This is the enable bit for uart_wakeup_int_st register.
+                WAKEUP_INT_ENA: u1,
+                padding: u12,
+            }),
+            ///  Interrupt clear bits
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the rxfifo_full_int_raw interrupt.
+                RXFIFO_FULL_INT_CLR: u1,
+                ///  Set this bit to clear txfifo_empty_int_raw interrupt.
+                TXFIFO_EMPTY_INT_CLR: u1,
+                ///  Set this bit to clear parity_err_int_raw interrupt.
+                PARITY_ERR_INT_CLR: u1,
+                ///  Set this bit to clear frm_err_int_raw interrupt.
+                FRM_ERR_INT_CLR: u1,
+                ///  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+                RXFIFO_OVF_INT_CLR: u1,
+                ///  Set this bit to clear the dsr_chg_int_raw interrupt.
+                DSR_CHG_INT_CLR: u1,
+                ///  Set this bit to clear the cts_chg_int_raw interrupt.
+                CTS_CHG_INT_CLR: u1,
+                ///  Set this bit to clear the brk_det_int_raw interrupt.
+                BRK_DET_INT_CLR: u1,
+                ///  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+                RXFIFO_TOUT_INT_CLR: u1,
+                ///  Set this bit to clear the sw_xon_int_raw interrupt.
+                SW_XON_INT_CLR: u1,
+                ///  Set this bit to clear the sw_xoff_int_raw interrupt.
+                SW_XOFF_INT_CLR: u1,
+                ///  Set this bit to clear the glitch_det_int_raw interrupt.
+                GLITCH_DET_INT_CLR: u1,
+                ///  Set this bit to clear the tx_brk_done_int_raw interrupt..
+                TX_BRK_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+                TX_BRK_IDLE_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the tx_done_int_raw interrupt.
+                TX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+                RS485_PARITY_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+                RS485_FRM_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_clash_int_raw interrupt.
+                RS485_CLASH_INT_CLR: u1,
+                ///  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+                AT_CMD_CHAR_DET_INT_CLR: u1,
+                ///  Set this bit to clear the uart_wakeup_int_raw interrupt.
+                WAKEUP_INT_CLR: u1,
+                padding: u12,
+            }),
+            ///  Clock divider configuration
+            CLKDIV: mmio.Mmio(packed struct(u32) {
+                ///  The integral part of the frequency divider factor.
+                CLKDIV: u12,
+                reserved20: u8,
+                ///  The decimal part of the frequency divider factor.
+                FRAG: u4,
+                padding: u8,
+            }),
+            ///  Rx Filter configuration
+            RX_FILT: mmio.Mmio(packed struct(u32) {
+                ///  when input pulse width is lower than this value, the pulse is ignored.
+                GLITCH_FILT: u8,
+                ///  Set this bit to enable Rx signal filter.
+                GLITCH_FILT_EN: u1,
+                padding: u23,
+            }),
+            ///  UART status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Stores the byte number of valid data in Rx-FIFO.
+                RXFIFO_CNT: u10,
+                reserved13: u3,
+                ///  The register represent the level value of the internal uart dsr signal.
+                DSRN: u1,
+                ///  This register represent the level value of the internal uart cts signal.
+                CTSN: u1,
+                ///  This register represent the level value of the internal uart rxd signal.
+                RXD: u1,
+                ///  Stores the byte number of data in Tx-FIFO.
+                TXFIFO_CNT: u10,
+                reserved29: u3,
+                ///  This bit represents the level of the internal uart dtr signal.
+                DTRN: u1,
+                ///  This bit represents the level of the internal uart rts signal.
+                RTSN: u1,
+                ///  This bit represents the level of the internal uart txd signal.
+                TXD: u1,
+            }),
+            ///  a
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the parity check mode.
+                PARITY: u1,
+                ///  Set this bit to enable uart parity check.
+                PARITY_EN: u1,
+                ///  This register is used to set the length of data.
+                BIT_NUM: u2,
+                ///  This register is used to set the length of stop bit.
+                STOP_BIT_NUM: u2,
+                ///  This register is used to configure the software rts signal which is used in software flow control.
+                SW_RTS: u1,
+                ///  This register is used to configure the software dtr signal which is used in software flow control.
+                SW_DTR: u1,
+                ///  Set this bit to enbale transmitter to send NULL when the process of sending data is done.
+                TXD_BRK: u1,
+                ///  Set this bit to enable IrDA loopback mode.
+                IRDA_DPLX: u1,
+                ///  This is the start enable bit for IrDA transmitter.
+                IRDA_TX_EN: u1,
+                ///  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
+                IRDA_WCTL: u1,
+                ///  Set this bit to invert the level of IrDA transmitter.
+                IRDA_TX_INV: u1,
+                ///  Set this bit to invert the level of IrDA receiver.
+                IRDA_RX_INV: u1,
+                ///  Set this bit to enable uart loopback test mode.
+                LOOPBACK: u1,
+                ///  Set this bit to enable flow control function for transmitter.
+                TX_FLOW_EN: u1,
+                ///  Set this bit to enable IrDA protocol.
+                IRDA_EN: u1,
+                ///  Set this bit to reset the uart receive-FIFO.
+                RXFIFO_RST: u1,
+                ///  Set this bit to reset the uart transmit-FIFO.
+                TXFIFO_RST: u1,
+                ///  Set this bit to inverse the level value of uart rxd signal.
+                RXD_INV: u1,
+                ///  Set this bit to inverse the level value of uart cts signal.
+                CTS_INV: u1,
+                ///  Set this bit to inverse the level value of uart dsr signal.
+                DSR_INV: u1,
+                ///  Set this bit to inverse the level value of uart txd signal.
+                TXD_INV: u1,
+                ///  Set this bit to inverse the level value of uart rts signal.
+                RTS_INV: u1,
+                ///  Set this bit to inverse the level value of uart dtr signal.
+                DTR_INV: u1,
+                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                ///  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.
+                ERR_WR_MASK: u1,
+                ///  This is the enable bit for detecting baudrate.
+                AUTOBAUD_EN: u1,
+                ///  UART memory clock gate enable signal.
+                MEM_CLK_EN: u1,
+                padding: u3,
+            }),
+            ///  Configuration register 1
+            CONF1: mmio.Mmio(packed struct(u32) {
+                ///  It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
+                RXFIFO_FULL_THRHD: u9,
+                ///  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
+                TXFIFO_EMPTY_THRHD: u9,
+                ///  Disable UART Rx data overflow detect.
+                DIS_RX_DAT_OVF: u1,
+                ///  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+                RX_TOUT_FLOW_DIS: u1,
+                ///  This is the flow enable bit for UART receiver.
+                RX_FLOW_EN: u1,
+                ///  This is the enble bit for uart receiver's timeout function.
+                RX_TOUT_EN: u1,
+                padding: u10,
+            }),
+            ///  Autobaud minimum low pulse duration register
+            LOWPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
+                MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud minimum high pulse duration register
+            HIGHPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
+                MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud edge change count register
+            RXD_CNT: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the count of rxd edge change. It is used in baud rate-detect process.
+                RXD_EDGE_CNT: u10,
+                padding: u22,
+            }),
+            ///  Software flow-control configuration
+            FLOW_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
+                SW_FLOW_CON_EN: u1,
+                ///  Set this bit to remove flow control char from the received data.
+                XONOFF_DEL: u1,
+                ///  Set this bit to enable the transmitter to go on sending data.
+                FORCE_XON: u1,
+                ///  Set this bit to stop the transmitter from sending data.
+                FORCE_XOFF: u1,
+                ///  Set this bit to send Xon char. It is cleared by hardware automatically.
+                SEND_XON: u1,
+                ///  Set this bit to send Xoff char. It is cleared by hardware automatically.
+                SEND_XOFF: u1,
+                padding: u26,
+            }),
+            ///  Sleep-mode configuration
+            SLEEP_CONF: mmio.Mmio(packed struct(u32) {
+                ///  The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
+                ACTIVE_THRESHOLD: u10,
+                padding: u22,
+            }),
+            ///  Software flow-control character configuration
+            SWFC_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
+                XOFF_THRESHOLD: u9,
+                ///  This register stores the Xoff flow control char.
+                XOFF_CHAR: u8,
+                padding: u15,
+            }),
+            ///  Software flow-control character configuration
+            SWFC_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
+                XON_THRESHOLD: u9,
+                ///  This register stores the Xon flow control char.
+                XON_CHAR: u8,
+                padding: u15,
+            }),
+            ///  Tx Break character configuration
+            TXBRK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
+                TX_BRK_NUM: u8,
+                padding: u24,
+            }),
+            ///  Frame-end idle configuration
+            IDLE_CONF: mmio.Mmio(packed struct(u32) {
+                ///  It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
+                RX_IDLE_THRHD: u10,
+                ///  This register is used to configure the duration time between transfers.
+                TX_IDLE_NUM: u10,
+                padding: u12,
+            }),
+            ///  RS485 mode configuration
+            RS485_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to choose the rs485 mode.
+                RS485_EN: u1,
+                ///  Set this bit to delay the stop bit by 1 bit.
+                DL0_EN: u1,
+                ///  Set this bit to delay the stop bit by 1 bit.
+                DL1_EN: u1,
+                ///  Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
+                RS485TX_RX_EN: u1,
+                ///  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+                RS485RXBY_TX_EN: u1,
+                ///  This register is used to delay the receiver's internal data signal.
+                RS485_RX_DLY_NUM: u1,
+                ///  This register is used to delay the transmitter's internal data signal.
+                RS485_TX_DLY_NUM: u4,
+                padding: u22,
+            }),
+            ///  Pre-sequence timing configuration
+            AT_CMD_PRECNT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the idle duration time before the first at_cmd is received by receiver.
+                PRE_IDLE_NUM: u16,
+                padding: u16,
+            }),
+            ///  Post-sequence timing configuration
+            AT_CMD_POSTCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the duration time between the last at_cmd and the next data.
+                POST_IDLE_NUM: u16,
+                padding: u16,
+            }),
+            ///  Timeout configuration
+            AT_CMD_GAPTOUT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the duration time between the at_cmd chars.
+                RX_GAP_TOUT: u16,
+                padding: u16,
+            }),
+            ///  AT escape sequence detection configuration
+            AT_CMD_CHAR: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the content of at_cmd char.
+                AT_CMD_CHAR: u8,
+                ///  This register is used to configure the num of continuous at_cmd chars received by receiver.
+                CHAR_NUM: u8,
+                padding: u16,
+            }),
+            ///  UART threshold and allocation configuration
+            MEM_CONF: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
+                RX_SIZE: u3,
+                ///  This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
+                TX_SIZE: u3,
+                ///  This register is used to configure the maximum amount of data that can be received when hardware flow control works.
+                RX_FLOW_THRHD: u9,
+                ///  This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
+                RX_TOUT_THRHD: u10,
+                ///  Set this bit to force power down UART memory.
+                MEM_FORCE_PD: u1,
+                ///  Set this bit to force power up UART memory.
+                MEM_FORCE_PU: u1,
+                padding: u4,
+            }),
+            ///  Tx-FIFO write and read offset address.
+            MEM_TX_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
+                APB_TX_WADDR: u10,
+                reserved11: u1,
+                ///  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
+                TX_RADDR: u10,
+                padding: u11,
+            }),
+            ///  Rx-FIFO write and read offset address.
+            MEM_RX_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+                APB_RX_RADDR: u10,
+                reserved11: u1,
+                ///  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+                RX_WADDR: u10,
+                padding: u11,
+            }),
+            ///  UART transmit and receive status.
+            FSM_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This is the status register of receiver.
+                ST_URX_OUT: u4,
+                ///  This is the status register of transmitter.
+                ST_UTX_OUT: u4,
+                padding: u24,
+            }),
+            ///  Autobaud high pulse register
+            POSPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
+                POSEDGE_MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud low pulse register
+            NEGPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
+                NEGEDGE_MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  UART core clock configuration
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  The denominator of the frequency divider factor.
+                SCLK_DIV_B: u6,
+                ///  The numerator of the frequency divider factor.
+                SCLK_DIV_A: u6,
+                ///  The integral part of the frequency divider factor.
+                SCLK_DIV_NUM: u8,
+                ///  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+                SCLK_SEL: u2,
+                ///  Set this bit to enable UART Tx/Rx clock.
+                SCLK_EN: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+                RST_CORE: u1,
+                ///  Set this bit to enable UART Tx clock.
+                TX_SCLK_EN: u1,
+                ///  Set this bit to enable UART Rx clock.
+                RX_SCLK_EN: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Tx.
+                TX_RST_CORE: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Rx.
+                RX_RST_CORE: u1,
+                padding: u4,
+            }),
+            ///  UART Version register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  This is the version register.
+                DATE: u32,
+            }),
+            ///  UART ID register
+            ID: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the uart_id.
+                ID: u30,
+                ///  This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
+                HIGH_SPEED: u1,
+                ///  Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
+                REG_UPDATE: u1,
+            }),
+        };
+
+        ///  Full-speed USB Serial/JTAG Controller
+        pub const USB_DEVICE = extern struct {
+            ///  USB_DEVICE_EP1_REG.
+            EP1: mmio.Mmio(packed struct(u32) {
+                ///  Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
+                RDWR_BYTE: u8,
+                padding: u24,
+            }),
+            ///  USB_DEVICE_EP1_CONF_REG.
+            EP1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+                WR_DONE: u1,
+                ///  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
+                SERIAL_IN_EP_DATA_FREE: u1,
+                ///  1'b1: Indicate there is data in UART Rx FIFO.
+                SERIAL_OUT_EP_DATA_AVAIL: u1,
+                padding: u29,
+            }),
+            ///  USB_DEVICE_INT_RAW_REG.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
+                JTAG_IN_FLUSH_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when SOF frame is received.
+                SOF_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
+                SERIAL_OUT_RECV_PKT_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+                SERIAL_IN_EMPTY_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when pid error is detected.
+                PID_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when CRC5 error is detected.
+                CRC5_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when CRC16 error is detected.
+                CRC16_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when stuff error is detected.
+                STUFF_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
+                IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when usb bus reset is detected.
+                USB_BUS_RESET_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
+                OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
+                OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_ST_REG.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+                SOF_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_ENA_REG.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+                SOF_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_CLR_REG.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+                SOF_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_CONF0_REG.
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  Select internal/external PHY
+                PHY_SEL: u1,
+                ///  Enable software control USB D+ D- exchange
+                EXCHG_PINS_OVERRIDE: u1,
+                ///  USB D+ D- exchange
+                EXCHG_PINS: u1,
+                ///  Control single-end input high threshold,1.76V to 2V, step 80mV
+                VREFH: u2,
+                ///  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+                VREFL: u2,
+                ///  Enable software control input threshold
+                VREF_OVERRIDE: u1,
+                ///  Enable software control USB D+ D- pullup pulldown
+                PAD_PULL_OVERRIDE: u1,
+                ///  Control USB D+ pull up.
+                DP_PULLUP: u1,
+                ///  Control USB D+ pull down.
+                DP_PULLDOWN: u1,
+                ///  Control USB D- pull up.
+                DM_PULLUP: u1,
+                ///  Control USB D- pull down.
+                DM_PULLDOWN: u1,
+                ///  Control pull up value.
+                PULLUP_VALUE: u1,
+                ///  Enable USB pad function.
+                USB_PAD_ENABLE: u1,
+                padding: u17,
+            }),
+            ///  USB_DEVICE_TEST_REG.
+            TEST: mmio.Mmio(packed struct(u32) {
+                ///  Enable test of the USB pad
+                ENABLE: u1,
+                ///  USB pad oen in test
+                USB_OE: u1,
+                ///  USB D+ tx value in test
+                TX_DP: u1,
+                ///  USB D- tx value in test
+                TX_DM: u1,
+                padding: u28,
+            }),
+            ///  USB_DEVICE_JFIFO_ST_REG.
+            JFIFO_ST: mmio.Mmio(packed struct(u32) {
+                ///  JTAT in fifo counter.
+                IN_FIFO_CNT: u2,
+                ///  1: JTAG in fifo is empty.
+                IN_FIFO_EMPTY: u1,
+                ///  1: JTAG in fifo is full.
+                IN_FIFO_FULL: u1,
+                ///  JTAT out fifo counter.
+                OUT_FIFO_CNT: u2,
+                ///  1: JTAG out fifo is empty.
+                OUT_FIFO_EMPTY: u1,
+                ///  1: JTAG out fifo is full.
+                OUT_FIFO_FULL: u1,
+                ///  Write 1 to reset JTAG in fifo.
+                IN_FIFO_RESET: u1,
+                ///  Write 1 to reset JTAG out fifo.
+                OUT_FIFO_RESET: u1,
+                padding: u22,
+            }),
+            ///  USB_DEVICE_FRAM_NUM_REG.
+            FRAM_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Frame index of received SOF frame.
+                SOF_FRAME_INDEX: u11,
+                padding: u21,
+            }),
+            ///  USB_DEVICE_IN_EP0_ST_REG.
+            IN_EP0_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 0.
+                IN_EP0_STATE: u2,
+                ///  Write data address of IN endpoint 0.
+                IN_EP0_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 0.
+                IN_EP0_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP1_ST_REG.
+            IN_EP1_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 1.
+                IN_EP1_STATE: u2,
+                ///  Write data address of IN endpoint 1.
+                IN_EP1_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 1.
+                IN_EP1_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP2_ST_REG.
+            IN_EP2_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 2.
+                IN_EP2_STATE: u2,
+                ///  Write data address of IN endpoint 2.
+                IN_EP2_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 2.
+                IN_EP2_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP3_ST_REG.
+            IN_EP3_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 3.
+                IN_EP3_STATE: u2,
+                ///  Write data address of IN endpoint 3.
+                IN_EP3_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 3.
+                IN_EP3_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_OUT_EP0_ST_REG.
+            OUT_EP0_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 0.
+                OUT_EP0_STATE: u2,
+                ///  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+                OUT_EP0_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 0.
+                OUT_EP0_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_OUT_EP1_ST_REG.
+            OUT_EP1_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 1.
+                OUT_EP1_STATE: u2,
+                ///  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+                OUT_EP1_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 1.
+                OUT_EP1_RD_ADDR: u7,
+                ///  Data count in OUT endpoint 1 when one packet is received.
+                OUT_EP1_REC_DATA_CNT: u7,
+                padding: u9,
+            }),
+            ///  USB_DEVICE_OUT_EP2_ST_REG.
+            OUT_EP2_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 2.
+                OUT_EP2_STATE: u2,
+                ///  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+                OUT_EP2_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 2.
+                OUT_EP2_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_MISC_CONF_REG.
+            MISC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  USB_DEVICE_MEM_CONF_REG.
+            MEM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  1: power down usb memory.
+                USB_MEM_PD: u1,
+                ///  1: Force clock on for usb memory.
+                USB_MEM_CLK_EN: u1,
+                padding: u30,
+            }),
+            reserved128: [52]u8,
+            ///  USB_DEVICE_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  register version.
+                DATE: u32,
+            }),
+        };
+
+        ///  Universal Host Controller Interface
+        pub const UHCI0 = extern struct {
+            ///  a
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  Write 1, then write 0 to this bit to reset decode state machine.
+                TX_RST: u1,
+                ///  Write 1, then write 0 to this bit to reset encode state machine.
+                RX_RST: u1,
+                ///  Set this bit to link up HCI and UART0.
+                UART0_CE: u1,
+                ///  Set this bit to link up HCI and UART1.
+                UART1_CE: u1,
+                reserved5: u1,
+                ///  Set this bit to separate the data frame using a special char.
+                SEPER_EN: u1,
+                ///  Set this bit to encode the data packet with a formatting header.
+                HEAD_EN: u1,
+                ///  Set this bit to enable UHCI to receive the 16 bit CRC.
+                CRC_REC_EN: u1,
+                ///  If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
+                UART_IDLE_EOF_EN: u1,
+                ///  If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
+                LEN_EOF_EN: u1,
+                ///  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
+                ENCODE_CRC_EN: u1,
+                ///  1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                ///  If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
+                UART_RX_BRK_EOF_EN: u1,
+                padding: u19,
+            }),
+            ///  a
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_RAW: u1,
+                ///  a
+                TX_START_INT_RAW: u1,
+                ///  a
+                RX_HUNG_INT_RAW: u1,
+                ///  a
+                TX_HUNG_INT_RAW: u1,
+                ///  a
+                SEND_S_REG_Q_INT_RAW: u1,
+                ///  a
+                SEND_A_REG_Q_INT_RAW: u1,
+                ///  This is the interrupt raw bit. Triggered when there are some errors in EOF in the
+                OUT_EOF_INT_RAW: u1,
+                ///  Soft control int raw bit.
+                APP_CTRL0_INT_RAW: u1,
+                ///  Soft control int raw bit.
+                APP_CTRL1_INT_RAW: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_ST: u1,
+                ///  a
+                TX_START_INT_ST: u1,
+                ///  a
+                RX_HUNG_INT_ST: u1,
+                ///  a
+                TX_HUNG_INT_ST: u1,
+                ///  a
+                SEND_S_REG_Q_INT_ST: u1,
+                ///  a
+                SEND_A_REG_Q_INT_ST: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_ST: u1,
+                ///  a
+                APP_CTRL0_INT_ST: u1,
+                ///  a
+                APP_CTRL1_INT_ST: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_ENA: u1,
+                ///  a
+                TX_START_INT_ENA: u1,
+                ///  a
+                RX_HUNG_INT_ENA: u1,
+                ///  a
+                TX_HUNG_INT_ENA: u1,
+                ///  a
+                SEND_S_REG_Q_INT_ENA: u1,
+                ///  a
+                SEND_A_REG_Q_INT_ENA: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_ENA: u1,
+                ///  a
+                APP_CTRL0_INT_ENA: u1,
+                ///  a
+                APP_CTRL1_INT_ENA: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_CLR: u1,
+                ///  a
+                TX_START_INT_CLR: u1,
+                ///  a
+                RX_HUNG_INT_CLR: u1,
+                ///  a
+                TX_HUNG_INT_CLR: u1,
+                ///  a
+                SEND_S_REG_Q_INT_CLR: u1,
+                ///  a
+                SEND_A_REG_Q_INT_CLR: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_CLR: u1,
+                ///  a
+                APP_CTRL0_INT_CLR: u1,
+                ///  a
+                APP_CTRL1_INT_CLR: u1,
+                padding: u23,
+            }),
+            ///  a
+            CONF1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                CHECK_SUM_EN: u1,
+                ///  a
+                CHECK_SEQ_EN: u1,
+                ///  a
+                CRC_DISABLE: u1,
+                ///  a
+                SAVE_HEAD: u1,
+                ///  a
+                TX_CHECK_SUM_RE: u1,
+                ///  a
+                TX_ACK_NUM_RE: u1,
+                reserved7: u1,
+                ///  a
+                WAIT_SW_START: u1,
+                ///  a
+                SW_START: u1,
+                padding: u23,
+            }),
+            ///  a
+            STATE0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_ERR_CAUSE: u3,
+                ///  a
+                DECODE_STATE: u3,
+                padding: u26,
+            }),
+            ///  a
+            STATE1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ENCODE_STATE: u3,
+                padding: u29,
+            }),
+            ///  a
+            ESCAPE_CONF: mmio.Mmio(packed struct(u32) {
+                ///  a
+                TX_C0_ESC_EN: u1,
+                ///  a
+                TX_DB_ESC_EN: u1,
+                ///  a
+                TX_11_ESC_EN: u1,
+                ///  a
+                TX_13_ESC_EN: u1,
+                ///  a
+                RX_C0_ESC_EN: u1,
+                ///  a
+                RX_DB_ESC_EN: u1,
+                ///  a
+                RX_11_ESC_EN: u1,
+                ///  a
+                RX_13_ESC_EN: u1,
+                padding: u24,
+            }),
+            ///  a
+            HUNG_CONF: mmio.Mmio(packed struct(u32) {
+                ///  a
+                TXFIFO_TIMEOUT: u8,
+                ///  a
+                TXFIFO_TIMEOUT_SHIFT: u3,
+                ///  a
+                TXFIFO_TIMEOUT_ENA: u1,
+                ///  a
+                RXFIFO_TIMEOUT: u8,
+                ///  a
+                RXFIFO_TIMEOUT_SHIFT: u3,
+                ///  a
+                RXFIFO_TIMEOUT_ENA: u1,
+                padding: u8,
+            }),
+            ///  a
+            ACK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ACK_NUM: u3,
+                ///  a
+                LOAD: u1,
+                padding: u28,
+            }),
+            ///  a
+            RX_HEAD: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_HEAD: u32,
+            }),
+            ///  a
+            QUICK_SENT: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SINGLE_SEND_NUM: u3,
+                ///  a
+                SINGLE_SEND_EN: u1,
+                ///  a
+                ALWAYS_SEND_NUM: u3,
+                ///  a
+                ALWAYS_SEND_EN: u1,
+                padding: u24,
+            }),
+            ///  a
+            REG_Q0_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q0_WORD0: u32,
+            }),
+            ///  a
+            REG_Q0_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q0_WORD1: u32,
+            }),
+            ///  a
+            REG_Q1_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q1_WORD0: u32,
+            }),
+            ///  a
+            REG_Q1_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q1_WORD1: u32,
+            }),
+            ///  a
+            REG_Q2_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q2_WORD0: u32,
+            }),
+            ///  a
+            REG_Q2_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q2_WORD1: u32,
+            }),
+            ///  a
+            REG_Q3_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q3_WORD0: u32,
+            }),
+            ///  a
+            REG_Q3_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q3_WORD1: u32,
+            }),
+            ///  a
+            REG_Q4_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q4_WORD0: u32,
+            }),
+            ///  a
+            REG_Q4_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q4_WORD1: u32,
+            }),
+            ///  a
+            REG_Q5_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q5_WORD0: u32,
+            }),
+            ///  a
+            REG_Q5_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q5_WORD1: u32,
+            }),
+            ///  a
+            REG_Q6_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q6_WORD0: u32,
+            }),
+            ///  a
+            REG_Q6_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q6_WORD1: u32,
+            }),
+            ///  a
+            ESC_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEPER_CHAR: u8,
+                ///  a
+                SEPER_ESC_CHAR0: u8,
+                ///  a
+                SEPER_ESC_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ0: u8,
+                ///  a
+                ESC_SEQ0_CHAR0: u8,
+                ///  a
+                ESC_SEQ0_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF2: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ1: u8,
+                ///  a
+                ESC_SEQ1_CHAR0: u8,
+                ///  a
+                ESC_SEQ1_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF3: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ2: u8,
+                ///  a
+                ESC_SEQ2_CHAR0: u8,
+                ///  a
+                ESC_SEQ2_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            PKT_THRES: mmio.Mmio(packed struct(u32) {
+                ///  a
+                PKT_THRS: u13,
+                padding: u19,
+            }),
+            ///  a
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  a
+                DATE: u32,
+            }),
+        };
+    };
+};
diff --git a/src/cpus.zig b/src/cpus.zig
new file mode 100644
index 0000000..b087d90
--- /dev/null
+++ b/src/cpus.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Cpu{
+    .name = "Espressif RISC-V",
+    .source = .{
+        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
+    },
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
diff --git a/src/package/esp32-c3.zig b/src/cpus/espressif-riscv.zig
similarity index 72%
rename from src/package/esp32-c3.zig
rename to src/cpus/espressif-riscv.zig
index 0ab4944..e20072d 100644
--- a/src/package/esp32-c3.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -1,7 +1,41 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const root = @import("root");
 
-pub const registers = @import("registers.zig").registers;
+pub const StatusRegister = enum(u8) {
+    // machine information
+    mvendorid,
+    marchid,
+    mimpid,
+    mhartid,
+
+    // machine trap setup
+    mstatus,
+    misa,
+    mtvec,
+};
+
+pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn cli() void {
+    clearStatusBit(.mstatus, 0x08);
+}
+
+pub inline fn sei() void {
+    setStatusBit(.mstatus, 0x08);
+}
 
 pub const startup_logic = struct {
     comptime {
@@ -35,7 +69,7 @@ pub const startup_logic = struct {
         );
         asm volatile ("la gp, __global_pointer$");
         microzig.cpu.setStatusBit(.mtvec, microzig.config.end_of_stack);
-        microzig.initializeSystemMemories();
+        root.initialize_system_memories();
         microzig_main();
     }
 
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 0518c53..5ee1eef 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -1,23 +1,28 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const TIMG0 = peripherals.TIMG0;
+const RTC_CNTL = peripherals.RTC_CNTL;
+const INTERRUPT_CORE0 = peripherals.INTERRUPT_CORE0;
+const GPIO = peripherals.GPIO;
 
 const dogfood: u32 = 0x50D83AA1;
 const super_dogfood: u32 = 0x8F1D312A;
 
 pub fn main() !void {
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.TIMG0.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = 0;
+    TIMG0.WDTWPROTECT.raw = dogfood;
+    TIMG0.WDTCONFIG0.raw = 0;
+    TIMG0.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.RTC_CNTL.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    RTC_CNTL.WDTCONFIG0.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
-    microzig.chip.registers.RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = 0;
+    RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    RTC_CNTL.SWD_WPROTECT.raw = 0;
 
-    microzig.chip.registers.INTERRUPT_CORE0.CPU_INT_ENABLE.* = 0;
+    INTERRUPT_CORE0.CPU_INT_ENABLE.raw = 0;
 
     microzig.hal.gpio.init(LED_R_PIN, .{
         .direction = .output,
@@ -35,15 +40,15 @@ pub fn main() !void {
     microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
     while (true) {
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
-        microzig.debug.busySleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
     }
 }
 
diff --git a/src/hal/root.zig b/src/hals/ESP32_C3.zig
similarity index 57%
rename from src/hal/root.zig
rename to src/hals/ESP32_C3.zig
index d87dab8..516ed15 100644
--- a/src/hal/root.zig
+++ b/src/hals/ESP32_C3.zig
@@ -1,16 +1,9 @@
 const std = @import("std");
 const microzig = @import("microzig");
-const regz = microzig.chip.registers;
+const peripherals = microzig.chip.peripherals;
+const GPIO = peripherals.GPIO;
 
 pub const gpio = struct {
-    fn getRegNamed(comptime fld: []const u8) @TypeOf(@field(regz.GPIO, fld)) {
-        return @field(regz.GPIO, fld);
-    }
-
-    fn getReg(comptime template: []const u8, comptime pin: comptime_int) @TypeOf(@field(regz.GPIO, std.fmt.comptimePrint(template, .{pin}))) {
-        return getRegNamed(comptime std.fmt.comptimePrint(template, .{pin}));
-    }
-
     fn assertRange(comptime p: comptime_int) void {
         if (p < 0 or p >= 21)
             @compileError(std.fmt.comptimePrint("GPIO {} does not exist. GPIO pins can be between 0 and 21", .{p}));
@@ -19,29 +12,29 @@ pub const gpio = struct {
     pub const Config = struct {
         function: u8 = 0x80,
         invert_function: bool = false,
-        direction: microzig.gpio.Direction,
+        direction: microzig.core.experimental.gpio.Direction,
         direct_io: bool = false,
         invert_direct_io: bool = false,
     };
 
     pub fn init(comptime pin: comptime_int, comptime config: Config) void {
         assertRange(pin);
-        getReg("FUNC{}_OUT_SEL_CFG", pin).modify(.{
+        GPIO.FUNC_OUT_SEL_CFG[pin].modify(.{
             .OUT_SEL = config.function,
             .INV_SEL = @boolToInt(config.invert_function),
             .OEN_SEL = @boolToInt(config.direct_io),
             .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
         });
         switch (config.direction) {
-            .input => microzig.chip.registers.GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
-            .output => microzig.chip.registers.GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
+            .input => GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
+            .output => GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
         }
     }
 };
 
 pub const uart = struct {
-    fn reg(comptime index: comptime_int) @TypeOf(@field(regz, std.fmt.comptimePrint("UART{}", .{index}))) {
-        return @field(regz, std.fmt.comptimePrint("UART{}", .{index}));
+    fn reg(comptime index: comptime_int) @TypeOf(@field(peripherals, std.fmt.comptimePrint("UART{}", .{index}))) {
+        return @field(peripherals, std.fmt.comptimePrint("UART{}", .{index}));
     }
 
     pub fn write(comptime index: comptime_int, slice: []const u8) void {
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
deleted file mode 100644
index 06d7bc4..0000000
--- a/src/package/espressif-riscv.zig
+++ /dev/null
@@ -1,39 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-pub const StatusRegister = enum(u8) {
-    // machine information
-    mvendorid,
-    marchid,
-    mimpid,
-    mhartid,
-
-    // machine trap setup
-    mstatus,
-    misa,
-    mtvec,
-};
-
-pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn cli() void {
-    clearStatusBit(.mstatus, 0x08);
-}
-
-pub inline fn sei() void {
-    setStatusBit(.mstatus, 0x08);
-}
-
-pub const startup_logic = microzig.chip.startup_logic;
diff --git a/src/package/registers.zig b/src/package/registers.zig
deleted file mode 100644
index 77bed3f..0000000
--- a/src/package/registers.zig
+++ /dev/null
@@ -1,37956 +0,0 @@
-// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz
-// commit: 62e33d0e2175e4c1621e1dbf9f6ac3ec18f6ba38
-//
-// vendor: ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
-// device: ESP32-C3
-// cpu: RV32IMC
-
-pub const registers = struct {
-    /// AES (Advanced Encryption Standard) Accelerator
-    pub const AES = struct {
-        pub const base_address = 0x6003a000;
-
-        /// address: 0x6003a000
-        /// Key material key_0 configure register
-        pub const KEY_0 = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0x6003a004
-        /// Key material key_1 configure register
-        pub const KEY_1 = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x6003a008
-        /// Key material key_2 configure register
-        pub const KEY_2 = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x6003a00c
-        /// Key material key_3 configure register
-        pub const KEY_3 = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x6003a010
-        /// Key material key_4 configure register
-        pub const KEY_4 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x6003a014
-        /// Key material key_5 configure register
-        pub const KEY_5 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x6003a018
-        /// Key material key_6 configure register
-        pub const KEY_6 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x6003a01c
-        /// Key material key_7 configure register
-        pub const KEY_7 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x6003a020
-        /// source text material text_in_0 configure register
-        pub const TEXT_IN_0 = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x6003a024
-        /// source text material text_in_1 configure register
-        pub const TEXT_IN_1 = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x6003a028
-        /// source text material text_in_2 configure register
-        pub const TEXT_IN_2 = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x6003a02c
-        /// source text material text_in_3 configure register
-        pub const TEXT_IN_3 = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x6003a030
-        /// result text material text_out_0 configure register
-        pub const TEXT_OUT_0 = @intToPtr(*volatile u32, base_address + 0x30);
-
-        /// address: 0x6003a034
-        /// result text material text_out_1 configure register
-        pub const TEXT_OUT_1 = @intToPtr(*volatile u32, base_address + 0x34);
-
-        /// address: 0x6003a038
-        /// result text material text_out_2 configure register
-        pub const TEXT_OUT_2 = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x6003a03c
-        /// result text material text_out_3 configure register
-        pub const TEXT_OUT_3 = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x6003a040
-        /// AES Mode register
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x40);
-
-        /// address: 0x6003a044
-        /// AES Endian configure register
-        pub const ENDIAN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44);
-
-        /// address: 0x6003a048
-        /// AES trigger register
-        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48);
-
-        /// address: 0x6003a04c
-        /// AES state register
-        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x4c);
-
-        /// address: 0x6003a050
-        /// The memory that stores initialization vector
-        pub const IV_MEM = @intToPtr(*volatile [16]u8, base_address + 0x50);
-
-        /// address: 0x6003a060
-        /// The memory that stores GCM hash subkey
-        pub const H_MEM = @intToPtr(*volatile [16]u8, base_address + 0x60);
-
-        /// address: 0x6003a070
-        /// The memory that stores J0
-        pub const J0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x70);
-
-        /// address: 0x6003a080
-        /// The memory that stores T0
-        pub const T0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x80);
-
-        /// address: 0x6003a090
-        /// DMA-AES working mode register
-        pub const DMA_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x90);
-
-        /// address: 0x6003a094
-        /// AES cipher block mode register
-        pub const BLOCK_MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x94);
-
-        /// address: 0x6003a098
-        /// AES block number register
-        pub const BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0x98);
-
-        /// address: 0x6003a09c
-        /// Standard incrementing function configure register
-        pub const INC_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x9c);
-
-        /// address: 0x6003a0a0
-        /// Additional Authential Data block number register
-        pub const AAD_BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0xa0);
-
-        /// address: 0x6003a0a4
-        /// AES remainder bit number register
-        pub const REMAINDER_BIT_NUM = @intToPtr(*volatile MmioInt(32, u7), base_address + 0xa4);
-
-        /// address: 0x6003a0a8
-        /// AES continue register
-        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa8);
-
-        /// address: 0x6003a0ac
-        /// AES Interrupt clear register
-        pub const INT_CLEAR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xac);
-
-        /// address: 0x6003a0b0
-        /// AES Interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb0);
-
-        /// address: 0x6003a0b4
-        /// AES version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xb4);
-
-        /// address: 0x6003a0b8
-        /// AES-DMA exit config
-        pub const DMA_EXIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb8);
-    };
-
-    /// Advanced Peripheral Bus Controller
-    pub const APB_CTRL = struct {
-        pub const base_address = 0x60026000;
-
-        /// address: 0x60026000
-        /// APB_CTRL_SYSCLK_CONF_REG
-        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_pre_div_cnt
-            PRE_DIV_CNT: u10,
-            /// reg_clk_320m_en
-            CLK_320M_EN: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            /// reg_rst_tick_cnt
-            RST_TICK_CNT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60026004
-        /// APB_CTRL_TICK_CONF_REG
-        pub const TICK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_xtal_tick_num
-            XTAL_TICK_NUM: u8,
-            /// reg_ck8m_tick_num
-            CK8M_TICK_NUM: u8,
-            /// reg_tick_enable
-            TICK_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60026008
-        /// APB_CTRL_CLK_OUT_EN_REG
-        pub const CLK_OUT_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_clk20_oen
-            CLK20_OEN: u1,
-            /// reg_clk22_oen
-            CLK22_OEN: u1,
-            /// reg_clk44_oen
-            CLK44_OEN: u1,
-            /// reg_clk_bb_oen
-            CLK_BB_OEN: u1,
-            /// reg_clk80_oen
-            CLK80_OEN: u1,
-            /// reg_clk160_oen
-            CLK160_OEN: u1,
-            /// reg_clk_320m_oen
-            CLK_320M_OEN: u1,
-            /// reg_clk_adc_inf_oen
-            CLK_ADC_INF_OEN: u1,
-            /// reg_clk_dac_cpu_oen
-            CLK_DAC_CPU_OEN: u1,
-            /// reg_clk40x_bb_oen
-            CLK40X_BB_OEN: u1,
-            /// reg_clk_xtal_oen
-            CLK_XTAL_OEN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002600c
-        /// APB_CTRL_WIFI_BB_CFG_REG
-        pub const WIFI_BB_CFG = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x60026010
-        /// APB_CTRL_WIFI_BB_CFG_2_REG
-        pub const WIFI_BB_CFG_2 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x60026014
-        /// APB_CTRL_WIFI_CLK_EN_REG
-        pub const WIFI_CLK_EN = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x60026018
-        /// APB_CTRL_WIFI_RST_EN_REG
-        pub const WIFI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wifi_rst
-            WIFI_RST: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002601c
-        /// APB_CTRL_HOST_INF_SEL_REG
-        pub const HOST_INF_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_io_swap
-            PERI_IO_SWAP: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60026020
-        /// APB_CTRL_EXT_MEM_PMS_LOCK_REG
-        pub const EXT_MEM_PMS_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
-
-        /// address: 0x60026028
-        /// APB_CTRL_FLASH_ACE0_ATTR_REG
-        pub const FLASH_ACE0_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x28);
-
-        /// address: 0x6002602c
-        /// APB_CTRL_FLASH_ACE1_ATTR_REG
-        pub const FLASH_ACE1_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x2c);
-
-        /// address: 0x60026030
-        /// APB_CTRL_FLASH_ACE2_ATTR_REG
-        pub const FLASH_ACE2_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x30);
-
-        /// address: 0x60026034
-        /// APB_CTRL_FLASH_ACE3_ATTR_REG
-        pub const FLASH_ACE3_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x34);
-
-        /// address: 0x60026038
-        /// APB_CTRL_FLASH_ACE0_ADDR_REG
-        pub const FLASH_ACE0_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace0_addr_s
-            S: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6002603c
-        /// APB_CTRL_FLASH_ACE1_ADDR_REG
-        pub const FLASH_ACE1_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace1_addr_s
-            S: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x60026040
-        /// APB_CTRL_FLASH_ACE2_ADDR_REG
-        pub const FLASH_ACE2_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace2_addr_s
-            S: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x60026044
-        /// APB_CTRL_FLASH_ACE3_ADDR_REG
-        pub const FLASH_ACE3_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace3_addr_s
-            S: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60026048
-        /// APB_CTRL_FLASH_ACE0_SIZE_REG
-        pub const FLASH_ACE0_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x48);
-
-        /// address: 0x6002604c
-        /// APB_CTRL_FLASH_ACE1_SIZE_REG
-        pub const FLASH_ACE1_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x4c);
-
-        /// address: 0x60026050
-        /// APB_CTRL_FLASH_ACE2_SIZE_REG
-        pub const FLASH_ACE2_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50);
-
-        /// address: 0x60026054
-        /// APB_CTRL_FLASH_ACE3_SIZE_REG
-        pub const FLASH_ACE3_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x54);
-
-        /// address: 0x60026088
-        /// APB_CTRL_SPI_MEM_PMS_CTRL_REG
-        pub const SPI_MEM_PMS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_spi_mem_reject_int
-            SPI_MEM_REJECT_INT: u1,
-            /// reg_spi_mem_reject_clr
-            SPI_MEM_REJECT_CLR: u1,
-            /// reg_spi_mem_reject_cde
-            SPI_MEM_REJECT_CDE: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6002608c
-        /// APB_CTRL_SPI_MEM_REJECT_ADDR_REG
-        pub const SPI_MEM_REJECT_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x60026090
-        /// APB_CTRL_SDIO_CTRL_REG
-        pub const SDIO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sdio_win_access_en
-            SDIO_WIN_ACCESS_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60026094
-        /// APB_CTRL_REDCY_SIG0_REG
-        pub const REDCY_SIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redcy_sig0
-            REDCY_SIG0: u31,
-            /// reg_redcy_andor
-            REDCY_ANDOR: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x60026098
-        /// APB_CTRL_REDCY_SIG1_REG
-        pub const REDCY_SIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redcy_sig1
-            REDCY_SIG1: u31,
-            /// reg_redcy_nandor
-            REDCY_NANDOR: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6002609c
-        /// APB_CTRL_FRONT_END_MEM_PD_REG
-        pub const FRONT_END_MEM_PD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_agc_mem_force_pu
-            AGC_MEM_FORCE_PU: u1,
-            /// reg_agc_mem_force_pd
-            AGC_MEM_FORCE_PD: u1,
-            /// reg_pbus_mem_force_pu
-            PBUS_MEM_FORCE_PU: u1,
-            /// reg_pbus_mem_force_pd
-            PBUS_MEM_FORCE_PD: u1,
-            /// reg_dc_mem_force_pu
-            DC_MEM_FORCE_PU: u1,
-            /// reg_dc_mem_force_pd
-            DC_MEM_FORCE_PD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600260a0
-        /// APB_CTRL_RETENTION_CTRL_REG
-        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_retention_link_addr
-            RETENTION_LINK_ADDR: u27,
-            /// reg_nobypass_cpu_iso_rst
-            NOBYPASS_CPU_ISO_RST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600260a4
-        /// APB_CTRL_CLKGATE_FORCE_ON_REG
-        pub const CLKGATE_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_clkgate_force_on
-            ROM_CLKGATE_FORCE_ON: u2,
-            /// reg_sram_clkgate_force_on
-            SRAM_CLKGATE_FORCE_ON: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600260a8
-        /// APB_CTRL_MEM_POWER_DOWN_REG
-        pub const MEM_POWER_DOWN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_power_down
-            ROM_POWER_DOWN: u2,
-            /// reg_sram_power_down
-            SRAM_POWER_DOWN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600260ac
-        /// APB_CTRL_MEM_POWER_UP_REG
-        pub const MEM_POWER_UP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_power_up
-            ROM_POWER_UP: u2,
-            /// reg_sram_power_up
-            SRAM_POWER_UP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600260b0
-        /// APB_CTRL_RND_DATA_REG
-        pub const RND_DATA = @intToPtr(*volatile u32, base_address + 0xb0);
-
-        /// address: 0x600260b4
-        /// APB_CTRL_PERI_BACKUP_CONFIG_REG
-        pub const PERI_BACKUP_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_peri_backup_flow_err
-            PERI_BACKUP_FLOW_ERR: u2,
-            reserved1: u1,
-            /// reg_peri_backup_burst_limit
-            PERI_BACKUP_BURST_LIMIT: u5,
-            /// reg_peri_backup_tout_thres
-            PERI_BACKUP_TOUT_THRES: u10,
-            /// reg_peri_backup_size
-            PERI_BACKUP_SIZE: u10,
-            /// reg_peri_backup_start
-            PERI_BACKUP_START: u1,
-            /// reg_peri_backup_to_mem
-            PERI_BACKUP_TO_MEM: u1,
-            /// reg_peri_backup_ena
-            PERI_BACKUP_ENA: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600260b8
-        /// APB_CTRL_PERI_BACKUP_APB_ADDR_REG
-        pub const PERI_BACKUP_APB_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_backup_apb_start_addr
-            BACKUP_APB_START_ADDR: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600260bc
-        /// APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
-        pub const PERI_BACKUP_MEM_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_backup_mem_start_addr
-            BACKUP_MEM_START_ADDR: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600260c0
-        /// APB_CTRL_PERI_BACKUP_INT_RAW_REG
-        pub const PERI_BACKUP_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_raw
-            PERI_BACKUP_DONE_INT_RAW: u1,
-            /// reg_peri_backup_err_int_raw
-            PERI_BACKUP_ERR_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600260c4
-        /// APB_CTRL_PERI_BACKUP_INT_ST_REG
-        pub const PERI_BACKUP_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_st
-            PERI_BACKUP_DONE_INT_ST: u1,
-            /// reg_peri_backup_err_int_st
-            PERI_BACKUP_ERR_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600260c8
-        /// APB_CTRL_PERI_BACKUP_INT_ENA_REG
-        pub const PERI_BACKUP_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_ena
-            PERI_BACKUP_DONE_INT_ENA: u1,
-            /// reg_peri_backup_err_int_ena
-            PERI_BACKUP_ERR_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600260d0
-        /// APB_CTRL_PERI_BACKUP_INT_CLR_REG
-        pub const PERI_BACKUP_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_clr
-            PERI_BACKUP_DONE_INT_CLR: u1,
-            /// reg_peri_backup_err_int_clr
-            PERI_BACKUP_ERR_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600263fc
-        /// APB_CTRL_DATE_REG
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x3fc);
-    };
-
-    /// Successive Approximation Register Analog to Digital Converter
-    pub const APB_SARADC = struct {
-        pub const base_address = 0x60040000;
-
-        /// address: 0x60040000
-        /// digital saradc configure register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// select software enable saradc sample
-            SARADC_START_FORCE: u1,
-            /// software enable saradc sample
-            SARADC_START: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// SAR clock gated
-            SARADC_SAR_CLK_GATED: u1,
-            /// SAR clock divider
-            SARADC_SAR_CLK_DIV: u8,
-            /// 0 ~ 15 means length 1 ~ 16
-            SARADC_SAR_PATT_LEN: u3,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// clear the pointer of pattern table for DIG ADC1 CTRL
-            SARADC_SAR_PATT_P_CLEAR: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// force option to xpd sar blocks
-            SARADC_XPD_SAR_FORCE: u2,
-            reserved12: u1,
-            /// wait arbit signal stable after sar_done
-            SARADC_WAIT_ARB_CYCLE: u2,
-        }), base_address + 0x0);
-
-        /// address: 0x60040004
-        /// digital saradc configure register
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable max meas num
-            SARADC_MEAS_NUM_LIMIT: u1,
-            /// max conversion number
-            SARADC_MAX_MEAS_NUM: u8,
-            /// 1: data to DIG ADC1 CTRL is inverted, otherwise not
-            SARADC_SAR1_INV: u1,
-            /// 1: data to DIG ADC2 CTRL is inverted, otherwise not
-            SARADC_SAR2_INV: u1,
-            reserved0: u1,
-            /// to set saradc timer target
-            SARADC_TIMER_TARGET: u12,
-            /// to enable saradc timer trigger
-            SARADC_TIMER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60040008
-        /// digital saradc configure register
-        pub const FILTER_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// Factor of saradc filter1
-            APB_SARADC_FILTER_FACTOR1: u3,
-            /// Factor of saradc filter0
-            APB_SARADC_FILTER_FACTOR0: u3,
-        }), base_address + 0x8);
-
-        /// address: 0x6004000c
-        /// digital saradc configure register
-        pub const FSM_WAIT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc_xpd_wait
-            SARADC_XPD_WAIT: u8,
-            /// saradc_rstb_wait
-            SARADC_RSTB_WAIT: u8,
-            /// saradc_standby_wait
-            SARADC_STANDBY_WAIT: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60040010
-        /// digital saradc configure register
-        pub const SAR1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc1 status about data and channel
-            SARADC_SAR1_STATUS: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60040014
-        /// digital saradc configure register
-        pub const SAR2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc2 status about data and channel
-            SARADC_SAR2_STATUS: u32,
-        }), base_address + 0x14);
-
-        /// address: 0x60040018
-        /// digital saradc configure register
-        pub const SAR_PATT_TAB1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// item 0 ~ 3 for pattern table 1 (each item one byte)
-            SARADC_SAR_PATT_TAB1: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6004001c
-        /// digital saradc configure register
-        pub const SAR_PATT_TAB2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Item 4 ~ 7 for pattern table 1 (each item one byte)
-            SARADC_SAR_PATT_TAB2: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60040020
-        /// digital saradc configure register
-        pub const ONETIME_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// configure onetime atten
-            SARADC_ONETIME_ATTEN: u2,
-            /// configure onetime channel
-            SARADC_ONETIME_CHANNEL: u4,
-            /// trigger adc onetime sample
-            SARADC_ONETIME_START: u1,
-            /// enable adc2 onetime sample
-            SARADC2_ONETIME_SAMPLE: u1,
-            /// enable adc1 onetime sample
-            SARADC1_ONETIME_SAMPLE: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60040024
-        /// digital saradc configure register
-        pub const ARB_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// adc2 arbiter force to enableapb controller
-            ADC_ARB_APB_FORCE: u1,
-            /// adc2 arbiter force to enable rtc controller
-            ADC_ARB_RTC_FORCE: u1,
-            /// adc2 arbiter force to enable wifi controller
-            ADC_ARB_WIFI_FORCE: u1,
-            /// adc2 arbiter force grant
-            ADC_ARB_GRANT_FORCE: u1,
-            /// Set adc2 arbiterapb priority
-            ADC_ARB_APB_PRIORITY: u2,
-            /// Set adc2 arbiter rtc priority
-            ADC_ARB_RTC_PRIORITY: u2,
-            /// Set adc2 arbiter wifi priority
-            ADC_ARB_WIFI_PRIORITY: u2,
-            /// adc2 arbiter uses fixed priority
-            ADC_ARB_FIX_PRIORITY: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60040028
-        /// digital saradc configure register
-        pub const FILTER_CTRL0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// configure filter1 to adc channel
-            APB_SARADC_FILTER_CHANNEL1: u4,
-            /// configure filter0 to adc channel
-            APB_SARADC_FILTER_CHANNEL0: u4,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// enable apb_adc1_filter
-            APB_SARADC_FILTER_RESET: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6004002c
-        /// digital saradc configure register
-        pub const SAR1DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc1 data
-            APB_SARADC1_DATA: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60040030
-        /// digital saradc configure register
-        pub const SAR2DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc2 data
-            APB_SARADC2_DATA: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60040034
-        /// digital saradc configure register
-        pub const THRES0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure thres0 to adc channel
-            APB_SARADC_THRES0_CHANNEL: u4,
-            reserved0: u1,
-            /// saradc thres0 monitor thres
-            APB_SARADC_THRES0_HIGH: u13,
-            /// saradc thres0 monitor thres
-            APB_SARADC_THRES0_LOW: u13,
-            padding0: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60040038
-        /// digital saradc configure register
-        pub const THRES1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure thres1 to adc channel
-            APB_SARADC_THRES1_CHANNEL: u4,
-            reserved0: u1,
-            /// saradc thres1 monitor thres
-            APB_SARADC_THRES1_HIGH: u13,
-            /// saradc thres1 monitor thres
-            APB_SARADC_THRES1_LOW: u13,
-            padding0: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6004003c
-        /// digital saradc configure register
-        pub const THRES_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// enable thres to all channel
-            APB_SARADC_THRES_ALL_EN: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// enable thres1
-            APB_SARADC_THRES1_EN: u1,
-            /// enable thres0
-            APB_SARADC_THRES0_EN: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60040040
-        /// digital saradc int register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt enable
-            APB_SARADC_THRES1_LOW_INT_ENA: u1,
-            /// saradc thres0 low interrupt enable
-            APB_SARADC_THRES0_LOW_INT_ENA: u1,
-            /// saradc thres1 high interrupt enable
-            APB_SARADC_THRES1_HIGH_INT_ENA: u1,
-            /// saradc thres0 high interrupt enable
-            APB_SARADC_THRES0_HIGH_INT_ENA: u1,
-            /// saradc2 done interrupt enable
-            APB_SARADC2_DONE_INT_ENA: u1,
-            /// saradc1 done interrupt enable
-            APB_SARADC1_DONE_INT_ENA: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60040044
-        /// digital saradc int register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt raw
-            APB_SARADC_THRES1_LOW_INT_RAW: u1,
-            /// saradc thres0 low interrupt raw
-            APB_SARADC_THRES0_LOW_INT_RAW: u1,
-            /// saradc thres1 high interrupt raw
-            APB_SARADC_THRES1_HIGH_INT_RAW: u1,
-            /// saradc thres0 high interrupt raw
-            APB_SARADC_THRES0_HIGH_INT_RAW: u1,
-            /// saradc2 done interrupt raw
-            APB_SARADC2_DONE_INT_RAW: u1,
-            /// saradc1 done interrupt raw
-            APB_SARADC1_DONE_INT_RAW: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60040048
-        /// digital saradc int register
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt state
-            APB_SARADC_THRES1_LOW_INT_ST: u1,
-            /// saradc thres0 low interrupt state
-            APB_SARADC_THRES0_LOW_INT_ST: u1,
-            /// saradc thres1 high interrupt state
-            APB_SARADC_THRES1_HIGH_INT_ST: u1,
-            /// saradc thres0 high interrupt state
-            APB_SARADC_THRES0_HIGH_INT_ST: u1,
-            /// saradc2 done interrupt state
-            APB_SARADC2_DONE_INT_ST: u1,
-            /// saradc1 done interrupt state
-            APB_SARADC1_DONE_INT_ST: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6004004c
-        /// digital saradc int register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt clear
-            APB_SARADC_THRES1_LOW_INT_CLR: u1,
-            /// saradc thres0 low interrupt clear
-            APB_SARADC_THRES0_LOW_INT_CLR: u1,
-            /// saradc thres1 high interrupt clear
-            APB_SARADC_THRES1_HIGH_INT_CLR: u1,
-            /// saradc thres0 high interrupt clear
-            APB_SARADC_THRES0_HIGH_INT_CLR: u1,
-            /// saradc2 done interrupt clear
-            APB_SARADC2_DONE_INT_CLR: u1,
-            /// saradc1 done interrupt clear
-            APB_SARADC1_DONE_INT_CLR: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60040050
-        /// digital saradc configure register
-        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the dma_in_suc_eof gen when sample cnt = spi_eof_num
-            APB_ADC_EOF_NUM: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// reset_apb_adc_state
-            APB_ADC_RESET_FSM: u1,
-            /// enable apb_adc use spi_dma
-            APB_ADC_TRANS: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60040054
-        /// digital saradc configure register
-        pub const CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S clock divider value
-            CLKM_DIV_NUM: u8,
-            /// Fractional clock divider numerator value
-            CLKM_DIV_B: u6,
-            /// Fractional clock divider denominator value
-            CLKM_DIV_A: u6,
-            /// reg clk en
-            CLK_EN: u1,
-            /// Set this bit to enable clk_apll
-            CLK_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60040058
-        /// digital tsens configure register
-        pub const APB_TSENS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// temperature sensor data out
-            TSENS_OUT: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// invert temperature sensor data
-            TSENS_IN_INV: u1,
-            /// temperature sensor clock divider
-            TSENS_CLK_DIV: u8,
-            /// temperature sensor power up
-            TSENS_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6004005c
-        /// digital tsens configure register
-        pub const TSENS_CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the time that power up tsens need wait
-            TSENS_XPD_WAIT: u12,
-            /// force power up tsens
-            TSENS_XPD_FORCE: u2,
-            /// inv tsens clk
-            TSENS_CLK_INV: u1,
-            /// tsens clk select
-            TSENS_CLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60040060
-        /// digital saradc configure register
-        pub const CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc cali factor
-            APB_SARADC_CALI_CFG: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600403fc
-        /// version
-        pub const CTRL_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// version
-            DATE: u32,
-        }), base_address + 0x3fc);
-    };
-
-    /// Debug Assist
-    pub const ASSIST_DEBUG = struct {
-        pub const base_address = 0x600ce000;
-
-        /// address: 0x600ce000
-        /// ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
-        pub const C0RE_0_MONTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_ena
-            CORE_0_AREA_DRAM0_0_RD_ENA: u1,
-            /// reg_core_0_area_dram0_0_wr_ena
-            CORE_0_AREA_DRAM0_0_WR_ENA: u1,
-            /// reg_core_0_area_dram0_1_rd_ena
-            CORE_0_AREA_DRAM0_1_RD_ENA: u1,
-            /// reg_core_0_area_dram0_1_wr_ena
-            CORE_0_AREA_DRAM0_1_WR_ENA: u1,
-            /// reg_core_0_area_pif_0_rd_ena
-            CORE_0_AREA_PIF_0_RD_ENA: u1,
-            /// reg_core_0_area_pif_0_wr_ena
-            CORE_0_AREA_PIF_0_WR_ENA: u1,
-            /// reg_core_0_area_pif_1_rd_ena
-            CORE_0_AREA_PIF_1_RD_ENA: u1,
-            /// reg_core_0_area_pif_1_wr_ena
-            CORE_0_AREA_PIF_1_WR_ENA: u1,
-            /// reg_core_0_sp_spill_min_ena
-            CORE_0_SP_SPILL_MIN_ENA: u1,
-            /// reg_core_0_sp_spill_max_ena
-            CORE_0_SP_SPILL_MAX_ENA: u1,
-            /// reg_core_0_iram0_exception_monitor_ena
-            CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
-            /// reg_core_0_dram0_exception_monitor_ena
-            CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600ce004
-        /// ASSIST_DEBUG_CORE_0_INTR_RAW_REG
-        pub const CORE_0_INTR_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_raw
-            CORE_0_AREA_DRAM0_0_RD_RAW: u1,
-            /// reg_core_0_area_dram0_0_wr_raw
-            CORE_0_AREA_DRAM0_0_WR_RAW: u1,
-            /// reg_core_0_area_dram0_1_rd_raw
-            CORE_0_AREA_DRAM0_1_RD_RAW: u1,
-            /// reg_core_0_area_dram0_1_wr_raw
-            CORE_0_AREA_DRAM0_1_WR_RAW: u1,
-            /// reg_core_0_area_pif_0_rd_raw
-            CORE_0_AREA_PIF_0_RD_RAW: u1,
-            /// reg_core_0_area_pif_0_wr_raw
-            CORE_0_AREA_PIF_0_WR_RAW: u1,
-            /// reg_core_0_area_pif_1_rd_raw
-            CORE_0_AREA_PIF_1_RD_RAW: u1,
-            /// reg_core_0_area_pif_1_wr_raw
-            CORE_0_AREA_PIF_1_WR_RAW: u1,
-            /// reg_core_0_sp_spill_min_raw
-            CORE_0_SP_SPILL_MIN_RAW: u1,
-            /// reg_core_0_sp_spill_max_raw
-            CORE_0_SP_SPILL_MAX_RAW: u1,
-            /// reg_core_0_iram0_exception_monitor_raw
-            CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
-            /// reg_core_0_dram0_exception_monitor_raw
-            CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600ce008
-        /// ASSIST_DEBUG_CORE_0_INTR_ENA_REG
-        pub const CORE_0_INTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_intr_ena
-            CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_0_wr_intr_ena
-            CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_1_rd_intr_ena
-            CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_1_wr_intr_ena
-            CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
-            /// reg_core_0_area_pif_0_rd_intr_ena
-            CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
-            /// reg_core_0_area_pif_0_wr_intr_ena
-            CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
-            /// reg_core_0_area_pif_1_rd_intr_ena
-            CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
-            /// reg_core_0_area_pif_1_wr_intr_ena
-            CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
-            /// reg_core_0_sp_spill_min_intr_ena
-            CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
-            /// reg_core_0_sp_spill_max_intr_ena
-            CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
-            /// reg_core_0_iram0_exception_monitor_ena
-            CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
-            /// reg_core_0_dram0_exception_monitor_ena
-            CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600ce00c
-        /// ASSIST_DEBUG_CORE_0_INTR_CLR_REG
-        pub const CORE_0_INTR_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_clr
-            CORE_0_AREA_DRAM0_0_RD_CLR: u1,
-            /// reg_core_0_area_dram0_0_wr_clr
-            CORE_0_AREA_DRAM0_0_WR_CLR: u1,
-            /// reg_core_0_area_dram0_1_rd_clr
-            CORE_0_AREA_DRAM0_1_RD_CLR: u1,
-            /// reg_core_0_area_dram0_1_wr_clr
-            CORE_0_AREA_DRAM0_1_WR_CLR: u1,
-            /// reg_core_0_area_pif_0_rd_clr
-            CORE_0_AREA_PIF_0_RD_CLR: u1,
-            /// reg_core_0_area_pif_0_wr_clr
-            CORE_0_AREA_PIF_0_WR_CLR: u1,
-            /// reg_core_0_area_pif_1_rd_clr
-            CORE_0_AREA_PIF_1_RD_CLR: u1,
-            /// reg_core_0_area_pif_1_wr_clr
-            CORE_0_AREA_PIF_1_WR_CLR: u1,
-            /// reg_core_0_sp_spill_min_clr
-            CORE_0_SP_SPILL_MIN_CLR: u1,
-            /// reg_core_0_sp_spill_max_clr
-            CORE_0_SP_SPILL_MAX_CLR: u1,
-            /// reg_core_0_iram0_exception_monitor_clr
-            CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
-            /// reg_core_0_dram0_exception_monitor_clr
-            CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600ce010
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
-        pub const CORE_0_AREA_DRAM0_0_MIN = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x600ce014
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
-        pub const CORE_0_AREA_DRAM0_0_MAX = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x600ce018
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
-        pub const CORE_0_AREA_DRAM0_1_MIN = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x600ce01c
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
-        pub const CORE_0_AREA_DRAM0_1_MAX = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x600ce020
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
-        pub const CORE_0_AREA_PIF_0_MIN = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x600ce024
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
-        pub const CORE_0_AREA_PIF_0_MAX = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x600ce028
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
-        pub const CORE_0_AREA_PIF_1_MIN = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x600ce02c
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
-        pub const CORE_0_AREA_PIF_1_MAX = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x600ce030
-        /// ASSIST_DEBUG_CORE_0_AREA_PC_REG
-        pub const CORE_0_AREA_PC = @intToPtr(*volatile u32, base_address + 0x30);
-
-        /// address: 0x600ce034
-        /// ASSIST_DEBUG_CORE_0_AREA_SP_REG
-        pub const CORE_0_AREA_SP = @intToPtr(*volatile u32, base_address + 0x34);
-
-        /// address: 0x600ce038
-        /// ASSIST_DEBUG_CORE_0_SP_MIN_REG
-        pub const CORE_0_SP_MIN = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x600ce03c
-        /// ASSIST_DEBUG_CORE_0_SP_MAX_REG
-        pub const CORE_0_SP_MAX = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x600ce040
-        /// ASSIST_DEBUG_CORE_0_SP_PC_REG
-        pub const CORE_0_SP_PC = @intToPtr(*volatile u32, base_address + 0x40);
-
-        /// address: 0x600ce044
-        /// ASSIST_DEBUG_CORE_0_RCD_EN_REG
-        pub const CORE_0_RCD_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_rcd_recorden
-            CORE_0_RCD_RECORDEN: u1,
-            /// reg_core_0_rcd_pdebugen
-            CORE_0_RCD_PDEBUGEN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600ce048
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
-        pub const CORE_0_RCD_PDEBUGPC = @intToPtr(*volatile u32, base_address + 0x48);
-
-        /// address: 0x600ce04c
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-        pub const CORE_0_RCD_PDEBUGSP = @intToPtr(*volatile u32, base_address + 0x4c);
-
-        /// address: 0x600ce050
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_iram0_recording_addr_0
-            CORE_0_IRAM0_RECORDING_ADDR_0: u24,
-            /// reg_core_0_iram0_recording_wr_0
-            CORE_0_IRAM0_RECORDING_WR_0: u1,
-            /// reg_core_0_iram0_recording_loadstore_0
-            CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600ce054
-        /// ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_iram0_recording_addr_1
-            CORE_0_IRAM0_RECORDING_ADDR_1: u24,
-            /// reg_core_0_iram0_recording_wr_1
-            CORE_0_IRAM0_RECORDING_WR_1: u1,
-            /// reg_core_0_iram0_recording_loadstore_1
-            CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600ce058
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_addr_0
-            CORE_0_DRAM0_RECORDING_ADDR_0: u24,
-            /// reg_core_0_dram0_recording_wr_0
-            CORE_0_DRAM0_RECORDING_WR_0: u1,
-            /// reg_core_0_dram0_recording_byteen_0
-            CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600ce05c
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_pc_0
-            CORE_0_DRAM0_RECORDING_PC_0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x600ce060
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_addr_1
-            CORE_0_DRAM0_RECORDING_ADDR_1: u24,
-            /// reg_core_0_dram0_recording_wr_1
-            CORE_0_DRAM0_RECORDING_WR_1: u1,
-            /// reg_core_0_dram0_recording_byteen_1
-            CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600ce064
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_pc_1
-            CORE_0_DRAM0_RECORDING_PC_1: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x600ce068
-        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
-        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_x_iram0_dram0_limit_cycle_0
-            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600ce06c
-        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_x_iram0_dram0_limit_cycle_1
-            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600ce070
-        /// ASSIST_DEBUG_LOG_SETTING
-        pub const LOG_SETTING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_ena
-            LOG_ENA: u3,
-            /// reg_log_mode
-            LOG_MODE: u4,
-            /// reg_log_mem_loop_enable
-            LOG_MEM_LOOP_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600ce074
-        /// ASSIST_DEBUG_LOG_DATA_0_REG
-        pub const LOG_DATA_0 = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x600ce078
-        /// ASSIST_DEBUG_LOG_DATA_MASK_REG
-        pub const LOG_DATA_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_data_size
-            LOG_DATA_SIZE: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600ce07c
-        /// ASSIST_DEBUG_LOG_MIN_REG
-        pub const LOG_MIN = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x600ce080
-        /// ASSIST_DEBUG_LOG_MAX_REG
-        pub const LOG_MAX = @intToPtr(*volatile u32, base_address + 0x80);
-
-        /// address: 0x600ce084
-        /// ASSIST_DEBUG_LOG_MEM_START_REG
-        pub const LOG_MEM_START = @intToPtr(*volatile u32, base_address + 0x84);
-
-        /// address: 0x600ce088
-        /// ASSIST_DEBUG_LOG_MEM_END_REG
-        pub const LOG_MEM_END = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0x600ce08c
-        /// ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
-        pub const LOG_MEM_WRITING_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x600ce090
-        /// ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
-        pub const LOG_MEM_FULL_FLAG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_mem_full_flag
-            LOG_MEM_FULL_FLAG: u1,
-            /// reg_clr_log_mem_full_flag
-            CLR_LOG_MEM_FULL_FLAG: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600ce094
-        /// ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
-        pub const C0RE_0_LASTPC_BEFORE_EXCEPTION = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_lastpc_before_exc
-            CORE_0_LASTPC_BEFORE_EXC: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x600ce098
-        /// ASSIST_DEBUG_C0RE_0_DEBUG_MODE
-        pub const C0RE_0_DEBUG_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_debug_mode
-            CORE_0_DEBUG_MODE: u1,
-            /// reg_core_0_debug_module_active
-            CORE_0_DEBUG_MODULE_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600ce1fc
-        /// ASSIST_DEBUG_DATE_REG
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_assist_debug_date
-            ASSIST_DEBUG_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1fc);
-    };
-
-    /// DMA (Direct Memory Access) Controller
-    pub const DMA = struct {
-        pub const base_address = 0x6003f000;
-
-        /// address: 0x6003f000
-        /// DMA_INT_RAW_CH0_REG.
-        pub const INT_RAW_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 0.
-            IN_DONE_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 0. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 0.
-            IN_SUC_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 0.
-            OUT_DONE_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 0.
-            OUT_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 0.
-            IN_DSCR_ERR_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 0.
-            OUT_DSCR_ERR_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 0.
-            IN_DSCR_EMPTY_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 0.
-            OUT_TOTAL_EOF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
-            /// overflow.
-            INFIFO_OVF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
-            /// underflow.
-            INFIFO_UDF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
-            /// overflow.
-            OUTFIFO_OVF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
-            /// underflow.
-            OUTFIFO_UDF_CH0_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6003f004
-        /// DMA_INT_ST_CH0_REG.
-        pub const INT_ST_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6003f008
-        /// DMA_INT_ENA_CH0_REG.
-        pub const INT_ENA_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6003f00c
-        /// DMA_INT_CLR_CH0_REG.
-        pub const INT_CLR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6003f010
-        /// DMA_INT_RAW_CH1_REG.
-        pub const INT_RAW_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 1.
-            IN_DONE_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 1. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 1.
-            IN_SUC_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 1.
-            OUT_DONE_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 1.
-            OUT_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 1.
-            IN_DSCR_ERR_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 1.
-            OUT_DSCR_ERR_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 1.
-            IN_DSCR_EMPTY_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 1.
-            OUT_TOTAL_EOF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
-            /// overflow.
-            INFIFO_OVF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
-            /// underflow.
-            INFIFO_UDF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
-            /// overflow.
-            OUTFIFO_OVF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
-            /// underflow.
-            OUTFIFO_UDF_CH1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6003f014
-        /// DMA_INT_ST_CH1_REG.
-        pub const INT_ST_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6003f018
-        /// DMA_INT_ENA_CH1_REG.
-        pub const INT_ENA_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6003f01c
-        /// DMA_INT_CLR_CH1_REG.
-        pub const INT_CLR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6003f020
-        /// DMA_INT_RAW_CH2_REG.
-        pub const INT_RAW_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 2.
-            IN_DONE_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 2. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 2.
-            IN_SUC_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 2.
-            OUT_DONE_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 2.
-            OUT_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 2.
-            IN_DSCR_ERR_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 2.
-            OUT_DSCR_ERR_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 2.
-            IN_DSCR_EMPTY_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 2.
-            OUT_TOTAL_EOF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
-            /// overflow.
-            INFIFO_OVF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
-            /// underflow.
-            INFIFO_UDF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
-            /// overflow.
-            OUTFIFO_OVF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
-            /// underflow.
-            OUTFIFO_UDF_CH2_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6003f024
-        /// DMA_INT_ST_CH2_REG.
-        pub const INT_ST_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6003f028
-        /// DMA_INT_ENA_CH2_REG.
-        pub const INT_ENA_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6003f02c
-        /// DMA_INT_CLR_CH2_REG.
-        pub const INT_CLR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x6003f040
-        /// DMA_AHB_TEST_REG.
-        pub const AHB_TEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved
-            AHB_TESTMODE: u3,
-            reserved0: u1,
-            /// reserved
-            AHB_TESTADDR: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6003f044
-        /// DMA_MISC_CONF_REG.
-        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit, then clear this bit to reset the internal ahb FSM.
-            AHBM_RST_INTER: u1,
-            reserved0: u1,
-            /// Set this bit to disable priority arbitration function.
-            ARB_PRI_DIS: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6003f048
-        /// DMA_DATE_REG.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x48);
-
-        /// address: 0x6003f070
-        /// DMA_IN_CONF0_CH0_REG.
-        pub const IN_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH0: u1,
-            /// reserved
-            IN_LOOP_TEST_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH0: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6003f074
-        /// DMA_IN_CONF1_CH0_REG.
-        pub const IN_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6003f078
-        /// DMA_INFIFO_STATUS_CH0_REG.
-        pub const INFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 0.
-            INFIFO_FULL_CH0: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 0.
-            INFIFO_EMPTY_CH0: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
-            INFIFO_CNT_CH0: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH0: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6003f07c
-        /// DMA_IN_POP_CH0_REG.
-        pub const IN_POP_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH0: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6003f080
-        /// DMA_IN_LINK_CH0_REG.
-        pub const IN_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH0: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH0: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH0: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH0: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH0: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x6003f084
-        /// DMA_IN_STATE_CH0_REG.
-        pub const IN_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH0: u18,
-            /// reserved
-            IN_DSCR_STATE_CH0: u2,
-            /// reserved
-            IN_STATE_CH0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x6003f088
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0x6003f08c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x6003f090
-        /// DMA_IN_DSCR_CH0_REG.
-        pub const IN_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH0: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x6003f094
-        /// DMA_IN_DSCR_BF0_CH0_REG.
-        pub const IN_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH0: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x6003f098
-        /// DMA_IN_DSCR_BF1_CH0_REG.
-        pub const IN_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH0: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6003f09c
-        /// DMA_IN_PRI_CH0_REG.
-        pub const IN_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 0. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x6003f0a0
-        /// DMA_IN_PERI_SEL_CH0_REG.
-        pub const IN_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH0: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x6003f0d0
-        /// DMA_OUT_CONF0_CH0_REG.
-        pub const OUT_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH0: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH0: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH0: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x6003f0d4
-        /// DMA_OUT_CONF1_CH0_REG.
-        pub const OUT_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x6003f0d8
-        /// DMA_OUTFIFO_STATUS_CH0_REG.
-        pub const OUTFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 0.
-            OUTFIFO_FULL_CH0: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 0.
-            OUTFIFO_EMPTY_CH0: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
-            OUTFIFO_CNT_CH0: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x6003f0dc
-        /// DMA_OUT_PUSH_CH0_REG.
-        pub const OUT_PUSH_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH0: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x6003f0e0
-        /// DMA_OUT_LINK_CH0_REG.
-        pub const OUT_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH0: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH0: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH0: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH0: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x6003f0e4
-        /// DMA_OUT_STATE_CH0_REG.
-        pub const OUT_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH0: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH0: u2,
-            /// reserved
-            OUT_STATE_CH0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x6003f0e8
-        /// DMA_OUT_EOF_DES_ADDR_CH0_REG.
-        pub const OUT_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xe8);
-
-        /// address: 0x6003f0ec
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xec);
-
-        /// address: 0x6003f0f0
-        /// DMA_OUT_DSCR_CH0_REG.
-        pub const OUT_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH0: u32,
-        }), base_address + 0xf0);
-
-        /// address: 0x6003f0f4
-        /// DMA_OUT_DSCR_BF0_CH0_REG.
-        pub const OUT_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH0: u32,
-        }), base_address + 0xf4);
-
-        /// address: 0x6003f0f8
-        /// DMA_OUT_DSCR_BF1_CH0_REG.
-        pub const OUT_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH0: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x6003f0fc
-        /// DMA_OUT_PRI_CH0_REG.
-        pub const OUT_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 0. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x6003f100
-        /// DMA_OUT_PERI_SEL_CH0_REG.
-        pub const OUT_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH0: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x6003f130
-        /// DMA_IN_CONF0_CH1_REG.
-        pub const IN_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH1: u1,
-            /// reserved
-            IN_LOOP_TEST_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH1: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x6003f134
-        /// DMA_IN_CONF1_CH1_REG.
-        pub const IN_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x6003f138
-        /// DMA_INFIFO_STATUS_CH1_REG.
-        pub const INFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 1.
-            INFIFO_FULL_CH1: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 1.
-            INFIFO_EMPTY_CH1: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
-            INFIFO_CNT_CH1: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH1: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x6003f13c
-        /// DMA_IN_POP_CH1_REG.
-        pub const IN_POP_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH1: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x13c);
-
-        /// address: 0x6003f140
-        /// DMA_IN_LINK_CH1_REG.
-        pub const IN_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH1: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH1: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH1: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH1: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH1: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x6003f144
-        /// DMA_IN_STATE_CH1_REG.
-        pub const IN_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH1: u18,
-            /// reserved
-            IN_DSCR_STATE_CH1: u2,
-            /// reserved
-            IN_STATE_CH1: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x6003f148
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x148);
-
-        /// address: 0x6003f14c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x14c);
-
-        /// address: 0x6003f150
-        /// DMA_IN_DSCR_CH1_REG.
-        pub const IN_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH1: u32,
-        }), base_address + 0x150);
-
-        /// address: 0x6003f154
-        /// DMA_IN_DSCR_BF0_CH1_REG.
-        pub const IN_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH1: u32,
-        }), base_address + 0x154);
-
-        /// address: 0x6003f158
-        /// DMA_IN_DSCR_BF1_CH1_REG.
-        pub const IN_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH1: u32,
-        }), base_address + 0x158);
-
-        /// address: 0x6003f15c
-        /// DMA_IN_PRI_CH1_REG.
-        pub const IN_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 1. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x6003f160
-        /// DMA_IN_PERI_SEL_CH1_REG.
-        pub const IN_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 1. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH1: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x6003f190
-        /// DMA_OUT_CONF0_CH1_REG.
-        pub const OUT_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH1: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH1: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH1: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x6003f194
-        /// DMA_OUT_CONF1_CH1_REG.
-        pub const OUT_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x194);
-
-        /// address: 0x6003f198
-        /// DMA_OUTFIFO_STATUS_CH1_REG.
-        pub const OUTFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 1.
-            OUTFIFO_FULL_CH1: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 1.
-            OUTFIFO_EMPTY_CH1: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
-            OUTFIFO_CNT_CH1: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x198);
-
-        /// address: 0x6003f19c
-        /// DMA_OUT_PUSH_CH1_REG.
-        pub const OUT_PUSH_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH1: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x19c);
-
-        /// address: 0x6003f1a0
-        /// DMA_OUT_LINK_CH1_REG.
-        pub const OUT_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH1: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH1: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH1: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH1: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1a0);
-
-        /// address: 0x6003f1a4
-        /// DMA_OUT_STATE_CH1_REG.
-        pub const OUT_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH1: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH1: u2,
-            /// reserved
-            OUT_STATE_CH1: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x1a4);
-
-        /// address: 0x6003f1a8
-        /// DMA_OUT_EOF_DES_ADDR_CH1_REG.
-        pub const OUT_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1a8);
-
-        /// address: 0x6003f1ac
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1ac);
-
-        /// address: 0x6003f1b0
-        /// DMA_OUT_DSCR_CH1_REG.
-        pub const OUT_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH1: u32,
-        }), base_address + 0x1b0);
-
-        /// address: 0x6003f1b4
-        /// DMA_OUT_DSCR_BF0_CH1_REG.
-        pub const OUT_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH1: u32,
-        }), base_address + 0x1b4);
-
-        /// address: 0x6003f1b8
-        /// DMA_OUT_DSCR_BF1_CH1_REG.
-        pub const OUT_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH1: u32,
-        }), base_address + 0x1b8);
-
-        /// address: 0x6003f1bc
-        /// DMA_OUT_PRI_CH1_REG.
-        pub const OUT_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 1. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1bc);
-
-        /// address: 0x6003f1c0
-        /// DMA_OUT_PERI_SEL_CH1_REG.
-        pub const OUT_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 1. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH1: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x6003f1f0
-        /// DMA_IN_CONF0_CH2_REG.
-        pub const IN_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH2: u1,
-            /// reserved
-            IN_LOOP_TEST_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH2: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x6003f1f4
-        /// DMA_IN_CONF1_CH2_REG.
-        pub const IN_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x6003f1f8
-        /// DMA_INFIFO_STATUS_CH2_REG.
-        pub const INFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 2.
-            INFIFO_FULL_CH2: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 2.
-            INFIFO_EMPTY_CH2: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
-            INFIFO_CNT_CH2: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH2: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1f8);
-
-        /// address: 0x6003f1fc
-        /// DMA_IN_POP_CH2_REG.
-        pub const IN_POP_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH2: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1fc);
-
-        /// address: 0x6003f200
-        /// DMA_IN_LINK_CH2_REG.
-        pub const IN_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH2: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH2: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH2: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH2: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH2: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x200);
-
-        /// address: 0x6003f204
-        /// DMA_IN_STATE_CH2_REG.
-        pub const IN_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH2: u18,
-            /// reserved
-            IN_DSCR_STATE_CH2: u2,
-            /// reserved
-            IN_STATE_CH2: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x204);
-
-        /// address: 0x6003f208
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x208);
-
-        /// address: 0x6003f20c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x20c);
-
-        /// address: 0x6003f210
-        /// DMA_IN_DSCR_CH2_REG.
-        pub const IN_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH2: u32,
-        }), base_address + 0x210);
-
-        /// address: 0x6003f214
-        /// DMA_IN_DSCR_BF0_CH2_REG.
-        pub const IN_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH2: u32,
-        }), base_address + 0x214);
-
-        /// address: 0x6003f218
-        /// DMA_IN_DSCR_BF1_CH2_REG.
-        pub const IN_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH2: u32,
-        }), base_address + 0x218);
-
-        /// address: 0x6003f21c
-        /// DMA_IN_PRI_CH2_REG.
-        pub const IN_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 2. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH2: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x21c);
-
-        /// address: 0x6003f220
-        /// DMA_IN_PERI_SEL_CH2_REG.
-        pub const IN_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 2. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH2: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x220);
-
-        /// address: 0x6003f250
-        /// DMA_OUT_CONF0_CH2_REG.
-        pub const OUT_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH2: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH2: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH2: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x250);
-
-        /// address: 0x6003f254
-        /// DMA_OUT_CONF1_CH2_REG.
-        pub const OUT_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x254);
-
-        /// address: 0x6003f258
-        /// DMA_OUTFIFO_STATUS_CH2_REG.
-        pub const OUTFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 2.
-            OUTFIFO_FULL_CH2: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 2.
-            OUTFIFO_EMPTY_CH2: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
-            OUTFIFO_CNT_CH2: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x258);
-
-        /// address: 0x6003f25c
-        /// DMA_OUT_PUSH_CH2_REG.
-        pub const OUT_PUSH_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH2: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x25c);
-
-        /// address: 0x6003f260
-        /// DMA_OUT_LINK_CH2_REG.
-        pub const OUT_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH2: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH2: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH2: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH2: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x260);
-
-        /// address: 0x6003f264
-        /// DMA_OUT_STATE_CH2_REG.
-        pub const OUT_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH2: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH2: u2,
-            /// reserved
-            OUT_STATE_CH2: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x264);
-
-        /// address: 0x6003f268
-        /// DMA_OUT_EOF_DES_ADDR_CH2_REG.
-        pub const OUT_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x268);
-
-        /// address: 0x6003f26c
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x26c);
-
-        /// address: 0x6003f270
-        /// DMA_OUT_DSCR_CH2_REG.
-        pub const OUT_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH2: u32,
-        }), base_address + 0x270);
-
-        /// address: 0x6003f274
-        /// DMA_OUT_DSCR_BF0_CH2_REG.
-        pub const OUT_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH2: u32,
-        }), base_address + 0x274);
-
-        /// address: 0x6003f278
-        /// DMA_OUT_DSCR_BF1_CH2_REG.
-        pub const OUT_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH2: u32,
-        }), base_address + 0x278);
-
-        /// address: 0x6003f27c
-        /// DMA_OUT_PRI_CH2_REG.
-        pub const OUT_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 2. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH2: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x27c);
-
-        /// address: 0x6003f280
-        /// DMA_OUT_PERI_SEL_CH2_REG.
-        pub const OUT_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 2. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH2: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x280);
-    };
-
-    /// Digital Signature
-    pub const DS = struct {
-        pub const base_address = 0x6003d000;
-
-        /// address: 0x6003d000
-        /// memory that stores Y
-        pub const Y_MEM = @intToPtr(*volatile [512]u8, base_address + 0x0);
-
-        /// address: 0x6003d200
-        /// memory that stores M
-        pub const M_MEM = @intToPtr(*volatile [512]u8, base_address + 0x200);
-
-        /// address: 0x6003d400
-        /// memory that stores Rb
-        pub const RB_MEM = @intToPtr(*volatile [512]u8, base_address + 0x400);
-
-        /// address: 0x6003d600
-        /// memory that stores BOX
-        pub const BOX_MEM = @intToPtr(*volatile [48]u8, base_address + 0x600);
-
-        /// address: 0x6003d800
-        /// memory that stores X
-        pub const X_MEM = @intToPtr(*volatile [512]u8, base_address + 0x800);
-
-        /// address: 0x6003da00
-        /// memory that stores Z
-        pub const Z_MEM = @intToPtr(*volatile [512]u8, base_address + 0xa00);
-
-        /// address: 0x6003de00
-        /// DS start control register
-        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe00);
-
-        /// address: 0x6003de04
-        /// DS continue control register
-        pub const SET_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe04);
-
-        /// address: 0x6003de08
-        /// DS finish control register
-        pub const SET_FINISH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe08);
-
-        /// address: 0x6003de0c
-        /// DS query busy register
-        pub const QUERY_BUSY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe0c);
-
-        /// address: 0x6003de10
-        /// DS query key-wrong counter register
-        pub const QUERY_KEY_WRONG = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xe10);
-
-        /// address: 0x6003de14
-        /// DS query check result register
-        pub const QUERY_CHECK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
-            MD_ERROR: u1,
-            /// padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
-            PADDING_BAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xe14);
-
-        /// address: 0x6003de20
-        /// DS version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xe20);
-    };
-
-    /// eFuse Controller
-    pub const EFUSE = struct {
-        pub const base_address = 0x60008800;
-
-        /// address: 0x60008800
-        /// Register 0 that stores data to be programmed.
-        pub const PGM_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 0th 32-bit data to be programmed.
-            PGM_DATA_0: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60008804
-        /// Register 1 that stores data to be programmed.
-        pub const PGM_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 1st 32-bit data to be programmed.
-            PGM_DATA_1: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60008808
-        /// Register 2 that stores data to be programmed.
-        pub const PGM_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 2nd 32-bit data to be programmed.
-            PGM_DATA_2: u32,
-        }), base_address + 0x8);
-
-        /// address: 0x6000880c
-        /// Register 3 that stores data to be programmed.
-        pub const PGM_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 3rd 32-bit data to be programmed.
-            PGM_DATA_3: u32,
-        }), base_address + 0xc);
-
-        /// address: 0x60008810
-        /// Register 4 that stores data to be programmed.
-        pub const PGM_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 4th 32-bit data to be programmed.
-            PGM_DATA_4: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60008814
-        /// Register 5 that stores data to be programmed.
-        pub const PGM_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 5th 32-bit data to be programmed.
-            PGM_DATA_5: u32,
-        }), base_address + 0x14);
-
-        /// address: 0x60008818
-        /// Register 6 that stores data to be programmed.
-        pub const PGM_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 6th 32-bit data to be programmed.
-            PGM_DATA_6: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6000881c
-        /// Register 7 that stores data to be programmed.
-        pub const PGM_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 7th 32-bit data to be programmed.
-            PGM_DATA_7: u32,
-        }), base_address + 0x1c);
-
-        /// address: 0x60008820
-        /// Register 0 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 0th 32-bit RS code to be programmed.
-            PGM_RS_DATA_0: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60008824
-        /// Register 1 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 1st 32-bit RS code to be programmed.
-            PGM_RS_DATA_1: u32,
-        }), base_address + 0x24);
-
-        /// address: 0x60008828
-        /// Register 2 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 2nd 32-bit RS code to be programmed.
-            PGM_RS_DATA_2: u32,
-        }), base_address + 0x28);
-
-        /// address: 0x6000882c
-        /// BLOCK0 data register 0.
-        pub const RD_WR_DIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Disable programming of individual eFuses.
-            WR_DIS: u32,
-        }), base_address + 0x2c);
-
-        /// address: 0x60008830
-        /// BLOCK0 data register 1.
-        pub const RD_REPEAT_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to disable reading from BlOCK4-10.
-            RD_DIS: u7,
-            /// Set this bit to disable boot from RTC RAM.
-            DIS_RTC_RAM_BOOT: u1,
-            /// Set this bit to disable Icache.
-            DIS_ICACHE: u1,
-            /// Set this bit to disable function of usb switch to jtag in module of usb device.
-            DIS_USB_JTAG: u1,
-            /// Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3,
-            /// 6, 7).
-            DIS_DOWNLOAD_ICACHE: u1,
-            /// Set this bit to disable usb device.
-            DIS_USB_DEVICE: u1,
-            /// Set this bit to disable the function that forces chip into download mode.
-            DIS_FORCE_DOWNLOAD: u1,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED6: u1,
-            /// Set this bit to disable CAN function.
-            DIS_CAN: u1,
-            /// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-            /// strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-            JTAG_SEL_ENABLE: u1,
-            /// Set these bits to disable JTAG in the soft way (odd number 1 means disable ).
-            /// JTAG can be enabled in HMAC module.
-            SOFT_DIS_JTAG: u3,
-            /// Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-            DIS_PAD_JTAG: u1,
-            /// Set this bit to disable flash encryption when in download boot modes.
-            DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
-            /// Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV,
-            /// stored in eFuse.
-            USB_DREFH: u2,
-            /// Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
-            /// stored in eFuse.
-            USB_DREFL: u2,
-            /// Set this bit to exchange USB D+ and D- pins.
-            USB_EXCHG_PINS: u1,
-            /// Set this bit to vdd spi pin function as gpio.
-            VDD_SPI_AS_GPIO: u1,
-            /// Enable btlc gpio.
-            BTLC_GPIO_ENABLE: u2,
-            /// Set this bit to enable power glitch function.
-            POWERGLITCH_EN: u1,
-            /// Sample delay configuration of power glitch.
-            POWER_GLITCH_DSENSE: u2,
-        }), base_address + 0x30);
-
-        /// address: 0x60008834
-        /// BLOCK0 data register 2.
-        pub const RD_REPEAT_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED2: u16,
-            /// Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000.
-            /// 1: 80000. 2: 160000. 3:320000.
-            WDT_DELAY_SEL: u2,
-            /// Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-            /// number of 1: disable.
-            SPI_BOOT_CRYPT_CNT: u3,
-            /// Set this bit to enable revoking first secure boot key.
-            SECURE_BOOT_KEY_REVOKE0: u1,
-            /// Set this bit to enable revoking second secure boot key.
-            SECURE_BOOT_KEY_REVOKE1: u1,
-            /// Set this bit to enable revoking third secure boot key.
-            SECURE_BOOT_KEY_REVOKE2: u1,
-            /// Purpose of Key0.
-            KEY_PURPOSE_0: u4,
-            /// Purpose of Key1.
-            KEY_PURPOSE_1: u4,
-        }), base_address + 0x34);
-
-        /// address: 0x60008838
-        /// BLOCK0 data register 3.
-        pub const RD_REPEAT_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Purpose of Key2.
-            KEY_PURPOSE_2: u4,
-            /// Purpose of Key3.
-            KEY_PURPOSE_3: u4,
-            /// Purpose of Key4.
-            KEY_PURPOSE_4: u4,
-            /// Purpose of Key5.
-            KEY_PURPOSE_5: u4,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED3: u4,
-            /// Set this bit to enable secure boot.
-            SECURE_BOOT_EN: u1,
-            /// Set this bit to enable revoking aggressive secure boot.
-            SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED0: u6,
-            /// Configures flash waiting time after power-up, in unit of ms. If the value is
-            /// less than 15, the waiting time is the configurable value; Otherwise, the waiting
-            /// time is twice the configurable value.
-            FLASH_TPUW: u4,
-        }), base_address + 0x38);
-
-        /// address: 0x6000883c
-        /// BLOCK0 data register 4.
-        pub const RD_REPEAT_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-            DIS_DOWNLOAD_MODE: u1,
-            /// Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
-            DIS_LEGACY_SPI_BOOT: u1,
-            /// Selectes the default UART print channel. 0: UART0. 1: UART1.
-            UART_PRINT_CHANNEL: u1,
-            /// Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
-            /// use 16to17 byte mode.
-            FLASH_ECC_MODE: u1,
-            /// Set this bit to disable UART download mode through USB.
-            DIS_USB_DOWNLOAD_MODE: u1,
-            /// Set this bit to enable secure UART download mode.
-            ENABLE_SECURITY_DOWNLOAD: u1,
-            /// Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when
-            /// GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-            UART_PRINT_CONTROL: u2,
-            /// GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-            PIN_POWER_SELECTION: u1,
-            /// Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-            FLASH_TYPE: u1,
-            /// Set Flash page size.
-            FLASH_PAGE_SIZE: u2,
-            /// Set 1 to enable ECC for flash boot.
-            FLASH_ECC_EN: u1,
-            /// Set this bit to force ROM code to send a resume command during SPI boot.
-            FORCE_SEND_RESUME: u1,
-            /// Secure version (used by ESP-IDF anti-rollback feature).
-            SECURE_VERSION: u16,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED1: u2,
-        }), base_address + 0x3c);
-
-        /// address: 0x60008840
-        /// BLOCK0 data register 5.
-        pub const RD_REPEAT_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED4: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60008844
-        /// BLOCK1 data register 0.
-        pub const RD_MAC_SPI_SYS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the low 32 bits of MAC address.
-            MAC_0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60008848
-        /// BLOCK1 data register 1.
-        pub const RD_MAC_SPI_SYS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the high 16 bits of MAC address.
-            MAC_1: u16,
-            /// Stores the zeroth part of SPI_PAD_CONF.
-            SPI_PAD_CONF_0: u16,
-        }), base_address + 0x48);
-
-        /// address: 0x6000884c
-        /// BLOCK1 data register 2.
-        pub const RD_MAC_SPI_SYS_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first part of SPI_PAD_CONF.
-            SPI_PAD_CONF_1: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60008850
-        /// BLOCK1 data register 3.
-        pub const RD_MAC_SPI_SYS_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second part of SPI_PAD_CONF.
-            SPI_PAD_CONF_2: u18,
-            /// Stores the fist 14 bits of the zeroth part of system data.
-            SYS_DATA_PART0_0: u14,
-        }), base_address + 0x50);
-
-        /// address: 0x60008854
-        /// BLOCK1 data register 4.
-        pub const RD_MAC_SPI_SYS_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fist 32 bits of the zeroth part of system data.
-            SYS_DATA_PART0_1: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60008858
-        /// BLOCK1 data register 5.
-        pub const RD_MAC_SPI_SYS_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of the zeroth part of system data.
-            SYS_DATA_PART0_2: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000885c
-        /// Register 0 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of the first part of system data.
-            SYS_DATA_PART1_0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60008860
-        /// Register 1 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of the first part of system data.
-            SYS_DATA_PART1_1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60008864
-        /// Register 2 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of the first part of system data.
-            SYS_DATA_PART1_2: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60008868
-        /// Register 3 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of the first part of system data.
-            SYS_DATA_PART1_3: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000886c
-        /// Register 4 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of the first part of system data.
-            SYS_DATA_PART1_4: u32,
-        }), base_address + 0x6c);
-
-        /// address: 0x60008870
-        /// Register 5 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of the first part of system data.
-            SYS_DATA_PART1_5: u32,
-        }), base_address + 0x70);
-
-        /// address: 0x60008874
-        /// Register 6 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of the first part of system data.
-            SYS_DATA_PART1_6: u32,
-        }), base_address + 0x74);
-
-        /// address: 0x60008878
-        /// Register 7 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of the first part of system data.
-            SYS_DATA_PART1_7: u32,
-        }), base_address + 0x78);
-
-        /// address: 0x6000887c
-        /// Register 0 of BLOCK3 (user).
-        pub const RD_USR_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of BLOCK3 (user).
-            USR_DATA0: u32,
-        }), base_address + 0x7c);
-
-        /// address: 0x60008880
-        /// Register 1 of BLOCK3 (user).
-        pub const RD_USR_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of BLOCK3 (user).
-            USR_DATA1: u32,
-        }), base_address + 0x80);
-
-        /// address: 0x60008884
-        /// Register 2 of BLOCK3 (user).
-        pub const RD_USR_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of BLOCK3 (user).
-            USR_DATA2: u32,
-        }), base_address + 0x84);
-
-        /// address: 0x60008888
-        /// Register 3 of BLOCK3 (user).
-        pub const RD_USR_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of BLOCK3 (user).
-            USR_DATA3: u32,
-        }), base_address + 0x88);
-
-        /// address: 0x6000888c
-        /// Register 4 of BLOCK3 (user).
-        pub const RD_USR_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of BLOCK3 (user).
-            USR_DATA4: u32,
-        }), base_address + 0x8c);
-
-        /// address: 0x60008890
-        /// Register 5 of BLOCK3 (user).
-        pub const RD_USR_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of BLOCK3 (user).
-            USR_DATA5: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x60008894
-        /// Register 6 of BLOCK3 (user).
-        pub const RD_USR_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of BLOCK3 (user).
-            USR_DATA6: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60008898
-        /// Register 7 of BLOCK3 (user).
-        pub const RD_USR_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of BLOCK3 (user).
-            USR_DATA7: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6000889c
-        /// Register 0 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY0.
-            KEY0_DATA0: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600088a0
-        /// Register 1 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY0.
-            KEY0_DATA1: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600088a4
-        /// Register 2 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY0.
-            KEY0_DATA2: u32,
-        }), base_address + 0xa4);
-
-        /// address: 0x600088a8
-        /// Register 3 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY0.
-            KEY0_DATA3: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600088ac
-        /// Register 4 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY0.
-            KEY0_DATA4: u32,
-        }), base_address + 0xac);
-
-        /// address: 0x600088b0
-        /// Register 5 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY0.
-            KEY0_DATA5: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600088b4
-        /// Register 6 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY0.
-            KEY0_DATA6: u32,
-        }), base_address + 0xb4);
-
-        /// address: 0x600088b8
-        /// Register 7 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY0.
-            KEY0_DATA7: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600088bc
-        /// Register 0 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY1.
-            KEY1_DATA0: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600088c0
-        /// Register 1 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY1.
-            KEY1_DATA1: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600088c4
-        /// Register 2 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY1.
-            KEY1_DATA2: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600088c8
-        /// Register 3 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY1.
-            KEY1_DATA3: u32,
-        }), base_address + 0xc8);
-
-        /// address: 0x600088cc
-        /// Register 4 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY1.
-            KEY1_DATA4: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600088d0
-        /// Register 5 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY1.
-            KEY1_DATA5: u32,
-        }), base_address + 0xd0);
-
-        /// address: 0x600088d4
-        /// Register 6 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY1.
-            KEY1_DATA6: u32,
-        }), base_address + 0xd4);
-
-        /// address: 0x600088d8
-        /// Register 7 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY1.
-            KEY1_DATA7: u32,
-        }), base_address + 0xd8);
-
-        /// address: 0x600088dc
-        /// Register 0 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY2.
-            KEY2_DATA0: u32,
-        }), base_address + 0xdc);
-
-        /// address: 0x600088e0
-        /// Register 1 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY2.
-            KEY2_DATA1: u32,
-        }), base_address + 0xe0);
-
-        /// address: 0x600088e4
-        /// Register 2 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY2.
-            KEY2_DATA2: u32,
-        }), base_address + 0xe4);
-
-        /// address: 0x600088e8
-        /// Register 3 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY2.
-            KEY2_DATA3: u32,
-        }), base_address + 0xe8);
-
-        /// address: 0x600088ec
-        /// Register 4 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY2.
-            KEY2_DATA4: u32,
-        }), base_address + 0xec);
-
-        /// address: 0x600088f0
-        /// Register 5 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY2.
-            KEY2_DATA5: u32,
-        }), base_address + 0xf0);
-
-        /// address: 0x600088f4
-        /// Register 6 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY2.
-            KEY2_DATA6: u32,
-        }), base_address + 0xf4);
-
-        /// address: 0x600088f8
-        /// Register 7 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY2.
-            KEY2_DATA7: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x600088fc
-        /// Register 0 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY3.
-            KEY3_DATA0: u32,
-        }), base_address + 0xfc);
-
-        /// address: 0x60008900
-        /// Register 1 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY3.
-            KEY3_DATA1: u32,
-        }), base_address + 0x100);
-
-        /// address: 0x60008904
-        /// Register 2 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY3.
-            KEY3_DATA2: u32,
-        }), base_address + 0x104);
-
-        /// address: 0x60008908
-        /// Register 3 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY3.
-            KEY3_DATA3: u32,
-        }), base_address + 0x108);
-
-        /// address: 0x6000890c
-        /// Register 4 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY3.
-            KEY3_DATA4: u32,
-        }), base_address + 0x10c);
-
-        /// address: 0x60008910
-        /// Register 5 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY3.
-            KEY3_DATA5: u32,
-        }), base_address + 0x110);
-
-        /// address: 0x60008914
-        /// Register 6 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY3.
-            KEY3_DATA6: u32,
-        }), base_address + 0x114);
-
-        /// address: 0x60008918
-        /// Register 7 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY3.
-            KEY3_DATA7: u32,
-        }), base_address + 0x118);
-
-        /// address: 0x6000891c
-        /// Register 0 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY4.
-            KEY4_DATA0: u32,
-        }), base_address + 0x11c);
-
-        /// address: 0x60008920
-        /// Register 1 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY4.
-            KEY4_DATA1: u32,
-        }), base_address + 0x120);
-
-        /// address: 0x60008924
-        /// Register 2 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY4.
-            KEY4_DATA2: u32,
-        }), base_address + 0x124);
-
-        /// address: 0x60008928
-        /// Register 3 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY4.
-            KEY4_DATA3: u32,
-        }), base_address + 0x128);
-
-        /// address: 0x6000892c
-        /// Register 4 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY4.
-            KEY4_DATA4: u32,
-        }), base_address + 0x12c);
-
-        /// address: 0x60008930
-        /// Register 5 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY4.
-            KEY4_DATA5: u32,
-        }), base_address + 0x130);
-
-        /// address: 0x60008934
-        /// Register 6 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY4.
-            KEY4_DATA6: u32,
-        }), base_address + 0x134);
-
-        /// address: 0x60008938
-        /// Register 7 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY4.
-            KEY4_DATA7: u32,
-        }), base_address + 0x138);
-
-        /// address: 0x6000893c
-        /// Register 0 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY5.
-            KEY5_DATA0: u32,
-        }), base_address + 0x13c);
-
-        /// address: 0x60008940
-        /// Register 1 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY5.
-            KEY5_DATA1: u32,
-        }), base_address + 0x140);
-
-        /// address: 0x60008944
-        /// Register 2 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY5.
-            KEY5_DATA2: u32,
-        }), base_address + 0x144);
-
-        /// address: 0x60008948
-        /// Register 3 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY5.
-            KEY5_DATA3: u32,
-        }), base_address + 0x148);
-
-        /// address: 0x6000894c
-        /// Register 4 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY5.
-            KEY5_DATA4: u32,
-        }), base_address + 0x14c);
-
-        /// address: 0x60008950
-        /// Register 5 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY5.
-            KEY5_DATA5: u32,
-        }), base_address + 0x150);
-
-        /// address: 0x60008954
-        /// Register 6 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY5.
-            KEY5_DATA6: u32,
-        }), base_address + 0x154);
-
-        /// address: 0x60008958
-        /// Register 7 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY5.
-            KEY5_DATA7: u32,
-        }), base_address + 0x158);
-
-        /// address: 0x6000895c
-        /// Register 0 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 0th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_0: u32,
-        }), base_address + 0x15c);
-
-        /// address: 0x60008960
-        /// Register 1 of BLOCK9 (KEY5).
-        pub const RD_SYS_PART2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 1st 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_1: u32,
-        }), base_address + 0x160);
-
-        /// address: 0x60008964
-        /// Register 2 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 2nd 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_2: u32,
-        }), base_address + 0x164);
-
-        /// address: 0x60008968
-        /// Register 3 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 3rd 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_3: u32,
-        }), base_address + 0x168);
-
-        /// address: 0x6000896c
-        /// Register 4 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 4th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_4: u32,
-        }), base_address + 0x16c);
-
-        /// address: 0x60008970
-        /// Register 5 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 5th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_5: u32,
-        }), base_address + 0x170);
-
-        /// address: 0x60008974
-        /// Register 6 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 6th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_6: u32,
-        }), base_address + 0x174);
-
-        /// address: 0x60008978
-        /// Register 7 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 7th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_7: u32,
-        }), base_address + 0x178);
-
-        /// address: 0x6000897c
-        /// Programming error record register 0 of BLOCK0.
-        pub const RD_REPEAT_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If any bit in RD_DIS is 1, then it indicates a programming error.
-            RD_DIS_ERR: u7,
-            /// If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
-            DIS_RTC_RAM_BOOT_ERR: u1,
-            /// If DIS_ICACHE is 1, then it indicates a programming error.
-            DIS_ICACHE_ERR: u1,
-            /// If DIS_USB_JTAG is 1, then it indicates a programming error.
-            DIS_USB_JTAG_ERR: u1,
-            /// If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_ICACHE_ERR: u1,
-            /// If DIS_USB_DEVICE is 1, then it indicates a programming error.
-            DIS_USB_DEVICE_ERR: u1,
-            /// If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
-            DIS_FORCE_DOWNLOAD_ERR: u1,
-            /// Reserved.
-            RPT4_RESERVED6_ERR: u1,
-            /// If DIS_CAN is 1, then it indicates a programming error.
-            DIS_CAN_ERR: u1,
-            /// If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
-            JTAG_SEL_ENABLE_ERR: u1,
-            /// If SOFT_DIS_JTAG is 1, then it indicates a programming error.
-            SOFT_DIS_JTAG_ERR: u3,
-            /// If DIS_PAD_JTAG is 1, then it indicates a programming error.
-            DIS_PAD_JTAG_ERR: u1,
-            /// If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
-            /// If any bit in USB_DREFH is 1, then it indicates a programming error.
-            USB_DREFH_ERR: u2,
-            /// If any bit in USB_DREFL is 1, then it indicates a programming error.
-            USB_DREFL_ERR: u2,
-            /// If USB_EXCHG_PINS is 1, then it indicates a programming error.
-            USB_EXCHG_PINS_ERR: u1,
-            /// If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
-            VDD_SPI_AS_GPIO_ERR: u1,
-            /// If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
-            BTLC_GPIO_ENABLE_ERR: u2,
-            /// If POWERGLITCH_EN is 1, then it indicates a programming error.
-            POWERGLITCH_EN_ERR: u1,
-            /// If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
-            POWER_GLITCH_DSENSE_ERR: u2,
-        }), base_address + 0x17c);
-
-        /// address: 0x60008980
-        /// Programming error record register 1 of BLOCK0.
-        pub const RD_REPEAT_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RPT4_RESERVED2_ERR: u16,
-            /// If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-            WDT_DELAY_SEL_ERR: u2,
-            /// If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
-            SPI_BOOT_CRYPT_CNT_ERR: u3,
-            /// If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE0_ERR: u1,
-            /// If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE1_ERR: u1,
-            /// If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE2_ERR: u1,
-            /// If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
-            KEY_PURPOSE_0_ERR: u4,
-            /// If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
-            KEY_PURPOSE_1_ERR: u4,
-        }), base_address + 0x180);
-
-        /// address: 0x60008984
-        /// Programming error record register 2 of BLOCK0.
-        pub const RD_REPEAT_ERR2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
-            KEY_PURPOSE_2_ERR: u4,
-            /// If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
-            KEY_PURPOSE_3_ERR: u4,
-            /// If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
-            KEY_PURPOSE_4_ERR: u4,
-            /// If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
-            KEY_PURPOSE_5_ERR: u4,
-            /// Reserved.
-            RPT4_RESERVED3_ERR: u4,
-            /// If SECURE_BOOT_EN is 1, then it indicates a programming error.
-            SECURE_BOOT_EN_ERR: u1,
-            /// If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
-            SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
-            /// Reserved.
-            RPT4_RESERVED0_ERR: u6,
-            /// If any bit in FLASH_TPUM is 1, then it indicates a programming error.
-            FLASH_TPUW_ERR: u4,
-        }), base_address + 0x184);
-
-        /// address: 0x60008988
-        /// Programming error record register 3 of BLOCK0.
-        pub const RD_REPEAT_ERR3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_MODE_ERR: u1,
-            /// If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
-            DIS_LEGACY_SPI_BOOT_ERR: u1,
-            /// If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
-            UART_PRINT_CHANNEL_ERR: u1,
-            /// If FLASH_ECC_MODE is 1, then it indicates a programming error.
-            FLASH_ECC_MODE_ERR: u1,
-            /// If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
-            DIS_USB_DOWNLOAD_MODE_ERR: u1,
-            /// If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
-            ENABLE_SECURITY_DOWNLOAD_ERR: u1,
-            /// If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-            UART_PRINT_CONTROL_ERR: u2,
-            /// If PIN_POWER_SELECTION is 1, then it indicates a programming error.
-            PIN_POWER_SELECTION_ERR: u1,
-            /// If FLASH_TYPE is 1, then it indicates a programming error.
-            FLASH_TYPE_ERR: u1,
-            /// If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
-            FLASH_PAGE_SIZE_ERR: u2,
-            /// If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
-            FLASH_ECC_EN_ERR: u1,
-            /// If FORCE_SEND_RESUME is 1, then it indicates a programming error.
-            FORCE_SEND_RESUME_ERR: u1,
-            /// If any bit in SECURE_VERSION is 1, then it indicates a programming error.
-            SECURE_VERSION_ERR: u16,
-            /// Reserved.
-            RPT4_RESERVED1_ERR: u2,
-        }), base_address + 0x188);
-
-        /// address: 0x60008990
-        /// Programming error record register 4 of BLOCK0.
-        pub const RD_REPEAT_ERR4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RPT4_RESERVED4_ERR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x600089c0
-        /// Programming error record register 0 of BLOCK1-10.
-        pub const RD_RS_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of this signal means the number of error bytes.
-            MAC_SPI_8M_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            MAC_SPI_8M_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            SYS_PART1_NUM: u3,
-            /// 0: Means no failure and that the data of system part1 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            SYS_PART1_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            USR_DATA_ERR_NUM: u3,
-            /// 0: Means no failure and that the user data is reliable 1: Means that programming
-            /// user data failed and the number of error bytes is over 6.
-            USR_DATA_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY0_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key0 is reliable 1: Means that
-            /// programming key0 failed and the number of error bytes is over 6.
-            KEY0_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY1_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key1 is reliable 1: Means that
-            /// programming key1 failed and the number of error bytes is over 6.
-            KEY1_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY2_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key2 is reliable 1: Means that
-            /// programming key2 failed and the number of error bytes is over 6.
-            KEY2_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY3_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key3 is reliable 1: Means that
-            /// programming key3 failed and the number of error bytes is over 6.
-            KEY3_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY4_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key4 is reliable 1: Means that
-            /// programming key4 failed and the number of error bytes is over 6.
-            KEY4_FAIL: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x600089c4
-        /// Programming error record register 1 of BLOCK1-10.
-        pub const RD_RS_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of this signal means the number of error bytes.
-            KEY5_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of KEY5 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            KEY5_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            SYS_PART2_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of system part2 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            SYS_PART2_FAIL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c4);
-
-        /// address: 0x600089c8
-        /// eFuse clcok configuration register.
-        pub const CLK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to force eFuse SRAM into power-saving mode.
-            EFUSE_MEM_FORCE_PD: u1,
-            /// Set this bit and force to activate clock signal of eFuse SRAM.
-            MEM_CLK_FORCE_ON: u1,
-            /// Set this bit to force eFuse SRAM into working mode.
-            EFUSE_MEM_FORCE_PU: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// Set this bit and force to enable clock signal of eFuse memory.
-            EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x1c8);
-
-        /// address: 0x600089cc
-        /// eFuse operation mode configuraiton register;
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0x5A5A: Operate programming command 0x5AA5: Operate read command.
-            OP_CODE: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1cc);
-
-        /// address: 0x600089d0
-        /// eFuse status register.
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Indicates the state of the eFuse state machine.
-            STATE: u4,
-            /// The value of OTP_LOAD_SW.
-            OTP_LOAD_SW: u1,
-            /// The value of OTP_VDDQ_C_SYNC2.
-            OTP_VDDQ_C_SYNC2: u1,
-            /// The value of OTP_STROBE_SW.
-            OTP_STROBE_SW: u1,
-            /// The value of OTP_CSB_SW.
-            OTP_CSB_SW: u1,
-            /// The value of OTP_PGENB_SW.
-            OTP_PGENB_SW: u1,
-            /// The value of OTP_VDDQ_IS_SW.
-            OTP_VDDQ_IS_SW: u1,
-            /// Indicates the number of error bits during programming BLOCK0.
-            REPEAT_ERR_CNT: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1d0);
-
-        /// address: 0x600089d4
-        /// eFuse command register.
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to send read command.
-            READ_CMD: u1,
-            /// Set this bit to send programming command.
-            PGM_CMD: u1,
-            /// The serial number of the block to be programmed. Value 0-10 corresponds to block
-            /// number 0-10, respectively.
-            BLK_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x1d4);
-
-        /// address: 0x600089d8
-        /// eFuse raw interrupt register.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw bit signal for read_done interrupt.
-            READ_DONE_INT_RAW: u1,
-            /// The raw bit signal for pgm_done interrupt.
-            PGM_DONE_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1d8);
-
-        /// address: 0x600089dc
-        /// eFuse interrupt status register.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status signal for read_done interrupt.
-            READ_DONE_INT_ST: u1,
-            /// The status signal for pgm_done interrupt.
-            PGM_DONE_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1dc);
-
-        /// address: 0x600089e0
-        /// eFuse interrupt enable register.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable signal for read_done interrupt.
-            READ_DONE_INT_ENA: u1,
-            /// The enable signal for pgm_done interrupt.
-            PGM_DONE_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1e0);
-
-        /// address: 0x600089e4
-        /// eFuse interrupt clear register.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear signal for read_done interrupt.
-            READ_DONE_INT_CLR: u1,
-            /// The clear signal for pgm_done interrupt.
-            PGM_DONE_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1e4);
-
-        /// address: 0x600089e8
-        /// Controls the eFuse programming voltage.
-        pub const DAC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Controls the division factor of the rising clock of the programming voltage.
-            DAC_CLK_DIV: u8,
-            /// Don't care.
-            DAC_CLK_PAD_SEL: u1,
-            /// Controls the rising period of the programming voltage.
-            DAC_NUM: u8,
-            /// Reduces the power supply of the programming voltage.
-            OE_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1e8);
-
-        /// address: 0x600089ec
-        /// Configures read timing parameters.
-        pub const RD_TIM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            /// Configures the initial read time of eFuse.
-            READ_INIT_NUM: u8,
-        }), base_address + 0x1ec);
-
-        /// address: 0x600089f0
-        /// Configurarion register 1 of eFuse programming timing parameters.
-        pub const WR_TIM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// Configures the power up time for VDDQ.
-            PWR_ON_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x600089f4
-        /// Configurarion register 2 of eFuse programming timing parameters.
-        pub const WR_TIM_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Configures the power outage time for VDDQ.
-            PWR_OFF_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x600089fc
-        /// eFuse version register.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x1fc);
-    };
-
-    /// External Memory
-    pub const EXTMEM = struct {
-        pub const base_address = 0x600c4000;
-
-        /// address: 0x600c4000
-        /// This description will be updated in the near future.
-        pub const ICACHE_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to activate the data cache. 0: disable, 1: enable
-            ICACHE_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600c4004
-        /// This description will be updated in the near future.
-        pub const ICACHE_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable core0 ibus, 0: enable, 1: disable
-            ICACHE_SHUT_IBUS: u1,
-            /// The bit is used to disable core1 ibus, 0: enable, 1: disable
-            ICACHE_SHUT_DBUS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600c4008
-        /// This description will be updated in the near future.
-        pub const ICACHE_TAG_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to close clock gating of icache tag memory. 1: close gating, 0:
-            /// open clock gating.
-            ICACHE_TAG_MEM_FORCE_ON: u1,
-            /// The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power
-            /// down
-            ICACHE_TAG_MEM_FORCE_PD: u1,
-            /// The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
-            ICACHE_TAG_MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600c400c
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable the first section of prelock function.
-            ICACHE_PRELOCK_SCT0_EN: u1,
-            /// The bit is used to enable the second section of prelock function.
-            ICACHE_PRELOCK_SCT1_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600c4010
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x600c4014
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x600c4018
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT_SIZE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to configure the second length of data locking, which is
-            /// combined with ICACHE_PRELOCK_SCT1_ADDR_REG
-            ICACHE_PRELOCK_SCT1_SIZE: u16,
-            /// The bits are used to configure the first length of data locking, which is
-            /// combined with ICACHE_PRELOCK_SCT0_ADDR_REG
-            ICACHE_PRELOCK_SCT0_SIZE: u16,
-        }), base_address + 0x18);
-
-        /// address: 0x600c401c
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable lock operation. It will be cleared by hardware after
-            /// lock operation done.
-            ICACHE_LOCK_ENA: u1,
-            /// The bit is used to enable unlock operation. It will be cleared by hardware after
-            /// unlock operation done.
-            ICACHE_UNLOCK_ENA: u1,
-            /// The bit is used to indicate unlock/lock operation is finished.
-            ICACHE_LOCK_DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c4020
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_ADDR = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x600c4024
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24);
-
-        /// address: 0x600c4028
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable invalidate operation. It will be cleared by hardware
-            /// after invalidate operation done.
-            ICACHE_INVALIDATE_ENA: u1,
-            /// The bit is used to indicate invalidate operation is finished.
-            ICACHE_SYNC_DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x600c402c
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_ADDR = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x600c4030
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_SIZE = @intToPtr(*volatile MmioInt(32, u23), base_address + 0x30);
-
-        /// address: 0x600c4034
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable preload operation. It will be cleared by hardware
-            /// after preload operation done.
-            ICACHE_PRELOAD_ENA: u1,
-            /// The bit is used to indicate preload operation is finished.
-            ICACHE_PRELOAD_DONE: u1,
-            /// The bit is used to configure the direction of preload operation. 1: descending,
-            /// 0: ascending.
-            ICACHE_PRELOAD_ORDER: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x600c4038
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_ADDR = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x600c403c
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c);
-
-        /// address: 0x600c4040
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to enable the first section for autoload operation.
-            ICACHE_AUTOLOAD_SCT0_ENA: u1,
-            /// The bits are used to enable the second section for autoload operation.
-            ICACHE_AUTOLOAD_SCT1_ENA: u1,
-            /// The bit is used to enable and disable autoload operation. It is combined with
-            /// icache_autoload_done. 1: enable, 0: disable.
-            ICACHE_AUTOLOAD_ENA: u1,
-            /// The bit is used to indicate autoload operation is finished.
-            ICACHE_AUTOLOAD_DONE: u1,
-            /// The bits are used to configure the direction of autoload. 1: descending, 0:
-            /// ascending.
-            ICACHE_AUTOLOAD_ORDER: u1,
-            /// The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
-            /// 1: cache hit, 2: both cache miss and hit.
-            ICACHE_AUTOLOAD_RQST: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c4044
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x44);
-
-        /// address: 0x600c4048
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT0_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x48);
-
-        /// address: 0x600c404c
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x4c);
-
-        /// address: 0x600c4050
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT1_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x50);
-
-        /// address: 0x600c4054
-        /// This description will be updated in the near future.
-        pub const IBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x54);
-
-        /// address: 0x600c4058
-        /// This description will be updated in the near future.
-        pub const IBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x58);
-
-        /// address: 0x600c405c
-        /// This description will be updated in the near future.
-        pub const DBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x5c);
-
-        /// address: 0x600c4060
-        /// This description will be updated in the near future.
-        pub const DBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x60);
-
-        /// address: 0x600c4064
-        /// This description will be updated in the near future.
-        pub const CACHE_ACS_CNT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear ibus counter.
-            IBUS_ACS_CNT_CLR: u1,
-            /// The bit is used to clear dbus counter.
-            DBUS_ACS_CNT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c4068
-        /// This description will be updated in the near future.
-        pub const IBUS_ACS_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x68);
-
-        /// address: 0x600c406c
-        /// This description will be updated in the near future.
-        pub const IBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x6c);
-
-        /// address: 0x600c4070
-        /// This description will be updated in the near future.
-        pub const DBUS_ACS_FLASH_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x70);
-
-        /// address: 0x600c4074
-        /// This description will be updated in the near future.
-        pub const DBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x600c4078
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to enable interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_INT_ENA: u1,
-            reserved3: u1,
-            /// The bit is used to enable interrupt by ibus counter overflow.
-            IBUS_CNT_OVF_INT_ENA: u1,
-            /// The bit is used to enable interrupt by dbus counter overflow.
-            DBUS_CNT_OVF_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c407c
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to clear interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_INT_CLR: u1,
-            reserved3: u1,
-            /// The bit is used to clear interrupt by ibus counter overflow.
-            IBUS_CNT_OVF_INT_CLR: u1,
-            /// The bit is used to clear interrupt by dbus counter overflow.
-            DBUS_CNT_OVF_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c4080
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_ST: u1,
-            /// The bit is used to indicate interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_ST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to indicate interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_ST: u1,
-            reserved3: u1,
-            /// The bit is used to indicate interrupt by ibus access flash/spiram counter
-            /// overflow.
-            IBUS_ACS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by ibus access flash/spiram miss counter
-            /// overflow.
-            IBUS_ACS_MISS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by dbus access flash/spiram counter
-            /// overflow.
-            DBUS_ACS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by dbus access flash miss counter
-            /// overflow.
-            DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c4084
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable interrupt by cpu access icache while the corresponding
-            /// ibus is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by authentication fail.
-            CORE0_IBUS_REJECT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by cpu access icache while the corresponding
-            /// dbus is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by authentication fail.
-            CORE0_DBUS_REJECT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_IC_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c4088
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear interrupt by cpu access icache while the corresponding
-            /// ibus is disabled or icache is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by authentication fail.
-            CORE0_IBUS_REJECT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by cpu access icache while the corresponding
-            /// dbus is disabled or icache is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by authentication fail.
-            CORE0_DBUS_REJECT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_IC_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c408c
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate interrupt by cpu access icache while the core0_ibus
-            /// is disabled or icache is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by authentication fail.
-            CORE0_IBUS_REJECT_ST: u1,
-            /// The bit is used to indicate interrupt by cpu access icache while the core0_dbus
-            /// is disabled or icache is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by authentication fail.
-            CORE0_DBUS_REJECT_ST: u1,
-            /// The bit is used to indicate interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_ICACHE_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c4090
-        /// This description will be updated in the near future.
-        pub const CORE0_DBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the attribute of CPU access dbus when
-            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4:
-            /// write-able.
-            CORE0_DBUS_ATTR: u3,
-            /// The bit is used to indicate the world of CPU access dbus when authentication
-            /// fail. 0: WORLD0, 1: WORLD1
-            CORE0_DBUS_WORLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c4094
-        /// This description will be updated in the near future.
-        pub const CORE0_DBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the virtual address of CPU access dbus when
-            /// authentication fail.
-            CORE0_DBUS_VADDR: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x600c4098
-        /// This description will be updated in the near future.
-        pub const CORE0_IBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the attribute of CPU access ibus when
-            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able
-            CORE0_IBUS_ATTR: u3,
-            /// The bit is used to indicate the world of CPU access ibus when authentication
-            /// fail. 0: WORLD0, 1: WORLD1
-            CORE0_IBUS_WORLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c409c
-        /// This description will be updated in the near future.
-        pub const CORE0_IBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the virtual address of CPU access ibus when
-            /// authentication fail.
-            CORE0_IBUS_VADDR: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600c40a0
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_FAULT_CONTENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the content of mmu entry which cause mmu fault..
-            CACHE_MMU_FAULT_CONTENT: u10,
-            /// The right-most 3 bits are used to indicate the operations which cause mmu fault
-            /// occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
-            /// evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
-            /// 7: external dma rx. The most significant bit is used to indicate this operation
-            /// occurs in which one icache.
-            CACHE_MMU_FAULT_CODE: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600c40a4
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_FAULT_VADDR = @intToPtr(*volatile u32, base_address + 0xa4);
-
-        /// address: 0x600c40a8
-        /// This description will be updated in the near future.
-        pub const CACHE_WRAP_AROUND_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable wrap around mode when read data from flash.
-            CACHE_FLASH_WRAP_AROUND: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600c40ac
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable clock gating to save power when access mmu memory, 0:
-            /// enable, 1: disable
-            CACHE_MMU_MEM_FORCE_ON: u1,
-            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
-            CACHE_MMU_MEM_FORCE_PD: u1,
-            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
-            CACHE_MMU_MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600c40b0
-        /// This description will be updated in the near future.
-        pub const CACHE_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate whether icache main fsm is in idle state or not. 1:
-            /// in idle state, 0: not in idle state
-            ICACHE_STATE: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600c40b4
-        /// This description will be updated in the near future.
-        pub const CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RECORD_DISABLE_DB_ENCRYPT: u1,
-            /// Reserved.
-            RECORD_DISABLE_G0CB_DECRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600c40b8
-        /// This description will be updated in the near future.
-        pub const CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
-            /// open clock gating.
-            CLK_FORCE_ON_MANUAL_CRYPT: u1,
-            /// The bit is used to close clock gating of automatic crypt clock. 1: close gating,
-            /// 0: open clock gating.
-            CLK_FORCE_ON_AUTO_CRYPT: u1,
-            /// The bit is used to close clock gating of external memory encrypt and decrypt
-            /// clock. 1: close gating, 0: open clock gating.
-            CLK_FORCE_ON_CRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600c40bc
-        /// This description will be updated in the near future.
-        pub const CACHE_PRELOAD_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_ST: u1,
-            /// The bit is used to enable the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_ENA: u1,
-            /// The bit is used to clear the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600c40c0
-        /// This description will be updated in the near future.
-        pub const CACHE_SYNC_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate the interrupt by icache sync done.
-            ICACHE_SYNC_INT_ST: u1,
-            /// The bit is used to enable the interrupt by icache sync done.
-            ICACHE_SYNC_INT_ENA: u1,
-            /// The bit is used to clear the interrupt by icache sync done.
-            ICACHE_SYNC_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600c40c4
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_OWNER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xc4);
-
-        /// address: 0x600c40c8
-        /// This description will be updated in the near future.
-        pub const CACHE_CONF_MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable checking mmu entry fault by preload operation.
-            CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
-            /// The bit is used to disable checking mmu entry fault by sync operation.
-            CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
-            /// The bit is used to enable cache trace function.
-            CACHE_TRACE_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600c40cc
-        /// This description will be updated in the near future.
-        pub const ICACHE_FREEZE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable icache freeze mode
-            ENA: u1,
-            /// The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert
-            /// hit if CPU miss
-            MODE: u1,
-            /// The bit is used to indicate icache freeze success
-            DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600c40d0
-        /// This description will be updated in the near future.
-        pub const ICACHE_ATOMIC_OPERATE_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xd0);
-
-        /// address: 0x600c40d4
-        /// This description will be updated in the near future.
-        pub const CACHE_REQUEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable request recording which could cause performance issue
-            BYPASS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600c40d8
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            IBUS_PMS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600c40dc
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            IBUS_PMS_BOUNDARY0: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600c40e0
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary1
-            IBUS_PMS_BOUNDARY1: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600c40e4
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary2
-            IBUS_PMS_BOUNDARY2: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x600c40e8
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure attribute of the ibus permission control section1,
-            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
-            /// in world1
-            IBUS_PMS_SCT1_ATTR: u4,
-            /// The bit is used to configure attribute of the ibus permission control section2,
-            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
-            /// in world1
-            IBUS_PMS_SCT2_ATTR: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x600c40ec
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            DBUS_PMS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xec);
-
-        /// address: 0x600c40f0
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary0
-            DBUS_PMS_BOUNDARY0: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x600c40f4
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary1
-            DBUS_PMS_BOUNDARY1: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600c40f8
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary2
-            DBUS_PMS_BOUNDARY2: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c40fc
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure attribute of the dbus permission control section1,
-            /// bit0: load in world0, bit2: load in world1
-            DBUS_PMS_SCT1_ATTR: u2,
-            /// The bit is used to configure attribute of the dbus permission control section2,
-            /// bit0: load in world0, bit2: load in world1
-            DBUS_PMS_SCT2_ATTR: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c4100
-        /// This description will be updated in the near future.
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clock gate enable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c43fc
-        /// This description will be updated in the near future.
-        pub const REG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// version information
-            DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x3fc);
-    };
-
-    /// General Purpose Input/Output
-    pub const GPIO = struct {
-        pub const base_address = 0x60004000;
-
-        /// address: 0x60004000
-        /// GPIO bit select register
-        pub const BT_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO bit select register
-            BT_SEL: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60004004
-        /// GPIO output register
-        pub const OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO output register for GPIO0-25
-            DATA_ORIG: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60004008
-        /// GPIO output set register
-        pub const OUT_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x8);
-
-        /// address: 0x6000400c
-        /// GPIO output clear register
-        pub const OUT_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0xc);
-
-        /// address: 0x6000401c
-        /// GPIO sdio select register
-        pub const SDIO_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO sdio select register
-            SDIO_SEL: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60004020
-        /// GPIO output enable register
-        pub const ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO output enable register for GPIO0-25
-            DATA: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60004024
-        /// GPIO output enable set register
-        pub const ENABLE_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x24);
-
-        /// address: 0x60004028
-        /// GPIO output enable clear register
-        pub const ENABLE_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x28);
-
-        /// address: 0x60004038
-        /// pad strapping register
-        pub const STRAP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pad strapping register
-            STRAPPING: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000403c
-        /// GPIO input register
-        pub const IN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO input register for GPIO0-25
-            DATA_NEXT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60004044
-        /// GPIO interrupt status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO interrupt status register for GPIO0-25
-            INTERRUPT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60004048
-        /// GPIO interrupt status set register
-        pub const STATUS_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x48);
-
-        /// address: 0x6000404c
-        /// GPIO interrupt status clear register
-        pub const STATUS_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x4c);
-
-        /// address: 0x6000405c
-        /// GPIO PRO_CPU interrupt status register
-        pub const PCPU_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO PRO_CPU interrupt status register for GPIO0-25
-            PROCPU_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60004060
-        /// GPIO PRO_CPU(not shielded) interrupt status register
-        pub const PCPU_NMI_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
-            PROCPU_NMI_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60004064
-        /// GPIO CPUSDIO interrupt status register
-        pub const CPUSDIO_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO CPUSDIO interrupt status register for GPIO0-25
-            SDIO_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60004074
-        /// GPIO pin configuration register
-        pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60004078
-        /// GPIO pin configuration register
-        pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000407c
-        /// GPIO pin configuration register
-        pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60004080
-        /// GPIO pin configuration register
-        pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60004084
-        /// GPIO pin configuration register
-        pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x60004088
-        /// GPIO pin configuration register
-        pub const PIN5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6000408c
-        /// GPIO pin configuration register
-        pub const PIN6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x60004090
-        /// GPIO pin configuration register
-        pub const PIN7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60004094
-        /// GPIO pin configuration register
-        pub const PIN8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x60004098
-        /// GPIO pin configuration register
-        pub const PIN9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6000409c
-        /// GPIO pin configuration register
-        pub const PIN10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600040a0
-        /// GPIO pin configuration register
-        pub const PIN11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600040a4
-        /// GPIO pin configuration register
-        pub const PIN12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600040a8
-        /// GPIO pin configuration register
-        pub const PIN13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600040ac
-        /// GPIO pin configuration register
-        pub const PIN14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600040b0
-        /// GPIO pin configuration register
-        pub const PIN15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600040b4
-        /// GPIO pin configuration register
-        pub const PIN16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600040b8
-        /// GPIO pin configuration register
-        pub const PIN17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600040bc
-        /// GPIO pin configuration register
-        pub const PIN18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600040c0
-        /// GPIO pin configuration register
-        pub const PIN19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600040c4
-        /// GPIO pin configuration register
-        pub const PIN20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600040c8
-        /// GPIO pin configuration register
-        pub const PIN21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600040cc
-        /// GPIO pin configuration register
-        pub const PIN22 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600040d0
-        /// GPIO pin configuration register
-        pub const PIN23 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600040d4
-        /// GPIO pin configuration register
-        pub const PIN24 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600040d8
-        /// GPIO pin configuration register
-        pub const PIN25 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x6000414c
-        /// GPIO interrupt source register
-        pub const STATUS_NEXT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO interrupt source register for GPIO0-25
-            STATUS_INTERRUPT_NEXT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x60004154
-        /// GPIO input function configuration register
-        pub const FUNC0_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x154);
-
-        /// address: 0x60004158
-        /// GPIO input function configuration register
-        pub const FUNC1_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x6000415c
-        /// GPIO input function configuration register
-        pub const FUNC2_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x60004160
-        /// GPIO input function configuration register
-        pub const FUNC3_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x60004164
-        /// GPIO input function configuration register
-        pub const FUNC4_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x60004168
-        /// GPIO input function configuration register
-        pub const FUNC5_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x6000416c
-        /// GPIO input function configuration register
-        pub const FUNC6_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x16c);
-
-        /// address: 0x60004170
-        /// GPIO input function configuration register
-        pub const FUNC7_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x60004174
-        /// GPIO input function configuration register
-        pub const FUNC8_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x174);
-
-        /// address: 0x60004178
-        /// GPIO input function configuration register
-        pub const FUNC9_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x178);
-
-        /// address: 0x6000417c
-        /// GPIO input function configuration register
-        pub const FUNC10_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x17c);
-
-        /// address: 0x60004180
-        /// GPIO input function configuration register
-        pub const FUNC11_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x180);
-
-        /// address: 0x60004184
-        /// GPIO input function configuration register
-        pub const FUNC12_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x184);
-
-        /// address: 0x60004188
-        /// GPIO input function configuration register
-        pub const FUNC13_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x188);
-
-        /// address: 0x6000418c
-        /// GPIO input function configuration register
-        pub const FUNC14_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x18c);
-
-        /// address: 0x60004190
-        /// GPIO input function configuration register
-        pub const FUNC15_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x60004194
-        /// GPIO input function configuration register
-        pub const FUNC16_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x194);
-
-        /// address: 0x60004198
-        /// GPIO input function configuration register
-        pub const FUNC17_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x198);
-
-        /// address: 0x6000419c
-        /// GPIO input function configuration register
-        pub const FUNC18_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x19c);
-
-        /// address: 0x600041a0
-        /// GPIO input function configuration register
-        pub const FUNC19_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a0);
-
-        /// address: 0x600041a4
-        /// GPIO input function configuration register
-        pub const FUNC20_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a4);
-
-        /// address: 0x600041a8
-        /// GPIO input function configuration register
-        pub const FUNC21_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a8);
-
-        /// address: 0x600041ac
-        /// GPIO input function configuration register
-        pub const FUNC22_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1ac);
-
-        /// address: 0x600041b0
-        /// GPIO input function configuration register
-        pub const FUNC23_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b0);
-
-        /// address: 0x600041b4
-        /// GPIO input function configuration register
-        pub const FUNC24_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b4);
-
-        /// address: 0x600041b8
-        /// GPIO input function configuration register
-        pub const FUNC25_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b8);
-
-        /// address: 0x600041bc
-        /// GPIO input function configuration register
-        pub const FUNC26_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1bc);
-
-        /// address: 0x600041c0
-        /// GPIO input function configuration register
-        pub const FUNC27_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x600041c4
-        /// GPIO input function configuration register
-        pub const FUNC28_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c4);
-
-        /// address: 0x600041c8
-        /// GPIO input function configuration register
-        pub const FUNC29_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c8);
-
-        /// address: 0x600041cc
-        /// GPIO input function configuration register
-        pub const FUNC30_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1cc);
-
-        /// address: 0x600041d0
-        /// GPIO input function configuration register
-        pub const FUNC31_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d0);
-
-        /// address: 0x600041d4
-        /// GPIO input function configuration register
-        pub const FUNC32_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d4);
-
-        /// address: 0x600041d8
-        /// GPIO input function configuration register
-        pub const FUNC33_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d8);
-
-        /// address: 0x600041dc
-        /// GPIO input function configuration register
-        pub const FUNC34_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1dc);
-
-        /// address: 0x600041e0
-        /// GPIO input function configuration register
-        pub const FUNC35_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e0);
-
-        /// address: 0x600041e4
-        /// GPIO input function configuration register
-        pub const FUNC36_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e4);
-
-        /// address: 0x600041e8
-        /// GPIO input function configuration register
-        pub const FUNC37_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e8);
-
-        /// address: 0x600041ec
-        /// GPIO input function configuration register
-        pub const FUNC38_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1ec);
-
-        /// address: 0x600041f0
-        /// GPIO input function configuration register
-        pub const FUNC39_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x600041f4
-        /// GPIO input function configuration register
-        pub const FUNC40_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x600041f8
-        /// GPIO input function configuration register
-        pub const FUNC41_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f8);
-
-        /// address: 0x600041fc
-        /// GPIO input function configuration register
-        pub const FUNC42_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1fc);
-
-        /// address: 0x60004200
-        /// GPIO input function configuration register
-        pub const FUNC43_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x200);
-
-        /// address: 0x60004204
-        /// GPIO input function configuration register
-        pub const FUNC44_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x204);
-
-        /// address: 0x60004208
-        /// GPIO input function configuration register
-        pub const FUNC45_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x208);
-
-        /// address: 0x6000420c
-        /// GPIO input function configuration register
-        pub const FUNC46_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x20c);
-
-        /// address: 0x60004210
-        /// GPIO input function configuration register
-        pub const FUNC47_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x210);
-
-        /// address: 0x60004214
-        /// GPIO input function configuration register
-        pub const FUNC48_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x214);
-
-        /// address: 0x60004218
-        /// GPIO input function configuration register
-        pub const FUNC49_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x218);
-
-        /// address: 0x6000421c
-        /// GPIO input function configuration register
-        pub const FUNC50_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x21c);
-
-        /// address: 0x60004220
-        /// GPIO input function configuration register
-        pub const FUNC51_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x220);
-
-        /// address: 0x60004224
-        /// GPIO input function configuration register
-        pub const FUNC52_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x224);
-
-        /// address: 0x60004228
-        /// GPIO input function configuration register
-        pub const FUNC53_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x228);
-
-        /// address: 0x6000422c
-        /// GPIO input function configuration register
-        pub const FUNC54_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x22c);
-
-        /// address: 0x60004230
-        /// GPIO input function configuration register
-        pub const FUNC55_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x230);
-
-        /// address: 0x60004234
-        /// GPIO input function configuration register
-        pub const FUNC56_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x234);
-
-        /// address: 0x60004238
-        /// GPIO input function configuration register
-        pub const FUNC57_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x238);
-
-        /// address: 0x6000423c
-        /// GPIO input function configuration register
-        pub const FUNC58_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x23c);
-
-        /// address: 0x60004240
-        /// GPIO input function configuration register
-        pub const FUNC59_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x240);
-
-        /// address: 0x60004244
-        /// GPIO input function configuration register
-        pub const FUNC60_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x244);
-
-        /// address: 0x60004248
-        /// GPIO input function configuration register
-        pub const FUNC61_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x248);
-
-        /// address: 0x6000424c
-        /// GPIO input function configuration register
-        pub const FUNC62_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x24c);
-
-        /// address: 0x60004250
-        /// GPIO input function configuration register
-        pub const FUNC63_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x250);
-
-        /// address: 0x60004254
-        /// GPIO input function configuration register
-        pub const FUNC64_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x254);
-
-        /// address: 0x60004258
-        /// GPIO input function configuration register
-        pub const FUNC65_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x258);
-
-        /// address: 0x6000425c
-        /// GPIO input function configuration register
-        pub const FUNC66_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x25c);
-
-        /// address: 0x60004260
-        /// GPIO input function configuration register
-        pub const FUNC67_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x260);
-
-        /// address: 0x60004264
-        /// GPIO input function configuration register
-        pub const FUNC68_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x264);
-
-        /// address: 0x60004268
-        /// GPIO input function configuration register
-        pub const FUNC69_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x268);
-
-        /// address: 0x6000426c
-        /// GPIO input function configuration register
-        pub const FUNC70_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x26c);
-
-        /// address: 0x60004270
-        /// GPIO input function configuration register
-        pub const FUNC71_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x270);
-
-        /// address: 0x60004274
-        /// GPIO input function configuration register
-        pub const FUNC72_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x274);
-
-        /// address: 0x60004278
-        /// GPIO input function configuration register
-        pub const FUNC73_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x278);
-
-        /// address: 0x6000427c
-        /// GPIO input function configuration register
-        pub const FUNC74_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x27c);
-
-        /// address: 0x60004280
-        /// GPIO input function configuration register
-        pub const FUNC75_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x280);
-
-        /// address: 0x60004284
-        /// GPIO input function configuration register
-        pub const FUNC76_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x284);
-
-        /// address: 0x60004288
-        /// GPIO input function configuration register
-        pub const FUNC77_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x288);
-
-        /// address: 0x6000428c
-        /// GPIO input function configuration register
-        pub const FUNC78_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x28c);
-
-        /// address: 0x60004290
-        /// GPIO input function configuration register
-        pub const FUNC79_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x290);
-
-        /// address: 0x60004294
-        /// GPIO input function configuration register
-        pub const FUNC80_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x294);
-
-        /// address: 0x60004298
-        /// GPIO input function configuration register
-        pub const FUNC81_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x298);
-
-        /// address: 0x6000429c
-        /// GPIO input function configuration register
-        pub const FUNC82_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x29c);
-
-        /// address: 0x600042a0
-        /// GPIO input function configuration register
-        pub const FUNC83_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a0);
-
-        /// address: 0x600042a4
-        /// GPIO input function configuration register
-        pub const FUNC84_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a4);
-
-        /// address: 0x600042a8
-        /// GPIO input function configuration register
-        pub const FUNC85_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a8);
-
-        /// address: 0x600042ac
-        /// GPIO input function configuration register
-        pub const FUNC86_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2ac);
-
-        /// address: 0x600042b0
-        /// GPIO input function configuration register
-        pub const FUNC87_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b0);
-
-        /// address: 0x600042b4
-        /// GPIO input function configuration register
-        pub const FUNC88_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b4);
-
-        /// address: 0x600042b8
-        /// GPIO input function configuration register
-        pub const FUNC89_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b8);
-
-        /// address: 0x600042bc
-        /// GPIO input function configuration register
-        pub const FUNC90_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2bc);
-
-        /// address: 0x600042c0
-        /// GPIO input function configuration register
-        pub const FUNC91_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c0);
-
-        /// address: 0x600042c4
-        /// GPIO input function configuration register
-        pub const FUNC92_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c4);
-
-        /// address: 0x600042c8
-        /// GPIO input function configuration register
-        pub const FUNC93_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c8);
-
-        /// address: 0x600042cc
-        /// GPIO input function configuration register
-        pub const FUNC94_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2cc);
-
-        /// address: 0x600042d0
-        /// GPIO input function configuration register
-        pub const FUNC95_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d0);
-
-        /// address: 0x600042d4
-        /// GPIO input function configuration register
-        pub const FUNC96_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d4);
-
-        /// address: 0x600042d8
-        /// GPIO input function configuration register
-        pub const FUNC97_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d8);
-
-        /// address: 0x600042dc
-        /// GPIO input function configuration register
-        pub const FUNC98_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2dc);
-
-        /// address: 0x600042e0
-        /// GPIO input function configuration register
-        pub const FUNC99_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e0);
-
-        /// address: 0x600042e4
-        /// GPIO input function configuration register
-        pub const FUNC100_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e4);
-
-        /// address: 0x600042e8
-        /// GPIO input function configuration register
-        pub const FUNC101_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e8);
-
-        /// address: 0x600042ec
-        /// GPIO input function configuration register
-        pub const FUNC102_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2ec);
-
-        /// address: 0x600042f0
-        /// GPIO input function configuration register
-        pub const FUNC103_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f0);
-
-        /// address: 0x600042f4
-        /// GPIO input function configuration register
-        pub const FUNC104_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f4);
-
-        /// address: 0x600042f8
-        /// GPIO input function configuration register
-        pub const FUNC105_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f8);
-
-        /// address: 0x600042fc
-        /// GPIO input function configuration register
-        pub const FUNC106_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2fc);
-
-        /// address: 0x60004300
-        /// GPIO input function configuration register
-        pub const FUNC107_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x300);
-
-        /// address: 0x60004304
-        /// GPIO input function configuration register
-        pub const FUNC108_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x304);
-
-        /// address: 0x60004308
-        /// GPIO input function configuration register
-        pub const FUNC109_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x308);
-
-        /// address: 0x6000430c
-        /// GPIO input function configuration register
-        pub const FUNC110_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x30c);
-
-        /// address: 0x60004310
-        /// GPIO input function configuration register
-        pub const FUNC111_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x310);
-
-        /// address: 0x60004314
-        /// GPIO input function configuration register
-        pub const FUNC112_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x314);
-
-        /// address: 0x60004318
-        /// GPIO input function configuration register
-        pub const FUNC113_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x318);
-
-        /// address: 0x6000431c
-        /// GPIO input function configuration register
-        pub const FUNC114_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x31c);
-
-        /// address: 0x60004320
-        /// GPIO input function configuration register
-        pub const FUNC115_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x320);
-
-        /// address: 0x60004324
-        /// GPIO input function configuration register
-        pub const FUNC116_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x324);
-
-        /// address: 0x60004328
-        /// GPIO input function configuration register
-        pub const FUNC117_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x328);
-
-        /// address: 0x6000432c
-        /// GPIO input function configuration register
-        pub const FUNC118_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x32c);
-
-        /// address: 0x60004330
-        /// GPIO input function configuration register
-        pub const FUNC119_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x330);
-
-        /// address: 0x60004334
-        /// GPIO input function configuration register
-        pub const FUNC120_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x334);
-
-        /// address: 0x60004338
-        /// GPIO input function configuration register
-        pub const FUNC121_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x338);
-
-        /// address: 0x6000433c
-        /// GPIO input function configuration register
-        pub const FUNC122_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x33c);
-
-        /// address: 0x60004340
-        /// GPIO input function configuration register
-        pub const FUNC123_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x340);
-
-        /// address: 0x60004344
-        /// GPIO input function configuration register
-        pub const FUNC124_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x344);
-
-        /// address: 0x60004348
-        /// GPIO input function configuration register
-        pub const FUNC125_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x348);
-
-        /// address: 0x6000434c
-        /// GPIO input function configuration register
-        pub const FUNC126_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x34c);
-
-        /// address: 0x60004350
-        /// GPIO input function configuration register
-        pub const FUNC127_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x350);
-
-        /// address: 0x60004554
-        /// GPIO output function select register
-        pub const FUNC0_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x554);
-
-        /// address: 0x60004558
-        /// GPIO output function select register
-        pub const FUNC1_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x558);
-
-        /// address: 0x6000455c
-        /// GPIO output function select register
-        pub const FUNC2_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x55c);
-
-        /// address: 0x60004560
-        /// GPIO output function select register
-        pub const FUNC3_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x560);
-
-        /// address: 0x60004564
-        /// GPIO output function select register
-        pub const FUNC4_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x564);
-
-        /// address: 0x60004568
-        /// GPIO output function select register
-        pub const FUNC5_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x568);
-
-        /// address: 0x6000456c
-        /// GPIO output function select register
-        pub const FUNC6_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x56c);
-
-        /// address: 0x60004570
-        /// GPIO output function select register
-        pub const FUNC7_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x570);
-
-        /// address: 0x60004574
-        /// GPIO output function select register
-        pub const FUNC8_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x574);
-
-        /// address: 0x60004578
-        /// GPIO output function select register
-        pub const FUNC9_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x578);
-
-        /// address: 0x6000457c
-        /// GPIO output function select register
-        pub const FUNC10_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x57c);
-
-        /// address: 0x60004580
-        /// GPIO output function select register
-        pub const FUNC11_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x580);
-
-        /// address: 0x60004584
-        /// GPIO output function select register
-        pub const FUNC12_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x584);
-
-        /// address: 0x60004588
-        /// GPIO output function select register
-        pub const FUNC13_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x588);
-
-        /// address: 0x6000458c
-        /// GPIO output function select register
-        pub const FUNC14_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x58c);
-
-        /// address: 0x60004590
-        /// GPIO output function select register
-        pub const FUNC15_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x590);
-
-        /// address: 0x60004594
-        /// GPIO output function select register
-        pub const FUNC16_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x594);
-
-        /// address: 0x60004598
-        /// GPIO output function select register
-        pub const FUNC17_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x598);
-
-        /// address: 0x6000459c
-        /// GPIO output function select register
-        pub const FUNC18_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x59c);
-
-        /// address: 0x600045a0
-        /// GPIO output function select register
-        pub const FUNC19_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a0);
-
-        /// address: 0x600045a4
-        /// GPIO output function select register
-        pub const FUNC20_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a4);
-
-        /// address: 0x600045a8
-        /// GPIO output function select register
-        pub const FUNC21_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a8);
-
-        /// address: 0x600045ac
-        /// GPIO output function select register
-        pub const FUNC22_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5ac);
-
-        /// address: 0x600045b0
-        /// GPIO output function select register
-        pub const FUNC23_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b0);
-
-        /// address: 0x600045b4
-        /// GPIO output function select register
-        pub const FUNC24_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b4);
-
-        /// address: 0x600045b8
-        /// GPIO output function select register
-        pub const FUNC25_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b8);
-
-        /// address: 0x6000462c
-        /// GPIO clock gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this bit to enable GPIO clock gate
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x62c);
-
-        /// address: 0x600046fc
-        /// GPIO version register
-        pub const REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x6fc);
-    };
-
-    /// Sigma-Delta Modulation
-    pub const GPIOSD = struct {
-        pub const base_address = 0x60004f00;
-
-        /// address: 0x60004f00
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60004f04
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60004f08
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x60004f0c
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60004f20
-        /// Clock Gating Configure Register
-        pub const SIGMADELTA_CG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// Clock enable bit of configuration registers for sigma delta modulation.
-            CLK_EN: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60004f24
-        /// MISC Register
-        pub const SIGMADELTA_MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            /// Clock enable bit of sigma delta modulation.
-            FUNCTION_CLK_EN: u1,
-            /// Reserved.
-            SPI_SWAP: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60004f28
-        /// Version Control Register
-        pub const SIGMADELTA_VERSION = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Version control register.
-            GPIO_SD_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x28);
-    };
-
-    /// HMAC (Hash-based Message Authentication Code) Accelerator
-    pub const HMAC = struct {
-        pub const base_address = 0x6003e000;
-
-        /// address: 0x6003e040
-        /// Process control register 0.
-        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
-
-        /// address: 0x6003e044
-        /// Configure purpose.
-        pub const SET_PARA_PURPOSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set hmac parameter purpose.
-            PURPOSE_SET: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6003e048
-        /// Configure key.
-        pub const SET_PARA_KEY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set hmac parameter key.
-            KEY_SET: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6003e04c
-        /// Finish initial configuration.
-        pub const SET_PARA_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Finish hmac configuration.
-            SET_PARA_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x6003e050
-        /// Process control register 1.
-        pub const SET_MESSAGE_ONE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Call SHA to calculate one message block.
-            SET_TEXT_ONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6003e054
-        /// Process control register 2.
-        pub const SET_MESSAGE_ING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Continue typical hmac.
-            SET_TEXT_ING: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6003e058
-        /// Process control register 3.
-        pub const SET_MESSAGE_END = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Start hardware padding.
-            SET_TEXT_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6003e05c
-        /// Process control register 4.
-        pub const SET_RESULT_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
-            /// After read result from upstream, then let hmac back to idle.
-            SET_RESULT_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6003e060
-        /// Invalidate register 0.
-        pub const SET_INVALIDATE_JTAG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x60);
-
-        /// address: 0x6003e064
-        /// Invalidate register 1.
-        pub const SET_INVALIDATE_DS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x64);
-
-        /// address: 0x6003e068
-        /// Error register.
-        pub const QUERY_ERROR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Hmac configuration state. 0: key are agree with purpose. 1: error
-            QUREY_CHECK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6003e06c
-        /// Busy register.
-        pub const QUERY_BUSY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Hmac state. 1'b0: idle. 1'b1: busy
-            BUSY_STATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6003e080
-        /// Message block memory.
-        pub const WR_MESSAGE_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
-
-        /// address: 0x6003e0c0
-        /// Result from upstream.
-        pub const RD_RESULT_MEM = @intToPtr(*volatile [32]u8, base_address + 0xc0);
-
-        /// address: 0x6003e0f0
-        /// Process control register 5.
-        pub const SET_MESSAGE_PAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Start software padding.
-            SET_TEXT_PAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x6003e0f4
-        /// Process control register 6.
-        pub const ONE_BLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Don't have to do padding.
-            SET_ONE_BLOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x6003e0f8
-        /// Jtag register 0.
-        pub const SOFT_JTAG_CTRL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xf8);
-
-        /// address: 0x6003e0fc
-        /// Jtag register 1.
-        pub const WR_JTAG = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-
-    /// I2C (Inter-Integrated Circuit) Controller
-    pub const I2C0 = struct {
-        pub const base_address = 0x60013000;
-
-        /// address: 0x60013000
-        /// I2C_SCL_LOW_PERIOD_REG
-        pub const SCL_LOW_PERIOD = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x0);
-
-        /// address: 0x60013004
-        /// I2C_CTR_REG
-        pub const CTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_force_out
-            SDA_FORCE_OUT: u1,
-            /// reg_scl_force_out
-            SCL_FORCE_OUT: u1,
-            /// reg_sample_scl_level
-            SAMPLE_SCL_LEVEL: u1,
-            /// reg_rx_full_ack_level
-            RX_FULL_ACK_LEVEL: u1,
-            /// reg_ms_mode
-            MS_MODE: u1,
-            /// reg_trans_start
-            TRANS_START: u1,
-            /// reg_tx_lsb_first
-            TX_LSB_FIRST: u1,
-            /// reg_rx_lsb_first
-            RX_LSB_FIRST: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            /// reg_arbitration_en
-            ARBITRATION_EN: u1,
-            /// reg_fsm_rst
-            FSM_RST: u1,
-            /// reg_conf_upgate
-            CONF_UPGATE: u1,
-            /// reg_slv_tx_auto_start_en
-            SLV_TX_AUTO_START_EN: u1,
-            /// reg_addr_10bit_rw_check_en
-            ADDR_10BIT_RW_CHECK_EN: u1,
-            /// reg_addr_broadcasting_en
-            ADDR_BROADCASTING_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60013008
-        /// I2C_SR_REG
-        pub const SR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_resp_rec
-            RESP_REC: u1,
-            /// reg_slave_rw
-            SLAVE_RW: u1,
-            reserved0: u1,
-            /// reg_arb_lost
-            ARB_LOST: u1,
-            /// reg_bus_busy
-            BUS_BUSY: u1,
-            /// reg_slave_addressed
-            SLAVE_ADDRESSED: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_rxfifo_cnt
-            RXFIFO_CNT: u6,
-            /// reg_stretch_cause
-            STRETCH_CAUSE: u2,
-            reserved3: u1,
-            reserved4: u1,
-            /// reg_txfifo_cnt
-            TXFIFO_CNT: u6,
-            /// reg_scl_main_state_last
-            SCL_MAIN_STATE_LAST: u3,
-            reserved5: u1,
-            /// reg_scl_state_last
-            SCL_STATE_LAST: u3,
-            padding0: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001300c
-        /// I2C_TO_REG
-        pub const TO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_time_out_value
-            TIME_OUT_VALUE: u5,
-            /// reg_time_out_en
-            TIME_OUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60013010
-        /// I2C_SLAVE_ADDR_REG
-        pub const SLAVE_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_slave_addr
-            SLAVE_ADDR: u15,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// reg_addr_10bit_en
-            ADDR_10BIT_EN: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60013014
-        /// I2C_FIFO_ST_REG
-        pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_raddr
-            RXFIFO_RADDR: u5,
-            /// reg_rxfifo_waddr
-            RXFIFO_WADDR: u5,
-            /// reg_txfifo_raddr
-            TXFIFO_RADDR: u5,
-            /// reg_txfifo_waddr
-            TXFIFO_WADDR: u5,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_slave_rw_point
-            SLAVE_RW_POINT: u8,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60013018
-        /// I2C_FIFO_CONF_REG
-        pub const FIFO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_thrhd
-            RXFIFO_WM_THRHD: u5,
-            /// reg_txfifo_wm_thrhd
-            TXFIFO_WM_THRHD: u5,
-            /// reg_nonfifo_en
-            NONFIFO_EN: u1,
-            /// reg_fifo_addr_cfg_en
-            FIFO_ADDR_CFG_EN: u1,
-            /// reg_rx_fifo_rst
-            RX_FIFO_RST: u1,
-            /// reg_tx_fifo_rst
-            TX_FIFO_RST: u1,
-            /// reg_fifo_prt_en
-            FIFO_PRT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001301c
-        /// I2C_FIFO_DATA_REG
-        pub const DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_fifo_rdata
-            FIFO_RDATA: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60013020
-        /// I2C_INT_RAW_REG
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_raw
-            RXFIFO_WM_INT_RAW: u1,
-            /// reg_txfifo_wm_int_raw
-            TXFIFO_WM_INT_RAW: u1,
-            /// reg_rxfifo_ovf_int_raw
-            RXFIFO_OVF_INT_RAW: u1,
-            /// reg_end_detect_int_raw
-            END_DETECT_INT_RAW: u1,
-            /// reg_byte_trans_done_int_raw
-            BYTE_TRANS_DONE_INT_RAW: u1,
-            /// reg_arbitration_lost_int_raw
-            ARBITRATION_LOST_INT_RAW: u1,
-            /// reg_mst_txfifo_udf_int_raw
-            MST_TXFIFO_UDF_INT_RAW: u1,
-            /// reg_trans_complete_int_raw
-            TRANS_COMPLETE_INT_RAW: u1,
-            /// reg_time_out_int_raw
-            TIME_OUT_INT_RAW: u1,
-            /// reg_trans_start_int_raw
-            TRANS_START_INT_RAW: u1,
-            /// reg_nack_int_raw
-            NACK_INT_RAW: u1,
-            /// reg_txfifo_ovf_int_raw
-            TXFIFO_OVF_INT_RAW: u1,
-            /// reg_rxfifo_udf_int_raw
-            RXFIFO_UDF_INT_RAW: u1,
-            /// reg_scl_st_to_int_raw
-            SCL_ST_TO_INT_RAW: u1,
-            /// reg_scl_main_st_to_int_raw
-            SCL_MAIN_ST_TO_INT_RAW: u1,
-            /// reg_det_start_int_raw
-            DET_START_INT_RAW: u1,
-            /// reg_slave_stretch_int_raw
-            SLAVE_STRETCH_INT_RAW: u1,
-            /// reg_general_call_int_raw
-            GENERAL_CALL_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60013024
-        /// I2C_INT_CLR_REG
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_clr
-            RXFIFO_WM_INT_CLR: u1,
-            /// reg_txfifo_wm_int_clr
-            TXFIFO_WM_INT_CLR: u1,
-            /// reg_rxfifo_ovf_int_clr
-            RXFIFO_OVF_INT_CLR: u1,
-            /// reg_end_detect_int_clr
-            END_DETECT_INT_CLR: u1,
-            /// reg_byte_trans_done_int_clr
-            BYTE_TRANS_DONE_INT_CLR: u1,
-            /// reg_arbitration_lost_int_clr
-            ARBITRATION_LOST_INT_CLR: u1,
-            /// reg_mst_txfifo_udf_int_clr
-            MST_TXFIFO_UDF_INT_CLR: u1,
-            /// reg_trans_complete_int_clr
-            TRANS_COMPLETE_INT_CLR: u1,
-            /// reg_time_out_int_clr
-            TIME_OUT_INT_CLR: u1,
-            /// reg_trans_start_int_clr
-            TRANS_START_INT_CLR: u1,
-            /// reg_nack_int_clr
-            NACK_INT_CLR: u1,
-            /// reg_txfifo_ovf_int_clr
-            TXFIFO_OVF_INT_CLR: u1,
-            /// reg_rxfifo_udf_int_clr
-            RXFIFO_UDF_INT_CLR: u1,
-            /// reg_scl_st_to_int_clr
-            SCL_ST_TO_INT_CLR: u1,
-            /// reg_scl_main_st_to_int_clr
-            SCL_MAIN_ST_TO_INT_CLR: u1,
-            /// reg_det_start_int_clr
-            DET_START_INT_CLR: u1,
-            /// reg_slave_stretch_int_clr
-            SLAVE_STRETCH_INT_CLR: u1,
-            /// reg_general_call_int_clr
-            GENERAL_CALL_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60013028
-        /// I2C_INT_ENA_REG
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_ena
-            RXFIFO_WM_INT_ENA: u1,
-            /// reg_txfifo_wm_int_ena
-            TXFIFO_WM_INT_ENA: u1,
-            /// reg_rxfifo_ovf_int_ena
-            RXFIFO_OVF_INT_ENA: u1,
-            /// reg_end_detect_int_ena
-            END_DETECT_INT_ENA: u1,
-            /// reg_byte_trans_done_int_ena
-            BYTE_TRANS_DONE_INT_ENA: u1,
-            /// reg_arbitration_lost_int_ena
-            ARBITRATION_LOST_INT_ENA: u1,
-            /// reg_mst_txfifo_udf_int_ena
-            MST_TXFIFO_UDF_INT_ENA: u1,
-            /// reg_trans_complete_int_ena
-            TRANS_COMPLETE_INT_ENA: u1,
-            /// reg_time_out_int_ena
-            TIME_OUT_INT_ENA: u1,
-            /// reg_trans_start_int_ena
-            TRANS_START_INT_ENA: u1,
-            /// reg_nack_int_ena
-            NACK_INT_ENA: u1,
-            /// reg_txfifo_ovf_int_ena
-            TXFIFO_OVF_INT_ENA: u1,
-            /// reg_rxfifo_udf_int_ena
-            RXFIFO_UDF_INT_ENA: u1,
-            /// reg_scl_st_to_int_ena
-            SCL_ST_TO_INT_ENA: u1,
-            /// reg_scl_main_st_to_int_ena
-            SCL_MAIN_ST_TO_INT_ENA: u1,
-            /// reg_det_start_int_ena
-            DET_START_INT_ENA: u1,
-            /// reg_slave_stretch_int_ena
-            SLAVE_STRETCH_INT_ENA: u1,
-            /// reg_general_call_int_ena
-            GENERAL_CALL_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001302c
-        /// I2C_INT_STATUS_REG
-        pub const INT_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_st
-            RXFIFO_WM_INT_ST: u1,
-            /// reg_txfifo_wm_int_st
-            TXFIFO_WM_INT_ST: u1,
-            /// reg_rxfifo_ovf_int_st
-            RXFIFO_OVF_INT_ST: u1,
-            /// reg_end_detect_int_st
-            END_DETECT_INT_ST: u1,
-            /// reg_byte_trans_done_int_st
-            BYTE_TRANS_DONE_INT_ST: u1,
-            /// reg_arbitration_lost_int_st
-            ARBITRATION_LOST_INT_ST: u1,
-            /// reg_mst_txfifo_udf_int_st
-            MST_TXFIFO_UDF_INT_ST: u1,
-            /// reg_trans_complete_int_st
-            TRANS_COMPLETE_INT_ST: u1,
-            /// reg_time_out_int_st
-            TIME_OUT_INT_ST: u1,
-            /// reg_trans_start_int_st
-            TRANS_START_INT_ST: u1,
-            /// reg_nack_int_st
-            NACK_INT_ST: u1,
-            /// reg_txfifo_ovf_int_st
-            TXFIFO_OVF_INT_ST: u1,
-            /// reg_rxfifo_udf_int_st
-            RXFIFO_UDF_INT_ST: u1,
-            /// reg_scl_st_to_int_st
-            SCL_ST_TO_INT_ST: u1,
-            /// reg_scl_main_st_to_int_st
-            SCL_MAIN_ST_TO_INT_ST: u1,
-            /// reg_det_start_int_st
-            DET_START_INT_ST: u1,
-            /// reg_slave_stretch_int_st
-            SLAVE_STRETCH_INT_ST: u1,
-            /// reg_general_call_int_st
-            GENERAL_CALL_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60013030
-        /// I2C_SDA_HOLD_REG
-        pub const SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60013034
-        /// I2C_SDA_SAMPLE_REG
-        pub const SDA_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_sample_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60013038
-        /// I2C_SCL_HIGH_PERIOD_REG
-        pub const SCL_HIGH_PERIOD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_high_period
-            SCL_HIGH_PERIOD: u9,
-            /// reg_scl_wait_high_period
-            SCL_WAIT_HIGH_PERIOD: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x60013040
-        /// I2C_SCL_START_HOLD_REG
-        pub const SCL_START_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_start_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60013044
-        /// I2C_SCL_RSTART_SETUP_REG
-        pub const SCL_RSTART_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_rstart_setup_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60013048
-        /// I2C_SCL_STOP_HOLD_REG
-        pub const SCL_STOP_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_stop_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001304c
-        /// I2C_SCL_STOP_SETUP_REG
-        pub const SCL_STOP_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_stop_setup_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60013050
-        /// I2C_FILTER_CFG_REG
-        pub const FILTER_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_filter_thres
-            SCL_FILTER_THRES: u4,
-            /// reg_sda_filter_thres
-            SDA_FILTER_THRES: u4,
-            /// reg_scl_filter_en
-            SCL_FILTER_EN: u1,
-            /// reg_sda_filter_en
-            SDA_FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60013054
-        /// I2C_CLK_CONF_REG
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sclk_div_num
-            SCLK_DIV_NUM: u8,
-            /// reg_sclk_div_a
-            SCLK_DIV_A: u6,
-            /// reg_sclk_div_b
-            SCLK_DIV_B: u6,
-            /// reg_sclk_sel
-            SCLK_SEL: u1,
-            /// reg_sclk_active
-            SCLK_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60013058
-        /// I2C_COMD%s_REG
-        pub const COMD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001305c
-        /// I2C_COMD%s_REG
-        pub const COMD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60013060
-        /// I2C_COMD%s_REG
-        pub const COMD2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60013064
-        /// I2C_COMD%s_REG
-        pub const COMD3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60013068
-        /// I2C_COMD%s_REG
-        pub const COMD4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001306c
-        /// I2C_COMD%s_REG
-        pub const COMD5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60013070
-        /// I2C_COMD%s_REG
-        pub const COMD6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60013074
-        /// I2C_COMD%s_REG
-        pub const COMD7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60013078
-        /// I2C_SCL_ST_TIME_OUT_REG
-        pub const SCL_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_st_to_regno more than 23
-            SCL_ST_TO_I2C: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001307c
-        /// I2C_SCL_MAIN_ST_TIME_OUT_REG
-        pub const SCL_MAIN_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_main_st_to_regno more than 23
-            SCL_MAIN_ST_TO_I2C: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60013080
-        /// I2C_SCL_SP_CONF_REG
-        pub const SCL_SP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_rst_slv_en
-            SCL_RST_SLV_EN: u1,
-            /// reg_scl_rst_slv_num
-            SCL_RST_SLV_NUM: u5,
-            /// reg_scl_pd_en
-            SCL_PD_EN: u1,
-            /// reg_sda_pd_en
-            SDA_PD_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60013084
-        /// I2C_SCL_STRETCH_CONF_REG
-        pub const SCL_STRETCH_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_stretch_protect_num
-            STRETCH_PROTECT_NUM: u10,
-            /// reg_slave_scl_stretch_en
-            SLAVE_SCL_STRETCH_EN: u1,
-            /// reg_slave_scl_stretch_clr
-            SLAVE_SCL_STRETCH_CLR: u1,
-            /// reg_slave_byte_ack_ctl_en
-            SLAVE_BYTE_ACK_CTL_EN: u1,
-            /// reg_slave_byte_ack_lvl
-            SLAVE_BYTE_ACK_LVL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600130f8
-        /// I2C_DATE_REG
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0xf8);
-
-        /// address: 0x60013100
-        /// I2C_TXFIFO_START_ADDR_REG
-        pub const TXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x100);
-
-        /// address: 0x60013180
-        /// I2C_RXFIFO_START_ADDR_REG
-        pub const RXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x180);
-    };
-
-    /// I2S (Inter-IC Sound) Controller
-    pub const I2S = struct {
-        pub const base_address = 0x6002d000;
-
-        /// address: 0x6002d00c
-        /// I2S interrupt raw register, valid in level.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6002d010
-        /// I2S interrupt status register.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The masked interrupt status bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6002d014
-        /// I2S interrupt enable register.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6002d018
-        /// I2S interrupt clear register.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the i2s_rx_done_int interrupt
-            RX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the i2s_tx_done_int interrupt
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_CLR: u1,
-            /// Set this bit to clear the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6002d020
-        /// I2S RX configure register
-        pub const RX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to reset receiver
-            RX_RESET: u1,
-            /// Set this bit to reset Rx AFIFO
-            RX_FIFO_RESET: u1,
-            /// Set this bit to start receiving data
-            RX_START: u1,
-            /// Set this bit to enable slave receiver mode
-            RX_SLAVE_MOD: u1,
-            reserved0: u1,
-            /// Set this bit to enable receiver in mono mode
-            RX_MONO: u1,
-            reserved1: u1,
-            /// I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr
-            /// value.
-            RX_BIG_ENDIAN: u1,
-            /// Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain.
-            /// This bit will be cleared by hardware after update register done.
-            RX_UPDATE: u1,
-            /// 1: The first channel data value is valid in I2S RX mono mode. 0: The second
-            /// channel data value is valid in I2S RX mono mode.
-            RX_MONO_FST_VLD: u1,
-            /// I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
-            /// &
-            RX_PCM_CONF: u2,
-            /// Set this bit to bypass Compress/Decompress module for received data.
-            RX_PCM_BYPASS: u1,
-            /// 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
-            /// 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-            RX_STOP_MODE: u2,
-            /// 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-            RX_LEFT_ALIGN: u1,
-            /// 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-            RX_24_FILL_EN: u1,
-            /// 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-            /// 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-            RX_WS_IDLE_POL: u1,
-            /// I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
-            /// MSB is received first.
-            RX_BIT_ORDER: u1,
-            /// 1: Enable I2S TDM Rx mode . 0: Disable.
-            RX_TDM_EN: u1,
-            /// 1: Enable I2S PDM Rx mode . 0: Disable.
-            RX_PDM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6002d024
-        /// I2S TX configure register
-        pub const TX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to reset transmitter
-            TX_RESET: u1,
-            /// Set this bit to reset Tx AFIFO
-            TX_FIFO_RESET: u1,
-            /// Set this bit to start transmitting data
-            TX_START: u1,
-            /// Set this bit to enable slave transmitter mode
-            TX_SLAVE_MOD: u1,
-            reserved0: u1,
-            /// Set this bit to enable transmitter in mono mode
-            TX_MONO: u1,
-            /// 1: The value of Left channel data is equal to the value of right channel data in
-            /// I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-            /// reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-            TX_CHAN_EQUAL: u1,
-            /// I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
-            /// value.
-            TX_BIG_ENDIAN: u1,
-            /// Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain.
-            /// This bit will be cleared by hardware after update register done.
-            TX_UPDATE: u1,
-            /// 1: The first channel data value is valid in I2S TX mono mode. 0: The second
-            /// channel data value is valid in I2S TX mono mode.
-            TX_MONO_FST_VLD: u1,
-            /// I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
-            /// &
-            TX_PCM_CONF: u2,
-            /// Set this bit to bypass Compress/Decompress module for transmitted data.
-            TX_PCM_BYPASS: u1,
-            /// Set this bit to stop disable output BCK signal and WS signal when tx FIFO is
-            /// emtpy
-            TX_STOP_EN: u1,
-            reserved1: u1,
-            /// 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-            TX_LEFT_ALIGN: u1,
-            /// 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-            TX_24_FILL_EN: u1,
-            /// 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
-            /// 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
-            TX_WS_IDLE_POL: u1,
-            /// I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
-            /// is sent first.
-            TX_BIT_ORDER: u1,
-            /// 1: Enable I2S TDM Tx mode . 0: Disable.
-            TX_TDM_EN: u1,
-            /// 1: Enable I2S PDM Tx mode . 0: Disable.
-            TX_PDM_EN: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// I2S transmitter channel mode configuration bits.
-            TX_CHAN_MOD: u3,
-            /// Enable signal loop back mode with transmitter module and receiver module sharing
-            /// the same WS and BCK signals.
-            SIG_LOOPBACK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6002d028
-        /// I2S RX configure register 1
-        pub const RX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
-            RX_TDM_WS_WIDTH: u7,
-            /// Bit clock configuration bits in receiver mode.
-            RX_BCK_DIV_NUM: u6,
-            /// Set the bits to configure the valid data bit length of I2S receiver channel. 7:
-            /// all the valid channel data is in 8-bit-mode. 15: all the valid channel data is
-            /// in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
-            /// valid channel data is in 32-bit-mode.
-            RX_BITS_MOD: u5,
-            /// I2S Rx half sample bits -1.
-            RX_HALF_SAMPLE_BITS: u6,
-            /// The Rx bit number for each channel minus 1in TDM mode.
-            RX_TDM_CHAN_BITS: u5,
-            /// Set this bit to enable receiver in Phillips standard mode
-            RX_MSB_SHIFT: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6002d02c
-        /// I2S TX configure register 1
-        pub const TX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
-            TX_TDM_WS_WIDTH: u7,
-            /// Bit clock configuration bits in transmitter mode.
-            TX_BCK_DIV_NUM: u6,
-            /// Set the bits to configure the valid data bit length of I2S transmitter channel.
-            /// 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data
-            /// is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
-            /// valid channel data is in 32-bit-mode.
-            TX_BITS_MOD: u5,
-            /// I2S Tx half sample bits -1.
-            TX_HALF_SAMPLE_BITS: u6,
-            /// The Tx bit number for each channel minus 1in TDM mode.
-            TX_TDM_CHAN_BITS: u5,
-            /// Set this bit to enable transmitter in Phillips standard mode
-            TX_MSB_SHIFT: u1,
-            /// 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
-            /// to generate pos/neg edge in master mode.
-            TX_BCK_NO_DLY: u1,
-            padding0: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x6002d030
-        /// I2S RX clock configure register
-        pub const RX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S clock divider value
-            RX_CLKM_DIV_NUM: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// I2S Rx module clock enable signal.
-            RX_CLK_ACTIVE: u1,
-            /// Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3:
-            /// I2S_MCLK_in.
-            RX_CLK_SEL: u2,
-            /// 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
-            /// I2S_MCLK_OUT.
-            MCLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6002d034
-        /// I2S TX clock configure register
-        pub const TX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
-            /// be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
-            /// a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-            /// (n+1)-div] + y * (n+1)-div.
-            TX_CLKM_DIV_NUM: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// I2S Tx module clock enable signal.
-            TX_CLK_ACTIVE: u1,
-            /// Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
-            /// I2S_MCLK_in.
-            TX_CLK_SEL: u2,
-            /// Set this bit to enable clk gate
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x6002d038
-        /// I2S RX module clock divider configure register
-        pub const RX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
-            /// I2S_RX_CLKM_DIV_Z is (a-b).
-            RX_CLKM_DIV_Z: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
-            /// of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-            RX_CLKM_DIV_Y: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
-            /// value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-            RX_CLKM_DIV_X: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-            /// I2S_RX_CLKM_DIV_YN1 is 1.
-            RX_CLKM_DIV_YN1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002d03c
-        /// I2S TX module clock divider configure register
-        pub const TX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
-            /// I2S_TX_CLKM_DIV_Z is (a-b).
-            TX_CLKM_DIV_Z: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
-            /// of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-            TX_CLKM_DIV_Y: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
-            /// value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-            TX_CLKM_DIV_X: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-            /// I2S_TX_CLKM_DIV_YN1 is 1.
-            TX_CLKM_DIV_YN1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x6002d040
-        /// I2S TX PCM2PDM configuration register
-        pub const TX_PCM2PDM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2S TX PDM bypass hp filter or not. The option has been removed.
-            TX_PDM_HP_BYPASS: u1,
-            /// I2S TX PDM OSR2 value
-            TX_PDM_SINC_OSR2: u4,
-            /// I2S TX PDM prescale for sigmadelta
-            TX_PDM_PRESCALE: u8,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_HP_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_LP_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_SINC_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_SIGMADELTA_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta dither2 value
-            TX_PDM_SIGMADELTA_DITHER2: u1,
-            /// I2S TX PDM sigmadelta dither value
-            TX_PDM_SIGMADELTA_DITHER: u1,
-            /// I2S TX PDM dac mode enable
-            TX_PDM_DAC_2OUT_EN: u1,
-            /// I2S TX PDM dac 2channel enable
-            TX_PDM_DAC_MODE_EN: u1,
-            /// I2S TX PDM Converter enable
-            PCM2PDM_CONV_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6002d044
-        /// I2S TX PCM2PDM configuration register
-        pub const TX_PCM2PDM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2S TX PDM Fp
-            TX_PDM_FP: u10,
-            /// I2S TX PDM Fs
-            TX_PDM_FS: u10,
-            /// The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-            /// I2S_TX_IIR_HP_MULT12_5[2:0])
-            TX_IIR_HP_MULT12_5: u3,
-            /// The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-            /// I2S_TX_IIR_HP_MULT12_0[2:0])
-            TX_IIR_HP_MULT12_0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6002d050
-        /// I2S TX TDM mode control register
-        pub const RX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN0_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN1_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN2_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN3_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN4_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN5_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN6_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN7_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0
-            /// in this channel.
-            RX_TDM_CHAN8_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0
-            /// in this channel.
-            RX_TDM_CHAN9_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN10_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN11_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN12_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN13_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN14_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN15_EN: u1,
-            /// The total channel number of I2S TX TDM mode.
-            RX_TDM_TOT_CHAN_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6002d054
-        /// I2S TX TDM mode control register
-        pub const TX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN0_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN1_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN2_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN3_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN4_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN5_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN6_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN7_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN8_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN9_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN10_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN11_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN12_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN13_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN14_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN15_EN: u1,
-            /// The total channel number of I2S TX TDM mode.
-            TX_TDM_TOT_CHAN_NUM: u4,
-            /// When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels,
-            /// and only the data of the enabled channels is sent, then this bit should be set.
-            /// Clear it when all the data stored in DMA TX buffer is for enabled channels.
-            TX_TDM_SKIP_MSK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6002d058
-        /// I2S RX timing control register
-        pub const RX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_SD_IN_DM: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_WS_OUT_DM: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_BCK_OUT_DM: u2,
-            reserved16: u1,
-            reserved17: u1,
-            /// The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_WS_IN_DM: u2,
-            reserved18: u1,
-            reserved19: u1,
-            /// The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_BCK_IN_DM: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002d05c
-        /// I2S TX timing control register
-        pub const TX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_SD_OUT_DM: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_SD1_OUT_DM: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_WS_OUT_DM: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_BCK_OUT_DM: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_WS_IN_DM: u2,
-            reserved16: u1,
-            reserved17: u1,
-            /// The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_BCK_IN_DM: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6002d060
-        /// I2S HUNG configure register.
-        pub const LC_HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-            /// when fifo hung counter is equal to this value
-            LC_FIFO_TIMEOUT: u8,
-            /// The bits are used to scale tick counter threshold. The tick counter is reset
-            /// when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-            LC_FIFO_TIMEOUT_SHIFT: u3,
-            /// The enable bit for FIFO timeout
-            LC_FIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x6002d064
-        /// I2S RX data number control register.
-        pub const RXEOF_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) *
-            /// (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the
-            /// configured DMA RX channel.
-            RX_EOF_NUM: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x6002d068
-        /// I2S signal data register
-        pub const CONF_SIGLE_DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The configured constant channel data to be sent out.
-            SINGLE_DATA: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6002d06c
-        /// I2S TX status register
-        pub const STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: i2s_tx is idle state. 0: i2s_tx is working.
-            TX_IDLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6002d080
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x80);
-    };
-
-    /// Interrupt Core
-    pub const INTERRUPT_CORE0 = struct {
-        pub const base_address = 0x600c2000;
-
-        /// address: 0x600c2000
-        /// mac intr map register
-        pub const MAC_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x0);
-
-        /// address: 0x600c2004
-        /// mac nmi_intr map register
-        pub const MAC_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4);
-
-        /// address: 0x600c2008
-        /// pwr intr map register
-        pub const PWR_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8);
-
-        /// address: 0x600c200c
-        /// bb intr map register
-        pub const BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc);
-
-        /// address: 0x600c2010
-        /// bt intr map register
-        pub const BT_MAC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x10);
-
-        /// address: 0x600c2014
-        /// bb_bt intr map register
-        pub const BT_BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14);
-
-        /// address: 0x600c2018
-        /// bb_bt_nmi intr map register
-        pub const BT_BB_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x18);
-
-        /// address: 0x600c201c
-        /// rwbt intr map register
-        pub const RWBT_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c);
-
-        /// address: 0x600c2020
-        /// rwble intr map register
-        pub const RWBLE_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x20);
-
-        /// address: 0x600c2024
-        /// rwbt_nmi intr map register
-        pub const RWBT_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24);
-
-        /// address: 0x600c2028
-        /// rwble_nmi intr map register
-        pub const RWBLE_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x28);
-
-        /// address: 0x600c202c
-        /// i2c intr map register
-        pub const I2C_MST_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
-
-        /// address: 0x600c2030
-        /// slc0 intr map register
-        pub const SLC0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x30);
-
-        /// address: 0x600c2034
-        /// slc1 intr map register
-        pub const SLC1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x34);
-
-        /// address: 0x600c2038
-        /// apb_ctrl intr map register
-        pub const APB_CTRL_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x38);
-
-        /// address: 0x600c203c
-        /// uchi0 intr map register
-        pub const UHCI0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x3c);
-
-        /// address: 0x600c2040
-        /// gpio intr map register
-        pub const GPIO_INTERRUPT_PRO_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x40);
-
-        /// address: 0x600c2044
-        /// gpio_pro intr map register
-        pub const GPIO_INTERRUPT_PRO_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x44);
-
-        /// address: 0x600c2048
-        /// gpio_pro_nmi intr map register
-        pub const SPI_INTR_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x48);
-
-        /// address: 0x600c204c
-        /// spi1 intr map register
-        pub const SPI_INTR_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4c);
-
-        /// address: 0x600c2050
-        /// spi2 intr map register
-        pub const I2S1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x50);
-
-        /// address: 0x600c2054
-        /// i2s1 intr map register
-        pub const UART_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x54);
-
-        /// address: 0x600c2058
-        /// uart1 intr map register
-        pub const UART1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x58);
-
-        /// address: 0x600c205c
-        /// ledc intr map register
-        pub const LEDC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x5c);
-
-        /// address: 0x600c2060
-        /// efuse intr map register
-        pub const EFUSE_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x60);
-
-        /// address: 0x600c2064
-        /// can intr map register
-        pub const CAN_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x64);
-
-        /// address: 0x600c2068
-        /// usb intr map register
-        pub const USB_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x68);
-
-        /// address: 0x600c206c
-        /// rtc intr map register
-        pub const RTC_CORE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x6c);
-
-        /// address: 0x600c2070
-        /// rmt intr map register
-        pub const RMT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x70);
-
-        /// address: 0x600c2074
-        /// i2c intr map register
-        pub const I2C_EXT0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x74);
-
-        /// address: 0x600c2078
-        /// timer1 intr map register
-        pub const TIMER_INT1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x78);
-
-        /// address: 0x600c207c
-        /// timer2 intr map register
-        pub const TIMER_INT2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x7c);
-
-        /// address: 0x600c2080
-        /// tg to intr map register
-        pub const TG_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x80);
-
-        /// address: 0x600c2084
-        /// tg wdt intr map register
-        pub const TG_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x84);
-
-        /// address: 0x600c2088
-        /// tg1 to intr map register
-        pub const TG1_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x88);
-
-        /// address: 0x600c208c
-        /// tg1 wdt intr map register
-        pub const TG1_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8c);
-
-        /// address: 0x600c2090
-        /// cache ia intr map register
-        pub const CACHE_IA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x90);
-
-        /// address: 0x600c2094
-        /// systimer intr map register
-        pub const SYSTIMER_TARGET0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x94);
-
-        /// address: 0x600c2098
-        /// systimer target1 intr map register
-        pub const SYSTIMER_TARGET1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x98);
-
-        /// address: 0x600c209c
-        /// systimer target2 intr map register
-        pub const SYSTIMER_TARGET2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x9c);
-
-        /// address: 0x600c20a0
-        /// spi mem reject intr map register
-        pub const SPI_MEM_REJECT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa0);
-
-        /// address: 0x600c20a4
-        /// icache perload intr map register
-        pub const ICACHE_PRELOAD_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa4);
-
-        /// address: 0x600c20a8
-        /// icache sync intr map register
-        pub const ICACHE_SYNC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa8);
-
-        /// address: 0x600c20ac
-        /// adc intr map register
-        pub const APB_ADC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xac);
-
-        /// address: 0x600c20b0
-        /// dma ch0 intr map register
-        pub const DMA_CH0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb0);
-
-        /// address: 0x600c20b4
-        /// dma ch1 intr map register
-        pub const DMA_CH1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb4);
-
-        /// address: 0x600c20b8
-        /// dma ch2 intr map register
-        pub const DMA_CH2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb8);
-
-        /// address: 0x600c20bc
-        /// rsa intr map register
-        pub const RSA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xbc);
-
-        /// address: 0x600c20c0
-        /// aes intr map register
-        pub const AES_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc0);
-
-        /// address: 0x600c20c4
-        /// sha intr map register
-        pub const SHA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc4);
-
-        /// address: 0x600c20c8
-        /// cpu from cpu 0 intr map register
-        pub const CPU_INTR_FROM_CPU_0_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc8);
-
-        /// address: 0x600c20cc
-        /// cpu from cpu 0 intr map register
-        pub const CPU_INTR_FROM_CPU_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xcc);
-
-        /// address: 0x600c20d0
-        /// cpu from cpu 1 intr map register
-        pub const CPU_INTR_FROM_CPU_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd0);
-
-        /// address: 0x600c20d4
-        /// cpu from cpu 3 intr map register
-        pub const CPU_INTR_FROM_CPU_3_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
-
-        /// address: 0x600c20d8
-        /// assist debug intr map register
-        pub const ASSIST_DEBUG_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd8);
-
-        /// address: 0x600c20dc
-        /// dma pms violatile intr map register
-        pub const DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xdc);
-
-        /// address: 0x600c20e0
-        /// iram0 pms violatile intr map register
-        pub const CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe0);
-
-        /// address: 0x600c20e4
-        /// mac intr map register
-        pub const CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe4);
-
-        /// address: 0x600c20e8
-        /// mac intr map register
-        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe8);
-
-        /// address: 0x600c20ec
-        /// mac intr map register
-        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
-
-        /// address: 0x600c20f0
-        /// mac intr map register
-        pub const BACKUP_PMS_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf0);
-
-        /// address: 0x600c20f4
-        /// mac intr map register
-        pub const CACHE_CORE0_ACS_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf4);
-
-        /// address: 0x600c20f8
-        /// mac intr map register
-        pub const INTR_STATUS_REG_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_intr_status_0
-            INTR_STATUS_0: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c20fc
-        /// mac intr map register
-        pub const INTR_STATUS_REG_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_intr_status_1
-            INTR_STATUS_1: u32,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c2100
-        /// mac intr map register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_reg_clk_en
-            REG_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c2104
-        /// mac intr map register
-        pub const CPU_INT_ENABLE = @intToPtr(*volatile u32, base_address + 0x104);
-
-        /// address: 0x600c2108
-        /// mac intr map register
-        pub const CPU_INT_TYPE = @intToPtr(*volatile u32, base_address + 0x108);
-
-        /// address: 0x600c210c
-        /// mac intr map register
-        pub const CPU_INT_CLEAR = @intToPtr(*volatile u32, base_address + 0x10c);
-
-        /// address: 0x600c2110
-        /// mac intr map register
-        pub const CPU_INT_EIP_STATUS = @intToPtr(*volatile u32, base_address + 0x110);
-
-        /// address: 0x600c2114
-        /// mac intr map register
-        pub const CPU_INT_PRI_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_0_map
-            CPU_PRI_0_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x600c2118
-        /// mac intr map register
-        pub const CPU_INT_PRI_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_1_map
-            CPU_PRI_1_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x600c211c
-        /// mac intr map register
-        pub const CPU_INT_PRI_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_2_map
-            CPU_PRI_2_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x11c);
-
-        /// address: 0x600c2120
-        /// mac intr map register
-        pub const CPU_INT_PRI_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_3_map
-            CPU_PRI_3_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x120);
-
-        /// address: 0x600c2124
-        /// mac intr map register
-        pub const CPU_INT_PRI_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_4_map
-            CPU_PRI_4_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600c2128
-        /// mac intr map register
-        pub const CPU_INT_PRI_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_5_map
-            CPU_PRI_5_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x128);
-
-        /// address: 0x600c212c
-        /// mac intr map register
-        pub const CPU_INT_PRI_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_6_map
-            CPU_PRI_6_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x12c);
-
-        /// address: 0x600c2130
-        /// mac intr map register
-        pub const CPU_INT_PRI_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_7_map
-            CPU_PRI_7_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x600c2134
-        /// mac intr map register
-        pub const CPU_INT_PRI_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_8_map
-            CPU_PRI_8_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x600c2138
-        /// mac intr map register
-        pub const CPU_INT_PRI_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_9_map
-            CPU_PRI_9_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x600c213c
-        /// mac intr map register
-        pub const CPU_INT_PRI_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_10_map
-            CPU_PRI_10_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x13c);
-
-        /// address: 0x600c2140
-        /// mac intr map register
-        pub const CPU_INT_PRI_11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_11_map
-            CPU_PRI_11_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x600c2144
-        /// mac intr map register
-        pub const CPU_INT_PRI_12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_12_map
-            CPU_PRI_12_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x600c2148
-        /// mac intr map register
-        pub const CPU_INT_PRI_13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_13_map
-            CPU_PRI_13_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x148);
-
-        /// address: 0x600c214c
-        /// mac intr map register
-        pub const CPU_INT_PRI_14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_14_map
-            CPU_PRI_14_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x600c2150
-        /// mac intr map register
-        pub const CPU_INT_PRI_15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_15_map
-            CPU_PRI_15_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x150);
-
-        /// address: 0x600c2154
-        /// mac intr map register
-        pub const CPU_INT_PRI_16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_16_map
-            CPU_PRI_16_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x154);
-
-        /// address: 0x600c2158
-        /// mac intr map register
-        pub const CPU_INT_PRI_17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_17_map
-            CPU_PRI_17_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x600c215c
-        /// mac intr map register
-        pub const CPU_INT_PRI_18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_18_map
-            CPU_PRI_18_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x600c2160
-        /// mac intr map register
-        pub const CPU_INT_PRI_19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_19_map
-            CPU_PRI_19_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x600c2164
-        /// mac intr map register
-        pub const CPU_INT_PRI_20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_20_map
-            CPU_PRI_20_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x600c2168
-        /// mac intr map register
-        pub const CPU_INT_PRI_21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_21_map
-            CPU_PRI_21_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x600c216c
-        /// mac intr map register
-        pub const CPU_INT_PRI_22 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_22_map
-            CPU_PRI_22_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x16c);
-
-        /// address: 0x600c2170
-        /// mac intr map register
-        pub const CPU_INT_PRI_23 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_23_map
-            CPU_PRI_23_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x600c2174
-        /// mac intr map register
-        pub const CPU_INT_PRI_24 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_24_map
-            CPU_PRI_24_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x174);
-
-        /// address: 0x600c2178
-        /// mac intr map register
-        pub const CPU_INT_PRI_25 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_25_map
-            CPU_PRI_25_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x178);
-
-        /// address: 0x600c217c
-        /// mac intr map register
-        pub const CPU_INT_PRI_26 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_26_map
-            CPU_PRI_26_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x17c);
-
-        /// address: 0x600c2180
-        /// mac intr map register
-        pub const CPU_INT_PRI_27 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_27_map
-            CPU_PRI_27_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x180);
-
-        /// address: 0x600c2184
-        /// mac intr map register
-        pub const CPU_INT_PRI_28 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_28_map
-            CPU_PRI_28_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x184);
-
-        /// address: 0x600c2188
-        /// mac intr map register
-        pub const CPU_INT_PRI_29 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_29_map
-            CPU_PRI_29_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x188);
-
-        /// address: 0x600c218c
-        /// mac intr map register
-        pub const CPU_INT_PRI_30 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_30_map
-            CPU_PRI_30_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x18c);
-
-        /// address: 0x600c2190
-        /// mac intr map register
-        pub const CPU_INT_PRI_31 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_31_map
-            CPU_PRI_31_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x600c2194
-        /// mac intr map register
-        pub const CPU_INT_THRESH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x194);
-
-        /// address: 0x600c27fc
-        /// mac intr map register
-        pub const INTERRUPT_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x7fc);
-    };
-
-    /// Input/Output Multiplexer
-    pub const IO_MUX = struct {
-        pub const base_address = 0x60009000;
-
-        /// address: 0x60009000
-        /// Clock Output Configuration Register
-        pub const PIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
-            /// CLK_OUT_out1 can be found in peripheral output signals.
-            CLK_OUT1: u4,
-            /// If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
-            /// CLK_OUT_out2 can be found in peripheral output signals.
-            CLK_OUT2: u4,
-            /// If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
-            /// CLK_OUT_out3 can be found in peripheral output signals.
-            CLK_OUT3: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60009004
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60009008
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000900c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60009010
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60009014
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60009018
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000901c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60009020
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60009024
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60009028
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000902c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60009030
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60009034
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60009038
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000903c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60009040
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60009044
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60009048
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000904c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60009050
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60009054
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60009058
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600090fc
-        /// IO MUX Version Control Register
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Version control register
-            REG_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// LED Control PWM (Pulse Width Modulation)
-    pub const LEDC = struct {
-        pub const base_address = 0x60019000;
-
-        /// address: 0x60019000
-        /// LEDC_LSCH0_CONF0.
-        pub const LSCH0_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch0.
-            TIMER_SEL_LSCH0: u2,
-            /// reg_sig_out_en_lsch0.
-            SIG_OUT_EN_LSCH0: u1,
-            /// reg_idle_lv_lsch0.
-            IDLE_LV_LSCH0: u1,
-            /// reg_para_up_lsch0.
-            PARA_UP_LSCH0: u1,
-            /// reg_ovf_num_lsch0.
-            OVF_NUM_LSCH0: u10,
-            /// reg_ovf_cnt_en_lsch0.
-            OVF_CNT_EN_LSCH0: u1,
-            /// reg_ovf_cnt_reset_lsch0.
-            OVF_CNT_RESET_LSCH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60019004
-        /// LEDC_LSCH0_HPOINT.
-        pub const LSCH0_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch0.
-            HPOINT_LSCH0: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60019008
-        /// LEDC_LSCH0_DUTY.
-        pub const LSCH0_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch0.
-            DUTY_LSCH0: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001900c
-        /// LEDC_LSCH0_CONF1.
-        pub const LSCH0_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch0.
-            DUTY_SCALE_LSCH0: u10,
-            /// reg_duty_cycle_lsch0.
-            DUTY_CYCLE_LSCH0: u10,
-            /// reg_duty_num_lsch0.
-            DUTY_NUM_LSCH0: u10,
-            /// reg_duty_inc_lsch0.
-            DUTY_INC_LSCH0: u1,
-            /// reg_duty_start_lsch0.
-            DUTY_START_LSCH0: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60019010
-        /// LEDC_LSCH0_DUTY_R.
-        pub const LSCH0_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch0_r.
-            DUTY_LSCH0_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60019014
-        /// LEDC_LSCH1_CONF0.
-        pub const LSCH1_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch1.
-            TIMER_SEL_LSCH1: u2,
-            /// reg_sig_out_en_lsch1.
-            SIG_OUT_EN_LSCH1: u1,
-            /// reg_idle_lv_lsch1.
-            IDLE_LV_LSCH1: u1,
-            /// reg_para_up_lsch1.
-            PARA_UP_LSCH1: u1,
-            /// reg_ovf_num_lsch1.
-            OVF_NUM_LSCH1: u10,
-            /// reg_ovf_cnt_en_lsch1.
-            OVF_CNT_EN_LSCH1: u1,
-            /// reg_ovf_cnt_reset_lsch1.
-            OVF_CNT_RESET_LSCH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60019018
-        /// LEDC_LSCH1_HPOINT.
-        pub const LSCH1_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch1.
-            HPOINT_LSCH1: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001901c
-        /// LEDC_LSCH1_DUTY.
-        pub const LSCH1_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch1.
-            DUTY_LSCH1: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60019020
-        /// LEDC_LSCH1_CONF1.
-        pub const LSCH1_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch1.
-            DUTY_SCALE_LSCH1: u10,
-            /// reg_duty_cycle_lsch1.
-            DUTY_CYCLE_LSCH1: u10,
-            /// reg_duty_num_lsch1.
-            DUTY_NUM_LSCH1: u10,
-            /// reg_duty_inc_lsch1.
-            DUTY_INC_LSCH1: u1,
-            /// reg_duty_start_lsch1.
-            DUTY_START_LSCH1: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60019024
-        /// LEDC_LSCH1_DUTY_R.
-        pub const LSCH1_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch1_r.
-            DUTY_LSCH1_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60019028
-        /// LEDC_LSCH2_CONF0.
-        pub const LSCH2_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch2.
-            TIMER_SEL_LSCH2: u2,
-            /// reg_sig_out_en_lsch2.
-            SIG_OUT_EN_LSCH2: u1,
-            /// reg_idle_lv_lsch2.
-            IDLE_LV_LSCH2: u1,
-            /// reg_para_up_lsch2.
-            PARA_UP_LSCH2: u1,
-            /// reg_ovf_num_lsch2.
-            OVF_NUM_LSCH2: u10,
-            /// reg_ovf_cnt_en_lsch2.
-            OVF_CNT_EN_LSCH2: u1,
-            /// reg_ovf_cnt_reset_lsch2.
-            OVF_CNT_RESET_LSCH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001902c
-        /// LEDC_LSCH2_HPOINT.
-        pub const LSCH2_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch2.
-            HPOINT_LSCH2: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60019030
-        /// LEDC_LSCH2_DUTY.
-        pub const LSCH2_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch2.
-            DUTY_LSCH2: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60019034
-        /// LEDC_LSCH2_CONF1.
-        pub const LSCH2_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch2.
-            DUTY_SCALE_LSCH2: u10,
-            /// reg_duty_cycle_lsch2.
-            DUTY_CYCLE_LSCH2: u10,
-            /// reg_duty_num_lsch2.
-            DUTY_NUM_LSCH2: u10,
-            /// reg_duty_inc_lsch2.
-            DUTY_INC_LSCH2: u1,
-            /// reg_duty_start_lsch2.
-            DUTY_START_LSCH2: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60019038
-        /// LEDC_LSCH2_DUTY_R.
-        pub const LSCH2_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch2_r.
-            DUTY_LSCH2_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001903c
-        /// LEDC_LSCH3_CONF0.
-        pub const LSCH3_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch3.
-            TIMER_SEL_LSCH3: u2,
-            /// reg_sig_out_en_lsch3.
-            SIG_OUT_EN_LSCH3: u1,
-            /// reg_idle_lv_lsch3.
-            IDLE_LV_LSCH3: u1,
-            /// reg_para_up_lsch3.
-            PARA_UP_LSCH3: u1,
-            /// reg_ovf_num_lsch3.
-            OVF_NUM_LSCH3: u10,
-            /// reg_ovf_cnt_en_lsch3.
-            OVF_CNT_EN_LSCH3: u1,
-            /// reg_ovf_cnt_reset_lsch3.
-            OVF_CNT_RESET_LSCH3: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60019040
-        /// LEDC_LSCH3_HPOINT.
-        pub const LSCH3_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch3.
-            HPOINT_LSCH3: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60019044
-        /// LEDC_LSCH3_DUTY.
-        pub const LSCH3_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch3.
-            DUTY_LSCH3: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60019048
-        /// LEDC_LSCH3_CONF1.
-        pub const LSCH3_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch3.
-            DUTY_SCALE_LSCH3: u10,
-            /// reg_duty_cycle_lsch3.
-            DUTY_CYCLE_LSCH3: u10,
-            /// reg_duty_num_lsch3.
-            DUTY_NUM_LSCH3: u10,
-            /// reg_duty_inc_lsch3.
-            DUTY_INC_LSCH3: u1,
-            /// reg_duty_start_lsch3.
-            DUTY_START_LSCH3: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001904c
-        /// LEDC_LSCH3_DUTY_R.
-        pub const LSCH3_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch3_r.
-            DUTY_LSCH3_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60019050
-        /// LEDC_LSCH4_CONF0.
-        pub const LSCH4_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch4.
-            TIMER_SEL_LSCH4: u2,
-            /// reg_sig_out_en_lsch4.
-            SIG_OUT_EN_LSCH4: u1,
-            /// reg_idle_lv_lsch4.
-            IDLE_LV_LSCH4: u1,
-            /// reg_para_up_lsch4.
-            PARA_UP_LSCH4: u1,
-            /// reg_ovf_num_lsch4.
-            OVF_NUM_LSCH4: u10,
-            /// reg_ovf_cnt_en_lsch4.
-            OVF_CNT_EN_LSCH4: u1,
-            /// reg_ovf_cnt_reset_lsch4.
-            OVF_CNT_RESET_LSCH4: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60019054
-        /// LEDC_LSCH4_HPOINT.
-        pub const LSCH4_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch4.
-            HPOINT_LSCH4: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60019058
-        /// LEDC_LSCH4_DUTY.
-        pub const LSCH4_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch4.
-            DUTY_LSCH4: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001905c
-        /// LEDC_LSCH4_CONF1.
-        pub const LSCH4_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch4.
-            DUTY_SCALE_LSCH4: u10,
-            /// reg_duty_cycle_lsch4.
-            DUTY_CYCLE_LSCH4: u10,
-            /// reg_duty_num_lsch4.
-            DUTY_NUM_LSCH4: u10,
-            /// reg_duty_inc_lsch4.
-            DUTY_INC_LSCH4: u1,
-            /// reg_duty_start_lsch4.
-            DUTY_START_LSCH4: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60019060
-        /// LEDC_LSCH4_DUTY_R.
-        pub const LSCH4_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch4_r.
-            DUTY_LSCH4_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60019064
-        /// LEDC_LSCH5_CONF0.
-        pub const LSCH5_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch5.
-            TIMER_SEL_LSCH5: u2,
-            /// reg_sig_out_en_lsch5.
-            SIG_OUT_EN_LSCH5: u1,
-            /// reg_idle_lv_lsch5.
-            IDLE_LV_LSCH5: u1,
-            /// reg_para_up_lsch5.
-            PARA_UP_LSCH5: u1,
-            /// reg_ovf_num_lsch5.
-            OVF_NUM_LSCH5: u10,
-            /// reg_ovf_cnt_en_lsch5.
-            OVF_CNT_EN_LSCH5: u1,
-            /// reg_ovf_cnt_reset_lsch5.
-            OVF_CNT_RESET_LSCH5: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60019068
-        /// LEDC_LSCH5_HPOINT.
-        pub const LSCH5_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch5.
-            HPOINT_LSCH5: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001906c
-        /// LEDC_LSCH5_DUTY.
-        pub const LSCH5_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch5.
-            DUTY_LSCH5: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60019070
-        /// LEDC_LSCH5_CONF1.
-        pub const LSCH5_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch5.
-            DUTY_SCALE_LSCH5: u10,
-            /// reg_duty_cycle_lsch5.
-            DUTY_CYCLE_LSCH5: u10,
-            /// reg_duty_num_lsch5.
-            DUTY_NUM_LSCH5: u10,
-            /// reg_duty_inc_lsch5.
-            DUTY_INC_LSCH5: u1,
-            /// reg_duty_start_lsch5.
-            DUTY_START_LSCH5: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60019074
-        /// LEDC_LSCH5_DUTY_R.
-        pub const LSCH5_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch5_r.
-            DUTY_LSCH5_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600190a0
-        /// LEDC_LSTIMER0_CONF.
-        pub const LSTIMER0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_duty_res.
-            LSTIMER0_DUTY_RES: u4,
-            /// reg_clk_div_lstimer0.
-            CLK_DIV_LSTIMER0: u18,
-            /// reg_lstimer0_pause.
-            LSTIMER0_PAUSE: u1,
-            /// reg_lstimer0_rst.
-            LSTIMER0_RST: u1,
-            /// reg_tick_sel_lstimer0.
-            TICK_SEL_LSTIMER0: u1,
-            /// reg_lstimer0_para_up.
-            LSTIMER0_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600190a4
-        /// LEDC_LSTIMER0_VALUE.
-        pub const LSTIMER0_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_cnt.
-            LSTIMER0_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600190a8
-        /// LEDC_LSTIMER1_CONF.
-        pub const LSTIMER1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer1_duty_res.
-            LSTIMER1_DUTY_RES: u4,
-            /// reg_clk_div_lstimer1.
-            CLK_DIV_LSTIMER1: u18,
-            /// reg_lstimer1_pause.
-            LSTIMER1_PAUSE: u1,
-            /// reg_lstimer1_rst.
-            LSTIMER1_RST: u1,
-            /// reg_tick_sel_lstimer1.
-            TICK_SEL_LSTIMER1: u1,
-            /// reg_lstimer1_para_up.
-            LSTIMER1_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600190ac
-        /// LEDC_LSTIMER1_VALUE.
-        pub const LSTIMER1_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer1_cnt.
-            LSTIMER1_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600190b0
-        /// LEDC_LSTIMER2_CONF.
-        pub const LSTIMER2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer2_duty_res.
-            LSTIMER2_DUTY_RES: u4,
-            /// reg_clk_div_lstimer2.
-            CLK_DIV_LSTIMER2: u18,
-            /// reg_lstimer2_pause.
-            LSTIMER2_PAUSE: u1,
-            /// reg_lstimer2_rst.
-            LSTIMER2_RST: u1,
-            /// reg_tick_sel_lstimer2.
-            TICK_SEL_LSTIMER2: u1,
-            /// reg_lstimer2_para_up.
-            LSTIMER2_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600190b4
-        /// LEDC_LSTIMER2_VALUE.
-        pub const LSTIMER2_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer2_cnt.
-            LSTIMER2_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600190b8
-        /// LEDC_LSTIMER3_CONF.
-        pub const LSTIMER3_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer3_duty_res.
-            LSTIMER3_DUTY_RES: u4,
-            /// reg_clk_div_lstimer3.
-            CLK_DIV_LSTIMER3: u18,
-            /// reg_lstimer3_pause.
-            LSTIMER3_PAUSE: u1,
-            /// reg_lstimer3_rst.
-            LSTIMER3_RST: u1,
-            /// reg_tick_sel_lstimer3.
-            TICK_SEL_LSTIMER3: u1,
-            /// reg_lstimer3_para_up.
-            LSTIMER3_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600190bc
-        /// LEDC_LSTIMER3_VALUE.
-        pub const LSTIMER3_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer3_cnt.
-            LSTIMER3_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600190c0
-        /// LEDC_INT_RAW.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_raw.
-            LSTIMER0_OVF_INT_RAW: u1,
-            /// reg_lstimer1_ovf_int_raw.
-            LSTIMER1_OVF_INT_RAW: u1,
-            /// reg_lstimer2_ovf_int_raw.
-            LSTIMER2_OVF_INT_RAW: u1,
-            /// reg_lstimer3_ovf_int_raw.
-            LSTIMER3_OVF_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch0_int_raw.
-            DUTY_CHNG_END_LSCH0_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch1_int_raw.
-            DUTY_CHNG_END_LSCH1_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch2_int_raw.
-            DUTY_CHNG_END_LSCH2_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch3_int_raw.
-            DUTY_CHNG_END_LSCH3_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch4_int_raw.
-            DUTY_CHNG_END_LSCH4_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch5_int_raw.
-            DUTY_CHNG_END_LSCH5_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch0_int_raw.
-            OVF_CNT_LSCH0_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch1_int_raw.
-            OVF_CNT_LSCH1_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch2_int_raw.
-            OVF_CNT_LSCH2_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch3_int_raw.
-            OVF_CNT_LSCH3_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch4_int_raw.
-            OVF_CNT_LSCH4_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch5_int_raw.
-            OVF_CNT_LSCH5_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600190c4
-        /// LEDC_INT_ST.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_st.
-            LSTIMER0_OVF_INT_ST: u1,
-            /// reg_lstimer1_ovf_int_st.
-            LSTIMER1_OVF_INT_ST: u1,
-            /// reg_lstimer2_ovf_int_st.
-            LSTIMER2_OVF_INT_ST: u1,
-            /// reg_lstimer3_ovf_int_st.
-            LSTIMER3_OVF_INT_ST: u1,
-            /// reg_duty_chng_end_lsch0_int_st.
-            DUTY_CHNG_END_LSCH0_INT_ST: u1,
-            /// reg_duty_chng_end_lsch1_int_st.
-            DUTY_CHNG_END_LSCH1_INT_ST: u1,
-            /// reg_duty_chng_end_lsch2_int_st.
-            DUTY_CHNG_END_LSCH2_INT_ST: u1,
-            /// reg_duty_chng_end_lsch3_int_st.
-            DUTY_CHNG_END_LSCH3_INT_ST: u1,
-            /// reg_duty_chng_end_lsch4_int_st.
-            DUTY_CHNG_END_LSCH4_INT_ST: u1,
-            /// reg_duty_chng_end_lsch5_int_st.
-            DUTY_CHNG_END_LSCH5_INT_ST: u1,
-            /// reg_ovf_cnt_lsch0_int_st.
-            OVF_CNT_LSCH0_INT_ST: u1,
-            /// reg_ovf_cnt_lsch1_int_st.
-            OVF_CNT_LSCH1_INT_ST: u1,
-            /// reg_ovf_cnt_lsch2_int_st.
-            OVF_CNT_LSCH2_INT_ST: u1,
-            /// reg_ovf_cnt_lsch3_int_st.
-            OVF_CNT_LSCH3_INT_ST: u1,
-            /// reg_ovf_cnt_lsch4_int_st.
-            OVF_CNT_LSCH4_INT_ST: u1,
-            /// reg_ovf_cnt_lsch5_int_st.
-            OVF_CNT_LSCH5_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600190c8
-        /// LEDC_INT_ENA.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_ena.
-            LSTIMER0_OVF_INT_ENA: u1,
-            /// reg_lstimer1_ovf_int_ena.
-            LSTIMER1_OVF_INT_ENA: u1,
-            /// reg_lstimer2_ovf_int_ena.
-            LSTIMER2_OVF_INT_ENA: u1,
-            /// reg_lstimer3_ovf_int_ena.
-            LSTIMER3_OVF_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch0_int_ena.
-            DUTY_CHNG_END_LSCH0_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch1_int_ena.
-            DUTY_CHNG_END_LSCH1_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch2_int_ena.
-            DUTY_CHNG_END_LSCH2_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch3_int_ena.
-            DUTY_CHNG_END_LSCH3_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch4_int_ena.
-            DUTY_CHNG_END_LSCH4_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch5_int_ena.
-            DUTY_CHNG_END_LSCH5_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch0_int_ena.
-            OVF_CNT_LSCH0_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch1_int_ena.
-            OVF_CNT_LSCH1_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch2_int_ena.
-            OVF_CNT_LSCH2_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch3_int_ena.
-            OVF_CNT_LSCH3_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch4_int_ena.
-            OVF_CNT_LSCH4_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch5_int_ena.
-            OVF_CNT_LSCH5_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600190cc
-        /// LEDC_INT_CLR.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_clr.
-            LSTIMER0_OVF_INT_CLR: u1,
-            /// reg_lstimer1_ovf_int_clr.
-            LSTIMER1_OVF_INT_CLR: u1,
-            /// reg_lstimer2_ovf_int_clr.
-            LSTIMER2_OVF_INT_CLR: u1,
-            /// reg_lstimer3_ovf_int_clr.
-            LSTIMER3_OVF_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch0_int_clr.
-            DUTY_CHNG_END_LSCH0_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch1_int_clr.
-            DUTY_CHNG_END_LSCH1_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch2_int_clr.
-            DUTY_CHNG_END_LSCH2_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch3_int_clr.
-            DUTY_CHNG_END_LSCH3_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch4_int_clr.
-            DUTY_CHNG_END_LSCH4_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch5_int_clr.
-            DUTY_CHNG_END_LSCH5_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch0_int_clr.
-            OVF_CNT_LSCH0_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch1_int_clr.
-            OVF_CNT_LSCH1_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch2_int_clr.
-            OVF_CNT_LSCH2_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch3_int_clr.
-            OVF_CNT_LSCH3_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch4_int_clr.
-            OVF_CNT_LSCH4_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch5_int_clr.
-            OVF_CNT_LSCH5_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600190d0
-        /// LEDC_CONF.
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_apb_clk_sel.
-            APB_CLK_SEL: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600190fc
-        /// LEDC_DATE.
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ledc_date.
-            LEDC_DATE: u32,
-        }), base_address + 0xfc);
-    };
-
-    /// Remote Control Peripheral
-    pub const RMT = struct {
-        pub const base_address = 0x60016000;
-
-        /// address: 0x60016000
-        /// RMT_CH0DATA_REG.
-        pub const CH0DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60016004
-        /// RMT_CH1DATA_REG.
-        pub const CH1DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60016008
-        /// RMT_CH2DATA_REG.
-        pub const CH2DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x8);
-
-        /// address: 0x6001600c
-        /// RMT_CH3DATA_REG.
-        pub const CH3DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0xc);
-
-        /// address: 0x60016010
-        /// RMT_CH%sCONF%s_REG.
-        pub const CH0_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_tx_start_ch0.
-            TX_START: u1,
-            /// reg_mem_rd_rst_ch0.
-            MEM_RD_RST: u1,
-            /// reg_apb_mem_rst_ch0.
-            APB_MEM_RST: u1,
-            /// reg_tx_conti_mode_ch0.
-            TX_CONTI_MODE: u1,
-            /// reg_mem_tx_wrap_en_ch0.
-            MEM_TX_WRAP_EN: u1,
-            /// reg_idle_out_lv_ch0.
-            IDLE_OUT_LV: u1,
-            /// reg_idle_out_en_ch0.
-            IDLE_OUT_EN: u1,
-            /// reg_tx_stop_ch0.
-            TX_STOP: u1,
-            /// reg_div_cnt_ch0.
-            DIV_CNT: u8,
-            /// reg_mem_size_ch0.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            /// reg_carrier_eff_en_ch0.
-            CARRIER_EFF_EN: u1,
-            /// reg_carrier_en_ch0.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch0.
-            CARRIER_OUT_LV: u1,
-            /// reg_afifo_rst_ch0.
-            AFIFO_RST: u1,
-            /// reg_reg_conf_update_ch0.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60016014
-        /// RMT_CH%sCONF%s_REG.
-        pub const CH1_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_tx_start_ch0.
-            TX_START: u1,
-            /// reg_mem_rd_rst_ch0.
-            MEM_RD_RST: u1,
-            /// reg_apb_mem_rst_ch0.
-            APB_MEM_RST: u1,
-            /// reg_tx_conti_mode_ch0.
-            TX_CONTI_MODE: u1,
-            /// reg_mem_tx_wrap_en_ch0.
-            MEM_TX_WRAP_EN: u1,
-            /// reg_idle_out_lv_ch0.
-            IDLE_OUT_LV: u1,
-            /// reg_idle_out_en_ch0.
-            IDLE_OUT_EN: u1,
-            /// reg_tx_stop_ch0.
-            TX_STOP: u1,
-            /// reg_div_cnt_ch0.
-            DIV_CNT: u8,
-            /// reg_mem_size_ch0.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            /// reg_carrier_eff_en_ch0.
-            CARRIER_EFF_EN: u1,
-            /// reg_carrier_en_ch0.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch0.
-            CARRIER_OUT_LV: u1,
-            /// reg_afifo_rst_ch0.
-            AFIFO_RST: u1,
-            /// reg_reg_conf_update_ch0.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60016018
-        /// RMT_CH2CONF0_REG.
-        pub const CH2_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_div_cnt_ch2.
-            DIV_CNT: u8,
-            /// reg_idle_thres_ch2.
-            IDLE_THRES: u15,
-            /// reg_mem_size_ch2.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_carrier_en_ch2.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch2.
-            CARRIER_OUT_LV: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x60016020
-        /// RMT_CH2CONF0_REG.
-        pub const CH3_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_div_cnt_ch2.
-            DIV_CNT: u8,
-            /// reg_idle_thres_ch2.
-            IDLE_THRES: u15,
-            /// reg_mem_size_ch2.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_carrier_en_ch2.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch2.
-            CARRIER_OUT_LV: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6001601c
-        /// RMT_CH2CONF1_REG.
-        pub const CH2CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rx_en_ch2.
-            RX_EN: u1,
-            /// reg_mem_wr_rst_ch2.
-            MEM_WR_RST: u1,
-            /// reg_apb_mem_rst_ch2.
-            APB_MEM_RST: u1,
-            /// reg_mem_owner_ch2.
-            MEM_OWNER: u1,
-            /// reg_rx_filter_en_ch2.
-            RX_FILTER_EN: u1,
-            /// reg_rx_filter_thres_ch2.
-            RX_FILTER_THRES: u8,
-            /// reg_mem_rx_wrap_en_ch2.
-            MEM_RX_WRAP_EN: u1,
-            /// reg_afifo_rst_ch2.
-            AFIFO_RST: u1,
-            /// reg_conf_update_ch2.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60016024
-        /// RMT_CH3CONF1_REG.
-        pub const CH3CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rx_en_ch3.
-            RX_EN: u1,
-            /// reg_mem_wr_rst_ch3.
-            MEM_WR_RST: u1,
-            /// reg_apb_mem_rst_ch3.
-            APB_MEM_RST: u1,
-            /// reg_mem_owner_ch3.
-            MEM_OWNER: u1,
-            /// reg_rx_filter_en_ch3.
-            RX_FILTER_EN: u1,
-            /// reg_rx_filter_thres_ch3.
-            RX_FILTER_THRES: u8,
-            /// reg_mem_rx_wrap_en_ch3.
-            MEM_RX_WRAP_EN: u1,
-            /// reg_afifo_rst_ch3.
-            AFIFO_RST: u1,
-            /// reg_conf_update_ch3.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60016028
-        /// RMT_CH0STATUS_REG.
-        pub const CH0STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_raddr_ex_ch0.
-            MEM_RADDR_EX: u9,
-            /// reg_state_ch0.
-            STATE: u3,
-            /// reg_apb_mem_waddr_ch0.
-            APB_MEM_WADDR: u9,
-            /// reg_apb_mem_rd_err_ch0.
-            APB_MEM_RD_ERR: u1,
-            /// reg_mem_empty_ch0.
-            MEM_EMPTY: u1,
-            /// reg_apb_mem_wr_err_ch0.
-            APB_MEM_WR_ERR: u1,
-            /// reg_apb_mem_raddr_ch0.
-            APB_MEM_RADDR: u8,
-        }), base_address + 0x28);
-
-        /// address: 0x6001602c
-        /// RMT_CH1STATUS_REG.
-        pub const CH1STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_raddr_ex_ch1.
-            MEM_RADDR_EX: u9,
-            /// reg_state_ch1.
-            STATE: u3,
-            /// reg_apb_mem_waddr_ch1.
-            APB_MEM_WADDR: u9,
-            /// reg_apb_mem_rd_err_ch1.
-            APB_MEM_RD_ERR: u1,
-            /// reg_mem_empty_ch1.
-            MEM_EMPTY: u1,
-            /// reg_apb_mem_wr_err_ch1.
-            APB_MEM_WR_ERR: u1,
-            /// reg_apb_mem_raddr_ch1.
-            APB_MEM_RADDR: u8,
-        }), base_address + 0x2c);
-
-        /// address: 0x60016030
-        /// RMT_CH2STATUS_REG.
-        pub const CH2STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_waddr_ex_ch2.
-            MEM_WADDR_EX: u9,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_apb_mem_raddr_ch2.
-            APB_MEM_RADDR: u9,
-            reserved3: u1,
-            /// reg_state_ch2.
-            STATE: u3,
-            /// reg_mem_owner_err_ch2.
-            MEM_OWNER_ERR: u1,
-            /// reg_mem_full_ch2.
-            MEM_FULL: u1,
-            /// reg_apb_mem_rd_err_ch2.
-            APB_MEM_RD_ERR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60016034
-        /// RMT_CH3STATUS_REG.
-        pub const CH3STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_waddr_ex_ch3.
-            MEM_WADDR_EX: u9,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_apb_mem_raddr_ch3.
-            APB_MEM_RADDR: u9,
-            reserved3: u1,
-            /// reg_state_ch3.
-            STATE: u3,
-            /// reg_mem_owner_err_ch3.
-            MEM_OWNER_ERR: u1,
-            /// reg_mem_full_ch3.
-            MEM_FULL: u1,
-            /// reg_apb_mem_rd_err_ch3.
-            APB_MEM_RD_ERR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60016038
-        /// RMT_INT_RAW_REG.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_RAW: u1,
-            CH1_TX_END_INT_RAW: u1,
-            CH2_RX_END_INT_RAW: u1,
-            CH3_RX_END_INT_RAW: u1,
-            CH0_TX_ERR_INT_RAW: u1,
-            CH1_TX_ERR_INT_RAW: u1,
-            CH2_RX_ERR_INT_RAW: u1,
-            CH3_RX_ERR_INT_RAW: u1,
-            CH0_TX_THR_EVENT_INT_RAW: u1,
-            CH1_TX_THR_EVENT_INT_RAW: u1,
-            /// reg_ch2_rx_thr_event_int_raw.
-            CH2_RX_THR_EVENT_INT_RAW: u1,
-            /// reg_ch3_rx_thr_event_int_raw.
-            CH3_RX_THR_EVENT_INT_RAW: u1,
-            CH0_TX_LOOP_INT_RAW: u1,
-            CH1_TX_LOOP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001603c
-        /// RMT_INT_ST_REG.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_ST: u1,
-            CH1_TX_END_INT_ST: u1,
-            CH2_RX_END_INT_ST: u1,
-            CH3_RX_END_INT_ST: u1,
-            CH0_TX_ERR_INT_ST: u1,
-            CH1_TX_ERR_INT_ST: u1,
-            CH2_RX_ERR_INT_ST: u1,
-            CH3_RX_ERR_INT_ST: u1,
-            CH0_TX_THR_EVENT_INT_ST: u1,
-            CH1_TX_THR_EVENT_INT_ST: u1,
-            /// reg_ch2_rx_thr_event_int_st.
-            CH2_RX_THR_EVENT_INT_ST: u1,
-            /// reg_ch3_rx_thr_event_int_st.
-            CH3_RX_THR_EVENT_INT_ST: u1,
-            CH0_TX_LOOP_INT_ST: u1,
-            CH1_TX_LOOP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60016040
-        /// RMT_INT_ENA_REG.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_ENA: u1,
-            CH1_TX_END_INT_ENA: u1,
-            CH2_RX_END_INT_ENA: u1,
-            CH3_RX_END_INT_ENA: u1,
-            CH0_TX_ERR_INT_ENA: u1,
-            CH1_TX_ERR_INT_ENA: u1,
-            CH2_RX_ERR_INT_ENA: u1,
-            CH3_RX_ERR_INT_ENA: u1,
-            CH0_TX_THR_EVENT_INT_ENA: u1,
-            CH1_TX_THR_EVENT_INT_ENA: u1,
-            /// reg_ch2_rx_thr_event_int_ena.
-            CH2_RX_THR_EVENT_INT_ENA: u1,
-            /// reg_ch3_rx_thr_event_int_ena.
-            CH3_RX_THR_EVENT_INT_ENA: u1,
-            CH0_TX_LOOP_INT_ENA: u1,
-            CH1_TX_LOOP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60016044
-        /// RMT_INT_CLR_REG.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_CLR: u1,
-            CH1_TX_END_INT_CLR: u1,
-            CH2_RX_END_INT_CLR: u1,
-            CH3_RX_END_INT_CLR: u1,
-            CH0_TX_ERR_INT_CLR: u1,
-            CH1_TX_ERR_INT_CLR: u1,
-            CH2_RX_ERR_INT_CLR: u1,
-            CH3_RX_ERR_INT_CLR: u1,
-            CH0_TX_THR_EVENT_INT_CLR: u1,
-            CH1_TX_THR_EVENT_INT_CLR: u1,
-            /// reg_ch2_rx_thr_event_int_clr.
-            CH2_RX_THR_EVENT_INT_CLR: u1,
-            /// reg_ch3_rx_thr_event_int_clr.
-            CH3_RX_THR_EVENT_INT_CLR: u1,
-            CH0_TX_LOOP_INT_CLR: u1,
-            CH1_TX_LOOP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60016048
-        /// RMT_CH0CARRIER_DUTY_REG.
-        pub const CH0CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_ch0.
-            CARRIER_LOW: u16,
-            /// reg_carrier_high_ch0.
-            CARRIER_HIGH: u16,
-        }), base_address + 0x48);
-
-        /// address: 0x6001604c
-        /// RMT_CH1CARRIER_DUTY_REG.
-        pub const CH1CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_ch1.
-            CARRIER_LOW: u16,
-            /// reg_carrier_high_ch1.
-            CARRIER_HIGH: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x60016050
-        /// RMT_CH2_RX_CARRIER_RM_REG.
-        pub const CH2_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_thres_ch2.
-            CARRIER_LOW_THRES: u16,
-            /// reg_carrier_high_thres_ch2.
-            CARRIER_HIGH_THRES: u16,
-        }), base_address + 0x50);
-
-        /// address: 0x60016054
-        /// RMT_CH3_RX_CARRIER_RM_REG.
-        pub const CH3_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_thres_ch3.
-            CARRIER_LOW_THRES: u16,
-            /// reg_carrier_high_thres_ch3.
-            CARRIER_HIGH_THRES: u16,
-        }), base_address + 0x54);
-
-        /// address: 0x60016058
-        /// RMT_CH%s_TX_LIM_REG.
-        pub const CH0_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_lim_ch0.
-            TX_LIM: u9,
-            /// reg_rmt_tx_loop_num_ch0.
-            TX_LOOP_NUM: u10,
-            /// reg_rmt_tx_loop_cnt_en_ch0.
-            TX_LOOP_CNT_EN: u1,
-            /// reg_loop_count_reset_ch0.
-            LOOP_COUNT_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001605c
-        /// RMT_CH%s_TX_LIM_REG.
-        pub const CH1_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_lim_ch0.
-            TX_LIM: u9,
-            /// reg_rmt_tx_loop_num_ch0.
-            TX_LOOP_NUM: u10,
-            /// reg_rmt_tx_loop_cnt_en_ch0.
-            TX_LOOP_CNT_EN: u1,
-            /// reg_loop_count_reset_ch0.
-            LOOP_COUNT_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60016060
-        /// RMT_CH2_RX_LIM_REG.
-        pub const CH2_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_rx_lim_ch2.
-            RX_LIM: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60016064
-        /// RMT_CH2_RX_LIM_REG.
-        pub const CH3_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_rx_lim_ch2.
-            RX_LIM: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60016068
-        /// RMT_SYS_CONF_REG.
-        pub const SYS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_apb_fifo_mask.
-            APB_FIFO_MASK: u1,
-            /// reg_mem_clk_force_on.
-            MEM_CLK_FORCE_ON: u1,
-            /// reg_rmt_mem_force_pd.
-            MEM_FORCE_PD: u1,
-            /// reg_rmt_mem_force_pu.
-            MEM_FORCE_PU: u1,
-            /// reg_rmt_sclk_div_num.
-            SCLK_DIV_NUM: u8,
-            /// reg_rmt_sclk_div_a.
-            SCLK_DIV_A: u6,
-            /// reg_rmt_sclk_div_b.
-            SCLK_DIV_B: u6,
-            /// reg_rmt_sclk_sel.
-            SCLK_SEL: u2,
-            /// reg_rmt_sclk_active.
-            SCLK_ACTIVE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001606c
-        /// RMT_TX_SIM_REG.
-        pub const TX_SIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_sim_ch0.
-            TX_SIM_CH0: u1,
-            /// reg_rmt_tx_sim_ch1.
-            TX_SIM_CH1: u1,
-            /// reg_rmt_tx_sim_en.
-            TX_SIM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60016070
-        /// RMT_REF_CNT_RST_REG.
-        pub const REF_CNT_RST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ref_cnt_rst_ch0.
-            CH0: u1,
-            /// reg_ref_cnt_rst_ch1.
-            CH1: u1,
-            /// reg_ref_cnt_rst_ch2.
-            CH2: u1,
-            /// reg_ref_cnt_rst_ch3.
-            CH3: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600160cc
-        /// RMT_DATE_REG.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xcc);
-    };
-
-    /// Hardware random number generator
-    pub const RNG = struct {
-        pub const base_address = 0x60026000;
-
-        /// address: 0x600260b0
-        /// Random number data
-        pub const DATA = @intToPtr(*volatile u32, base_address + 0xb0);
-    };
-
-    /// RSA (Rivest Shamir Adleman) Accelerator
-    pub const RSA = struct {
-        pub const base_address = 0x6003c000;
-
-        /// address: 0x6003c000
-        /// The memory that stores M
-        pub const M_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
-
-        /// address: 0x6003c200
-        /// The memory that stores Z
-        pub const Z_MEM = @intToPtr(*volatile [16]u8, base_address + 0x200);
-
-        /// address: 0x6003c400
-        /// The memory that stores Y
-        pub const Y_MEM = @intToPtr(*volatile [16]u8, base_address + 0x400);
-
-        /// address: 0x6003c600
-        /// The memory that stores X
-        pub const X_MEM = @intToPtr(*volatile [16]u8, base_address + 0x600);
-
-        /// address: 0x6003c800
-        /// RSA M_prime register
-        pub const M_PRIME = @intToPtr(*volatile u32, base_address + 0x800);
-
-        /// address: 0x6003c804
-        /// RSA mode register
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x804);
-
-        /// address: 0x6003c808
-        /// RSA query clean register
-        pub const QUERY_CLEAN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x808);
-
-        /// address: 0x6003c80c
-        /// RSA modular exponentiation trigger register.
-        pub const SET_START_MODEXP = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x80c);
-
-        /// address: 0x6003c810
-        /// RSA modular multiplication trigger register.
-        pub const SET_START_MODMULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x810);
-
-        /// address: 0x6003c814
-        /// RSA normal multiplication trigger register.
-        pub const SET_START_MULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x814);
-
-        /// address: 0x6003c818
-        /// RSA query idle register
-        pub const QUERY_IDLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x818);
-
-        /// address: 0x6003c81c
-        /// RSA interrupt clear register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this bit to clear RSA interrupt.
-            CLEAR_INTERRUPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x81c);
-
-        /// address: 0x6003c820
-        /// RSA constant time option register
-        pub const CONSTANT_TIME = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x820);
-
-        /// address: 0x6003c824
-        /// RSA search option
-        pub const SEARCH_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x824);
-
-        /// address: 0x6003c828
-        /// RSA search position configure register
-        pub const SEARCH_POS = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x828);
-
-        /// address: 0x6003c82c
-        /// RSA interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x82c);
-
-        /// address: 0x6003c830
-        /// RSA version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x830);
-    };
-
-    /// Real-Time Clock Control
-    pub const RTC_CNTL = struct {
-        pub const base_address = 0x60008000;
-
-        /// address: 0x60008000
-        /// rtc configure register
-        pub const OPTIONS0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall
-            /// APP CPU
-            SW_STALL_APPCPU_C0: u2,
-            /// {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall
-            /// PRO CPU
-            SW_STALL_PROCPU_C0: u2,
-            /// APP CPU SW reset
-            SW_APPCPU_RST: u1,
-            /// PRO CPU SW reset
-            SW_PROCPU_RST: u1,
-            /// BB_I2C force power down
-            BB_I2C_FORCE_PD: u1,
-            /// BB_I2C force power up
-            BB_I2C_FORCE_PU: u1,
-            /// BB_PLL _I2C force power down
-            BBPLL_I2C_FORCE_PD: u1,
-            /// BB_PLL_I2C force power up
-            BBPLL_I2C_FORCE_PU: u1,
-            /// BB_PLL force power down
-            BBPLL_FORCE_PD: u1,
-            /// BB_PLL force power up
-            BBPLL_FORCE_PU: u1,
-            /// crystall force power down
-            XTL_FORCE_PD: u1,
-            /// crystall force power up
-            XTL_FORCE_PU: u1,
-            /// wait bias_sleep and current source wakeup
-            XTL_EN_WAIT: u4,
-            reserved0: u1,
-            reserved1: u1,
-            /// analog configure
-            XTL_EXT_CTR_SEL: u3,
-            /// analog configure
-            XTL_FORCE_ISO: u1,
-            /// analog configure
-            PLL_FORCE_ISO: u1,
-            /// analog configure
-            ANALOG_FORCE_ISO: u1,
-            /// analog configure
-            XTL_FORCE_NOISO: u1,
-            /// analog configure
-            PLL_FORCE_NOISO: u1,
-            /// analog configure
-            ANALOG_FORCE_NOISO: u1,
-            /// digital wrap force reset in deep sleep
-            DG_WRAP_FORCE_RST: u1,
-            /// digital core force no reset in deep sleep
-            DG_WRAP_FORCE_NORST: u1,
-            /// SW system reset
-            SW_SYS_RST: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60008004
-        /// rtc configure register
-        pub const SLP_TIMER0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure the sleep time
-            SLP_VAL_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60008008
-        /// rtc configure register
-        pub const SLP_TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC sleep timer high 16 bits
-            SLP_VAL_HI: u16,
-            /// timer alarm enable bit
-            RTC_MAIN_TIMER_ALARM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000800c
-        /// rtc configure register
-        pub const TIME_UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// Enable to record system stall time
-            TIMER_SYS_STALL: u1,
-            /// Enable to record 40M XTAL OFF time
-            TIMER_XTL_OFF: u1,
-            /// enable to record system reset time
-            TIMER_SYS_RST: u1,
-            reserved27: u1,
-            /// Set 1: to update register with RTC timer
-            RTC_TIME_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60008010
-        /// rtc configure register
-        pub const TIME_LOW0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer low 32 bits
-            RTC_TIMER_VALUE0_LOW: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60008014
-        /// rtc configure register
-        pub const TIME_HIGH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer high 16 bits
-            RTC_TIMER_VALUE0_HIGH: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60008018
-        /// rtc configure register
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc software interrupt to main cpu
-            RTC_SW_CPU_INT: u1,
-            /// clear rtc sleep reject cause
-            RTC_SLP_REJECT_CAUSE_CLR: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// 1: APB to RTC using bridge
-            APB2RTC_BRIDGE_SEL: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            /// SDIO active indication
-            SDIO_ACTIVE_IND: u1,
-            /// leep wakeup bit
-            SLP_WAKEUP: u1,
-            /// leep reject bit
-            SLP_REJECT: u1,
-            /// sleep enable bit
-            SLEEP_EN: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000801c
-        /// rtc configure register
-        pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// CPU stall enable bit
-            CPU_STALL_EN: u1,
-            /// CPU stall wait cycles in fast_clk_rtc
-            CPU_STALL_WAIT: u5,
-            /// CK8M wait cycles in slow_clk_rtc
-            CK8M_WAIT: u8,
-            /// XTAL wait cycles in slow_clk_rtc
-            XTL_BUF_WAIT: u10,
-            /// PLL wait cycles in slow_clk_rtc
-            PLL_BUF_WAIT: u8,
-        }), base_address + 0x1c);
-
-        /// address: 0x60008020
-        /// rtc configure register
-        pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            /// minimal cycles in slow_clk_rtc for CK8M in power down state
-            MIN_TIME_CK8M_OFF: u8,
-        }), base_address + 0x20);
-
-        /// address: 0x60008024
-        /// rtc configure register
-        pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wifi power domain wakeup time
-            WIFI_WAIT_TIMER: u9,
-            /// wifi power domain power on time
-            WIFI_POWERUP_TIMER: u7,
-            /// bt power domain wakeup time
-            BT_WAIT_TIMER: u9,
-            /// bt power domain power on time
-            BT_POWERUP_TIMER: u7,
-        }), base_address + 0x24);
-
-        /// address: 0x60008028
-        /// rtc configure register
-        pub const TIMER4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cpu top power domain wakeup time
-            CPU_TOP_WAIT_TIMER: u9,
-            /// cpu top power domain power on time
-            CPU_TOP_POWERUP_TIMER: u7,
-            /// digital wrap power domain wakeup time
-            DG_WRAP_WAIT_TIMER: u9,
-            /// digital wrap power domain power on time
-            DG_WRAP_POWERUP_TIMER: u7,
-        }), base_address + 0x28);
-
-        /// address: 0x6000802c
-        /// rtc configure register
-        pub const TIMER5 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// minimal sleep cycles in slow_clk_rtc
-            MIN_SLP_VAL: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60008030
-        /// rtc configure register
-        pub const TIMER6 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// digital peri power domain wakeup time
-            DG_PERI_WAIT_TIMER: u9,
-            /// digital peri power domain power on time
-            DG_PERI_POWERUP_TIMER: u7,
-        }), base_address + 0x30);
-
-        /// address: 0x60008034
-        /// rtc configure register
-        pub const ANA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// force no bypass i2c power on reset
-            RESET_POR_FORCE_PD: u1,
-            /// force bypass i2c power on reset
-            RESET_POR_FORCE_PU: u1,
-            /// enable glitch reset
-            GLITCH_RST_EN: u1,
-            reserved18: u1,
-            /// PLLA force power up
-            SAR_I2C_PU: u1,
-            /// PLLA force power down
-            PLLA_FORCE_PD: u1,
-            /// PLLA force power up
-            PLLA_FORCE_PU: u1,
-            /// start BBPLL calibration during sleep
-            BBPLL_CAL_SLP_START: u1,
-            /// 1: PVTMON power up
-            PVTMON_PU: u1,
-            /// 1: TXRF_I2C power up
-            TXRF_I2C_PU: u1,
-            /// 1: RFRX_PBUS power up
-            RFRX_PBUS_PU: u1,
-            reserved19: u1,
-            /// 1: CKGEN_I2C power up
-            CKGEN_I2C_PU: u1,
-            /// power up pll i2c
-            PLL_I2C_PU: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60008038
-        /// rtc configure register
-        pub const RESET_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reset cause of PRO CPU
-            RESET_CAUSE_PROCPU: u6,
-            /// reset cause of APP CPU
-            RESET_CAUSE_APPCPU: u6,
-            /// APP CPU state vector sel
-            STAT_VECTOR_SEL_APPCPU: u1,
-            /// PRO CPU state vector sel
-            STAT_VECTOR_SEL_PROCPU: u1,
-            /// PRO CPU reset_flag
-            ALL_RESET_FLAG_PROCPU: u1,
-            /// APP CPU reset flag
-            ALL_RESET_FLAG_APPCPU: u1,
-            /// clear PRO CPU reset_flag
-            ALL_RESET_FLAG_CLR_PROCPU: u1,
-            /// clear APP CPU reset flag
-            ALL_RESET_FLAG_CLR_APPCPU: u1,
-            /// APPCPU OcdHaltOnReset
-            OCD_HALT_ON_RESET_APPCPU: u1,
-            /// PROCPU OcdHaltOnReset
-            OCD_HALT_ON_RESET_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_APPCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_CLR_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_CLR_APPCPU: u1,
-            /// configure dreset configure
-            RTC_DRESET_MASK_APPCPU: u1,
-            /// configure dreset configure
-            RTC_DRESET_MASK_PROCPU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000803c
-        /// rtc configure register
-        pub const WAKEUP_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// wakeup enable bitmap
-            RTC_WAKEUP_ENA: u17,
-        }), base_address + 0x3c);
-
-        /// address: 0x60008040
-        /// rtc configure register
-        pub const INT_ENA_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable sleep wakeup interrupt
-            SLP_WAKEUP_INT_ENA: u1,
-            /// enable sleep reject interrupt
-            SLP_REJECT_INT_ENA: u1,
-            reserved0: u1,
-            /// enable RTC WDT interrupt
-            RTC_WDT_INT_ENA: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// enable brown out interrupt
-            RTC_BROWN_OUT_INT_ENA: u1,
-            /// enable RTC main timer interrupt
-            RTC_MAIN_TIMER_INT_ENA: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable super watch dog interrupt
-            RTC_SWD_INT_ENA: u1,
-            /// enable xtal32k_dead interrupt
-            RTC_XTAL32K_DEAD_INT_ENA: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// enbale gitch det interrupt
-            RTC_GLITCH_DET_INT_ENA: u1,
-            /// enbale bbpll cal end interrupt
-            RTC_BBPLL_CAL_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60008044
-        /// rtc configure register
-        pub const INT_RAW_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup interrupt raw
-            SLP_WAKEUP_INT_RAW: u1,
-            /// sleep reject interrupt raw
-            SLP_REJECT_INT_RAW: u1,
-            reserved0: u1,
-            /// RTC WDT interrupt raw
-            RTC_WDT_INT_RAW: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// brown out interrupt raw
-            RTC_BROWN_OUT_INT_RAW: u1,
-            /// RTC main timer interrupt raw
-            RTC_MAIN_TIMER_INT_RAW: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// super watch dog interrupt raw
-            RTC_SWD_INT_RAW: u1,
-            /// xtal32k dead detection interrupt raw
-            RTC_XTAL32K_DEAD_INT_RAW: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// glitch_det_interrupt_raw
-            RTC_GLITCH_DET_INT_RAW: u1,
-            /// bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60008048
-        /// rtc configure register
-        pub const INT_ST_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup interrupt state
-            SLP_WAKEUP_INT_ST: u1,
-            /// sleep reject interrupt state
-            SLP_REJECT_INT_ST: u1,
-            reserved0: u1,
-            /// RTC WDT interrupt state
-            RTC_WDT_INT_ST: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// brown out interrupt state
-            RTC_BROWN_OUT_INT_ST: u1,
-            /// RTC main timer interrupt state
-            RTC_MAIN_TIMER_INT_ST: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// super watch dog interrupt state
-            RTC_SWD_INT_ST: u1,
-            /// xtal32k dead detection interrupt state
-            RTC_XTAL32K_DEAD_INT_ST: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// glitch_det_interrupt state
-            RTC_GLITCH_DET_INT_ST: u1,
-            /// bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000804c
-        /// rtc configure register
-        pub const INT_CLR_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear sleep wakeup interrupt state
-            SLP_WAKEUP_INT_CLR: u1,
-            /// Clear sleep reject interrupt state
-            SLP_REJECT_INT_CLR: u1,
-            reserved0: u1,
-            /// Clear RTC WDT interrupt state
-            RTC_WDT_INT_CLR: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Clear brown out interrupt state
-            RTC_BROWN_OUT_INT_CLR: u1,
-            /// Clear RTC main timer interrupt state
-            RTC_MAIN_TIMER_INT_CLR: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// Clear super watch dog interrupt state
-            RTC_SWD_INT_CLR: u1,
-            /// Clear RTC WDT interrupt state
-            RTC_XTAL32K_DEAD_INT_CLR: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Clear glitch det interrupt state
-            RTC_GLITCH_DET_INT_CLR: u1,
-            /// clear bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60008050
-        /// rtc configure register
-        pub const STORE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH0: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60008054
-        /// rtc configure register
-        pub const STORE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH1: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60008058
-        /// rtc configure register
-        pub const STORE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH2: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000805c
-        /// rtc configure register
-        pub const STORE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH3: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60008060
-        /// rtc configure register
-        pub const EXT_XTL_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// xtal 32k watch dog enable
-            XTAL32K_WDT_EN: u1,
-            /// xtal 32k watch dog clock force on
-            XTAL32K_WDT_CLK_FO: u1,
-            /// xtal 32k watch dog sw reset
-            XTAL32K_WDT_RESET: u1,
-            /// xtal 32k external xtal clock force on
-            XTAL32K_EXT_CLK_FO: u1,
-            /// xtal 32k switch to back up clock when xtal is dead
-            XTAL32K_AUTO_BACKUP: u1,
-            /// xtal 32k restart xtal when xtal is dead
-            XTAL32K_AUTO_RESTART: u1,
-            /// xtal 32k switch back xtal when xtal is restarted
-            XTAL32K_AUTO_RETURN: u1,
-            /// Xtal 32k xpd control by sw or fsm
-            XTAL32K_XPD_FORCE: u1,
-            /// apply an internal clock to help xtal 32k to start
-            ENCKINIT_XTAL_32K: u1,
-            /// 0: single-end buffer 1: differential buffer
-            DBUF_XTAL_32K: u1,
-            /// xtal_32k gm control
-            DGM_XTAL_32K: u3,
-            /// DRES_XTAL_32K
-            DRES_XTAL_32K: u3,
-            /// XPD_XTAL_32K
-            XPD_XTAL_32K: u1,
-            /// DAC_XTAL_32K
-            DAC_XTAL_32K: u3,
-            /// state of 32k_wdt
-            RTC_WDT_STATE: u3,
-            /// XTAL_32K sel. 0: external XTAL_32K
-            RTC_XTAL32K_GPIO_SEL: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// 0: power down XTAL at high level
-            XTL_EXT_CTR_LV: u1,
-            /// enable gpio configure xtal power on
-            XTL_EXT_CTR_EN: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60008064
-        /// rtc configure register
-        pub const EXT_WAKEUP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// enable filter for gpio wakeup event
-            GPIO_WAKEUP_FILTER: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60008068
-        /// rtc configure register
-        pub const SLP_REJECT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// sleep reject enable
-            RTC_SLEEP_REJECT_ENA: u18,
-            /// enable reject for light sleep
-            LIGHT_SLP_REJECT_EN: u1,
-            /// enable reject for deep sleep
-            DEEP_SLP_REJECT_EN: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6000806c
-        /// rtc configure register
-        pub const CPU_PERIOD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// CPU sel option
-            RTC_CPUSEL_CONF: u1,
-            /// CPU clk sel option
-            RTC_CPUPERIOD_SEL: u2,
-        }), base_address + 0x6c);
-
-        /// address: 0x60008070
-        /// rtc configure register
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// efuse_clk_force_gating
-            EFUSE_CLK_FORCE_GATING: u1,
-            /// efuse_clk_force_nogating
-            EFUSE_CLK_FORCE_NOGATING: u1,
-            /// used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
-            CK8M_DIV_SEL_VLD: u1,
-            /// CK8M_D256_OUT divider. 00: div128
-            CK8M_DIV: u2,
-            /// disable CK8M and CK8M_D256_OUT
-            ENB_CK8M: u1,
-            /// 1: CK8M_D256_OUT is actually CK8M
-            ENB_CK8M_DIV: u1,
-            /// enable CK_XTAL_32K for digital core (no relationship with RTC core)
-            DIG_XTAL32K_EN: u1,
-            /// enable CK8M_D256_OUT for digital core (no relationship with RTC core)
-            DIG_CLK8M_D256_EN: u1,
-            /// enable CK8M for digital core (no relationship with RTC core)
-            DIG_CLK8M_EN: u1,
-            reserved1: u1,
-            /// divider = reg_ck8m_div_sel + 1
-            CK8M_DIV_SEL: u3,
-            /// XTAL force no gating during sleep
-            XTAL_FORCE_NOGATING: u1,
-            /// CK8M force no gating during sleep
-            CK8M_FORCE_NOGATING: u1,
-            /// CK8M_DFREQ
-            CK8M_DFREQ: u8,
-            /// CK8M force power down
-            CK8M_FORCE_PD: u1,
-            /// CK8M force power up
-            CK8M_FORCE_PU: u1,
-            /// force enable xtal clk gating
-            XTAL_GLOBAL_FORCE_GATING: u1,
-            /// force bypass xtal clk gating
-            XTAL_GLOBAL_FORCE_NOGATING: u1,
-            /// fast_clk_rtc sel. 0: XTAL div 4
-            FAST_CLK_RTC_SEL: u1,
-            /// slelect rtc slow clk
-            ANA_CLK_RTC_SEL: u2,
-        }), base_address + 0x70);
-
-        /// address: 0x60008074
-        /// rtc configure register
-        pub const SLOW_CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            /// used to sync div bus. clear vld before set reg_rtc_ana_clk_div
-            RTC_ANA_CLK_DIV_VLD: u1,
-            /// the clk divider num of RTC_CLK
-            RTC_ANA_CLK_DIV: u8,
-            /// flag rtc_slow_clk_next_edge
-            RTC_SLOW_CLK_NEXT_EDGE: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60008078
-        /// rtc configure register
-        pub const SDIO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer count to apply reg_sdio_dcap after sdio power on
-            SDIO_TIMER_TARGET: u8,
-            reserved0: u1,
-            /// Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
-            SDIO_DTHDRV: u2,
-            /// ability to prevent LDO from overshoot
-            SDIO_DCAP: u2,
-            /// add resistor from ldo output to ground. 0: no res
-            SDIO_INITI: u2,
-            /// 0 to set init[1:0]=0
-            SDIO_EN_INITI: u1,
-            /// tune current limit threshold when tieh = 0. About 800mA/(8+d)
-            SDIO_DCURLIM: u3,
-            /// select current limit mode
-            SDIO_MODECURLIM: u1,
-            /// enable current limit
-            SDIO_ENCURLIM: u1,
-            /// power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
-            SDIO_REG_PD_EN: u1,
-            /// 1: use SW option to control SDIO_REG
-            SDIO_FORCE: u1,
-            /// SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
-            SDIO_TIEH: u1,
-            /// read only register for REG1P8_READY
-            _1P8_READY: u1,
-            /// SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
-            DREFL_SDIO: u2,
-            /// SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
-            DREFM_SDIO: u2,
-            /// SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
-            DREFH_SDIO: u2,
-            XPD_SDIO: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000807c
-        /// rtc configure register
-        pub const BIAS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            DG_VDD_DRV_B_SLP: u8,
-            DG_VDD_DRV_B_SLP_EN: u1,
-            reserved0: u1,
-            /// bias buf when rtc in normal work state
-            BIAS_BUF_IDLE: u1,
-            /// bias buf when rtc in wakeup state
-            BIAS_BUF_WAKE: u1,
-            /// bias buf when rtc in sleep state
-            BIAS_BUF_DEEP_SLP: u1,
-            /// bias buf when rtc in monitor state
-            BIAS_BUF_MONITOR: u1,
-            /// xpd cur when rtc in sleep_state
-            PD_CUR_DEEP_SLP: u1,
-            /// xpd cur when rtc in monitor state
-            PD_CUR_MONITOR: u1,
-            /// bias_sleep when rtc in sleep_state
-            BIAS_SLEEP_DEEP_SLP: u1,
-            /// bias_sleep when rtc in monitor state
-            BIAS_SLEEP_MONITOR: u1,
-            /// DBG_ATTEN when rtc in sleep state
-            DBG_ATTEN_DEEP_SLP: u4,
-            /// DBG_ATTEN when rtc in monitor state
-            DBG_ATTEN_MONITOR: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60008080
-        /// rtc configure register
-        pub const RTC_CNTL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// software enable digital regulator cali
-            DIG_REG_CAL_EN: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// SCK_DCAP
-            SCK_DCAP: u8,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            /// RTC_DBOOST force power down
-            DBOOST_FORCE_PD: u1,
-            /// RTC_DBOOST force power up
-            DBOOST_FORCE_PU: u1,
-            /// RTC_REG force power down (for RTC_REG power down means decrease the voltage to
-            /// 0.8v or lower )
-            REGULATOR_FORCE_PD: u1,
-            /// RTC_REG force power up
-            REGULATOR_FORCE_PU: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60008084
-        /// rtc configure register
-        pub const PWC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            /// rtc pad force hold
-            RTC_PAD_FORCE_HOLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x60008088
-        /// rtc configure register
-        pub const DIG_PWC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// vdd_spi drv's software value
-            VDD_SPI_PWR_DRV: u2,
-            /// vdd_spi drv use software value
-            VDD_SPI_PWR_FORCE: u1,
-            /// memories in digital core force PD in sleep
-            LSLP_MEM_FORCE_PD: u1,
-            /// memories in digital core force PU in sleep
-            LSLP_MEM_FORCE_PU: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// bt force power down
-            BT_FORCE_PD: u1,
-            /// bt force power up
-            BT_FORCE_PU: u1,
-            /// digital peri force power down
-            DG_PERI_FORCE_PD: u1,
-            /// digital peri force power up
-            DG_PERI_FORCE_PU: u1,
-            /// fastmemory retention mode in sleep
-            RTC_FASTMEM_FORCE_LPD: u1,
-            /// fastmemory donlt entry retention mode in sleep
-            RTC_FASTMEM_FORCE_LPU: u1,
-            /// wifi force power down
-            WIFI_FORCE_PD: u1,
-            /// wifi force power up
-            WIFI_FORCE_PU: u1,
-            /// digital core force power down
-            DG_WRAP_FORCE_PD: u1,
-            /// digital core force power up
-            DG_WRAP_FORCE_PU: u1,
-            /// cpu core force power down
-            CPU_TOP_FORCE_PD: u1,
-            /// cpu force power up
-            CPU_TOP_FORCE_PU: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable power down bt in sleep
-            BT_PD_EN: u1,
-            /// enable power down digital peri in sleep
-            DG_PERI_PD_EN: u1,
-            /// enable power down cpu in sleep
-            CPU_TOP_PD_EN: u1,
-            /// enable power down wifi in sleep
-            WIFI_PD_EN: u1,
-            /// enable power down digital wrap in sleep
-            DG_WRAP_PD_EN: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6000808c
-        /// rtc configure register
-        pub const DIG_ISO = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// DIG_ISO force off
-            FORCE_OFF: u1,
-            /// DIG_ISO force on
-            FORCE_ON: u1,
-            /// read only register to indicate digital pad auto-hold status
-            DG_PAD_AUTOHOLD: u1,
-            /// wtite only register to clear digital pad auto-hold
-            CLR_DG_PAD_AUTOHOLD: u1,
-            /// digital pad enable auto-hold
-            DG_PAD_AUTOHOLD_EN: u1,
-            /// digital pad force no ISO
-            DG_PAD_FORCE_NOISO: u1,
-            /// digital pad force ISO
-            DG_PAD_FORCE_ISO: u1,
-            /// digital pad force un-hold
-            DG_PAD_FORCE_UNHOLD: u1,
-            /// digital pad force hold
-            DG_PAD_FORCE_HOLD: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// bt force ISO
-            BT_FORCE_ISO: u1,
-            /// bt force no ISO
-            BT_FORCE_NOISO: u1,
-            /// Digital peri force ISO
-            DG_PERI_FORCE_ISO: u1,
-            /// digital peri force no ISO
-            DG_PERI_FORCE_NOISO: u1,
-            /// cpu force ISO
-            CPU_TOP_FORCE_ISO: u1,
-            /// cpu force no ISO
-            CPU_TOP_FORCE_NOISO: u1,
-            /// wifi force ISO
-            WIFI_FORCE_ISO: u1,
-            /// wifi force no ISO
-            WIFI_FORCE_NOISO: u1,
-            /// digital core force ISO
-            DG_WRAP_FORCE_ISO: u1,
-            /// digital core force no ISO
-            DG_WRAP_FORCE_NOISO: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x60008090
-        /// rtc configure register
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// chip reset siginal pulse width
-            WDT_CHIP_RESET_WIDTH: u8,
-            /// wdt reset whole chip enable
-            WDT_CHIP_RESET_EN: u1,
-            /// pause WDT in sleep
-            WDT_PAUSE_IN_SLP: u1,
-            /// enable WDT reset APP CPU
-            WDT_APPCPU_RESET_EN: u1,
-            /// enable WDT reset PRO CPU
-            WDT_PROCPU_RESET_EN: u1,
-            /// enable WDT in flash boot
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// system reset counter length
-            WDT_SYS_RESET_LENGTH: u3,
-            /// CPU reset counter length
-            WDT_CPU_RESET_LENGTH: u3,
-            /// 1: interrupt stage en
-            WDT_STG3: u3,
-            /// 1: interrupt stage en
-            WDT_STG2: u3,
-            /// 1: interrupt stage en
-            WDT_STG1: u3,
-            /// 1: interrupt stage en
-            WDT_STG0: u3,
-            /// enable rtc wdt
-            WDT_EN: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60008094
-        /// rtc configure register
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage0
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60008098
-        /// rtc configure register
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage1
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6000809c
-        /// rtc configure register
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage2
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600080a0
-        /// rtc configure register
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage3
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600080a4
-        /// rtc configure register
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// sw feed rtc wdt
-            RTC_WDT_FEED: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600080a8
-        /// rtc configure register
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the key of rtc wdt
-            WDT_WKEY: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600080ac
-        /// rtc configure register
-        pub const SWD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// swd reset flag
-            SWD_RESET_FLAG: u1,
-            /// swd interrupt for feeding
-            SWD_FEED_INT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// Bypass swd rst
-            SWD_BYPASS_RST: u1,
-            /// adjust signal width send to swd
-            SWD_SIGNAL_WIDTH: u10,
-            /// reset swd reset flag
-            SWD_RST_FLAG_CLR: u1,
-            /// Sw feed swd
-            SWD_FEED: u1,
-            /// disabel SWD
-            SWD_DISABLE: u1,
-            /// automatically feed swd when int comes
-            SWD_AUTO_FEED_EN: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600080b0
-        /// rtc configure register
-        pub const SWD_WPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the key of super wdt
-            SWD_WKEY: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600080b4
-        /// rtc configure register
-        pub const SW_CPU_STALL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// {reg_sw_stall_appcpu_c1[5:0]
-            SW_STALL_APPCPU_C1: u6,
-            /// stall cpu by software
-            SW_STALL_PROCPU_C1: u6,
-        }), base_address + 0xb4);
-
-        /// address: 0x600080b8
-        /// rtc configure register
-        pub const STORE4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH4: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600080bc
-        /// rtc configure register
-        pub const STORE5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH5: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600080c0
-        /// rtc configure register
-        pub const STORE6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH6: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600080c4
-        /// rtc configure register
-        pub const STORE7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH7: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600080c8
-        /// rtc configure register
-        pub const LOW_POWER_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rom0 power down
-            XPD_ROM0: u1,
-            reserved0: u1,
-            /// External DCDC power down
-            XPD_DIG_DCDC: u1,
-            /// rtc peripheral iso
-            RTC_PERI_ISO: u1,
-            /// rtc peripheral power down
-            XPD_RTC_PERI: u1,
-            /// wifi iso
-            WIFI_ISO: u1,
-            /// wifi wrap power down
-            XPD_WIFI: u1,
-            /// digital wrap iso
-            DIG_ISO: u1,
-            /// digital wrap power down
-            XPD_DIG: u1,
-            /// touch should start to work
-            RTC_TOUCH_STATE_START: u1,
-            /// touch is about to working. Switch rtc main state
-            RTC_TOUCH_STATE_SWITCH: u1,
-            /// touch is in sleep state
-            RTC_TOUCH_STATE_SLP: u1,
-            /// touch is done
-            RTC_TOUCH_STATE_DONE: u1,
-            /// ulp/cocpu should start to work
-            RTC_COCPU_STATE_START: u1,
-            /// ulp/cocpu is about to working. Switch rtc main state
-            RTC_COCPU_STATE_SWITCH: u1,
-            /// ulp/cocpu is in sleep state
-            RTC_COCPU_STATE_SLP: u1,
-            /// ulp/cocpu is done
-            RTC_COCPU_STATE_DONE: u1,
-            /// no use any more
-            RTC_MAIN_STATE_XTAL_ISO: u1,
-            /// rtc main state machine is in states that pll should be running
-            RTC_MAIN_STATE_PLL_ON: u1,
-            /// rtc is ready to receive wake up trigger from wake up source
-            RTC_RDY_FOR_WAKEUP: u1,
-            /// rtc main state machine has been waited for some cycles
-            RTC_MAIN_STATE_WAIT_END: u1,
-            /// rtc main state machine is in the states of wakeup process
-            RTC_IN_WAKEUP_STATE: u1,
-            /// rtc main state machine is in the states of low power
-            RTC_IN_LOW_POWER_STATE: u1,
-            /// rtc main state machine is in wait 8m state
-            RTC_MAIN_STATE_IN_WAIT_8M: u1,
-            /// rtc main state machine is in wait pll state
-            RTC_MAIN_STATE_IN_WAIT_PLL: u1,
-            /// rtc main state machine is in wait xtal state
-            RTC_MAIN_STATE_IN_WAIT_XTL: u1,
-            /// rtc main state machine is in sleep state
-            RTC_MAIN_STATE_IN_SLP: u1,
-            /// rtc main state machine is in idle state
-            RTC_MAIN_STATE_IN_IDLE: u1,
-            /// rtc main state machine status
-            RTC_MAIN_STATE: u4,
-        }), base_address + 0xc8);
-
-        /// address: 0x600080cc
-        /// rtc configure register
-        pub const DIAG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC_LOW_POWER_DIAG1: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600080d0
-        /// rtc configure register
-        pub const PAD_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold configure of rtc gpio0
-            RTC_GPIO_PIN0_HOLD: u1,
-            /// the hold configure of rtc gpio1
-            RTC_GPIO_PIN1_HOLD: u1,
-            /// the hold configure of rtc gpio2
-            RTC_GPIO_PIN2_HOLD: u1,
-            /// the hold configure of rtc gpio3
-            RTC_GPIO_PIN3_HOLD: u1,
-            /// the hold configure of rtc gpio4
-            RTC_GPIO_PIN4_HOLD: u1,
-            /// the hold configure of rtc gpio5
-            RTC_GPIO_PIN5_HOLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600080d4
-        /// rtc configure register
-        pub const DIG_PAD_HOLD = @intToPtr(*volatile u32, base_address + 0xd4);
-
-        /// address: 0x600080d8
-        /// rtc configure register
-        pub const BROWN_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// brown out interrupt wait cycles
-            INT_WAIT: u10,
-            /// enable close flash when brown out happens
-            CLOSE_FLASH_ENA: u1,
-            /// enable power down RF when brown out happens
-            PD_RF_ENA: u1,
-            /// brown out reset wait cycles
-            RST_WAIT: u10,
-            /// enable brown out reset
-            RST_ENA: u1,
-            /// 1: 4-pos reset
-            RST_SEL: u1,
-            /// brown_out origin reset enable
-            ANA_RST_EN: u1,
-            /// clear brown out counter
-            CNT_CLR: u1,
-            /// enable brown out
-            ENA: u1,
-            /// the flag of brown det from analog
-            DET: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600080dc
-        /// rtc configure register
-        pub const TIME_LOW1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer low 32 bits
-            RTC_TIMER_VALUE1_LOW: u32,
-        }), base_address + 0xdc);
-
-        /// address: 0x600080e0
-        /// rtc configure register
-        pub const TIME_HIGH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer high 16 bits
-            RTC_TIMER_VALUE1_HIGH: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600080e4
-        /// rtc configure register
-        pub const XTAL32K_CLK_FACTOR = @intToPtr(*volatile u32, base_address + 0xe4);
-
-        /// address: 0x600080e8
-        /// rtc configure register
-        pub const XTAL32K_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cycles to wait to return noral xtal 32k
-            XTAL32K_RETURN_WAIT: u4,
-            /// cycles to wait to repower on xtal 32k
-            XTAL32K_RESTART_WAIT: u16,
-            /// If no clock detected for this amount of time
-            XTAL32K_WDT_TIMEOUT: u8,
-            /// if restarted xtal32k period is smaller than this
-            XTAL32K_STABLE_THRES: u4,
-        }), base_address + 0xe8);
-
-        /// address: 0x600080ec
-        /// rtc configure register
-        pub const USB_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// disable io_mux reset
-            IO_MUX_RESET_DISABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0xec);
-
-        /// address: 0x600080f0
-        /// RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
-        pub const SLP_REJECT_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep reject cause
-            REJECT_CAUSE: u18,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x600080f4
-        /// rtc configure register
-        pub const OPTION1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// force chip entry download mode
-            FORCE_DOWNLOAD_BOOT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600080f8
-        /// RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
-        pub const SLP_WAKEUP_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup cause
-            WAKEUP_CAUSE: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600080fc
-        /// rtc configure register
-        pub const ULP_CP_TIMER_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// sleep cycles for ULP-coprocessor timer
-            ULP_CP_TIMER_SLP_CYCLE: u24,
-        }), base_address + 0xfc);
-
-        /// address: 0x60008100
-        /// rtc configure register
-        pub const INT_ENA_RTC_W1TS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable sleep wakeup interrupt
-            SLP_WAKEUP_INT_ENA_W1TS: u1,
-            /// enable sleep reject interrupt
-            SLP_REJECT_INT_ENA_W1TS: u1,
-            reserved0: u1,
-            /// enable RTC WDT interrupt
-            RTC_WDT_INT_ENA_W1TS: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// enable brown out interrupt
-            RTC_BROWN_OUT_INT_ENA_W1TS: u1,
-            /// enable RTC main timer interrupt
-            RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable super watch dog interrupt
-            RTC_SWD_INT_ENA_W1TS: u1,
-            /// enable xtal32k_dead interrupt
-            RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// enbale gitch det interrupt
-            RTC_GLITCH_DET_INT_ENA_W1TS: u1,
-            /// enbale bbpll cal interrupt
-            RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x60008104
-        /// rtc configure register
-        pub const INT_ENA_RTC_W1TC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clear sleep wakeup interrupt enable
-            SLP_WAKEUP_INT_ENA_W1TC: u1,
-            /// clear sleep reject interrupt enable
-            SLP_REJECT_INT_ENA_W1TC: u1,
-            reserved0: u1,
-            /// clear RTC WDT interrupt enable
-            RTC_WDT_INT_ENA_W1TC: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// clear brown out interrupt enable
-            RTC_BROWN_OUT_INT_ENA_W1TC: u1,
-            /// Clear RTC main timer interrupt enable
-            RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// clear super watch dog interrupt enable
-            RTC_SWD_INT_ENA_W1TC: u1,
-            /// clear xtal32k_dead interrupt enable
-            RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// clear gitch det interrupt enable
-            RTC_GLITCH_DET_INT_ENA_W1TC: u1,
-            /// clear bbpll cal interrupt enable
-            RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x104);
-
-        /// address: 0x60008108
-        /// rtc configure register
-        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// Retention clk sel
-            RETENTION_CLK_SEL: u1,
-            /// Retention done wait time
-            RETENTION_DONE_WAIT: u3,
-            /// Retention clkoff wait time
-            RETENTION_CLKOFF_WAIT: u4,
-            /// enable cpu retention when light sleep
-            RETENTION_EN: u1,
-            /// wait cycles for rention operation
-            RETENTION_WAIT: u5,
-        }), base_address + 0x108);
-
-        /// address: 0x6000810c
-        /// rtc configure register
-        pub const FIB_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// select use analog fib signal
-            RTC_FIB_SEL: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x10c);
-
-        /// address: 0x60008110
-        /// rtc configure register
-        pub const GPIO_WAKEUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc gpio wakeup flag
-            RTC_GPIO_WAKEUP_STATUS: u6,
-            /// clear rtc gpio wakeup flag
-            RTC_GPIO_WAKEUP_STATUS_CLR: u1,
-            /// enable rtc io clk gate
-            RTC_GPIO_PIN_CLK_GATE: u1,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN5_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN4_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN3_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN2_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN1_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN0_INT_TYPE: u3,
-            /// enable wakeup from rtc gpio5
-            RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio4
-            RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio3
-            RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio2
-            RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio1
-            RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio0
-            RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
-        }), base_address + 0x110);
-
-        /// address: 0x60008114
-        /// rtc configure register
-        pub const DBG_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// use for debug
-            RTC_DEBUG_12M_NO_GATING: u1,
-            /// use for debug
-            RTC_DEBUG_BIT_SEL: u5,
-            /// use for debug
-            RTC_DEBUG_SEL0: u5,
-            /// use for debug
-            RTC_DEBUG_SEL1: u5,
-            /// use for debug
-            RTC_DEBUG_SEL2: u5,
-            /// use for debug
-            RTC_DEBUG_SEL3: u5,
-            /// use for debug
-            RTC_DEBUG_SEL4: u5,
-        }), base_address + 0x114);
-
-        /// address: 0x60008118
-        /// rtc configure register
-        pub const DBG_MAP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// use for debug
-            RTC_GPIO_PIN5_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN4_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN3_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN2_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN1_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN0_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN5_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN4_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN3_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN2_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN1_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN0_FUN_SEL: u4,
-        }), base_address + 0x118);
-
-        /// address: 0x6000811c
-        /// rtc configure register
-        pub const SENSOR_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// reg_sar2_pwdet_cct
-            SAR2_PWDET_CCT: u3,
-            /// force power up SAR
-            FORCE_XPD_SAR: u2,
-        }), base_address + 0x11c);
-
-        /// address: 0x60008120
-        /// rtc configure register
-        pub const DBG_SAR_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// use for debug
-            SAR_DEBUG_SEL: u5,
-        }), base_address + 0x120);
-
-        /// address: 0x60008124
-        /// rtc configure register
-        pub const PG_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// power glitch desense
-            POWER_GLITCH_DSENSE: u2,
-            /// force disable power glitch
-            POWER_GLITCH_FORCE_PD: u1,
-            /// force enable power glitch
-            POWER_GLITCH_FORCE_PU: u1,
-            /// use efuse value control power glitch enable
-            POWER_GLITCH_EFUSE_SEL: u1,
-            /// enable power glitch
-            POWER_GLITCH_EN: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600081fc
-        /// rtc configure register
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// verision
-            RTC_CNTL_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1fc);
-    };
-
-    /// Sensitive
-    pub const SENSITIVE = struct {
-        pub const base_address = 0x600c1000;
-
-        /// address: 0x600c1000
-        /// SENSITIVE_ROM_TABLE_LOCK_REG
-        pub const ROM_TABLE_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
-
-        /// address: 0x600c1004
-        /// SENSITIVE_ROM_TABLE_REG
-        pub const ROM_TABLE = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x600c1008
-        /// SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
-        pub const PRIVILEGE_MODE_SEL_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8);
-
-        /// address: 0x600c100c
-        /// SENSITIVE_PRIVILEGE_MODE_SEL_REG
-        pub const PRIVILEGE_MODE_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc);
-
-        /// address: 0x600c1010
-        /// SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
-        pub const APB_PERIPHERAL_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// apb_peripheral_access_lock
-            APB_PERIPHERAL_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x600c1014
-        /// SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
-        pub const APB_PERIPHERAL_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// apb_peripheral_access_split_burst
-            APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x600c1018
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
-        pub const INTERNAL_SRAM_USAGE_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_lock
-            INTERNAL_SRAM_USAGE_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x600c101c
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
-        pub const INTERNAL_SRAM_USAGE_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_cpu_cache
-            INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
-            /// internal_sram_usage_cpu_sram
-            INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c1020
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
-        pub const INTERNAL_SRAM_USAGE_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_mac_dump_sram
-            INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
-            /// internal_sram_alloc_mac_dump
-            INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x600c1024
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
-        pub const INTERNAL_SRAM_USAGE_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_log_sram
-            INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x600c1028
-        /// SENSITIVE_CACHE_TAG_ACCESS_0_REG
-        pub const CACHE_TAG_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cache_tag_access_lock
-            CACHE_TAG_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x600c102c
-        /// SENSITIVE_CACHE_TAG_ACCESS_1_REG
-        pub const CACHE_TAG_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pro_i_tag_rd_acs
-            PRO_I_TAG_RD_ACS: u1,
-            /// pro_i_tag_wr_acs
-            PRO_I_TAG_WR_ACS: u1,
-            /// pro_d_tag_rd_acs
-            PRO_D_TAG_RD_ACS: u1,
-            /// pro_d_tag_wr_acs
-            PRO_D_TAG_WR_ACS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x600c1030
-        /// SENSITIVE_CACHE_MMU_ACCESS_0_REG
-        pub const CACHE_MMU_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cache_mmu_access_lock
-            CACHE_MMU_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x600c1034
-        /// SENSITIVE_CACHE_MMU_ACCESS_1_REG
-        pub const CACHE_MMU_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pro_mmu_rd_acs
-            PRO_MMU_RD_ACS: u1,
-            /// pro_mmu_wr_acs
-            PRO_MMU_WR_ACS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x600c1038
-        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_spi2_pms_constrain_lock
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x600c103c
-        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x600c1040
-        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_uchi0_pms_constrain_lock
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c1044
-        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600c1048
-        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_i2s0_pms_constrain_lock
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x600c104c
-        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x600c1050
-        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_mac_pms_constrain_lock
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600c1054
-        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600c1058
-        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_backup_pms_constrain_lock
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600c105c
-        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x600c1060
-        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_lc_pms_constrain_lock
-            DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600c1064
-        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c1068
-        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_aes_pms_constrain_lock
-            DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600c106c
-        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600c1070
-        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_sha_pms_constrain_lock
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600c1074
-        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600c1078
-        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_adc_dac_pms_constrain_lock
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c107c
-        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c1080
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
-        pub const DMA_APBPERI_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_lock
-            DMA_APBPERI_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c1084
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
-        pub const DMA_APBPERI_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_clr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// dma_apbperi_pms_monitor_violate_en
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c1088
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
-        pub const DMA_APBPERI_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_intr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// dma_apbperi_pms_monitor_violate_status_world
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// dma_apbperi_pms_monitor_violate_status_addr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c108c
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
-        pub const DMA_APBPERI_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_status_wr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// dma_apbperi_pms_monitor_violate_status_byteen
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c1090
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_dram0_dma_split_line_constrain_lock
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c1094
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_dram0_dma_sram_category_0
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
-            /// core_x_iram0_dram0_dma_sram_category_1
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
-            /// core_x_iram0_dram0_dma_sram_category_2
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_dram0_dma_sram_splitaddr
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x600c1098
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_sram_line_0_category_0
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
-            /// core_x_iram0_sram_line_0_category_1
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
-            /// core_x_iram0_sram_line_0_category_2
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_sram_line_0_splitaddr
-            CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c109c
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_sram_line_1_category_0
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
-            /// core_x_iram0_sram_line_1_category_1
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
-            /// core_x_iram0_sram_line_1_category_2
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_sram_line_1_splitaddr
-            CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600c10a0
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_dma_sram_line_0_category_0
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
-            /// core_x_dram0_dma_sram_line_0_category_1
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
-            /// core_x_dram0_dma_sram_line_0_category_2
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_dma_sram_line_0_splitaddr
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600c10a4
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_dma_sram_line_1_category_0
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
-            /// core_x_dram0_dma_sram_line_1_category_1
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
-            /// core_x_dram0_dma_sram_line_1_category_2
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_dma_sram_line_1_splitaddr
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600c10a8
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_lock
-            CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600c10ac
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_1
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_2
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_3
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// core_x_iram0_pms_constrain_rom_world_1_pms
-            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600c10b0
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_1
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_2
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_3
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// core_x_iram0_pms_constrain_rom_world_0_pms
-            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600c10b4
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_lock
-            CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600c10b8
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_violate_clr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_iram0_pms_monitor_violate_en
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600c10bc
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_violate_intr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_iram0_pms_monitor_violate_status_wr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// core_0_iram0_pms_monitor_violate_status_loadstore
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
-            /// core_0_iram0_pms_monitor_violate_status_world
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// core_0_iram0_pms_monitor_violate_status_addr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600c10c0
-        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
-        pub const CORE_X_DRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_pms_constrain_lock
-            CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600c10c4
-        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
-        pub const CORE_X_DRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_0
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_1
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_2
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_3
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_0
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_1
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_2
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_3
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_pms_constrain_rom_world_0_pms
-            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
-            /// core_x_dram0_pms_constrain_rom_world_1_pms
-            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600c10c8
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_lock
-            CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600c10cc
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_clr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_dram0_pms_monitor_violate_en
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600c10d0
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_intr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_dram0_pms_monitor_violate_status_lock
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
-            /// core_0_dram0_pms_monitor_violate_status_world
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// core_0_dram0_pms_monitor_violate_status_addr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600c10d4
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_status_wr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// core_0_dram0_pms_monitor_violate_status_byteen
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600c10d8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_lock
-            CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600c10dc
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_uart
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
-            /// core_0_pif_pms_constrain_world_0_g0spi_1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
-            /// core_0_pif_pms_constrain_world_0_g0spi_0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
-            /// core_0_pif_pms_constrain_world_0_gpio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
-            /// core_0_pif_pms_constrain_world_0_fe2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
-            /// core_0_pif_pms_constrain_world_0_fe
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
-            /// core_0_pif_pms_constrain_world_0_timer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
-            /// core_0_pif_pms_constrain_world_0_rtc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
-            /// core_0_pif_pms_constrain_world_0_io_mux
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
-            /// core_0_pif_pms_constrain_world_0_wdg
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_misc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
-            /// core_0_pif_pms_constrain_world_0_i2c
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_0_uart1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
-        }), base_address + 0xdc);
-
-        /// address: 0x600c10e0
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_bt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_i2c_ext0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
-            /// core_0_pif_pms_constrain_world_0_uhci0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_rmt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_0_ledc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// core_0_pif_pms_constrain_world_0_bb
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_0_timergroup
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
-            /// core_0_pif_pms_constrain_world_0_timergroup1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
-            /// core_0_pif_pms_constrain_world_0_systimer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
-        }), base_address + 0xe0);
-
-        /// address: 0x600c10e4
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_spi_2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_apb_ctrl
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_0_can
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_0_i2s1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_0_rwbt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// core_0_pif_pms_constrain_world_0_wifimac
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
-            /// core_0_pif_pms_constrain_world_0_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x600c10e8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_usb_wrap
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
-            /// core_0_pif_pms_constrain_world_0_crypto_peri
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
-            /// core_0_pif_pms_constrain_world_0_crypto_dma
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
-            /// core_0_pif_pms_constrain_world_0_apb_adc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_bt_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
-            /// core_0_pif_pms_constrain_world_0_usb_device
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
-            /// core_0_pif_pms_constrain_world_0_system
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
-            /// core_0_pif_pms_constrain_world_0_sensitive
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
-            /// core_0_pif_pms_constrain_world_0_interrupt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
-            /// core_0_pif_pms_constrain_world_0_dma_copy
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
-            /// core_0_pif_pms_constrain_world_0_cache_config
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
-            /// core_0_pif_pms_constrain_world_0_ad
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
-            /// core_0_pif_pms_constrain_world_0_dio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
-            /// core_0_pif_pms_constrain_world_0_world_controller
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
-        }), base_address + 0xe8);
-
-        /// address: 0x600c10ec
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_uart
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
-            /// core_0_pif_pms_constrain_world_1_g0spi_1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
-            /// core_0_pif_pms_constrain_world_1_g0spi_0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
-            /// core_0_pif_pms_constrain_world_1_gpio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
-            /// core_0_pif_pms_constrain_world_1_fe2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
-            /// core_0_pif_pms_constrain_world_1_fe
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
-            /// core_0_pif_pms_constrain_world_1_timer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
-            /// core_0_pif_pms_constrain_world_1_rtc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
-            /// core_0_pif_pms_constrain_world_1_io_mux
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
-            /// core_0_pif_pms_constrain_world_1_wdg
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_misc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
-            /// core_0_pif_pms_constrain_world_1_i2c
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_1_uart1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
-        }), base_address + 0xec);
-
-        /// address: 0x600c10f0
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_bt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_i2c_ext0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
-            /// core_0_pif_pms_constrain_world_1_uhci0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_rmt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_1_ledc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// core_0_pif_pms_constrain_world_1_bb
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_1_timergroup
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
-            /// core_0_pif_pms_constrain_world_1_timergroup1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
-            /// core_0_pif_pms_constrain_world_1_systimer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
-        }), base_address + 0xf0);
-
-        /// address: 0x600c10f4
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_spi_2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_apb_ctrl
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_1_can
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_1_i2s1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_1_rwbt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// core_0_pif_pms_constrain_world_1_wifimac
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
-            /// core_0_pif_pms_constrain_world_1_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600c10f8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_usb_wrap
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
-            /// core_0_pif_pms_constrain_world_1_crypto_peri
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
-            /// core_0_pif_pms_constrain_world_1_crypto_dma
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
-            /// core_0_pif_pms_constrain_world_1_apb_adc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_bt_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
-            /// core_0_pif_pms_constrain_world_1_usb_device
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
-            /// core_0_pif_pms_constrain_world_1_system
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
-            /// core_0_pif_pms_constrain_world_1_sensitive
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
-            /// core_0_pif_pms_constrain_world_1_interrupt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
-            /// core_0_pif_pms_constrain_world_1_dma_copy
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
-            /// core_0_pif_pms_constrain_world_1_cache_config
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
-            /// core_0_pif_pms_constrain_world_1_ad
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
-            /// core_0_pif_pms_constrain_world_1_dio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
-            /// core_0_pif_pms_constrain_world_1_world_controller
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c10fc
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
-            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c1100
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_rtcfast_world_0_l
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_0_h
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_1_l
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_1_h
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c1104
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
-        pub const REGION_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_lock
-            REGION_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x104);
-
-        /// address: 0x600c1108
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
-        pub const REGION_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_world_0_area_0
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
-            /// region_pms_constrain_world_0_area_1
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
-            /// region_pms_constrain_world_0_area_2
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
-            /// region_pms_constrain_world_0_area_3
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
-            /// region_pms_constrain_world_0_area_4
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
-            /// region_pms_constrain_world_0_area_5
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
-            /// region_pms_constrain_world_0_area_6
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x108);
-
-        /// address: 0x600c110c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
-        pub const REGION_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_world_1_area_0
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
-            /// region_pms_constrain_world_1_area_1
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
-            /// region_pms_constrain_world_1_area_2
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
-            /// region_pms_constrain_world_1_area_3
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
-            /// region_pms_constrain_world_1_area_4
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
-            /// region_pms_constrain_world_1_area_5
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
-            /// region_pms_constrain_world_1_area_6
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x10c);
-
-        /// address: 0x600c1110
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
-        pub const REGION_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_0
-            REGION_PMS_CONSTRAIN_ADDR_0: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x110);
-
-        /// address: 0x600c1114
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
-        pub const REGION_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_1
-            REGION_PMS_CONSTRAIN_ADDR_1: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x600c1118
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
-        pub const REGION_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_2
-            REGION_PMS_CONSTRAIN_ADDR_2: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x600c111c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
-        pub const REGION_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_3
-            REGION_PMS_CONSTRAIN_ADDR_3: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x11c);
-
-        /// address: 0x600c1120
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
-        pub const REGION_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_4
-            REGION_PMS_CONSTRAIN_ADDR_4: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x120);
-
-        /// address: 0x600c1124
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
-        pub const REGION_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_5
-            REGION_PMS_CONSTRAIN_ADDR_5: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600c1128
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
-        pub const REGION_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_6
-            REGION_PMS_CONSTRAIN_ADDR_6: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x128);
-
-        /// address: 0x600c112c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
-        pub const REGION_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_7
-            REGION_PMS_CONSTRAIN_ADDR_7: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x12c);
-
-        /// address: 0x600c1130
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
-        pub const CORE_0_PIF_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_lock
-            CORE_0_PIF_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x600c1134
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
-        pub const CORE_0_PIF_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_clr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_pif_pms_monitor_violate_en
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x600c1138
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
-        pub const CORE_0_PIF_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_intr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_pif_pms_monitor_violate_status_hport_0
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
-            /// core_0_pif_pms_monitor_violate_status_hsize
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-            /// core_0_pif_pms_monitor_violate_status_hwrite
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-            /// core_0_pif_pms_monitor_violate_status_hworld
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x600c113c
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
-        pub const CORE_0_PIF_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_status_haddr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
-        }), base_address + 0x13c);
-
-        /// address: 0x600c1140
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
-        pub const CORE_0_PIF_PMS_MONITOR_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_clr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
-            /// core_0_pif_pms_monitor_nonword_violate_en
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x600c1144
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
-        pub const CORE_0_PIF_PMS_MONITOR_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_intr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
-            /// core_0_pif_pms_monitor_nonword_violate_status_hsize
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
-            /// core_0_pif_pms_monitor_nonword_violate_status_hworld
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x600c1148
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
-        pub const CORE_0_PIF_PMS_MONITOR_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_status_haddr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
-        }), base_address + 0x148);
-
-        /// address: 0x600c114c
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_lock
-            BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x600c1150
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_uart
-            BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
-            /// backup_bus_pms_constrain_g0spi_1
-            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
-            /// backup_bus_pms_constrain_g0spi_0
-            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
-            /// backup_bus_pms_constrain_gpio
-            BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
-            /// backup_bus_pms_constrain_fe2
-            BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
-            /// backup_bus_pms_constrain_fe
-            BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
-            /// backup_bus_pms_constrain_timer
-            BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
-            /// backup_bus_pms_constrain_rtc
-            BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
-            /// backup_bus_pms_constrain_io_mux
-            BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
-            /// backup_bus_pms_constrain_wdg
-            BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_misc
-            BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
-            /// backup_bus_pms_constrain_i2c
-            BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// backup_bus_pms_constrain_uart1
-            BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
-        }), base_address + 0x150);
-
-        /// address: 0x600c1154
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_bt
-            BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_i2c_ext0
-            BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
-            /// backup_bus_pms_constrain_uhci0
-            BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_rmt
-            BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// backup_bus_pms_constrain_ledc
-            BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// backup_bus_pms_constrain_bb
-            BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// backup_bus_pms_constrain_timergroup
-            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
-            /// backup_bus_pms_constrain_timergroup1
-            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
-            /// backup_bus_pms_constrain_systimer
-            BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
-        }), base_address + 0x154);
-
-        /// address: 0x600c1158
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_spi_2
-            BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_apb_ctrl
-            BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// backup_bus_pms_constrain_can
-            BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// backup_bus_pms_constrain_i2s1
-            BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// backup_bus_pms_constrain_rwbt
-            BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// backup_bus_pms_constrain_wifimac
-            BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
-            /// backup_bus_pms_constrain_pwr
-            BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x600c115c
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_usb_wrap
-            BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
-            /// backup_bus_pms_constrain_crypto_peri
-            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
-            /// backup_bus_pms_constrain_crypto_dma
-            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
-            /// backup_bus_pms_constrain_apb_adc
-            BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_bt_pwr
-            BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
-            /// backup_bus_pms_constrain_usb_device
-            BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x600c1160
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
-        pub const BACKUP_BUS_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_lock
-            BACKUP_BUS_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x600c1164
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
-        pub const BACKUP_BUS_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_clr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// backup_bus_pms_monitor_violate_en
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x600c1168
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
-        pub const BACKUP_BUS_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_intr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// backup_bus_pms_monitor_violate_status_htrans
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
-            /// backup_bus_pms_monitor_violate_status_hsize
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-            /// backup_bus_pms_monitor_violate_status_hwrite
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x600c116c
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
-        pub const BACKUP_BUS_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_haddr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
-        }), base_address + 0x16c);
-
-        /// address: 0x600c1170
-        /// SENSITIVE_CLOCK_GATE_REG
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x600c1ffc
-        /// SENSITIVE_DATE_REG
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
-    };
-
-    /// SHA (Secure Hash Algorithm) Accelerator
-    pub const SHA = struct {
-        pub const base_address = 0x6003b000;
-
-        /// address: 0x6003b000
-        /// Initial configuration register.
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x0);
-
-        /// address: 0x6003b004
-        /// SHA 512/t configuration register 0.
-        pub const T_STRING = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x6003b008
-        /// SHA 512/t configuration register 1.
-        pub const T_LENGTH = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8);
-
-        /// address: 0x6003b00c
-        /// DMA configuration register 0.
-        pub const DMA_BLOCK_NUM = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xc);
-
-        /// address: 0x6003b010
-        /// Typical SHA configuration register 0.
-        pub const START = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x10);
-
-        /// address: 0x6003b014
-        /// Typical SHA configuration register 1.
-        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x14);
-
-        /// address: 0x6003b018
-        /// Busy register.
-        pub const BUSY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sha busy state. 1'b0: idle. 1'b1: busy.
-            STATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6003b01c
-        /// DMA configuration register 1.
-        pub const DMA_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c);
-
-        /// address: 0x6003b020
-        /// DMA configuration register 2.
-        pub const DMA_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
-
-        /// address: 0x6003b024
-        /// Interrupt clear register.
-        pub const CLEAR_IRQ = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear sha interrupt.
-            CLEAR_INTERRUPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6003b028
-        /// Interrupt enable register.
-        pub const IRQ_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
-            INTERRUPT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6003b02c
-        /// Date register.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c);
-
-        /// address: 0x6003b040
-        /// Sha H memory which contains intermediate hash or finial hash.
-        pub const H_MEM = @intToPtr(*volatile [64]u8, base_address + 0x40);
-
-        /// address: 0x6003b080
-        /// Sha M memory which contains message.
-        pub const M_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI0 = struct {
-        pub const base_address = 0x60003000;
-
-        /// address: 0x60003008
-        /// SPI0 control register.
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller.
-            FDUMMY_OUT: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable
-            FCMD_QUAD: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
-            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-            FASTRD_MODE: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            FREAD_DUAL: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low
-            D_POL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            FREAD_QUAD: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
-            WP: u1,
-            reserved13: u1,
-            /// In the read operations address phase and read-data phase apply 2 signals. 1:
-            /// enable 0: disable.
-            FREAD_DIO: u1,
-            /// In the read operations address phase and read-data phase apply 4 signals. 1:
-            /// enable 0: disable.
-            FREAD_QIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000300c
-        /// SPI0 control1 register.
-        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on.
-            CLK_MODE: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            /// SPI0 RX FIFO reset signal.
-            RXFIFO_RST: u1,
-            padding0: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60003010
-        /// SPI0 control2 register.
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// (cycles-1) of prepare phase by spi clock this bits are combined with
-            /// spi_mem_cs_setup bit.
-            CS_SETUP_TIME: u5,
-            /// Spi cs signal is delayed to inactive by spi clock this bits are combined with
-            /// spi_mem_cs_hold bit.
-            CS_HOLD_TIME: u5,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// These bits are used to set the minimum CS high time tSHSL between SPI burst
-            /// transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
-            /// core clock cycles.
-            CS_HOLD_DELAY: u6,
-            /// The FSM will be reset.
-            SYNC_RESET: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60003014
-        /// SPI clock division control register.
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_mem_clkcnt_N.
-            CLKCNT_L: u8,
-            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-            CLKCNT_H: u8,
-            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-            /// system/(spi_mem_clkcnt_N+1)
-            CLKCNT_N: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// Set this bit in 1-division mode.
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60003018
-        /// SPI0 user register.
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// spi cs keep low when spi is in done phase. 1: enable 0: disable.
-            CS_HOLD: u1,
-            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
-            CS_SETUP: u1,
-            reserved6: u1,
-            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
-            /// mode.
-            CK_OUT_EDGE: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// spi clock is disable in dummy phase when the bit is enable.
-            USR_DUMMY_IDLE: u1,
-            reserved23: u1,
-            reserved24: u1,
-            /// This bit enable the dummy phase of an operation.
-            USR_DUMMY: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000301c
-        /// SPI0 user1 register.
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1).
-            USR_DUMMY_CYCLELEN: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            USR_ADDR_BITLEN: u6,
-        }), base_address + 0x1c);
-
-        /// address: 0x60003020
-        /// SPI0 user2 register.
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1)
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x20);
-
-        /// address: 0x6000302c
-        /// SPI0 read control register.
-        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
-            /// bit.
-            WB_MODE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60003034
-        /// SPI0 misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to indicate the spi0_mst_st controlled transmitting is done.
-            TRANS_END: u1,
-            /// The bit is used to enable the interrupt of spi0_mst_st controlled transmitting
-            /// is done.
-            TRANS_END_INT_ENA: u1,
-            /// The bit is used to indicate the spi0_slv_st controlled transmitting is done.
-            CSPI_ST_TRANS_END: u1,
-            /// The bit is used to enable the interrupt of spi0_slv_st controlled transmitting
-            /// is done.
-            CSPI_ST_TRANS_END_INT_ENA: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set.
-            CS_KEEP_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x6000303c
-        /// SPI0 bit mode control register.
-        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For SPI0, Cache access enable, 1: enable, 0:disable.
-            CACHE_REQ_EN: u1,
-            /// For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
-            CACHE_USR_ADDR_4BYTE: u1,
-            /// For SPI0, cache read flash for user define command, 1: enable, 0:disable.
-            CACHE_FLASH_USR_CMD: u1,
-            /// For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FDIN_DUAL: u1,
-            /// For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FDOUT_DUAL: u1,
-            /// For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
-            /// the same with spi_mem_fread_dio.
-            FADDR_DUAL: u1,
-            /// For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FDIN_QUAD: u1,
-            /// For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FDOUT_QUAD: u1,
-            /// For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
-            /// the same with spi_mem_fread_qio.
-            FADDR_QUAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60003054
-        /// SPI0 FSM status register
-        pub const FSM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
-            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
-            /// state, 6:write data state, 7: done state, 8: read data end state.
-            CSPI_ST: u4,
-            /// The current status of SPI0 master FSM: spi0_mst_st. 0: idle state,
-            /// 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4:
-            /// wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
-            EM_ST: u3,
-            /// The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
-            CSPI_LOCK_DELAY_TIME: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600030a8
-        /// SPI0 timing calibration register
-        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable timing adjust clock for all reading operations.
-            TIMING_CLK_ENA: u1,
-            /// The bit is used to enable timing auto-calibration for all reading operations.
-            TIMING_CALI: u1,
-            /// add extra dummy spi clock cycle length for spi clock calibration.
-            EXTRA_DUMMY_CYCLELEN: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600030ac
-        /// SPI0 input delay mode control register
-        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN0_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN1_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN2_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN3_MODE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600030b0
-        /// SPI0 input delay number control register
-        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN0_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN1_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN2_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN3_NUM: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600030b4
-        /// SPI0 output delay mode control register
-        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT0_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT1_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT2_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT3_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600030dc
-        /// SPI0 clk_gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Register clock gate enable signal. 1: Enable. 0: Disable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600030e0
-        /// SPI0 module clock select register
-        pub const CORE_CLK_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the digital system clock selects PLL clock and the frequency of PLL clock
-            /// is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is
-            /// 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk)
-            /// 160MHz. 3: Not used. When the digital system clock selects PLL clock and the
-            /// frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1
-            /// module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1
-            /// module clock (clk) 160MHz. 3: Not used.
-            SPI01_CLK_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600033fc
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI1 = struct {
-        pub const base_address = 0x60002000;
-
-        /// address: 0x60002000
-        /// SPI1 memory command register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The current status of SPI1 master FSM.
-            SPI1_MST_ST: u4,
-            /// The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
-            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
-            /// state, 6:write data state, 7: done state, 8: read data end state.
-            MSPI_ST: u4,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In user mode, it is set to indicate that program/erase operation will be
-            /// triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared
-            /// once the operation done.1: enable 0: disable.
-            FLASH_PE: u1,
-            /// User define command enable. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            USR: u1,
-            /// Drive Flash into high performance mode. The bit will be cleared once the
-            /// operation done.1: enable 0: disable.
-            FLASH_HPM: u1,
-            /// This bit combined with reg_resandres bit releases Flash from the power-down
-            /// state or high performance mode and obtains the devices ID. The bit will be
-            /// cleared once the operation done.1: enable 0: disable.
-            FLASH_RES: u1,
-            /// Drive Flash into power down. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_DP: u1,
-            /// Chip erase enable. Chip erase operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_CE: u1,
-            /// Block erase enable(32KB) . Block erase operation will be triggered when the bit
-            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_BE: u1,
-            /// Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_SE: u1,
-            /// Page program enable(1 byte ~256 bytes data to be programmed). Page program
-            /// operation will be triggered when the bit is set. The bit will be cleared once
-            /// the operation done .1: enable 0: disable.
-            FLASH_PP: u1,
-            /// Write status register enable. Write status operation will be triggered when the
-            /// bit is set. The bit will be cleared once the operation done.1: enable 0:
-            /// disable.
-            FLASH_WRSR: u1,
-            /// Read status register-1. Read status operation will be triggered when the bit is
-            /// set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_RDSR: u1,
-            /// Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will
-            /// be cleared once the operation done. 1: enable 0: disable.
-            FLASH_RDID: u1,
-            /// Write flash disable. Write disable command will be sent when the bit is set. The
-            /// bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_WRDI: u1,
-            /// Write flash enable. Write enable command will be sent when the bit is set. The
-            /// bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_WREN: u1,
-            /// Read flash enable. Read flash operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_READ: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60002004
-        /// SPI1 address register
-        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In user mode, it is the memory address. other then the bit0-bit23 is the memory
-            /// address, the bit24-bit31 are the byte length of a transfer.
-            USR_ADDR_VALUE: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60002008
-        /// SPI1 control register.
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller.
-            FDUMMY_OUT: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable
-            FCMD_QUAD: u1,
-            reserved6: u1,
-            /// For SPI1, initialize crc32 module before writing encrypted data to flash. Active
-            /// low.
-            FCS_CRC_EN: u1,
-            /// For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
-            TX_CRC_EN: u1,
-            reserved7: u1,
-            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
-            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-            FASTRD_MODE: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            FREAD_DUAL: u1,
-            /// The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
-            /// spi_mem_flash_res bit. 1: enable 0: disable.
-            RESANDRES: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low
-            D_POL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            FREAD_QUAD: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
-            WP: u1,
-            /// two bytes data will be written to status register when it is set. 1: enable 0:
-            /// disable.
-            WRSR_2B: u1,
-            /// In the read operations address phase and read-data phase apply 2 signals. 1:
-            /// enable 0: disable.
-            FREAD_DIO: u1,
-            /// In the read operations address phase and read-data phase apply 4 signals. 1:
-            /// enable 0: disable.
-            FREAD_QIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000200c
-        /// SPI1 control1 register.
-        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on.
-            CLK_MODE: u2,
-            /// After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
-            /// 512) SPI_CLK cycles.
-            CS_HOLD_DLY_RES: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60002010
-        /// SPI1 control2 register.
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// The FSM will be reset.
-            SYNC_RESET: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60002014
-        /// SPI1 clock division control register.
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_mem_clkcnt_N.
-            CLKCNT_L: u8,
-            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-            CLKCNT_H: u8,
-            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-            /// system/(spi_mem_clkcnt_N+1)
-            CLKCNT_N: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// reserved
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60002018
-        /// SPI1 user register.
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
-            /// mode.
-            CK_OUT_EDGE: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// In the write operations read-data phase apply 2 signals
-            FWRITE_DUAL: u1,
-            /// In the write operations read-data phase apply 4 signals
-            FWRITE_QUAD: u1,
-            /// In the write operations address phase and read-data phase apply 2 signals.
-            FWRITE_DIO: u1,
-            /// In the write operations address phase and read-data phase apply 4 signals.
-            FWRITE_QIO: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            /// read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-            /// 1: enable 0: disable.
-            USR_MISO_HIGHPART: u1,
-            /// write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-            /// 1: enable 0: disable.
-            USR_MOSI_HIGHPART: u1,
-            /// SPI clock is disable in dummy phase when the bit is enable.
-            USR_DUMMY_IDLE: u1,
-            /// This bit enable the write-data phase of an operation.
-            USR_MOSI: u1,
-            /// This bit enable the read-data phase of an operation.
-            USR_MISO: u1,
-            /// This bit enable the dummy phase of an operation.
-            USR_DUMMY: u1,
-            /// This bit enable the address phase of an operation.
-            USR_ADDR: u1,
-            /// This bit enable the command phase of an operation.
-            USR_COMMAND: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000201c
-        /// SPI1 user1 register.
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1).
-            USR_DUMMY_CYCLELEN: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            USR_ADDR_BITLEN: u6,
-        }), base_address + 0x1c);
-
-        /// address: 0x60002020
-        /// SPI1 user2 register.
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1)
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x20);
-
-        /// address: 0x60002024
-        /// SPI1 send data bit length control register.
-        pub const MOSI_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in bits of write-data. The register value shall be (bit_num-1).
-            USR_MOSI_DBITLEN: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60002028
-        /// SPI1 receive data bit length control register.
-        pub const MISO_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in bits of read-data. The register value shall be (bit_num-1).
-            USR_MISO_DBITLEN: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000202c
-        /// SPI1 status register.
-        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
-            STATUS: u16,
-            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
-            /// bit.
-            WB_MODE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60002034
-        /// SPI1 misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
-            /// device, such as flash, external RAM and so on.
-            CS0_DIS: u1,
-            /// SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
-            /// device, such as flash, external RAM and so on.
-            CS1_DIS: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set.
-            CS_KEEP_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60002038
-        /// SPI1 TX CRC data register.
-        pub const TX_CRC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For SPI1, the value of crc32.
-            DATA: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6000203c
-        /// SPI1 bit mode control register.
-        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
-            CACHE_USR_ADDR_4BYTE: u1,
-            reserved1: u1,
-            /// For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_dio.
-            FDIN_DUAL: u1,
-            /// For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_dio.
-            FDOUT_DUAL: u1,
-            /// For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FADDR_DUAL: u1,
-            /// For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_qio.
-            FDIN_QUAD: u1,
-            /// For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_qio.
-            FDOUT_QUAD: u1,
-            /// For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FADDR_QUAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60002058
-        /// SPI1 memory data buffer0
-        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF0: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000205c
-        /// SPI1 memory data buffer1
-        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF1: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60002060
-        /// SPI1 memory data buffer2
-        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF2: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60002064
-        /// SPI1 memory data buffer3
-        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF3: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60002068
-        /// SPI1 memory data buffer4
-        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF4: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000206c
-        /// SPI1 memory data buffer5
-        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF5: u32,
-        }), base_address + 0x6c);
-
-        /// address: 0x60002070
-        /// SPI1 memory data buffer6
-        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF6: u32,
-        }), base_address + 0x70);
-
-        /// address: 0x60002074
-        /// SPI1 memory data buffer7
-        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF7: u32,
-        }), base_address + 0x74);
-
-        /// address: 0x60002078
-        /// SPI1 memory data buffer8
-        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF8: u32,
-        }), base_address + 0x78);
-
-        /// address: 0x6000207c
-        /// SPI1 memory data buffer9
-        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF9: u32,
-        }), base_address + 0x7c);
-
-        /// address: 0x60002080
-        /// SPI1 memory data buffer10
-        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF10: u32,
-        }), base_address + 0x80);
-
-        /// address: 0x60002084
-        /// SPI1 memory data buffer11
-        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF11: u32,
-        }), base_address + 0x84);
-
-        /// address: 0x60002088
-        /// SPI1 memory data buffer12
-        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF12: u32,
-        }), base_address + 0x88);
-
-        /// address: 0x6000208c
-        /// SPI1 memory data buffer13
-        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF13: u32,
-        }), base_address + 0x8c);
-
-        /// address: 0x60002090
-        /// SPI1 memory data buffer14
-        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF14: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x60002094
-        /// SPI1 memory data buffer15
-        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF15: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60002098
-        /// SPI1 wait idle control register
-        pub const FLASH_WAITI_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// The dummy phase enable when wait flash idle (RDSR)
-            WAITI_DUMMY: u1,
-            /// The command to wait flash idle(RDSR).
-            WAITI_CMD: u8,
-            /// The dummy cycle length when wait flash idle(RDSR).
-            WAITI_DUMMY_CYCLELEN: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6000209c
-        /// SPI1 flash suspend control register
-        pub const FLASH_SUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// program erase resume bit, program erase suspend operation will be triggered when
-            /// the bit is set. The bit will be cleared once the operation done.1: enable 0:
-            /// disable.
-            FLASH_PER: u1,
-            /// program erase suspend bit, program erase suspend operation will be triggered
-            /// when the bit is set. The bit will be cleared once the operation done.1: enable
-            /// 0: disable.
-            FLASH_PES: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-            /// program erase resume command is sent. 0: SPI1 does not wait after program erase
-            /// resume command is sent.
-            FLASH_PER_WAIT_EN: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-            /// program erase suspend command is sent. 0: SPI1 does not wait after program erase
-            /// suspend command is sent.
-            FLASH_PES_WAIT_EN: u1,
-            /// Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
-            /// application should send PER after PES is done.
-            PES_PER_EN: u1,
-            /// Set this bit to enable Auto-suspending function.
-            FLASH_PES_EN: u1,
-            /// The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-            /// status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-            /// out, status_in[15:0] is valid when two bytes of data are read out),
-            /// SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
-            PESR_END_MSK: u16,
-            /// 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte
-            /// when check flash SUS/SUS1/SUS2 status bit
-            RD_SUS_2B: u1,
-            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
-            /// of flash. 0: Only need to check WIP is 0.
-            PER_END_EN: u1,
-            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend
-            /// status of flash. 0: Only need to check WIP is 0.
-            PES_END_EN: u1,
-            /// When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
-            /// it will be treated as check pass.
-            SUS_TIMEOUT_CNT: u7,
-        }), base_address + 0x9c);
-
-        /// address: 0x600020a0
-        /// SPI1 flash suspend command register
-        pub const FLASH_SUS_CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Program/Erase resume command.
-            FLASH_PER_COMMAND: u8,
-            /// Program/Erase suspend command.
-            FLASH_PES_COMMAND: u8,
-            /// Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
-            /// SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of
-            /// flash.
-            WAIT_PESR_COMMAND: u16,
-        }), base_address + 0xa0);
-
-        /// address: 0x600020a4
-        /// SPI1 flash suspend status register
-        pub const SUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status of flash suspend, only used in SPI1.
-            FLASH_SUS: u1,
-            /// 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-            /// SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
-            WAIT_PESR_CMD_2B: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after HPM command is sent.
-            FLASH_HPM_DLY_128: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after RES command is sent.
-            FLASH_RES_DLY_128: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after DP command is sent.
-            FLASH_DP_DLY_128: u1,
-            /// Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
-            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
-            /// command is sent.
-            FLASH_PER_DLY_128: u1,
-            /// Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
-            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
-            /// command is sent.
-            FLASH_PES_DLY_128: u1,
-            /// 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
-            SPI0_LOCK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600020a8
-        /// SPI1 timing control register
-        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// The bit is used to enable timing auto-calibration for all reading operations.
-            TIMING_CALI: u1,
-            /// add extra dummy spi clock cycle length for spi clock calibration.
-            EXTRA_DUMMY_CYCLELEN: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600020c0
-        /// SPI1 interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600020c4
-        /// SPI1 interrupt clear register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600020c8
-        /// SPI1 interrupt raw register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
-            /// command (0x7A) is sent and flash is resumed. 0: Others.
-            PER_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
-            /// command (0x75) is sent and flash is suspended. 0: Others.
-            PES_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
-            /// WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
-            WPE_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
-            /// is changed from non idle state to idle state. It means that SPI_CS raises high.
-            /// 0: Others
-            SLV_ST_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
-            /// is changed from non idle state to idle state. 0: Others.
-            MST_ST_END_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600020cc
-        /// SPI1 interrupt status register
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600020dc
-        /// SPI1 clk_gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Register clock gate enable signal. 1: Enable. 0: Disable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600023fc
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI2 = struct {
-        pub const base_address = 0x60024000;
-
-        /// address: 0x60024000
-        /// Command control register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
-            CONF_BITLEN: u18,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// Set this bit to synchronize SPI registers from APB clock domain into SPI module
-            /// clock domain, which is only used in SPI master mode.
-            UPDATE: u1,
-            /// User define command enable. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-            /// changed by CONF_buf.
-            USR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60024004
-        /// Address value register
-        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Address to slave. Can be configured in CONF state.
-            USR_ADDR_VALUE: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60024008
-        /// SPI control register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller. Can
-            /// be configured in CONF state.
-            DUMMY_OUT: u1,
-            reserved3: u1,
-            /// Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-            /// state.
-            FADDR_DUAL: u1,
-            /// Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-            /// state.
-            FADDR_QUAD: u1,
-            reserved4: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable. Can be configured in
-            /// CONF state.
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable. Can be configured in
-            /// CONF state.
-            FCMD_QUAD: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            /// Can be configured in CONF state.
-            FREAD_DUAL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            /// Can be configured in CONF state.
-            FREAD_QUAD: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-            /// CONF state.
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-            /// CONF state.
-            D_POL: u1,
-            /// SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-            /// configured in CONF state.
-            HOLD_POL: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low. Can
-            /// be configured in CONF state.
-            WP_POL: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-            /// state.
-            RD_BIT_ORDER: u1,
-            /// In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-            /// configured in CONF state.
-            WR_BIT_ORDER: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002400c
-        /// SPI clock control register
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must
-            /// be 0. Can be configured in CONF state.
-            CLKCNT_L: u6,
-            /// In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-            /// must be 0. Can be configured in CONF state.
-            CLKCNT_H: u6,
-            /// In the master mode it is the divider of spi_clk. So spi_clk frequency is
-            /// system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-            CLKCNT_N: u6,
-            /// In the master mode it is pre-divider of spi_clk. Can be configured in CONF
-            /// state.
-            CLKDIV_PRE: u4,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from
-            /// system clock. Can be configured in CONF state.
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60024010
-        /// SPI USER control register
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            DOUTDIN: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Both for master mode and slave mode. 1: spi controller is in QPI mode. 0:
-            /// others. Can be configured in CONF state.
-            QPI_MODE: u1,
-            reserved2: u1,
-            /// In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
-            /// = spi_ck_i. 1:tsck = !spi_ck_i.
-            TSCK_I_EDGE: u1,
-            /// spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            CS_HOLD: u1,
-            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            CS_SETUP: u1,
-            /// In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
-            /// = !spi_ck_i. 1:rsck = spi_ck_i.
-            RSCK_I_EDGE: u1,
-            /// the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.
-            /// Can be configured in CONF state.
-            CK_OUT_EDGE: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// In the write operations read-data phase apply 2 signals. Can be configured in
-            /// CONF state.
-            FWRITE_DUAL: u1,
-            /// In the write operations read-data phase apply 4 signals. Can be configured in
-            /// CONF state.
-            FWRITE_QUAD: u1,
-            reserved5: u1,
-            /// 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-            /// will continue. 0: The seg-trans will end after the current SPI seg-trans or this
-            /// is not seg-trans mode. Can be configured in CONF state.
-            USR_CONF_NXT: u1,
-            reserved6: u1,
-            /// Set the bit to enable 3-line half duplex communication mosi and miso signals
-            /// share the same pin. 1: enable 0: disable. Can be configured in CONF state.
-            SIO: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-            /// 0: disable. Can be configured in CONF state.
-            USR_MISO_HIGHPART: u1,
-            /// write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1:
-            /// enable 0: disable. Can be configured in CONF state.
-            USR_MOSI_HIGHPART: u1,
-            /// spi clock is disable in dummy phase when the bit is enable. Can be configured in
-            /// CONF state.
-            USR_DUMMY_IDLE: u1,
-            /// This bit enable the write-data phase of an operation. Can be configured in CONF
-            /// state.
-            USR_MOSI: u1,
-            /// This bit enable the read-data phase of an operation. Can be configured in CONF
-            /// state.
-            USR_MISO: u1,
-            /// This bit enable the dummy phase of an operation. Can be configured in CONF
-            /// state.
-            USR_DUMMY: u1,
-            /// This bit enable the address phase of an operation. Can be configured in CONF
-            /// state.
-            USR_ADDR: u1,
-            /// This bit enable the command phase of an operation. Can be configured in CONF
-            /// state.
-            USR_COMMAND: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60024014
-        /// SPI USER control register 1
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1). Can be configured in CONF state.
-            USR_DUMMY_CYCLELEN: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-            /// FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
-            /// in GP-SPI master FD/HD-mode.
-            MST_WFULL_ERR_END_EN: u1,
-            /// (cycles+1) of prepare phase by spi clock this bits are combined with
-            /// spi_cs_setup bit. Can be configured in CONF state.
-            CS_SETUP_TIME: u5,
-            /// delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-            /// Can be configured in CONF state.
-            CS_HOLD_TIME: u5,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            /// Can be configured in CONF state.
-            USR_ADDR_BITLEN: u5,
-        }), base_address + 0x14);
-
-        /// address: 0x60024018
-        /// SPI USER control register 2
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command. Can be configured in CONF state.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-            /// master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty
-            /// error is valid in GP-SPI master FD/HD-mode.
-            MST_REMPTY_ERR_END_EN: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1).
-            /// Can be configured in CONF state.
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x18);
-
-        /// address: 0x6002401c
-        /// SPI data bit length control register
-        pub const MS_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of these bits is the configured SPI transmission data bit length in
-            /// master mode DMA controlled transfer or CPU controlled transfer. The value is
-            /// also the configured bit length in slave mode DMA RX controlled transfer. The
-            /// register value shall be (bit_num-1). Can be configured in CONF state.
-            MS_DATA_BITLEN: u18,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60024020
-        /// SPI misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be
-            /// configured in CONF state.
-            CS0_DIS: u1,
-            /// SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be
-            /// configured in CONF state.
-            CS1_DIS: u1,
-            /// SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be
-            /// configured in CONF state.
-            CS2_DIS: u1,
-            /// SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be
-            /// configured in CONF state.
-            CS3_DIS: u1,
-            /// SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be
-            /// configured in CONF state.
-            CS4_DIS: u1,
-            /// SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be
-            /// configured in CONF state.
-            CS5_DIS: u1,
-            /// 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
-            CK_DIS: u1,
-            /// In the master mode the bits are the polarity of spi cs line, the value is
-            /// equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-            MASTER_CS_POL: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// spi slave input cs polarity select. 1: inv 0: not change. Can be configured in
-            /// CONF state.
-            SLAVE_CS_POL: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be
-            /// configured in CONF state.
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set. Can be configured in CONF state.
-            CS_KEEP_ACTIVE: u1,
-            /// 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured
-            /// in CONF state.
-            QUAD_DIN_PIN_SWAP: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60024024
-        /// SPI input delay mode configuration
-        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN0_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN1_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN2_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN3_MODE: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in
-            /// CONF state.
-            TIMING_HCLK_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60024028
-        /// SPI input delay number configuration
-        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN0_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN1_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN2_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN3_NUM: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6002402c
-        /// SPI output delay mode configuration
-        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The output signal 0 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT0_MODE: u1,
-            /// The output signal 1 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT1_MODE: u1,
-            /// The output signal 2 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT2_MODE: u1,
-            /// The output signal 3 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT3_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60024030
-        /// SPI DMA control register
-        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-            DMA_SLV_SEG_TRANS_EN: u1,
-            /// 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-            /// spi_dma_infifo_full_vld is cleared by spi_trans_done.
-            SLV_RX_SEG_TRANS_CLR_EN: u1,
-            /// 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-            /// spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-            SLV_TX_SEG_TRANS_CLR_EN: u1,
-            /// 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal
-            /// to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0:
-            /// spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-            /// spi_dma_seg_trans_done in seg-trans.
-            RX_EOF_EN: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// Set this bit to enable SPI DMA controlled receive data mode.
-            DMA_RX_ENA: u1,
-            /// Set this bit to enable SPI DMA controlled send data mode.
-            DMA_TX_ENA: u1,
-            /// Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-            /// slave mode transfer.
-            RX_AFIFO_RST: u1,
-            /// Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-            /// controlled mode transfer and master mode transfer.
-            BUF_AFIFO_RST: u1,
-            /// Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
-            /// DMA controlled mode transfer.
-            DMA_AFIFO_RST: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60024034
-        /// SPI DMA interrupt enable register
-        pub const DMA_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
-            /// The enable bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_ENA: u1,
-            /// The enable bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_ENA: u1,
-            /// The enable bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_APP2_INT interrupt.
-            APP2_INT_ENA: u1,
-            /// The enable bit for SPI_APP1_INT interrupt.
-            APP1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60024038
-        /// SPI DMA interrupt clear register
-        pub const DMA_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
-            /// The clear bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_CLR: u1,
-            /// The clear bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_CLR: u1,
-            /// The clear bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_APP2_INT interrupt.
-            APP2_INT_CLR: u1,
-            /// The clear bit for SPI_APP1_INT interrupt.
-            APP1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002403c
-        /// SPI DMA interrupt raw register
-        pub const DMA_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
-            /// the receive data. 0: Others.
-            DMA_INFIFO_FULL_ERR_INT_RAW: u1,
-            /// 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-            /// master mode and send out all 0 in slave mode. 0: Others.
-            DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
-            /// The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI
-            /// transmission is ended. 0: Others.
-            SLV_EX_QPI_INT_RAW: u1,
-            /// The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI
-            /// transmission is ended. 0: Others.
-            SLV_EN_QPI_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-            /// ended. 0: Others.
-            SLV_CMD7_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-            /// ended. 0: Others.
-            SLV_CMD8_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-            /// ended. 0: Others.
-            SLV_CMD9_INT_RAW: u1,
-            /// The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-            /// ended. 0: Others.
-            SLV_CMDA_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-            /// transmission is ended. 0: Others.
-            SLV_RD_DMA_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-            /// transmission is ended. 0: Others.
-            SLV_WR_DMA_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-            /// transmission is ended. 0: Others.
-            SLV_RD_BUF_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-            /// transmission is ended. 0: Others.
-            SLV_WR_BUF_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-            /// ended. 0: others.
-            TRANS_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA
-            /// full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-            /// And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans
-            /// is not ended or not occurred.
-            DMA_SEG_TRANS_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF
-            /// buffer is error in the DMA seg-conf-trans. 0: others.
-            SEG_MAGIC_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data
-            /// address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF
-            /// transmission is bigger than 63. 0: Others.
-            SLV_BUF_ADDR_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-            /// current SPI slave HD mode transmission is not supported. 0: Others.
-            SLV_CMD_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-            /// write-full error when SPI inputs data in master mode. 0: Others.
-            MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-            /// AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-            MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_APP2_INT interrupt. The value is only controlled by
-            /// application.
-            APP2_INT_RAW: u1,
-            /// The raw bit for SPI_APP1_INT interrupt. The value is only controlled by
-            /// application.
-            APP1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60024040
-        /// SPI DMA interrupt status register
-        pub const DMA_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_ST: u1,
-            /// The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
-            /// The status bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_ST: u1,
-            /// The status bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_ST: u1,
-            /// The status bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_ST: u1,
-            /// The status bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_ST: u1,
-            /// The status bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_ST: u1,
-            /// The status bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_ST: u1,
-            /// The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_ST: u1,
-            /// The status bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_ST: u1,
-            /// The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_ST: u1,
-            /// The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_ST: u1,
-            /// The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_ST: u1,
-            /// The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_ST: u1,
-            /// The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
-            /// The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
-            /// The status bit for SPI_APP2_INT interrupt.
-            APP2_INT_ST: u1,
-            /// The status bit for SPI_APP1_INT interrupt.
-            APP1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60024098
-        /// SPI CPU-controlled buffer0
-        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF0: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6002409c
-        /// SPI CPU-controlled buffer1
-        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF1: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600240a0
-        /// SPI CPU-controlled buffer2
-        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF2: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600240a4
-        /// SPI CPU-controlled buffer3
-        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF3: u32,
-        }), base_address + 0xa4);
-
-        /// address: 0x600240a8
-        /// SPI CPU-controlled buffer4
-        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF4: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600240ac
-        /// SPI CPU-controlled buffer5
-        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF5: u32,
-        }), base_address + 0xac);
-
-        /// address: 0x600240b0
-        /// SPI CPU-controlled buffer6
-        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF6: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600240b4
-        /// SPI CPU-controlled buffer7
-        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF7: u32,
-        }), base_address + 0xb4);
-
-        /// address: 0x600240b8
-        /// SPI CPU-controlled buffer8
-        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF8: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600240bc
-        /// SPI CPU-controlled buffer9
-        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF9: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600240c0
-        /// SPI CPU-controlled buffer10
-        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF10: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600240c4
-        /// SPI CPU-controlled buffer11
-        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF11: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600240c8
-        /// SPI CPU-controlled buffer12
-        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF12: u32,
-        }), base_address + 0xc8);
-
-        /// address: 0x600240cc
-        /// SPI CPU-controlled buffer13
-        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF13: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600240d0
-        /// SPI CPU-controlled buffer14
-        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF14: u32,
-        }), base_address + 0xd0);
-
-        /// address: 0x600240d4
-        /// SPI CPU-controlled buffer15
-        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF15: u32,
-        }), base_address + 0xd4);
-
-        /// address: 0x600240e0
-        /// SPI slave control register
-        pub const SLAVE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
-            CLK_MODE: u2,
-            /// {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
-            /// 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-            CLK_MODE_13: u1,
-            /// It saves half a cycle when tsck is the same as rsck. 1: output data at rsck
-            /// posedge 0: output data at tsck posedge
-            RSCK_DATA_OUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
-            /// in DMA controlled mode(Rd_DMA). 0: others
-            SLV_RDDMA_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
-            /// length in DMA controlled mode(Wr_DMA). 0: others
-            SLV_WRDMA_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
-            /// in CPU controlled mode(Rd_BUF). 0: others
-            SLV_RDBUF_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
-            /// length in CPU controlled mode(Wr_BUF). 0: others
-            SLV_WRBUF_BITLEN_EN: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// The magic value of BM table in master DMA seg-trans.
-            DMA_SEG_MAGIC_VALUE: u4,
-            /// Set SPI work mode. 1: slave mode 0: master mode.
-            MODE: u1,
-            /// Software reset enable, reset the spi clock line cs line and data lines. Can be
-            /// configured in CONF state.
-            SOFT_RESET: u1,
-            /// 1: Enable the DMA CONF phase of current seg-trans operation, which means
-            /// seg-trans will start. 0: This is not seg-trans mode.
-            USR_CONF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600240e4
-        /// SPI slave control register 1
-        pub const SLAVE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The transferred data bit length in SPI slave FD and HD mode.
-            SLV_DATA_BITLEN: u18,
-            /// In the slave mode it is the value of command.
-            SLV_LAST_COMMAND: u8,
-            /// In the slave mode it is the value of address.
-            SLV_LAST_ADDR: u6,
-        }), base_address + 0xe4);
-
-        /// address: 0x600240e8
-        /// SPI module clock and register clock control
-        pub const CLK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable clk gate
-            CLK_EN: u1,
-            /// Set this bit to power on the SPI module clock.
-            MST_CLK_ACTIVE: u1,
-            /// This bit is used to select SPI module clock source in master mode. 1:
-            /// PLL_CLK_80M. 0: XTAL CLK.
-            MST_CLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x600240f0
-        /// Version control
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xf0);
-    };
-
-    /// System
-    pub const SYSTEM = struct {
-        pub const base_address = 0x600c0000;
-
-        /// address: 0x600c0000
-        /// cpu_peripheral clock gating register
-        pub const CPU_PERI_CLK_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// reg_clk_en_assist_debug
-            CLK_EN_ASSIST_DEBUG: u1,
-            /// reg_clk_en_dedicated_gpio
-            CLK_EN_DEDICATED_GPIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600c0004
-        /// cpu_peripheral reset register
-        pub const CPU_PERI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// reg_rst_en_assist_debug
-            RST_EN_ASSIST_DEBUG: u1,
-            /// reg_rst_en_dedicated_gpio
-            RST_EN_DEDICATED_GPIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600c0008
-        /// cpu clock config register
-        pub const CPU_PER_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_cpuperiod_sel
-            CPUPERIOD_SEL: u2,
-            /// reg_pll_freq_sel
-            PLL_FREQ_SEL: u1,
-            /// reg_cpu_wait_mode_force_on
-            CPU_WAIT_MODE_FORCE_ON: u1,
-            /// reg_cpu_waiti_delay_num
-            CPU_WAITI_DELAY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600c000c
-        /// memory power down mask register
-        pub const MEM_PD_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lslp_mem_pd_mask
-            LSLP_MEM_PD_MASK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600c0010
-        /// peripheral clock gating register
-        pub const PERIP_CLK_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timers_clk_en
-            TIMERS_CLK_EN: u1,
-            /// reg_spi01_clk_en
-            SPI01_CLK_EN: u1,
-            /// reg_uart_clk_en
-            UART_CLK_EN: u1,
-            /// reg_wdg_clk_en
-            WDG_CLK_EN: u1,
-            /// reg_i2s0_clk_en
-            I2S0_CLK_EN: u1,
-            /// reg_uart1_clk_en
-            UART1_CLK_EN: u1,
-            /// reg_spi2_clk_en
-            SPI2_CLK_EN: u1,
-            /// reg_ext0_clk_en
-            I2C_EXT0_CLK_EN: u1,
-            /// reg_uhci0_clk_en
-            UHCI0_CLK_EN: u1,
-            /// reg_rmt_clk_en
-            RMT_CLK_EN: u1,
-            /// reg_pcnt_clk_en
-            PCNT_CLK_EN: u1,
-            /// reg_ledc_clk_en
-            LEDC_CLK_EN: u1,
-            /// reg_uhci1_clk_en
-            UHCI1_CLK_EN: u1,
-            /// reg_timergroup_clk_en
-            TIMERGROUP_CLK_EN: u1,
-            /// reg_efuse_clk_en
-            EFUSE_CLK_EN: u1,
-            /// reg_timergroup1_clk_en
-            TIMERGROUP1_CLK_EN: u1,
-            /// reg_spi3_clk_en
-            SPI3_CLK_EN: u1,
-            /// reg_pwm0_clk_en
-            PWM0_CLK_EN: u1,
-            /// reg_ext1_clk_en
-            EXT1_CLK_EN: u1,
-            /// reg_can_clk_en
-            CAN_CLK_EN: u1,
-            /// reg_pwm1_clk_en
-            PWM1_CLK_EN: u1,
-            /// reg_i2s1_clk_en
-            I2S1_CLK_EN: u1,
-            /// reg_spi2_dma_clk_en
-            SPI2_DMA_CLK_EN: u1,
-            /// reg_usb_device_clk_en
-            USB_DEVICE_CLK_EN: u1,
-            /// reg_uart_mem_clk_en
-            UART_MEM_CLK_EN: u1,
-            /// reg_pwm2_clk_en
-            PWM2_CLK_EN: u1,
-            /// reg_pwm3_clk_en
-            PWM3_CLK_EN: u1,
-            /// reg_spi3_dma_clk_en
-            SPI3_DMA_CLK_EN: u1,
-            /// reg_apb_saradc_clk_en
-            APB_SARADC_CLK_EN: u1,
-            /// reg_systimer_clk_en
-            SYSTIMER_CLK_EN: u1,
-            /// reg_adc2_arb_clk_en
-            ADC2_ARB_CLK_EN: u1,
-            /// reg_spi4_clk_en
-            SPI4_CLK_EN: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x600c0014
-        /// peripheral clock gating register
-        pub const PERIP_CLK_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_crypto_aes_clk_en
-            CRYPTO_AES_CLK_EN: u1,
-            /// reg_crypto_sha_clk_en
-            CRYPTO_SHA_CLK_EN: u1,
-            /// reg_crypto_rsa_clk_en
-            CRYPTO_RSA_CLK_EN: u1,
-            /// reg_crypto_ds_clk_en
-            CRYPTO_DS_CLK_EN: u1,
-            /// reg_crypto_hmac_clk_en
-            CRYPTO_HMAC_CLK_EN: u1,
-            /// reg_dma_clk_en
-            DMA_CLK_EN: u1,
-            /// reg_sdio_host_clk_en
-            SDIO_HOST_CLK_EN: u1,
-            /// reg_lcd_cam_clk_en
-            LCD_CAM_CLK_EN: u1,
-            /// reg_uart2_clk_en
-            UART2_CLK_EN: u1,
-            /// reg_tsens_clk_en
-            TSENS_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x600c0018
-        /// reserved
-        pub const PERIP_RST_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timers_rst
-            TIMERS_RST: u1,
-            /// reg_spi01_rst
-            SPI01_RST: u1,
-            /// reg_uart_rst
-            UART_RST: u1,
-            /// reg_wdg_rst
-            WDG_RST: u1,
-            /// reg_i2s0_rst
-            I2S0_RST: u1,
-            /// reg_uart1_rst
-            UART1_RST: u1,
-            /// reg_spi2_rst
-            SPI2_RST: u1,
-            /// reg_ext0_rst
-            I2C_EXT0_RST: u1,
-            /// reg_uhci0_rst
-            UHCI0_RST: u1,
-            /// reg_rmt_rst
-            RMT_RST: u1,
-            /// reg_pcnt_rst
-            PCNT_RST: u1,
-            /// reg_ledc_rst
-            LEDC_RST: u1,
-            /// reg_uhci1_rst
-            UHCI1_RST: u1,
-            /// reg_timergroup_rst
-            TIMERGROUP_RST: u1,
-            /// reg_efuse_rst
-            EFUSE_RST: u1,
-            /// reg_timergroup1_rst
-            TIMERGROUP1_RST: u1,
-            /// reg_spi3_rst
-            SPI3_RST: u1,
-            /// reg_pwm0_rst
-            PWM0_RST: u1,
-            /// reg_ext1_rst
-            EXT1_RST: u1,
-            /// reg_can_rst
-            CAN_RST: u1,
-            /// reg_pwm1_rst
-            PWM1_RST: u1,
-            /// reg_i2s1_rst
-            I2S1_RST: u1,
-            /// reg_spi2_dma_rst
-            SPI2_DMA_RST: u1,
-            /// reg_usb_device_rst
-            USB_DEVICE_RST: u1,
-            /// reg_uart_mem_rst
-            UART_MEM_RST: u1,
-            /// reg_pwm2_rst
-            PWM2_RST: u1,
-            /// reg_pwm3_rst
-            PWM3_RST: u1,
-            /// reg_spi3_dma_rst
-            SPI3_DMA_RST: u1,
-            /// reg_apb_saradc_rst
-            APB_SARADC_RST: u1,
-            /// reg_systimer_rst
-            SYSTIMER_RST: u1,
-            /// reg_adc2_arb_rst
-            ADC2_ARB_RST: u1,
-            /// reg_spi4_rst
-            SPI4_RST: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x600c001c
-        /// peripheral reset register
-        pub const PERIP_RST_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_crypto_aes_rst
-            CRYPTO_AES_RST: u1,
-            /// reg_crypto_sha_rst
-            CRYPTO_SHA_RST: u1,
-            /// reg_crypto_rsa_rst
-            CRYPTO_RSA_RST: u1,
-            /// reg_crypto_ds_rst
-            CRYPTO_DS_RST: u1,
-            /// reg_crypto_hmac_rst
-            CRYPTO_HMAC_RST: u1,
-            /// reg_dma_rst
-            DMA_RST: u1,
-            /// reg_sdio_host_rst
-            SDIO_HOST_RST: u1,
-            /// reg_lcd_cam_rst
-            LCD_CAM_RST: u1,
-            /// reg_uart2_rst
-            UART2_RST: u1,
-            /// reg_tsens_rst
-            TSENS_RST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c0020
-        /// clock config register
-        pub const BT_LPCK_DIV_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_bt_lpck_div_num
-            BT_LPCK_DIV_NUM: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x600c0024
-        /// clock config register
-        pub const BT_LPCK_DIV_FRAC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_bt_lpck_div_b
-            BT_LPCK_DIV_B: u12,
-            /// reg_bt_lpck_div_a
-            BT_LPCK_DIV_A: u12,
-            /// reg_lpclk_sel_rtc_slow
-            LPCLK_SEL_RTC_SLOW: u1,
-            /// reg_lpclk_sel_8m
-            LPCLK_SEL_8M: u1,
-            /// reg_lpclk_sel_xtal
-            LPCLK_SEL_XTAL: u1,
-            /// reg_lpclk_sel_xtal32k
-            LPCLK_SEL_XTAL32K: u1,
-            /// reg_lpclk_rtc_en
-            LPCLK_RTC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x600c0028
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_0 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x28);
-
-        /// address: 0x600c002c
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_1 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x2c);
-
-        /// address: 0x600c0030
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_2 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30);
-
-        /// address: 0x600c0034
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_3 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x34);
-
-        /// address: 0x600c0038
-        /// rsa memory power control register
-        pub const RSA_PD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rsa_mem_pd
-            RSA_MEM_PD: u1,
-            /// reg_rsa_mem_force_pu
-            RSA_MEM_FORCE_PU: u1,
-            /// reg_rsa_mem_force_pd
-            RSA_MEM_FORCE_PD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x600c003c
-        /// edma clcok and reset register
-        pub const EDMA_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_edma_clk_on
-            EDMA_CLK_ON: u1,
-            /// reg_edma_reset
-            EDMA_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x600c0040
-        /// cache control register
-        pub const CACHE_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_icache_clk_on
-            ICACHE_CLK_ON: u1,
-            /// reg_icache_reset
-            ICACHE_RESET: u1,
-            /// reg_dcache_clk_on
-            DCACHE_CLK_ON: u1,
-            /// reg_dcache_reset
-            DCACHE_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c0044
-        /// SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
-        pub const EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_enable_spi_manual_encrypt
-            ENABLE_SPI_MANUAL_ENCRYPT: u1,
-            /// reg_enable_download_db_encrypt
-            ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
-            /// reg_enable_download_g0cb_decrypt
-            ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
-            /// reg_enable_download_manual_encrypt
-            ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600c0048
-        /// fast memory config register
-        pub const RTC_FASTMEM_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// reg_rtc_mem_crc_start
-            RTC_MEM_CRC_START: u1,
-            /// reg_rtc_mem_crc_addr
-            RTC_MEM_CRC_ADDR: u11,
-            /// reg_rtc_mem_crc_len
-            RTC_MEM_CRC_LEN: u11,
-            /// reg_rtc_mem_crc_finish
-            RTC_MEM_CRC_FINISH: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x600c004c
-        /// reserved
-        pub const RTC_FASTMEM_CRC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rtc_mem_crc_res
-            RTC_MEM_CRC_RES: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x600c0050
-        /// eco register
-        pub const REDUNDANT_ECO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redundant_eco_drive
-            REDUNDANT_ECO_DRIVE: u1,
-            /// reg_redundant_eco_result
-            REDUNDANT_ECO_RESULT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600c0054
-        /// clock gating register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600c0058
-        /// system clock config register
-        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_pre_div_cnt
-            PRE_DIV_CNT: u10,
-            /// reg_soc_clk_sel
-            SOC_CLK_SEL: u2,
-            /// reg_clk_xtal_freq
-            CLK_XTAL_FREQ: u7,
-            /// reg_clk_div_en
-            CLK_DIV_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600c005c
-        /// mem pvt register
-        pub const MEM_PVT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_path_len
-            MEM_PATH_LEN: u4,
-            /// reg_mem_err_cnt_clr
-            MEM_ERR_CNT_CLR: u1,
-            /// reg_mem_pvt_monitor_en
-            MONITOR_EN: u1,
-            /// reg_mem_timing_err_cnt
-            MEM_TIMING_ERR_CNT: u16,
-            /// reg_mem_vt_sel
-            MEM_VT_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x600c0060
-        /// mem pvt register
-        pub const COMB_PVT_LVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_lvt
-            COMB_PATH_LEN_LVT: u5,
-            /// reg_comb_err_cnt_clr_lvt
-            COMB_ERR_CNT_CLR_LVT: u1,
-            /// reg_comb_pvt_monitor_en_lvt
-            COMB_PVT_MONITOR_EN_LVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600c0064
-        /// mem pvt register
-        pub const COMB_PVT_NVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_nvt
-            COMB_PATH_LEN_NVT: u5,
-            /// reg_comb_err_cnt_clr_nvt
-            COMB_ERR_CNT_CLR_NVT: u1,
-            /// reg_comb_pvt_monitor_en_nvt
-            COMB_PVT_MONITOR_EN_NVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c0068
-        /// mem pvt register
-        pub const COMB_PVT_HVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_hvt
-            COMB_PATH_LEN_HVT: u5,
-            /// reg_comb_err_cnt_clr_hvt
-            COMB_ERR_CNT_CLR_HVT: u1,
-            /// reg_comb_pvt_monitor_en_hvt
-            COMB_PVT_MONITOR_EN_HVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600c006c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site0
-            COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600c0070
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site0
-            COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600c0074
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site0
-            COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600c0078
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site1
-            COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c007c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site1
-            COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c0080
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site1
-            COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c0084
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site2
-            COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c0088
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site2
-            COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c008c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site2
-            COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c0090
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site3
-            COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c0094
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site3
-            COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x600c0098
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site3
-            COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c0ffc
-        /// Version register
-        pub const SYSTEM_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
-    };
-
-    /// System Timer
-    pub const SYSTIMER = struct {
-        pub const base_address = 0x60023000;
-
-        /// address: 0x60023000
-        /// SYSTIMER_CONF.
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// systimer clock force on
-            SYSTIMER_CLK_FO: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            /// target2 work enable
-            TARGET2_WORK_EN: u1,
-            /// target1 work enable
-            TARGET1_WORK_EN: u1,
-            /// target0 work enable
-            TARGET0_WORK_EN: u1,
-            /// If timer unit1 is stalled when core1 stalled
-            TIMER_UNIT1_CORE1_STALL_EN: u1,
-            /// If timer unit1 is stalled when core0 stalled
-            TIMER_UNIT1_CORE0_STALL_EN: u1,
-            /// If timer unit0 is stalled when core1 stalled
-            TIMER_UNIT0_CORE1_STALL_EN: u1,
-            /// If timer unit0 is stalled when core0 stalled
-            TIMER_UNIT0_CORE0_STALL_EN: u1,
-            /// timer unit1 work enable
-            TIMER_UNIT1_WORK_EN: u1,
-            /// timer unit0 work enable
-            TIMER_UNIT0_WORK_EN: u1,
-            /// register file clk gating
-            CLK_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60023004
-        /// SYSTIMER_UNIT0_OP.
-        pub const UNIT0_OP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_timer_unit0_value_valid
-            TIMER_UNIT0_VALUE_VALID: u1,
-            /// update timer_unit0
-            TIMER_UNIT0_UPDATE: u1,
-            padding0: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60023008
-        /// SYSTIMER_UNIT1_OP.
-        pub const UNIT1_OP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// timer value is sync and valid
-            TIMER_UNIT1_VALUE_VALID: u1,
-            /// update timer unit1
-            TIMER_UNIT1_UPDATE: u1,
-            padding0: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002300c
-        /// SYSTIMER_UNIT0_LOAD_HI.
-        pub const UNIT0_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load high 32 bit
-            TIMER_UNIT0_LOAD_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60023010
-        /// SYSTIMER_UNIT0_LOAD_LO.
-        pub const UNIT0_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load low 32 bit
-            TIMER_UNIT0_LOAD_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60023014
-        /// SYSTIMER_UNIT1_LOAD_HI.
-        pub const UNIT1_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load high 32 bit
-            TIMER_UNIT1_LOAD_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60023018
-        /// SYSTIMER_UNIT1_LOAD_LO.
-        pub const UNIT1_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load low 32 bit
-            TIMER_UNIT1_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002301c
-        /// SYSTIMER_TARGET0_HI.
-        pub const TARGET0_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget0 high 32 bit
-            TIMER_TARGET0_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60023020
-        /// SYSTIMER_TARGET0_LO.
-        pub const TARGET0_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget0 low 32 bit
-            TIMER_TARGET0_LO: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60023024
-        /// SYSTIMER_TARGET1_HI.
-        pub const TARGET1_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget1 high 32 bit
-            TIMER_TARGET1_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60023028
-        /// SYSTIMER_TARGET1_LO.
-        pub const TARGET1_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget1 low 32 bit
-            TIMER_TARGET1_LO: u32,
-        }), base_address + 0x28);
-
-        /// address: 0x6002302c
-        /// SYSTIMER_TARGET2_HI.
-        pub const TARGET2_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget2 high 32 bit
-            TIMER_TARGET2_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60023030
-        /// SYSTIMER_TARGET2_LO.
-        pub const TARGET2_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget2 low 32 bit
-            TIMER_TARGET2_LO: u32,
-        }), base_address + 0x30);
-
-        /// address: 0x60023034
-        /// SYSTIMER_TARGET0_CONF.
-        pub const TARGET0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target0 period
-            TARGET0_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target0 to period mode
-            TARGET0_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET0_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60023038
-        /// SYSTIMER_TARGET1_CONF.
-        pub const TARGET1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target1 period
-            TARGET1_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target1 to period mode
-            TARGET1_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET1_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002303c
-        /// SYSTIMER_TARGET2_CONF.
-        pub const TARGET2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target2 period
-            TARGET2_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target2 to period mode
-            TARGET2_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET2_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60023040
-        /// SYSTIMER_UNIT0_VALUE_HI.
-        pub const UNIT0_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value high 32bit
-            TIMER_UNIT0_VALUE_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60023044
-        /// SYSTIMER_UNIT0_VALUE_LO.
-        pub const UNIT0_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value low 32bit
-            TIMER_UNIT0_VALUE_LO: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60023048
-        /// SYSTIMER_UNIT1_VALUE_HI.
-        pub const UNIT1_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value high 32bit
-            TIMER_UNIT1_VALUE_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002304c
-        /// SYSTIMER_UNIT1_VALUE_LO.
-        pub const UNIT1_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value low 32bit
-            TIMER_UNIT1_VALUE_LO: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60023050
-        /// SYSTIMER_COMP0_LOAD.
-        pub const COMP0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp0 load value
-            TIMER_COMP0_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60023054
-        /// SYSTIMER_COMP1_LOAD.
-        pub const COMP1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp1 load value
-            TIMER_COMP1_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60023058
-        /// SYSTIMER_COMP2_LOAD.
-        pub const COMP2_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp2 load value
-            TIMER_COMP2_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002305c
-        /// SYSTIMER_UNIT0_LOAD.
-        pub const UNIT0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load value
-            TIMER_UNIT0_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60023060
-        /// SYSTIMER_UNIT1_LOAD.
-        pub const UNIT1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load value
-            TIMER_UNIT1_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60023064
-        /// SYSTIMER_INT_ENA.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 enable
-            TARGET0_INT_ENA: u1,
-            /// interupt1 enable
-            TARGET1_INT_ENA: u1,
-            /// interupt2 enable
-            TARGET2_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60023068
-        /// SYSTIMER_INT_RAW.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 raw
-            TARGET0_INT_RAW: u1,
-            /// interupt1 raw
-            TARGET1_INT_RAW: u1,
-            /// interupt2 raw
-            TARGET2_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002306c
-        /// SYSTIMER_INT_CLR.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 clear
-            TARGET0_INT_CLR: u1,
-            /// interupt1 clear
-            TARGET1_INT_CLR: u1,
-            /// interupt2 clear
-            TARGET2_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60023070
-        /// SYSTIMER_INT_ST.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_target0_int_st
-            TARGET0_INT_ST: u1,
-            /// reg_target1_int_st
-            TARGET1_INT_ST: u1,
-            /// reg_target2_int_st
-            TARGET2_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600230fc
-        /// SYSTIMER_DATE.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-
-    /// Timer Group
-    pub const TIMG0 = struct {
-        pub const base_address = 0x6001f000;
-
-        /// address: 0x6001f000
-        /// TIMG_T0CONFIG_REG.
-        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// reg_t0_use_xtal.
-            T0_USE_XTAL: u1,
-            /// reg_t0_alarm_en.
-            T0_ALARM_EN: u1,
-            reserved9: u1,
-            /// reg_t0_divcnt_rst.
-            T0_DIVCNT_RST: u1,
-            /// reg_t0_divider.
-            T0_DIVIDER: u16,
-            /// reg_t0_autoreload.
-            T0_AUTORELOAD: u1,
-            /// reg_t0_increase.
-            T0_INCREASE: u1,
-            /// reg_t0_en.
-            T0_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6001f004
-        /// TIMG_T0LO_REG.
-        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_lo
-            T0_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x6001f008
-        /// TIMG_T0HI_REG.
-        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_hi
-            T0_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001f00c
-        /// TIMG_T0UPDATE_REG.
-        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// t0_update
-            T0_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6001f010
-        /// TIMG_T0ALARMLO_REG.
-        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_lo.
-            T0_ALARM_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x6001f014
-        /// TIMG_T0ALARMHI_REG.
-        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_hi.
-            T0_ALARM_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6001f018
-        /// TIMG_T0LOADLO_REG.
-        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_lo.
-            T0_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6001f01c
-        /// TIMG_T0LOADHI_REG.
-        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_hi.
-            T0_LOAD_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6001f020
-        /// TIMG_T0LOAD_REG.
-        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_load
-            T0_LOAD: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x6001f048
-        /// TIMG_WDTCONFIG0_REG.
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_wdt_appcpu_reset_en.
-            WDT_APPCPU_RESET_EN: u1,
-            /// reg_wdt_procpu_reset_en.
-            WDT_PROCPU_RESET_EN: u1,
-            /// reg_wdt_flashboot_mod_en.
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// reg_wdt_sys_reset_length.
-            WDT_SYS_RESET_LENGTH: u3,
-            /// reg_wdt_cpu_reset_length.
-            WDT_CPU_RESET_LENGTH: u3,
-            /// reg_wdt_use_xtal.
-            WDT_USE_XTAL: u1,
-            /// reg_wdt_conf_update_en.
-            WDT_CONF_UPDATE_EN: u1,
-            /// reg_wdt_stg3.
-            WDT_STG3: u2,
-            /// reg_wdt_stg2.
-            WDT_STG2: u2,
-            /// reg_wdt_stg1.
-            WDT_STG1: u2,
-            /// reg_wdt_stg0.
-            WDT_STG0: u2,
-            /// reg_wdt_en.
-            WDT_EN: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001f04c
-        /// TIMG_WDTCONFIG1_REG.
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_divcnt_rst.
-            WDT_DIVCNT_RST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reg_wdt_clk_prescale.
-            WDT_CLK_PRESCALE: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x6001f050
-        /// TIMG_WDTCONFIG2_REG.
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg0_hold.
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x6001f054
-        /// TIMG_WDTCONFIG3_REG.
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg1_hold.
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x6001f058
-        /// TIMG_WDTCONFIG4_REG.
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg2_hold.
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6001f05c
-        /// TIMG_WDTCONFIG5_REG.
-        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg3_hold.
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x6001f060
-        /// TIMG_WDTFEED_REG.
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wdt_feed
-            WDT_FEED: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x6001f064
-        /// TIMG_WDTWPROTECT_REG.
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_wkey.
-            WDT_WKEY: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x6001f068
-        /// TIMG_RTCCALICFG_REG.
-        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_rtc_cali_start_cycling.
-            RTC_CALI_START_CYCLING: u1,
-            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-            RTC_CALI_CLK_SEL: u2,
-            /// rtc_cali_rdy
-            RTC_CALI_RDY: u1,
-            /// reg_rtc_cali_max.
-            RTC_CALI_MAX: u15,
-            /// reg_rtc_cali_start.
-            RTC_CALI_START: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001f06c
-        /// TIMG_RTCCALICFG1_REG.
-        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc_cali_cycling_data_vld
-            RTC_CALI_CYCLING_DATA_VLD: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// rtc_cali_value
-            RTC_CALI_VALUE: u25,
-        }), base_address + 0x6c);
-
-        /// address: 0x6001f070
-        /// INT_ENA_TIMG_REG
-        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_ena
-            T0_INT_ENA: u1,
-            /// wdt_int_ena
-            WDT_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6001f074
-        /// INT_RAW_TIMG_REG
-        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_raw
-            T0_INT_RAW: u1,
-            /// wdt_int_raw
-            WDT_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6001f078
-        /// INT_ST_TIMG_REG
-        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_st
-            T0_INT_ST: u1,
-            /// wdt_int_st
-            WDT_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001f07c
-        /// INT_CLR_TIMG_REG
-        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_clr
-            T0_INT_CLR: u1,
-            /// wdt_int_clr
-            WDT_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6001f080
-        /// TIMG_RTCCALICFG2_REG.
-        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timeoutindicator
-            RTC_CALI_TIMEOUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-            RTC_CALI_TIMEOUT_RST_CNT: u4,
-            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-            RTC_CALI_TIMEOUT_THRES: u25,
-        }), base_address + 0x80);
-
-        /// address: 0x6001f0f8
-        /// TIMG_NTIMG_DATE_REG.
-        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ntimers_date.
-            NTIMGS_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x6001f0fc
-        /// TIMG_REGCLK_REG.
-        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_wdt_clk_is_active.
-            WDT_CLK_IS_ACTIVE: u1,
-            /// reg_timer_clk_is_active.
-            TIMER_CLK_IS_ACTIVE: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// Timer Group
-    pub const TIMG1 = struct {
-        pub const base_address = 0x60020000;
-
-        /// address: 0x60020000
-        /// TIMG_T0CONFIG_REG.
-        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// reg_t0_use_xtal.
-            T0_USE_XTAL: u1,
-            /// reg_t0_alarm_en.
-            T0_ALARM_EN: u1,
-            reserved9: u1,
-            /// reg_t0_divcnt_rst.
-            T0_DIVCNT_RST: u1,
-            /// reg_t0_divider.
-            T0_DIVIDER: u16,
-            /// reg_t0_autoreload.
-            T0_AUTORELOAD: u1,
-            /// reg_t0_increase.
-            T0_INCREASE: u1,
-            /// reg_t0_en.
-            T0_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60020004
-        /// TIMG_T0LO_REG.
-        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_lo
-            T0_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60020008
-        /// TIMG_T0HI_REG.
-        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_hi
-            T0_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002000c
-        /// TIMG_T0UPDATE_REG.
-        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// t0_update
-            T0_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60020010
-        /// TIMG_T0ALARMLO_REG.
-        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_lo.
-            T0_ALARM_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60020014
-        /// TIMG_T0ALARMHI_REG.
-        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_hi.
-            T0_ALARM_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60020018
-        /// TIMG_T0LOADLO_REG.
-        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_lo.
-            T0_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002001c
-        /// TIMG_T0LOADHI_REG.
-        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_hi.
-            T0_LOAD_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60020020
-        /// TIMG_T0LOAD_REG.
-        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_load
-            T0_LOAD: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60020048
-        /// TIMG_WDTCONFIG0_REG.
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_wdt_appcpu_reset_en.
-            WDT_APPCPU_RESET_EN: u1,
-            /// reg_wdt_procpu_reset_en.
-            WDT_PROCPU_RESET_EN: u1,
-            /// reg_wdt_flashboot_mod_en.
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// reg_wdt_sys_reset_length.
-            WDT_SYS_RESET_LENGTH: u3,
-            /// reg_wdt_cpu_reset_length.
-            WDT_CPU_RESET_LENGTH: u3,
-            /// reg_wdt_use_xtal.
-            WDT_USE_XTAL: u1,
-            /// reg_wdt_conf_update_en.
-            WDT_CONF_UPDATE_EN: u1,
-            /// reg_wdt_stg3.
-            WDT_STG3: u2,
-            /// reg_wdt_stg2.
-            WDT_STG2: u2,
-            /// reg_wdt_stg1.
-            WDT_STG1: u2,
-            /// reg_wdt_stg0.
-            WDT_STG0: u2,
-            /// reg_wdt_en.
-            WDT_EN: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002004c
-        /// TIMG_WDTCONFIG1_REG.
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_divcnt_rst.
-            WDT_DIVCNT_RST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reg_wdt_clk_prescale.
-            WDT_CLK_PRESCALE: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x60020050
-        /// TIMG_WDTCONFIG2_REG.
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg0_hold.
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60020054
-        /// TIMG_WDTCONFIG3_REG.
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg1_hold.
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60020058
-        /// TIMG_WDTCONFIG4_REG.
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg2_hold.
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6002005c
-        /// TIMG_WDTCONFIG5_REG.
-        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg3_hold.
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60020060
-        /// TIMG_WDTFEED_REG.
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wdt_feed
-            WDT_FEED: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60020064
-        /// TIMG_WDTWPROTECT_REG.
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_wkey.
-            WDT_WKEY: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60020068
-        /// TIMG_RTCCALICFG_REG.
-        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_rtc_cali_start_cycling.
-            RTC_CALI_START_CYCLING: u1,
-            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-            RTC_CALI_CLK_SEL: u2,
-            /// rtc_cali_rdy
-            RTC_CALI_RDY: u1,
-            /// reg_rtc_cali_max.
-            RTC_CALI_MAX: u15,
-            /// reg_rtc_cali_start.
-            RTC_CALI_START: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002006c
-        /// TIMG_RTCCALICFG1_REG.
-        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc_cali_cycling_data_vld
-            RTC_CALI_CYCLING_DATA_VLD: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// rtc_cali_value
-            RTC_CALI_VALUE: u25,
-        }), base_address + 0x6c);
-
-        /// address: 0x60020070
-        /// INT_ENA_TIMG_REG
-        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_ena
-            T0_INT_ENA: u1,
-            /// wdt_int_ena
-            WDT_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60020074
-        /// INT_RAW_TIMG_REG
-        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_raw
-            T0_INT_RAW: u1,
-            /// wdt_int_raw
-            WDT_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60020078
-        /// INT_ST_TIMG_REG
-        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_st
-            T0_INT_ST: u1,
-            /// wdt_int_st
-            WDT_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6002007c
-        /// INT_CLR_TIMG_REG
-        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_clr
-            T0_INT_CLR: u1,
-            /// wdt_int_clr
-            WDT_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60020080
-        /// TIMG_RTCCALICFG2_REG.
-        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timeoutindicator
-            RTC_CALI_TIMEOUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-            RTC_CALI_TIMEOUT_RST_CNT: u4,
-            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-            RTC_CALI_TIMEOUT_THRES: u25,
-        }), base_address + 0x80);
-
-        /// address: 0x600200f8
-        /// TIMG_NTIMG_DATE_REG.
-        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ntimers_date.
-            NTIMGS_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600200fc
-        /// TIMG_REGCLK_REG.
-        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_wdt_clk_is_active.
-            WDT_CLK_IS_ACTIVE: u1,
-            /// reg_timer_clk_is_active.
-            TIMER_CLK_IS_ACTIVE: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// Two-Wire Automotive Interface
-    pub const TWAI = struct {
-        pub const base_address = 0x6002b000;
-
-        /// address: 0x6002b000
-        /// Mode Register
-        pub const MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to configure the operating mode of the TWAI Controller. 1:
-            /// Reset mode; 0: Operating mode.
-            RESET_MODE: u1,
-            /// 1: Listen only mode. In this mode the nodes will only receive messages from the
-            /// bus, without generating the acknowledge signal nor updating the RX error
-            /// counter.
-            LISTEN_ONLY_MODE: u1,
-            /// 1: Self test mode. In this mode the TX nodes can perform a successful
-            /// transmission without receiving the acknowledge signal. This mode is often used
-            /// to test a single node with the self reception request command.
-            SELF_TEST_MODE: u1,
-            /// This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single
-            /// filter mode.
-            RX_FILTER_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6002b004
-        /// Command Register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set the bit to 1 to allow the driving nodes start transmission.
-            TX_REQ: u1,
-            /// Set the bit to 1 to cancel a pending transmission request.
-            ABORT_TX: u1,
-            /// Set the bit to 1 to release the RX buffer.
-            RELEASE_BUF: u1,
-            /// Set the bit to 1 to clear the data overrun status bit.
-            CLR_OVERRUN: u1,
-            /// Self reception request command. Set the bit to 1 to allow a message be
-            /// transmitted and received simultaneously.
-            SELF_RX_REQ: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6002b008
-        /// Status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: The data in the RX buffer is not empty, with at least one received data
-            /// packet.
-            RX_BUF_ST: u1,
-            /// 1: The RX FIFO is full and data overrun has occurred.
-            OVERRUN_ST: u1,
-            /// 1: The TX buffer is empty, the CPU may write a message into it.
-            TX_BUF_ST: u1,
-            /// 1: The TWAI controller has successfully received a packet from the bus.
-            TX_COMPLETE: u1,
-            /// 1: The TWAI Controller is receiving a message from the bus.
-            RX_ST: u1,
-            /// 1: The TWAI Controller is transmitting a message to the bus.
-            TX_ST: u1,
-            /// 1: At least one of the RX/TX error counter has reached or exceeded the value set
-            /// in register TWAI_ERR_WARNING_LIMIT_REG.
-            ERR_ST: u1,
-            /// 1: In bus-off status, the TWAI Controller is no longer involved in bus
-            /// activities.
-            BUS_OFF_ST: u1,
-            /// This bit reflects whether the data packet in the RX FIFO is complete. 1: The
-            /// current packet is missing; 0: The current packet is complete
-            MISS_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002b00c
-        /// Interrupt Register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive interrupt. If this bit is set to 1, it indicates there are messages to
-            /// be handled in the RX FIFO.
-            RX_INT_ST: u1,
-            /// Transmit interrupt. If this bit is set to 1, it indicates the message
-            /// transmitting mis- sion is finished and a new transmission is able to execute.
-            TX_INT_ST: u1,
-            /// Error warning interrupt. If this bit is set to 1, it indicates the error status
-            /// signal and the bus-off status signal of Status register have changed (e.g.,
-            /// switched from 0 to 1 or from 1 to 0).
-            ERR_WARN_INT_ST: u1,
-            /// Data overrun interrupt. If this bit is set to 1, it indicates a data overrun
-            /// interrupt is generated in the RX FIFO.
-            OVERRUN_INT_ST: u1,
-            reserved0: u1,
-            /// Error passive interrupt. If this bit is set to 1, it indicates the TWAI
-            /// Controller is switched between error active status and error passive status due
-            /// to the change of error counters.
-            ERR_PASSIVE_INT_ST: u1,
-            /// Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration
-            /// lost interrupt is generated.
-            ARB_LOST_INT_ST: u1,
-            /// Error interrupt. If this bit is set to 1, it indicates an error is detected on
-            /// the bus.
-            BUS_ERR_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6002b010
-        /// Interrupt Enable Register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to 1 to enable receive interrupt.
-            RX_INT_ENA: u1,
-            /// Set this bit to 1 to enable transmit interrupt.
-            TX_INT_ENA: u1,
-            /// Set this bit to 1 to enable error warning interrupt.
-            ERR_WARN_INT_ENA: u1,
-            /// Set this bit to 1 to enable data overrun interrupt.
-            OVERRUN_INT_ENA: u1,
-            reserved0: u1,
-            /// Set this bit to 1 to enable error passive interrupt.
-            ERR_PASSIVE_INT_ENA: u1,
-            /// Set this bit to 1 to enable arbitration lost interrupt.
-            ARB_LOST_INT_ENA: u1,
-            /// Set this bit to 1 to enable error interrupt.
-            BUS_ERR_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6002b018
-        /// Bus Timing Register 0
-        pub const BUS_TIMING_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Baud Rate Prescaler, determines the frequency dividing ratio.
-            BAUD_PRESC: u13,
-            reserved0: u1,
-            /// Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
-            SYNC_JUMP_WIDTH: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6002b01c
-        /// Bus Timing Register 1
-        pub const BUS_TIMING_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of PBS1.
-            TIME_SEG1: u4,
-            /// The width of PBS2.
-            TIME_SEG2: u3,
-            /// The number of sample points. 0: the bus is sampled once; 1: the bus is sampled
-            /// three times
-            TIME_SAMP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6002b02c
-        /// Arbitration Lost Capture Register
-        pub const ARB_LOST_CAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
-
-        /// address: 0x6002b030
-        /// Error Code Capture Register
-        pub const ERR_CODE_CAP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register contains information about the location of errors, see Table 181
-            /// for details.
-            ECC_SEGMENT: u5,
-            /// This register contains information about transmission direction of the node when
-            /// error occurs. 1: Error occurs when receiving a message; 0: Error occurs when
-            /// transmitting a message
-            ECC_DIRECTION: u1,
-            /// This register contains information about error types: 00: bit error; 01: form
-            /// error; 10: stuff error; 11: other type of error
-            ECC_TYPE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6002b034
-        /// Error Warning Limit Register
-        pub const ERR_WARNING_LIMIT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
-
-        /// address: 0x6002b038
-        /// Receive Error Counter Register
-        pub const RX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x38);
-
-        /// address: 0x6002b03c
-        /// Transmit Error Counter Register
-        pub const TX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x3c);
-
-        /// address: 0x6002b040
-        /// Data register 0
-        pub const DATA_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 0 with R/W Permission. In
-            /// operation mode, it stores the 0th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_0: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6002b044
-        /// Data register 1
-        pub const DATA_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 1 with R/W Permission. In
-            /// operation mode, it stores the 1st byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6002b048
-        /// Data register 2
-        pub const DATA_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 2 with R/W Permission. In
-            /// operation mode, it stores the 2nd byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_2: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002b04c
-        /// Data register 3
-        pub const DATA_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 3 with R/W Permission. In
-            /// operation mode, it stores the 3rd byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_3: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x6002b050
-        /// Data register 4
-        pub const DATA_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 0 with R/W Permission. In
-            /// operation mode, it stores the 4th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_4: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6002b054
-        /// Data register 5
-        pub const DATA_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 1 with R/W Permission. In
-            /// operation mode, it stores the 5th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_5: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6002b058
-        /// Data register 6
-        pub const DATA_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 2 with R/W Permission. In
-            /// operation mode, it stores the 6th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_6: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002b05c
-        /// Data register 7
-        pub const DATA_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 3 with R/W Permission. In
-            /// operation mode, it stores the 7th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_7: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6002b060
-        /// Data register 8
-        pub const DATA_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 8th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_8: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x6002b064
-        /// Data register 9
-        pub const DATA_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 9th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_9: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x6002b068
-        /// Data register 10
-        pub const DATA_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 10th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_10: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002b06c
-        /// Data register 11
-        pub const DATA_11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 11th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_11: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6002b070
-        /// Data register 12
-        pub const DATA_12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 12th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_12: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6002b074
-        /// Receive Message Counter Register
-        pub const RX_MESSAGE_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register reflects the number of messages available within the RX FIFO.
-            RX_MESSAGE_COUNTER: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6002b07c
-        /// Clock Divider register
-        pub const CLOCK_DIVIDER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits are used to configure frequency dividing coefficients of the external
-            /// CLKOUT pin.
-            CD: u8,
-            /// This bit can be configured under reset mode. 1: Disable the external CLKOUT pin;
-            /// 0: Enable the external CLKOUT pin
-            CLOCK_OFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x7c);
-    };
-
-    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
-    pub const UART0 = struct {
-        pub const base_address = 0x60000000;
-
-        /// address: 0x60000000
-        /// FIFO data register
-        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART 0 accesses FIFO via this register.
-            RXFIFO_RD_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60000004
-        /// Raw interrupt status
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// what rxfifo_full_thrhd specifies.
-            RXFIFO_FULL_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-            /// less than what txfifo_empty_thrhd specifies .
-            TXFIFO_EMPTY_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// in the data.
-            PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error .
-            FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// the FIFO can store.
-            RXFIFO_OVF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of DSRn signal.
-            DSR_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of CTSn signal.
-            CTS_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
-            /// stop bit.
-            BRK_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver takes more time than
-            /// rx_tout_thrhd to receive a byte.
-            RXFIFO_TOUT_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XON_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XOFF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
-            /// middle of a start bit.
-            GLITCH_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter completes sending
-            /// NULL characters, after all data in Tx-FIFO are sent.
-            TX_BRK_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has kept the
-            /// shortest duration after sending the last data.
-            TX_BRK_IDLE_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has send out all
-            /// data in FIFO.
-            TX_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// from the echo of transmitter in rs485 mode.
-            RS485_PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error from the echo of transmitter in rs485 mode.
-            RS485_FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when detects a clash between
-            /// transmitter and receiver in rs485 mode.
-            RS485_CLASH_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the configured
-            /// at_cmd char.
-            AT_CMD_CHAR_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when input rxd edge changes more
-            /// times than what reg_active_threshold specifies in light sleeping mode.
-            WAKEUP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60000008
-        /// Masked interrupt status
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
-            /// to 1.
-            RXFIFO_FULL_INT_ST: u1,
-            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
-            /// to 1.
-            TXFIFO_EMPTY_INT_ST: u1,
-            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-            /// 1.
-            PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-            FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-            /// 1.
-            RXFIFO_OVF_INT_ST: u1,
-            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-            DSR_CHG_INT_ST: u1,
-            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-            CTS_CHG_INT_ST: u1,
-            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-            BRK_DET_INT_ST: u1,
-            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
-            /// to 1.
-            RXFIFO_TOUT_INT_ST: u1,
-            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-            SW_XON_INT_ST: u1,
-            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-            SW_XOFF_INT_ST: u1,
-            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-            /// 1.
-            GLITCH_DET_INT_ST: u1,
-            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
-            /// to 1.
-            TX_BRK_DONE_INT_ST: u1,
-            /// This is the stauts bit for tx_brk_idle_done_int_raw when
-            /// tx_brk_idle_done_int_ena is set to 1.
-            TX_BRK_IDLE_DONE_INT_ST: u1,
-            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-            TX_DONE_INT_ST: u1,
-            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-            /// set to 1.
-            RS485_PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
-            /// set to 1.
-            RS485_FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
-            /// to 1.
-            RS485_CLASH_INT_ST: u1,
-            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
-            /// set to 1.
-            AT_CMD_CHAR_DET_INT_ST: u1,
-            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
-            /// to 1.
-            WAKEUP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000000c
-        /// Interrupt enable bits
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the enable bit for rxfifo_full_int_st register.
-            RXFIFO_FULL_INT_ENA: u1,
-            /// This is the enable bit for txfifo_empty_int_st register.
-            TXFIFO_EMPTY_INT_ENA: u1,
-            /// This is the enable bit for parity_err_int_st register.
-            PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for frm_err_int_st register.
-            FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_ovf_int_st register.
-            RXFIFO_OVF_INT_ENA: u1,
-            /// This is the enable bit for dsr_chg_int_st register.
-            DSR_CHG_INT_ENA: u1,
-            /// This is the enable bit for cts_chg_int_st register.
-            CTS_CHG_INT_ENA: u1,
-            /// This is the enable bit for brk_det_int_st register.
-            BRK_DET_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_tout_int_st register.
-            RXFIFO_TOUT_INT_ENA: u1,
-            /// This is the enable bit for sw_xon_int_st register.
-            SW_XON_INT_ENA: u1,
-            /// This is the enable bit for sw_xoff_int_st register.
-            SW_XOFF_INT_ENA: u1,
-            /// This is the enable bit for glitch_det_int_st register.
-            GLITCH_DET_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_done_int_st register.
-            TX_BRK_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_idle_done_int_st register.
-            TX_BRK_IDLE_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_done_int_st register.
-            TX_DONE_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_clash_int_st register.
-            RS485_CLASH_INT_ENA: u1,
-            /// This is the enable bit for at_cmd_char_det_int_st register.
-            AT_CMD_CHAR_DET_INT_ENA: u1,
-            /// This is the enable bit for uart_wakeup_int_st register.
-            WAKEUP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60000010
-        /// Interrupt clear bits
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
-            RXFIFO_FULL_INT_CLR: u1,
-            /// Set this bit to clear txfifo_empty_int_raw interrupt.
-            TXFIFO_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear parity_err_int_raw interrupt.
-            PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear frm_err_int_raw interrupt.
-            FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
-            RXFIFO_OVF_INT_CLR: u1,
-            /// Set this bit to clear the dsr_chg_int_raw interrupt.
-            DSR_CHG_INT_CLR: u1,
-            /// Set this bit to clear the cts_chg_int_raw interrupt.
-            CTS_CHG_INT_CLR: u1,
-            /// Set this bit to clear the brk_det_int_raw interrupt.
-            BRK_DET_INT_CLR: u1,
-            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
-            RXFIFO_TOUT_INT_CLR: u1,
-            /// Set this bit to clear the sw_xon_int_raw interrupt.
-            SW_XON_INT_CLR: u1,
-            /// Set this bit to clear the sw_xoff_int_raw interrupt.
-            SW_XOFF_INT_CLR: u1,
-            /// Set this bit to clear the glitch_det_int_raw interrupt.
-            GLITCH_DET_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
-            TX_BRK_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-            TX_BRK_IDLE_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_done_int_raw interrupt.
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
-            RS485_PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
-            RS485_FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_clash_int_raw interrupt.
-            RS485_CLASH_INT_CLR: u1,
-            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-            AT_CMD_CHAR_DET_INT_CLR: u1,
-            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
-            WAKEUP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60000014
-        /// Clock divider configuration
-        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integral part of the frequency divider factor.
-            CLKDIV: u12,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// The decimal part of the frequency divider factor.
-            FRAG: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60000018
-        /// Rx Filter configuration
-        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// when input pulse width is lower than this value, the pulse is ignored.
-            GLITCH_FILT: u8,
-            /// Set this bit to enable Rx signal filter.
-            GLITCH_FILT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000001c
-        /// UART status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the byte number of valid data in Rx-FIFO.
-            RXFIFO_CNT: u10,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The register represent the level value of the internal uart dsr signal.
-            DSRN: u1,
-            /// This register represent the level value of the internal uart cts signal.
-            CTSN: u1,
-            /// This register represent the level value of the internal uart rxd signal.
-            RXD: u1,
-            /// Stores the byte number of data in Tx-FIFO.
-            TXFIFO_CNT: u10,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// This bit represents the level of the internal uart dtr signal.
-            DTRN: u1,
-            /// This bit represents the level of the internal uart rts signal.
-            RTSN: u1,
-            /// This bit represents the level of the internal uart txd signal.
-            TXD: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60000020
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the parity check mode.
-            PARITY: u1,
-            /// Set this bit to enable uart parity check.
-            PARITY_EN: u1,
-            /// This register is used to set the length of data.
-            BIT_NUM: u2,
-            /// This register is used to set the length of stop bit.
-            STOP_BIT_NUM: u2,
-            /// This register is used to configure the software rts signal which is used in
-            /// software flow control.
-            SW_RTS: u1,
-            /// This register is used to configure the software dtr signal which is used in
-            /// software flow control.
-            SW_DTR: u1,
-            /// Set this bit to enbale transmitter to send NULL when the process of sending data
-            /// is done.
-            TXD_BRK: u1,
-            /// Set this bit to enable IrDA loopback mode.
-            IRDA_DPLX: u1,
-            /// This is the start enable bit for IrDA transmitter.
-            IRDA_TX_EN: u1,
-            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-            /// transmitter's 11th bit to 0.
-            IRDA_WCTL: u1,
-            /// Set this bit to invert the level of IrDA transmitter.
-            IRDA_TX_INV: u1,
-            /// Set this bit to invert the level of IrDA receiver.
-            IRDA_RX_INV: u1,
-            /// Set this bit to enable uart loopback test mode.
-            LOOPBACK: u1,
-            /// Set this bit to enable flow control function for transmitter.
-            TX_FLOW_EN: u1,
-            /// Set this bit to enable IrDA protocol.
-            IRDA_EN: u1,
-            /// Set this bit to reset the uart receive-FIFO.
-            RXFIFO_RST: u1,
-            /// Set this bit to reset the uart transmit-FIFO.
-            TXFIFO_RST: u1,
-            /// Set this bit to inverse the level value of uart rxd signal.
-            RXD_INV: u1,
-            /// Set this bit to inverse the level value of uart cts signal.
-            CTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dsr signal.
-            DSR_INV: u1,
-            /// Set this bit to inverse the level value of uart txd signal.
-            TXD_INV: u1,
-            /// Set this bit to inverse the level value of uart rts signal.
-            RTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dtr signal.
-            DTR_INV: u1,
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-            /// stores the data even if the received data is wrong.
-            ERR_WR_MASK: u1,
-            /// This is the enable bit for detecting baudrate.
-            AUTOBAUD_EN: u1,
-            /// UART memory clock gate enable signal.
-            MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60000024
-        /// Configuration register 1
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
-            /// this register value.
-            RXFIFO_FULL_THRHD: u9,
-            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
-            /// less than this register value.
-            TXFIFO_EMPTY_THRHD: u9,
-            /// Disable UART Rx data overflow detect.
-            DIS_RX_DAT_OVF: u1,
-            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
-            RX_TOUT_FLOW_DIS: u1,
-            /// This is the flow enable bit for UART receiver.
-            RX_FLOW_EN: u1,
-            /// This is the enble bit for uart receiver's timeout function.
-            RX_TOUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60000028
-        /// Autobaud minimum low pulse duration register
-        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the minimum duration time of the low level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000002c
-        /// Autobaud minimum high pulse duration register
-        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the maxinum duration time for the high level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60000030
-        /// Autobaud edge change count register
-        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the count of rxd edge change. It is used in baud
-            /// rate-detect process.
-            RXD_EDGE_CNT: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60000034
-        /// Software flow-control configuration
-        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable software flow control. It is used with register sw_xon or
-            /// sw_xoff.
-            SW_FLOW_CON_EN: u1,
-            /// Set this bit to remove flow control char from the received data.
-            XONOFF_DEL: u1,
-            /// Set this bit to enable the transmitter to go on sending data.
-            FORCE_XON: u1,
-            /// Set this bit to stop the transmitter from sending data.
-            FORCE_XOFF: u1,
-            /// Set this bit to send Xon char. It is cleared by hardware automatically.
-            SEND_XON: u1,
-            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
-            SEND_XOFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60000038
-        /// Sleep-mode configuration
-        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The uart is activated from light sleeping mode when the input rxd edge changes
-            /// more times than this register value.
-            ACTIVE_THRESHOLD: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000003c
-        /// Software flow-control character configuration
-        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is more than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
-            XOFF_THRESHOLD: u9,
-            /// This register stores the Xoff flow control char.
-            XOFF_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60000040
-        /// Software flow-control character configuration
-        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is less than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
-            XON_THRESHOLD: u9,
-            /// This register stores the Xon flow control char.
-            XON_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60000044
-        /// Tx Break character configuration
-        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the number of 0 to be sent after the process
-            /// of sending data is done. It is active when txd_brk is set to 1.
-            TX_BRK_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60000048
-        /// Frame-end idle configuration
-        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce frame end signal when receiver takes more time to receive one
-            /// byte data than this register value.
-            RX_IDLE_THRHD: u10,
-            /// This register is used to configure the duration time between transfers.
-            TX_IDLE_NUM: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000004c
-        /// RS485 mode configuration
-        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to choose the rs485 mode.
-            RS485_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL0_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL1_EN: u1,
-            /// Set this bit to enable receiver could receive data when the transmitter is
-            /// transmitting data in rs485 mode.
-            RS485TX_RX_EN: u1,
-            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-            RS485RXBY_TX_EN: u1,
-            /// This register is used to delay the receiver's internal data signal.
-            RS485_RX_DLY_NUM: u1,
-            /// This register is used to delay the transmitter's internal data signal.
-            RS485_TX_DLY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60000050
-        /// Pre-sequence timing configuration
-        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the idle duration time before the first
-            /// at_cmd is received by receiver.
-            PRE_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60000054
-        /// Post-sequence timing configuration
-        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the last at_cmd and
-            /// the next data.
-            POST_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60000058
-        /// Timeout configuration
-        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the at_cmd chars.
-            RX_GAP_TOUT: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6000005c
-        /// AT escape sequence detection configuration
-        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the content of at_cmd char.
-            AT_CMD_CHAR: u8,
-            /// This register is used to configure the num of continuous at_cmd chars received
-            /// by receiver.
-            CHAR_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60000060
-        /// UART threshold and allocation configuration
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// This register is used to configure the amount of mem allocated for receive-FIFO.
-            /// The default number is 128 bytes.
-            RX_SIZE: u3,
-            /// This register is used to configure the amount of mem allocated for
-            /// transmit-FIFO. The default number is 128 bytes.
-            TX_SIZE: u3,
-            /// This register is used to configure the maximum amount of data that can be
-            /// received when hardware flow control works.
-            RX_FLOW_THRHD: u9,
-            /// This register is used to configure the threshold time that receiver takes to
-            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
-            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
-            RX_TOUT_THRHD: u10,
-            /// Set this bit to force power down UART memory.
-            MEM_FORCE_PD: u1,
-            /// Set this bit to force power up UART memory.
-            MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60000064
-        /// Tx-FIFO write and read offset address.
-        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-            /// via APB.
-            APB_TX_WADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
-            /// Tx-FIFO_Ctrl.
-            TX_RADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60000068
-        /// Rx-FIFO write and read offset address.
-        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in RX-FIFO when software reads data from
-            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-            APB_RX_RADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
-            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-            RX_WADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6000006c
-        /// UART transmit and receive status.
-        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status register of receiver.
-            ST_URX_OUT: u4,
-            /// This is the status register of transmitter.
-            ST_UTX_OUT: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60000070
-        /// Autobaud high pulse register
-        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two positive edges.
-            /// It is used in boudrate-detect process.
-            POSEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60000074
-        /// Autobaud low pulse register
-        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two negative edges.
-            /// It is used in boudrate-detect process.
-            NEGEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60000078
-        /// UART core clock configuration
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The denominator of the frequency divider factor.
-            SCLK_DIV_B: u6,
-            /// The numerator of the frequency divider factor.
-            SCLK_DIV_A: u6,
-            /// The integral part of the frequency divider factor.
-            SCLK_DIV_NUM: u8,
-            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-            SCLK_SEL: u2,
-            /// Set this bit to enable UART Tx/Rx clock.
-            SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
-            RST_CORE: u1,
-            /// Set this bit to enable UART Tx clock.
-            TX_SCLK_EN: u1,
-            /// Set this bit to enable UART Rx clock.
-            RX_SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx.
-            TX_RST_CORE: u1,
-            /// Write 1 then write 0 to this bit, reset UART Rx.
-            RX_RST_CORE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000007c
-        /// UART Version register
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x60000080
-        /// UART ID register
-        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the uart_id.
-            ID: u30,
-            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
-            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
-            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
-            /// synchronize registers.
-            HIGH_SPEED: u1,
-            /// Software write 1 would synchronize registers into UART Core clock domain and
-            /// would be cleared by hardware after synchronization is done.
-            REG_UPDATE: u1,
-        }), base_address + 0x80);
-    };
-
-    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
-    pub const UART1 = struct {
-        pub const base_address = 0x60010000;
-
-        /// address: 0x60010000
-        /// FIFO data register
-        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART 0 accesses FIFO via this register.
-            RXFIFO_RD_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60010004
-        /// Raw interrupt status
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// what rxfifo_full_thrhd specifies.
-            RXFIFO_FULL_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-            /// less than what txfifo_empty_thrhd specifies .
-            TXFIFO_EMPTY_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// in the data.
-            PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error .
-            FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// the FIFO can store.
-            RXFIFO_OVF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of DSRn signal.
-            DSR_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of CTSn signal.
-            CTS_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
-            /// stop bit.
-            BRK_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver takes more time than
-            /// rx_tout_thrhd to receive a byte.
-            RXFIFO_TOUT_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XON_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XOFF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
-            /// middle of a start bit.
-            GLITCH_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter completes sending
-            /// NULL characters, after all data in Tx-FIFO are sent.
-            TX_BRK_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has kept the
-            /// shortest duration after sending the last data.
-            TX_BRK_IDLE_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has send out all
-            /// data in FIFO.
-            TX_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// from the echo of transmitter in rs485 mode.
-            RS485_PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error from the echo of transmitter in rs485 mode.
-            RS485_FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when detects a clash between
-            /// transmitter and receiver in rs485 mode.
-            RS485_CLASH_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the configured
-            /// at_cmd char.
-            AT_CMD_CHAR_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when input rxd edge changes more
-            /// times than what reg_active_threshold specifies in light sleeping mode.
-            WAKEUP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60010008
-        /// Masked interrupt status
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
-            /// to 1.
-            RXFIFO_FULL_INT_ST: u1,
-            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
-            /// to 1.
-            TXFIFO_EMPTY_INT_ST: u1,
-            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-            /// 1.
-            PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-            FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-            /// 1.
-            RXFIFO_OVF_INT_ST: u1,
-            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-            DSR_CHG_INT_ST: u1,
-            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-            CTS_CHG_INT_ST: u1,
-            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-            BRK_DET_INT_ST: u1,
-            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
-            /// to 1.
-            RXFIFO_TOUT_INT_ST: u1,
-            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-            SW_XON_INT_ST: u1,
-            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-            SW_XOFF_INT_ST: u1,
-            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-            /// 1.
-            GLITCH_DET_INT_ST: u1,
-            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
-            /// to 1.
-            TX_BRK_DONE_INT_ST: u1,
-            /// This is the stauts bit for tx_brk_idle_done_int_raw when
-            /// tx_brk_idle_done_int_ena is set to 1.
-            TX_BRK_IDLE_DONE_INT_ST: u1,
-            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-            TX_DONE_INT_ST: u1,
-            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-            /// set to 1.
-            RS485_PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
-            /// set to 1.
-            RS485_FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
-            /// to 1.
-            RS485_CLASH_INT_ST: u1,
-            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
-            /// set to 1.
-            AT_CMD_CHAR_DET_INT_ST: u1,
-            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
-            /// to 1.
-            WAKEUP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001000c
-        /// Interrupt enable bits
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the enable bit for rxfifo_full_int_st register.
-            RXFIFO_FULL_INT_ENA: u1,
-            /// This is the enable bit for txfifo_empty_int_st register.
-            TXFIFO_EMPTY_INT_ENA: u1,
-            /// This is the enable bit for parity_err_int_st register.
-            PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for frm_err_int_st register.
-            FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_ovf_int_st register.
-            RXFIFO_OVF_INT_ENA: u1,
-            /// This is the enable bit for dsr_chg_int_st register.
-            DSR_CHG_INT_ENA: u1,
-            /// This is the enable bit for cts_chg_int_st register.
-            CTS_CHG_INT_ENA: u1,
-            /// This is the enable bit for brk_det_int_st register.
-            BRK_DET_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_tout_int_st register.
-            RXFIFO_TOUT_INT_ENA: u1,
-            /// This is the enable bit for sw_xon_int_st register.
-            SW_XON_INT_ENA: u1,
-            /// This is the enable bit for sw_xoff_int_st register.
-            SW_XOFF_INT_ENA: u1,
-            /// This is the enable bit for glitch_det_int_st register.
-            GLITCH_DET_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_done_int_st register.
-            TX_BRK_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_idle_done_int_st register.
-            TX_BRK_IDLE_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_done_int_st register.
-            TX_DONE_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_clash_int_st register.
-            RS485_CLASH_INT_ENA: u1,
-            /// This is the enable bit for at_cmd_char_det_int_st register.
-            AT_CMD_CHAR_DET_INT_ENA: u1,
-            /// This is the enable bit for uart_wakeup_int_st register.
-            WAKEUP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60010010
-        /// Interrupt clear bits
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
-            RXFIFO_FULL_INT_CLR: u1,
-            /// Set this bit to clear txfifo_empty_int_raw interrupt.
-            TXFIFO_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear parity_err_int_raw interrupt.
-            PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear frm_err_int_raw interrupt.
-            FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
-            RXFIFO_OVF_INT_CLR: u1,
-            /// Set this bit to clear the dsr_chg_int_raw interrupt.
-            DSR_CHG_INT_CLR: u1,
-            /// Set this bit to clear the cts_chg_int_raw interrupt.
-            CTS_CHG_INT_CLR: u1,
-            /// Set this bit to clear the brk_det_int_raw interrupt.
-            BRK_DET_INT_CLR: u1,
-            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
-            RXFIFO_TOUT_INT_CLR: u1,
-            /// Set this bit to clear the sw_xon_int_raw interrupt.
-            SW_XON_INT_CLR: u1,
-            /// Set this bit to clear the sw_xoff_int_raw interrupt.
-            SW_XOFF_INT_CLR: u1,
-            /// Set this bit to clear the glitch_det_int_raw interrupt.
-            GLITCH_DET_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
-            TX_BRK_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-            TX_BRK_IDLE_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_done_int_raw interrupt.
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
-            RS485_PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
-            RS485_FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_clash_int_raw interrupt.
-            RS485_CLASH_INT_CLR: u1,
-            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-            AT_CMD_CHAR_DET_INT_CLR: u1,
-            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
-            WAKEUP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60010014
-        /// Clock divider configuration
-        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integral part of the frequency divider factor.
-            CLKDIV: u12,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// The decimal part of the frequency divider factor.
-            FRAG: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60010018
-        /// Rx Filter configuration
-        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// when input pulse width is lower than this value, the pulse is ignored.
-            GLITCH_FILT: u8,
-            /// Set this bit to enable Rx signal filter.
-            GLITCH_FILT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001001c
-        /// UART status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the byte number of valid data in Rx-FIFO.
-            RXFIFO_CNT: u10,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The register represent the level value of the internal uart dsr signal.
-            DSRN: u1,
-            /// This register represent the level value of the internal uart cts signal.
-            CTSN: u1,
-            /// This register represent the level value of the internal uart rxd signal.
-            RXD: u1,
-            /// Stores the byte number of data in Tx-FIFO.
-            TXFIFO_CNT: u10,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// This bit represents the level of the internal uart dtr signal.
-            DTRN: u1,
-            /// This bit represents the level of the internal uart rts signal.
-            RTSN: u1,
-            /// This bit represents the level of the internal uart txd signal.
-            TXD: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60010020
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the parity check mode.
-            PARITY: u1,
-            /// Set this bit to enable uart parity check.
-            PARITY_EN: u1,
-            /// This register is used to set the length of data.
-            BIT_NUM: u2,
-            /// This register is used to set the length of stop bit.
-            STOP_BIT_NUM: u2,
-            /// This register is used to configure the software rts signal which is used in
-            /// software flow control.
-            SW_RTS: u1,
-            /// This register is used to configure the software dtr signal which is used in
-            /// software flow control.
-            SW_DTR: u1,
-            /// Set this bit to enbale transmitter to send NULL when the process of sending data
-            /// is done.
-            TXD_BRK: u1,
-            /// Set this bit to enable IrDA loopback mode.
-            IRDA_DPLX: u1,
-            /// This is the start enable bit for IrDA transmitter.
-            IRDA_TX_EN: u1,
-            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-            /// transmitter's 11th bit to 0.
-            IRDA_WCTL: u1,
-            /// Set this bit to invert the level of IrDA transmitter.
-            IRDA_TX_INV: u1,
-            /// Set this bit to invert the level of IrDA receiver.
-            IRDA_RX_INV: u1,
-            /// Set this bit to enable uart loopback test mode.
-            LOOPBACK: u1,
-            /// Set this bit to enable flow control function for transmitter.
-            TX_FLOW_EN: u1,
-            /// Set this bit to enable IrDA protocol.
-            IRDA_EN: u1,
-            /// Set this bit to reset the uart receive-FIFO.
-            RXFIFO_RST: u1,
-            /// Set this bit to reset the uart transmit-FIFO.
-            TXFIFO_RST: u1,
-            /// Set this bit to inverse the level value of uart rxd signal.
-            RXD_INV: u1,
-            /// Set this bit to inverse the level value of uart cts signal.
-            CTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dsr signal.
-            DSR_INV: u1,
-            /// Set this bit to inverse the level value of uart txd signal.
-            TXD_INV: u1,
-            /// Set this bit to inverse the level value of uart rts signal.
-            RTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dtr signal.
-            DTR_INV: u1,
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-            /// stores the data even if the received data is wrong.
-            ERR_WR_MASK: u1,
-            /// This is the enable bit for detecting baudrate.
-            AUTOBAUD_EN: u1,
-            /// UART memory clock gate enable signal.
-            MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60010024
-        /// Configuration register 1
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
-            /// this register value.
-            RXFIFO_FULL_THRHD: u9,
-            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
-            /// less than this register value.
-            TXFIFO_EMPTY_THRHD: u9,
-            /// Disable UART Rx data overflow detect.
-            DIS_RX_DAT_OVF: u1,
-            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
-            RX_TOUT_FLOW_DIS: u1,
-            /// This is the flow enable bit for UART receiver.
-            RX_FLOW_EN: u1,
-            /// This is the enble bit for uart receiver's timeout function.
-            RX_TOUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60010028
-        /// Autobaud minimum low pulse duration register
-        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the minimum duration time of the low level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001002c
-        /// Autobaud minimum high pulse duration register
-        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the maxinum duration time for the high level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60010030
-        /// Autobaud edge change count register
-        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the count of rxd edge change. It is used in baud
-            /// rate-detect process.
-            RXD_EDGE_CNT: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60010034
-        /// Software flow-control configuration
-        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable software flow control. It is used with register sw_xon or
-            /// sw_xoff.
-            SW_FLOW_CON_EN: u1,
-            /// Set this bit to remove flow control char from the received data.
-            XONOFF_DEL: u1,
-            /// Set this bit to enable the transmitter to go on sending data.
-            FORCE_XON: u1,
-            /// Set this bit to stop the transmitter from sending data.
-            FORCE_XOFF: u1,
-            /// Set this bit to send Xon char. It is cleared by hardware automatically.
-            SEND_XON: u1,
-            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
-            SEND_XOFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60010038
-        /// Sleep-mode configuration
-        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The uart is activated from light sleeping mode when the input rxd edge changes
-            /// more times than this register value.
-            ACTIVE_THRESHOLD: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001003c
-        /// Software flow-control character configuration
-        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is more than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
-            XOFF_THRESHOLD: u9,
-            /// This register stores the Xoff flow control char.
-            XOFF_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60010040
-        /// Software flow-control character configuration
-        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is less than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
-            XON_THRESHOLD: u9,
-            /// This register stores the Xon flow control char.
-            XON_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60010044
-        /// Tx Break character configuration
-        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the number of 0 to be sent after the process
-            /// of sending data is done. It is active when txd_brk is set to 1.
-            TX_BRK_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60010048
-        /// Frame-end idle configuration
-        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce frame end signal when receiver takes more time to receive one
-            /// byte data than this register value.
-            RX_IDLE_THRHD: u10,
-            /// This register is used to configure the duration time between transfers.
-            TX_IDLE_NUM: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001004c
-        /// RS485 mode configuration
-        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to choose the rs485 mode.
-            RS485_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL0_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL1_EN: u1,
-            /// Set this bit to enable receiver could receive data when the transmitter is
-            /// transmitting data in rs485 mode.
-            RS485TX_RX_EN: u1,
-            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-            RS485RXBY_TX_EN: u1,
-            /// This register is used to delay the receiver's internal data signal.
-            RS485_RX_DLY_NUM: u1,
-            /// This register is used to delay the transmitter's internal data signal.
-            RS485_TX_DLY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60010050
-        /// Pre-sequence timing configuration
-        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the idle duration time before the first
-            /// at_cmd is received by receiver.
-            PRE_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60010054
-        /// Post-sequence timing configuration
-        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the last at_cmd and
-            /// the next data.
-            POST_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60010058
-        /// Timeout configuration
-        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the at_cmd chars.
-            RX_GAP_TOUT: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001005c
-        /// AT escape sequence detection configuration
-        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the content of at_cmd char.
-            AT_CMD_CHAR: u8,
-            /// This register is used to configure the num of continuous at_cmd chars received
-            /// by receiver.
-            CHAR_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60010060
-        /// UART threshold and allocation configuration
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// This register is used to configure the amount of mem allocated for receive-FIFO.
-            /// The default number is 128 bytes.
-            RX_SIZE: u3,
-            /// This register is used to configure the amount of mem allocated for
-            /// transmit-FIFO. The default number is 128 bytes.
-            TX_SIZE: u3,
-            /// This register is used to configure the maximum amount of data that can be
-            /// received when hardware flow control works.
-            RX_FLOW_THRHD: u9,
-            /// This register is used to configure the threshold time that receiver takes to
-            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
-            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
-            RX_TOUT_THRHD: u10,
-            /// Set this bit to force power down UART memory.
-            MEM_FORCE_PD: u1,
-            /// Set this bit to force power up UART memory.
-            MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60010064
-        /// Tx-FIFO write and read offset address.
-        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-            /// via APB.
-            APB_TX_WADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
-            /// Tx-FIFO_Ctrl.
-            TX_RADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60010068
-        /// Rx-FIFO write and read offset address.
-        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in RX-FIFO when software reads data from
-            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-            APB_RX_RADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
-            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-            RX_WADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001006c
-        /// UART transmit and receive status.
-        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status register of receiver.
-            ST_URX_OUT: u4,
-            /// This is the status register of transmitter.
-            ST_UTX_OUT: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60010070
-        /// Autobaud high pulse register
-        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two positive edges.
-            /// It is used in boudrate-detect process.
-            POSEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60010074
-        /// Autobaud low pulse register
-        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two negative edges.
-            /// It is used in boudrate-detect process.
-            NEGEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60010078
-        /// UART core clock configuration
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The denominator of the frequency divider factor.
-            SCLK_DIV_B: u6,
-            /// The numerator of the frequency divider factor.
-            SCLK_DIV_A: u6,
-            /// The integral part of the frequency divider factor.
-            SCLK_DIV_NUM: u8,
-            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-            SCLK_SEL: u2,
-            /// Set this bit to enable UART Tx/Rx clock.
-            SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
-            RST_CORE: u1,
-            /// Set this bit to enable UART Tx clock.
-            TX_SCLK_EN: u1,
-            /// Set this bit to enable UART Rx clock.
-            RX_SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx.
-            TX_RST_CORE: u1,
-            /// Write 1 then write 0 to this bit, reset UART Rx.
-            RX_RST_CORE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001007c
-        /// UART Version register
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x60010080
-        /// UART ID register
-        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the uart_id.
-            ID: u30,
-            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
-            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
-            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
-            /// synchronize registers.
-            HIGH_SPEED: u1,
-            /// Software write 1 would synchronize registers into UART Core clock domain and
-            /// would be cleared by hardware after synchronization is done.
-            REG_UPDATE: u1,
-        }), base_address + 0x80);
-    };
-
-    /// Universal Host Controller Interface
-    pub const UHCI0 = struct {
-        pub const base_address = 0x60014000;
-
-        /// address: 0x60014000
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write 1, then write 0 to this bit to reset decode state machine.
-            TX_RST: u1,
-            /// Write 1, then write 0 to this bit to reset encode state machine.
-            RX_RST: u1,
-            /// Set this bit to link up HCI and UART0.
-            UART0_CE: u1,
-            /// Set this bit to link up HCI and UART1.
-            UART1_CE: u1,
-            reserved0: u1,
-            /// Set this bit to separate the data frame using a special char.
-            SEPER_EN: u1,
-            /// Set this bit to encode the data packet with a formatting header.
-            HEAD_EN: u1,
-            /// Set this bit to enable UHCI to receive the 16 bit CRC.
-            CRC_REC_EN: u1,
-            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
-            /// has been in idle state.
-            UART_IDLE_EOF_EN: u1,
-            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
-            /// receiving byte count has reached the specified value. The value is payload
-            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
-            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
-            /// decoder receiving payload data is end when 0xc0 is received.
-            LEN_EOF_EN: u1,
-            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
-            /// to end of the payload.
-            ENCODE_CRC_EN: u1,
-            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
-            /// is received by UART.
-            UART_RX_BRK_EOF_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60014004
-        /// a
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_RAW: u1,
-            /// a
-            TX_START_INT_RAW: u1,
-            /// a
-            RX_HUNG_INT_RAW: u1,
-            /// a
-            TX_HUNG_INT_RAW: u1,
-            /// a
-            SEND_S_REG_Q_INT_RAW: u1,
-            /// a
-            SEND_A_REG_Q_INT_RAW: u1,
-            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
-            /// the
-            OUT_EOF_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL0_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60014008
-        /// a
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ST: u1,
-            /// a
-            TX_START_INT_ST: u1,
-            /// a
-            RX_HUNG_INT_ST: u1,
-            /// a
-            TX_HUNG_INT_ST: u1,
-            /// a
-            SEND_S_REG_Q_INT_ST: u1,
-            /// a
-            SEND_A_REG_Q_INT_ST: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ST: u1,
-            /// a
-            APP_CTRL0_INT_ST: u1,
-            /// a
-            APP_CTRL1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001400c
-        /// a
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ENA: u1,
-            /// a
-            TX_START_INT_ENA: u1,
-            /// a
-            RX_HUNG_INT_ENA: u1,
-            /// a
-            TX_HUNG_INT_ENA: u1,
-            /// a
-            SEND_S_REG_Q_INT_ENA: u1,
-            /// a
-            SEND_A_REG_Q_INT_ENA: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ENA: u1,
-            /// a
-            APP_CTRL0_INT_ENA: u1,
-            /// a
-            APP_CTRL1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60014010
-        /// a
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_CLR: u1,
-            /// a
-            TX_START_INT_CLR: u1,
-            /// a
-            RX_HUNG_INT_CLR: u1,
-            /// a
-            TX_HUNG_INT_CLR: u1,
-            /// a
-            SEND_S_REG_Q_INT_CLR: u1,
-            /// a
-            SEND_A_REG_Q_INT_CLR: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_CLR: u1,
-            /// a
-            APP_CTRL0_INT_CLR: u1,
-            /// a
-            APP_CTRL1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60014014
-        /// a
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            CHECK_SUM_EN: u1,
-            /// a
-            CHECK_SEQ_EN: u1,
-            /// a
-            CRC_DISABLE: u1,
-            /// a
-            SAVE_HEAD: u1,
-            /// a
-            TX_CHECK_SUM_RE: u1,
-            /// a
-            TX_ACK_NUM_RE: u1,
-            reserved0: u1,
-            /// a
-            WAIT_SW_START: u1,
-            /// a
-            SW_START: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60014018
-        /// a
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_ERR_CAUSE: u3,
-            /// a
-            DECODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001401c
-        /// a
-        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ENCODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60014020
-        /// a
-        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TX_C0_ESC_EN: u1,
-            /// a
-            TX_DB_ESC_EN: u1,
-            /// a
-            TX_11_ESC_EN: u1,
-            /// a
-            TX_13_ESC_EN: u1,
-            /// a
-            RX_C0_ESC_EN: u1,
-            /// a
-            RX_DB_ESC_EN: u1,
-            /// a
-            RX_11_ESC_EN: u1,
-            /// a
-            RX_13_ESC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60014024
-        /// a
-        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TXFIFO_TIMEOUT: u8,
-            /// a
-            TXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            TXFIFO_TIMEOUT_ENA: u1,
-            /// a
-            RXFIFO_TIMEOUT: u8,
-            /// a
-            RXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            RXFIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60014028
-        /// a
-        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ACK_NUM: u3,
-            /// a
-            LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001402c
-        /// a
-        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x60014030
-        /// a
-        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SINGLE_SEND_NUM: u3,
-            /// a
-            SINGLE_SEND_EN: u1,
-            /// a
-            ALWAYS_SEND_NUM: u3,
-            /// a
-            ALWAYS_SEND_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60014034
-        /// a
-        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD0: u32,
-        }), base_address + 0x34);
-
-        /// address: 0x60014038
-        /// a
-        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD1: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6001403c
-        /// a
-        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD0: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x60014040
-        /// a
-        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD1: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x60014044
-        /// a
-        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60014048
-        /// a
-        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD1: u32,
-        }), base_address + 0x48);
-
-        /// address: 0x6001404c
-        /// a
-        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD0: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60014050
-        /// a
-        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD1: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60014054
-        /// a
-        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD0: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60014058
-        /// a
-        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD1: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6001405c
-        /// a
-        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60014060
-        /// a
-        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60014064
-        /// a
-        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD0: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60014068
-        /// a
-        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD1: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6001406c
-        /// a
-        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEPER_CHAR: u8,
-            /// a
-            SEPER_ESC_CHAR0: u8,
-            /// a
-            SEPER_ESC_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60014070
-        /// a
-        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ0: u8,
-            /// a
-            ESC_SEQ0_CHAR0: u8,
-            /// a
-            ESC_SEQ0_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60014074
-        /// a
-        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ1: u8,
-            /// a
-            ESC_SEQ1_CHAR0: u8,
-            /// a
-            ESC_SEQ1_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60014078
-        /// a
-        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ2: u8,
-            /// a
-            ESC_SEQ2_CHAR0: u8,
-            /// a
-            ESC_SEQ2_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001407c
-        /// a
-        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            PKT_THRS: u13,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60014080
-        /// a
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// Universal Host Controller Interface
-    pub const UHCI1 = struct {
-        pub const base_address = 0x6000c000;
-
-        /// address: 0x6000c000
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write 1, then write 0 to this bit to reset decode state machine.
-            TX_RST: u1,
-            /// Write 1, then write 0 to this bit to reset encode state machine.
-            RX_RST: u1,
-            /// Set this bit to link up HCI and UART0.
-            UART0_CE: u1,
-            /// Set this bit to link up HCI and UART1.
-            UART1_CE: u1,
-            reserved0: u1,
-            /// Set this bit to separate the data frame using a special char.
-            SEPER_EN: u1,
-            /// Set this bit to encode the data packet with a formatting header.
-            HEAD_EN: u1,
-            /// Set this bit to enable UHCI to receive the 16 bit CRC.
-            CRC_REC_EN: u1,
-            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
-            /// has been in idle state.
-            UART_IDLE_EOF_EN: u1,
-            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
-            /// receiving byte count has reached the specified value. The value is payload
-            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
-            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
-            /// decoder receiving payload data is end when 0xc0 is received.
-            LEN_EOF_EN: u1,
-            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
-            /// to end of the payload.
-            ENCODE_CRC_EN: u1,
-            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
-            /// is received by UART.
-            UART_RX_BRK_EOF_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6000c004
-        /// a
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_RAW: u1,
-            /// a
-            TX_START_INT_RAW: u1,
-            /// a
-            RX_HUNG_INT_RAW: u1,
-            /// a
-            TX_HUNG_INT_RAW: u1,
-            /// a
-            SEND_S_REG_Q_INT_RAW: u1,
-            /// a
-            SEND_A_REG_Q_INT_RAW: u1,
-            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
-            /// the
-            OUT_EOF_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL0_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6000c008
-        /// a
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ST: u1,
-            /// a
-            TX_START_INT_ST: u1,
-            /// a
-            RX_HUNG_INT_ST: u1,
-            /// a
-            TX_HUNG_INT_ST: u1,
-            /// a
-            SEND_S_REG_Q_INT_ST: u1,
-            /// a
-            SEND_A_REG_Q_INT_ST: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ST: u1,
-            /// a
-            APP_CTRL0_INT_ST: u1,
-            /// a
-            APP_CTRL1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000c00c
-        /// a
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ENA: u1,
-            /// a
-            TX_START_INT_ENA: u1,
-            /// a
-            RX_HUNG_INT_ENA: u1,
-            /// a
-            TX_HUNG_INT_ENA: u1,
-            /// a
-            SEND_S_REG_Q_INT_ENA: u1,
-            /// a
-            SEND_A_REG_Q_INT_ENA: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ENA: u1,
-            /// a
-            APP_CTRL0_INT_ENA: u1,
-            /// a
-            APP_CTRL1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6000c010
-        /// a
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_CLR: u1,
-            /// a
-            TX_START_INT_CLR: u1,
-            /// a
-            RX_HUNG_INT_CLR: u1,
-            /// a
-            TX_HUNG_INT_CLR: u1,
-            /// a
-            SEND_S_REG_Q_INT_CLR: u1,
-            /// a
-            SEND_A_REG_Q_INT_CLR: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_CLR: u1,
-            /// a
-            APP_CTRL0_INT_CLR: u1,
-            /// a
-            APP_CTRL1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6000c014
-        /// a
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            CHECK_SUM_EN: u1,
-            /// a
-            CHECK_SEQ_EN: u1,
-            /// a
-            CRC_DISABLE: u1,
-            /// a
-            SAVE_HEAD: u1,
-            /// a
-            TX_CHECK_SUM_RE: u1,
-            /// a
-            TX_ACK_NUM_RE: u1,
-            reserved0: u1,
-            /// a
-            WAIT_SW_START: u1,
-            /// a
-            SW_START: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6000c018
-        /// a
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_ERR_CAUSE: u3,
-            /// a
-            DECODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000c01c
-        /// a
-        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ENCODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6000c020
-        /// a
-        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TX_C0_ESC_EN: u1,
-            /// a
-            TX_DB_ESC_EN: u1,
-            /// a
-            TX_11_ESC_EN: u1,
-            /// a
-            TX_13_ESC_EN: u1,
-            /// a
-            RX_C0_ESC_EN: u1,
-            /// a
-            RX_DB_ESC_EN: u1,
-            /// a
-            RX_11_ESC_EN: u1,
-            /// a
-            RX_13_ESC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6000c024
-        /// a
-        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TXFIFO_TIMEOUT: u8,
-            /// a
-            TXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            TXFIFO_TIMEOUT_ENA: u1,
-            /// a
-            RXFIFO_TIMEOUT: u8,
-            /// a
-            RXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            RXFIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6000c028
-        /// a
-        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ACK_NUM: u3,
-            /// a
-            LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000c02c
-        /// a
-        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x6000c030
-        /// a
-        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SINGLE_SEND_NUM: u3,
-            /// a
-            SINGLE_SEND_EN: u1,
-            /// a
-            ALWAYS_SEND_NUM: u3,
-            /// a
-            ALWAYS_SEND_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6000c034
-        /// a
-        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD0: u32,
-        }), base_address + 0x34);
-
-        /// address: 0x6000c038
-        /// a
-        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD1: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6000c03c
-        /// a
-        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD0: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x6000c040
-        /// a
-        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD1: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x6000c044
-        /// a
-        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x6000c048
-        /// a
-        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD1: u32,
-        }), base_address + 0x48);
-
-        /// address: 0x6000c04c
-        /// a
-        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD0: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x6000c050
-        /// a
-        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD1: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x6000c054
-        /// a
-        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD0: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x6000c058
-        /// a
-        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD1: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000c05c
-        /// a
-        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x6000c060
-        /// a
-        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x6000c064
-        /// a
-        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD0: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x6000c068
-        /// a
-        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD1: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000c06c
-        /// a
-        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEPER_CHAR: u8,
-            /// a
-            SEPER_ESC_CHAR0: u8,
-            /// a
-            SEPER_ESC_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6000c070
-        /// a
-        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ0: u8,
-            /// a
-            ESC_SEQ0_CHAR0: u8,
-            /// a
-            ESC_SEQ0_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6000c074
-        /// a
-        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ1: u8,
-            /// a
-            ESC_SEQ1_CHAR0: u8,
-            /// a
-            ESC_SEQ1_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6000c078
-        /// a
-        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ2: u8,
-            /// a
-            ESC_SEQ2_CHAR0: u8,
-            /// a
-            ESC_SEQ2_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000c07c
-        /// a
-        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            PKT_THRS: u13,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6000c080
-        /// a
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// Full-speed USB Serial/JTAG Controller
-    pub const USB_DEVICE = struct {
-        pub const base_address = 0x60043000;
-
-        /// address: 0x60043000
-        /// USB_DEVICE_EP1_REG.
-        pub const EP1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write and read byte data to/from UART Tx/Rx FIFO through this field. When
-            /// USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
-            /// into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can
-            /// check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many
-            /// data is received, then read data from UART Rx FIFO.
-            RDWR_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60043004
-        /// USB_DEVICE_EP1_CONF_REG.
-        pub const EP1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to indicate writing byte data to UART Tx FIFO is done.
-            WR_DONE: u1,
-            /// 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
-            /// writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is
-            /// read by USB Host.
-            SERIAL_IN_EP_DATA_FREE: u1,
-            /// 1'b1: Indicate there is data in UART Rx FIFO.
-            SERIAL_OUT_EP_DATA_AVAIL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60043008
-        /// USB_DEVICE_INT_RAW_REG.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when flush cmd is received for IN
-            /// endpoint 2 of JTAG.
-            JTAG_IN_FLUSH_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when SOF frame is received.
-            SOF_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
-            /// one packet.
-            SERIAL_OUT_RECV_PKT_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-            SERIAL_IN_EMPTY_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when pid error is detected.
-            PID_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when CRC5 error is detected.
-            CRC5_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when CRC16 error is detected.
-            CRC16_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when stuff error is detected.
-            STUFF_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
-            /// received.
-            IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when usb bus reset is detected.
-            USB_BUS_RESET_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when OUT endpoint 1 received packet
-            /// with zero palyload.
-            OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when OUT endpoint 2 received packet
-            /// with zero palyload.
-            OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6004300c
-        /// USB_DEVICE_INT_ST_REG.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
-            SOF_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT
-            /// interrupt.
-            SERIAL_OUT_RECV_PKT_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT
-            /// interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT
-            /// interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT
-            /// interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60043010
-        /// USB_DEVICE_INT_ENA_REG.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
-            SOF_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-            SERIAL_OUT_RECV_PKT_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60043014
-        /// USB_DEVICE_INT_CLR_REG.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
-            SOF_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-            SERIAL_OUT_RECV_PKT_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60043018
-        /// USB_DEVICE_CONF0_REG.
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Select internal/external PHY
-            PHY_SEL: u1,
-            /// Enable software control USB D+ D- exchange
-            EXCHG_PINS_OVERRIDE: u1,
-            /// USB D+ D- exchange
-            EXCHG_PINS: u1,
-            /// Control single-end input high threshold,1.76V to 2V, step 80mV
-            VREFH: u2,
-            /// Control single-end input low threshold,0.8V to 1.04V, step 80mV
-            VREFL: u2,
-            /// Enable software control input threshold
-            VREF_OVERRIDE: u1,
-            /// Enable software control USB D+ D- pullup pulldown
-            PAD_PULL_OVERRIDE: u1,
-            /// Control USB D+ pull up.
-            DP_PULLUP: u1,
-            /// Control USB D+ pull down.
-            DP_PULLDOWN: u1,
-            /// Control USB D- pull up.
-            DM_PULLUP: u1,
-            /// Control USB D- pull down.
-            DM_PULLDOWN: u1,
-            /// Control pull up value.
-            PULLUP_VALUE: u1,
-            /// Enable USB pad function.
-            USB_PAD_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6004301c
-        /// USB_DEVICE_TEST_REG.
-        pub const TEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable test of the USB pad
-            ENABLE: u1,
-            /// USB pad oen in test
-            USB_OE: u1,
-            /// USB D+ tx value in test
-            TX_DP: u1,
-            /// USB D- tx value in test
-            TX_DM: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60043020
-        /// USB_DEVICE_JFIFO_ST_REG.
-        pub const JFIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// JTAT in fifo counter.
-            IN_FIFO_CNT: u2,
-            /// 1: JTAG in fifo is empty.
-            IN_FIFO_EMPTY: u1,
-            /// 1: JTAG in fifo is full.
-            IN_FIFO_FULL: u1,
-            /// JTAT out fifo counter.
-            OUT_FIFO_CNT: u2,
-            /// 1: JTAG out fifo is empty.
-            OUT_FIFO_EMPTY: u1,
-            /// 1: JTAG out fifo is full.
-            OUT_FIFO_FULL: u1,
-            /// Write 1 to reset JTAG in fifo.
-            IN_FIFO_RESET: u1,
-            /// Write 1 to reset JTAG out fifo.
-            OUT_FIFO_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60043024
-        /// USB_DEVICE_FRAM_NUM_REG.
-        pub const FRAM_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Frame index of received SOF frame.
-            SOF_FRAME_INDEX: u11,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60043028
-        /// USB_DEVICE_IN_EP0_ST_REG.
-        pub const IN_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 0.
-            IN_EP0_STATE: u2,
-            /// Write data address of IN endpoint 0.
-            IN_EP0_WR_ADDR: u7,
-            /// Read data address of IN endpoint 0.
-            IN_EP0_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6004302c
-        /// USB_DEVICE_IN_EP1_ST_REG.
-        pub const IN_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 1.
-            IN_EP1_STATE: u2,
-            /// Write data address of IN endpoint 1.
-            IN_EP1_WR_ADDR: u7,
-            /// Read data address of IN endpoint 1.
-            IN_EP1_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60043030
-        /// USB_DEVICE_IN_EP2_ST_REG.
-        pub const IN_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 2.
-            IN_EP2_STATE: u2,
-            /// Write data address of IN endpoint 2.
-            IN_EP2_WR_ADDR: u7,
-            /// Read data address of IN endpoint 2.
-            IN_EP2_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60043034
-        /// USB_DEVICE_IN_EP3_ST_REG.
-        pub const IN_EP3_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 3.
-            IN_EP3_STATE: u2,
-            /// Write data address of IN endpoint 3.
-            IN_EP3_WR_ADDR: u7,
-            /// Read data address of IN endpoint 3.
-            IN_EP3_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60043038
-        /// USB_DEVICE_OUT_EP0_ST_REG.
-        pub const OUT_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 0.
-            OUT_EP0_STATE: u2,
-            /// Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-            OUT_EP0_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 0.
-            OUT_EP0_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6004303c
-        /// USB_DEVICE_OUT_EP1_ST_REG.
-        pub const OUT_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 1.
-            OUT_EP1_STATE: u2,
-            /// Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-            OUT_EP1_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 1.
-            OUT_EP1_RD_ADDR: u7,
-            /// Data count in OUT endpoint 1 when one packet is received.
-            OUT_EP1_REC_DATA_CNT: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60043040
-        /// USB_DEVICE_OUT_EP2_ST_REG.
-        pub const OUT_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 2.
-            OUT_EP2_STATE: u2,
-            /// Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-            OUT_EP2_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 2.
-            OUT_EP2_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60043044
-        /// USB_DEVICE_MISC_CONF_REG.
-        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60043048
-        /// USB_DEVICE_MEM_CONF_REG.
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: power down usb memory.
-            USB_MEM_PD: u1,
-            /// 1: Force clock on for usb memory.
-            USB_MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x60043080
-        /// USB_DEVICE_DATE_REG.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// XTS-AES-128 Flash Encryption
-    pub const XTS_AES = struct {
-        pub const base_address = 0x600cc000;
-
-        /// address: 0x600cc000
-        /// The memory that stores plaintext
-        pub const PLAIN_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
-
-        /// address: 0x600cc040
-        /// XTS-AES line-size register
-        pub const LINESIZE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
-
-        /// address: 0x600cc044
-        /// XTS-AES destination register
-        pub const DESTINATION = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44);
-
-        /// address: 0x600cc048
-        /// XTS-AES physical address register
-        pub const PHYSICAL_ADDRESS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x48);
-
-        /// address: 0x600cc04c
-        /// XTS-AES trigger register
-        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4c);
-
-        /// address: 0x600cc050
-        /// XTS-AES release register
-        pub const RELEASE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50);
-
-        /// address: 0x600cc054
-        /// XTS-AES destroy register
-        pub const DESTROY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x54);
-
-        /// address: 0x600cc058
-        /// XTS-AES status register
-        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x58);
-
-        /// address: 0x600cc05c
-        /// XTS-AES version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x5c);
-    };
-};
-
-const std = @import("std");
-
-pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) {
-    return @intToPtr(*volatile Mmio(size, PackedT), addr);
-}
-
-pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
-    if ((size % 8) != 0)
-        @compileError("size must be divisible by 8!");
-
-    if (!std.math.isPowerOfTwo(size / 8))
-        @compileError("size must encode a power of two number of bytes!");
-
-    const IntT = std.meta.Int(.unsigned, size);
-
-    if (@sizeOf(PackedT) != (size / 8))
-        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
-
-    return extern struct {
-        const Self = @This();
-
-        raw: IntT,
-
-        pub const underlying_type = PackedT;
-
-        pub inline fn read(addr: *volatile Self) PackedT {
-            return @bitCast(PackedT, addr.raw);
-        }
-
-        pub inline fn write(addr: *volatile Self, val: PackedT) void {
-            // This is a workaround for a compiler bug related to miscompilation
-            // If the tmp var is not used, result location will fuck things up
-            var tmp = @bitCast(IntT, val);
-            addr.raw = tmp;
-        }
-
-        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, field.name) = @field(fields, field.name);
-            }
-            write(addr, val);
-        }
-
-        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
-            }
-            write(addr, val);
-        }
-    };
-}
-
-pub fn MmioInt(comptime size: u8, comptime T: type) type {
-    return extern struct {
-        const Self = @This();
-
-        raw: std.meta.Int(.unsigned, size),
-
-        pub inline fn read(addr: *volatile Self) T {
-            return @truncate(T, addr.raw);
-        }
-
-        pub inline fn modify(addr: *volatile Self, val: T) void {
-            const Int = std.meta.Int(.unsigned, size);
-            const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1);
-
-            var tmp = addr.raw;
-            addr.raw = (tmp & mask) | val;
-        }
-    };
-}
-
-pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) {
-    return @intToPtr(*volatile MmioInt(size, T), addr);
-}
-
-pub const InterruptVector = extern union {
-    C: fn () callconv(.C) void,
-    Naked: fn () callconv(.Naked) void,
-    // Interrupt is not supported on arm
-};
-
-const unhandled = InterruptVector{
-    .C = struct {
-        fn tmp() callconv(.C) noreturn {
-            @panic("unhandled interrupt");
-        }
-    }.tmp,
-};

From e92707cc11afea619a41a133515dacaac3d98230 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:31:11 -0700
Subject: [PATCH 12/29] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b..6f5b726 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 6b7b7a6ec47d064bbd5ed35269c854c3ca4f9c0f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:55:14 -0700
Subject: [PATCH 13/29] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b726..dabc932 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 66fd9718330b4075d94d83ade1ffa774ada568c1 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:27:44 -0700
Subject: [PATCH 14/29] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 4 ++++
 deps/microzig | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 65801a9..9bf6631 100644
--- a/README.adoc
+++ b/README.adoc
@@ -3,3 +3,7 @@
 [WIP]
 
 SVD is copied from https://github.com/esp-rs/esp-pacs
+
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index dabc932..5b0176e 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 3f5786f9386ab97d837bbf4d5c60dcdb49f0f263 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:17 -0700
Subject: [PATCH 15/29] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index 9bf6631..4123f3c 100644
--- a/README.adoc
+++ b/README.adoc
@@ -6,4 +6,4 @@ SVD is copied from https://github.com/esp-rs/esp-pacs
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index 5b0176e..ceaa9dd 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From 10e700b6e799589ff4a38866fb4c76fb9ca248d3 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:22 -0700
Subject: [PATCH 16/29] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9dd..23482a6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 6cb89c778de67ca8abb64c31ab60ec4c34c7f943 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:12 -0700
Subject: [PATCH 17/29] Update microzig (#13)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/build.zig b/build.zig
index f96f446..8cb289d 100644
--- a/build.zig
+++ b/build.zig
@@ -15,5 +15,5 @@ pub fn build(b: *std.build.Builder) void {
         .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.install();
+    exe.installArtifact(b);
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a6..ae6e619 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From c9ff9fcc404ee7121196279416d357689a7e1228 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:42 -0700
Subject: [PATCH 18/29] update microzig (#15)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e619..dd491cc 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From 5e5e11c80fb754e985c03a4e1051b674bb5f3177 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:00 -0700
Subject: [PATCH 19/29] update microzig (#16)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc..658648b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From e8cf979268d7194d9f305fb0978243c14a57f024 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:50 -0700
Subject: [PATCH 20/29] Update microzig (#18)

* update microzig

* update cpu

---------

Co-authored-by: mattnite 
---
 deps/microzig                | 2 +-
 src/cpus/espressif-riscv.zig | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b..b5edf6d 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
diff --git a/src/cpus/espressif-riscv.zig b/src/cpus/espressif-riscv.zig
index e20072d..dc2edb7 100644
--- a/src/cpus/espressif-riscv.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -29,11 +29,11 @@ pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
     );
 }
 
-pub inline fn cli() void {
+pub inline fn disable_interrupts() void {
     clearStatusBit(.mstatus, 0x08);
 }
 
-pub inline fn sei() void {
+pub inline fn enable_interrupts() void {
     setStatusBit(.mstatus, 0x08);
 }
 
@@ -62,7 +62,7 @@ pub const startup_logic = struct {
     extern fn microzig_main() noreturn;
 
     export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
-        microzig.cpu.cli();
+        microzig.cpu.disable_interrupts();
         asm volatile ("mv sp, %[eos]"
             :
             : [eos] "r" (@as(u32, microzig.config.end_of_stack)),

From c47778854f6e4f63facf40ada1b0aa0e1665767d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:13 -0700
Subject: [PATCH 21/29] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6d..4e62e99 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From d90b4f6caf3739e5964b8d0005032dd7444c9ab8 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:47:36 -0700
Subject: [PATCH 22/29] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99..9588941 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From f74311e78502d500f4ae921549ce54a71c33b210 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:31:52 -0700
Subject: [PATCH 23/29] update microzig (#23)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 9588941..9392fe0 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From 03a53c756c0a54a04d43220696e9cd1946c1b30c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 00:01:43 +0200
Subject: [PATCH 24/29] Update to zig-0.11.0 (#24)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 build.zig                    | 17 +++++++--
 build.zig.zon                | 10 +++++
 deps/microzig                |  1 -
 src/chips.zig                |  2 +-
 src/chips/ESP32_C3.zig       | 72 ++++++++++++++++++------------------
 src/cpus.zig                 |  2 +-
 src/cpus/espressif-riscv.zig |  2 +-
 src/example/blinky.zig       |  6 +--
 src/hals/ESP32_C3.zig        |  6 +--
 zpm.zig                      |  8 ----
 10 files changed, 69 insertions(+), 57 deletions(-)
 create mode 100644 build.zig.zon
 delete mode 160000 deps/microzig
 delete mode 100644 zpm.zig

diff --git a/build.zig b/build.zig
index 8cb289d..e04ab94 100644
--- a/build.zig
+++ b/build.zig
@@ -1,10 +1,10 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 pub const chips = @import("src/chips.zig");
 pub const cpus = @import("src/cpus.zig");
 
-pub fn build(b: *std.build.Builder) void {
+pub fn build(b: *std.Build) void {
     const optimize = b.standardOptimizeOption(.{});
 
     var exe = microzig.addEmbeddedExecutable(b, .{
@@ -15,5 +15,16 @@ pub fn build(b: *std.build.Builder) void {
         .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.installArtifact(b);
+
+    const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+        .format = .bin,
+    });
+
+    const fw_bin = fw_objcopy.getOutput();
+
+    const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
+
+    b.getInstallStep().dependOn(&install_fw_bin.step);
+
+    b.installArtifact(exe.inner);
 }
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 0000000..e8787ef
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,10 @@
+.{
+    .name = "microzig-espressif-esp",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
+        },
+    },
+}
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0..0000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/chips.zig b/src/chips.zig
index 14769f3..3baa05a 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 const cpus = @import("cpus.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
index 50a3263..8a632a0 100644
--- a/src/chips/ESP32_C3.zig
+++ b/src/chips/ESP32_C3.zig
@@ -33,77 +33,77 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x60000000);
+            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60000000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI1, 0x60002000);
+            pub const SPI1 = @as(*volatile types.peripherals.SPI1, @ptrFromInt(0x60002000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x60003000);
+            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x60003000));
             ///  General Purpose Input/Output
-            pub const GPIO = @intToPtr(*volatile types.peripherals.GPIO, 0x60004000);
+            pub const GPIO = @as(*volatile types.peripherals.GPIO, @ptrFromInt(0x60004000));
             ///  Sigma-Delta Modulation
-            pub const GPIOSD = @intToPtr(*volatile types.peripherals.GPIOSD, 0x60004f00);
+            pub const GPIOSD = @as(*volatile types.peripherals.GPIOSD, @ptrFromInt(0x60004f00));
             ///  Real-Time Clock Control
-            pub const RTC_CNTL = @intToPtr(*volatile types.peripherals.RTC_CNTL, 0x60008000);
+            pub const RTC_CNTL = @as(*volatile types.peripherals.RTC_CNTL, @ptrFromInt(0x60008000));
             ///  eFuse Controller
-            pub const EFUSE = @intToPtr(*volatile types.peripherals.EFUSE, 0x60008800);
+            pub const EFUSE = @as(*volatile types.peripherals.EFUSE, @ptrFromInt(0x60008800));
             ///  Input/Output Multiplexer
-            pub const IO_MUX = @intToPtr(*volatile types.peripherals.IO_MUX, 0x60009000);
+            pub const IO_MUX = @as(*volatile types.peripherals.IO_MUX, @ptrFromInt(0x60009000));
             ///  Universal Host Controller Interface
-            pub const UHCI1 = @intToPtr(*volatile types.peripherals.UHCI0, 0x6000c000);
+            pub const UHCI1 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x6000c000));
             ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x60010000);
+            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60010000));
             ///  I2C (Inter-Integrated Circuit) Controller
-            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x60013000);
+            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x60013000));
             ///  Universal Host Controller Interface
-            pub const UHCI0 = @intToPtr(*volatile types.peripherals.UHCI0, 0x60014000);
+            pub const UHCI0 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x60014000));
             ///  Remote Control Peripheral
-            pub const RMT = @intToPtr(*volatile types.peripherals.RMT, 0x60016000);
+            pub const RMT = @as(*volatile types.peripherals.RMT, @ptrFromInt(0x60016000));
             ///  LED Control PWM (Pulse Width Modulation)
-            pub const LEDC = @intToPtr(*volatile types.peripherals.LEDC, 0x60019000);
+            pub const LEDC = @as(*volatile types.peripherals.LEDC, @ptrFromInt(0x60019000));
             ///  Timer Group
-            pub const TIMG0 = @intToPtr(*volatile types.peripherals.TIMG0, 0x6001f000);
+            pub const TIMG0 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x6001f000));
             ///  Timer Group
-            pub const TIMG1 = @intToPtr(*volatile types.peripherals.TIMG0, 0x60020000);
+            pub const TIMG1 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x60020000));
             ///  System Timer
-            pub const SYSTIMER = @intToPtr(*volatile types.peripherals.SYSTIMER, 0x60023000);
+            pub const SYSTIMER = @as(*volatile types.peripherals.SYSTIMER, @ptrFromInt(0x60023000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI2, 0x60024000);
+            pub const SPI2 = @as(*volatile types.peripherals.SPI2, @ptrFromInt(0x60024000));
             ///  Advanced Peripheral Bus Controller
-            pub const APB_CTRL = @intToPtr(*volatile types.peripherals.APB_CTRL, 0x60026000);
+            pub const APB_CTRL = @as(*volatile types.peripherals.APB_CTRL, @ptrFromInt(0x60026000));
             ///  Hardware random number generator
-            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x60026000);
+            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x60026000));
             ///  Two-Wire Automotive Interface
-            pub const TWAI = @intToPtr(*volatile types.peripherals.TWAI, 0x6002b000);
+            pub const TWAI = @as(*volatile types.peripherals.TWAI, @ptrFromInt(0x6002b000));
             ///  I2S (Inter-IC Sound) Controller
-            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x6002d000);
+            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x6002d000));
             ///  AES (Advanced Encryption Standard) Accelerator
-            pub const AES = @intToPtr(*volatile types.peripherals.AES, 0x6003a000);
+            pub const AES = @as(*volatile types.peripherals.AES, @ptrFromInt(0x6003a000));
             ///  SHA (Secure Hash Algorithm) Accelerator
-            pub const SHA = @intToPtr(*volatile types.peripherals.SHA, 0x6003b000);
+            pub const SHA = @as(*volatile types.peripherals.SHA, @ptrFromInt(0x6003b000));
             ///  RSA (Rivest Shamir Adleman) Accelerator
-            pub const RSA = @intToPtr(*volatile types.peripherals.RSA, 0x6003c000);
+            pub const RSA = @as(*volatile types.peripherals.RSA, @ptrFromInt(0x6003c000));
             ///  Digital Signature
-            pub const DS = @intToPtr(*volatile types.peripherals.DS, 0x6003d000);
+            pub const DS = @as(*volatile types.peripherals.DS, @ptrFromInt(0x6003d000));
             ///  HMAC (Hash-based Message Authentication Code) Accelerator
-            pub const HMAC = @intToPtr(*volatile types.peripherals.HMAC, 0x6003e000);
+            pub const HMAC = @as(*volatile types.peripherals.HMAC, @ptrFromInt(0x6003e000));
             ///  DMA (Direct Memory Access) Controller
-            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x6003f000);
+            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x6003f000));
             ///  Successive Approximation Register Analog to Digital Converter
-            pub const APB_SARADC = @intToPtr(*volatile types.peripherals.APB_SARADC, 0x60040000);
+            pub const APB_SARADC = @as(*volatile types.peripherals.APB_SARADC, @ptrFromInt(0x60040000));
             ///  Full-speed USB Serial/JTAG Controller
-            pub const USB_DEVICE = @intToPtr(*volatile types.peripherals.USB_DEVICE, 0x60043000);
+            pub const USB_DEVICE = @as(*volatile types.peripherals.USB_DEVICE, @ptrFromInt(0x60043000));
             ///  System
-            pub const SYSTEM = @intToPtr(*volatile types.peripherals.SYSTEM, 0x600c0000);
+            pub const SYSTEM = @as(*volatile types.peripherals.SYSTEM, @ptrFromInt(0x600c0000));
             ///  Sensitive
-            pub const SENSITIVE = @intToPtr(*volatile types.peripherals.SENSITIVE, 0x600c1000);
+            pub const SENSITIVE = @as(*volatile types.peripherals.SENSITIVE, @ptrFromInt(0x600c1000));
             ///  Interrupt Core
-            pub const INTERRUPT_CORE0 = @intToPtr(*volatile types.peripherals.INTERRUPT_CORE0, 0x600c2000);
+            pub const INTERRUPT_CORE0 = @as(*volatile types.peripherals.INTERRUPT_CORE0, @ptrFromInt(0x600c2000));
             ///  External Memory
-            pub const EXTMEM = @intToPtr(*volatile types.peripherals.EXTMEM, 0x600c4000);
+            pub const EXTMEM = @as(*volatile types.peripherals.EXTMEM, @ptrFromInt(0x600c4000));
             ///  XTS-AES-128 Flash Encryption
-            pub const XTS_AES = @intToPtr(*volatile types.peripherals.XTS_AES, 0x600cc000);
+            pub const XTS_AES = @as(*volatile types.peripherals.XTS_AES, @ptrFromInt(0x600cc000));
             ///  Debug Assist
-            pub const ASSIST_DEBUG = @intToPtr(*volatile types.peripherals.ASSIST_DEBUG, 0x600ce000);
+            pub const ASSIST_DEBUG = @as(*volatile types.peripherals.ASSIST_DEBUG, @ptrFromInt(0x600ce000));
         };
     };
 };
diff --git a/src/cpus.zig b/src/cpus.zig
index b087d90..c8bda91 100644
--- a/src/cpus.zig
+++ b/src/cpus.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse unreachable;
diff --git a/src/cpus/espressif-riscv.zig b/src/cpus/espressif-riscv.zig
index dc2edb7..5aab92d 100644
--- a/src/cpus/espressif-riscv.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -61,7 +61,7 @@ pub const startup_logic = struct {
 
     extern fn microzig_main() noreturn;
 
-    export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
+    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
         microzig.cpu.disable_interrupts();
         asm volatile ("mv sp, %[eos]"
             :
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 5ee1eef..811b048 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -42,13 +42,13 @@ pub fn main() !void {
     while (true) {
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
     }
 }
 
diff --git a/src/hals/ESP32_C3.zig b/src/hals/ESP32_C3.zig
index 516ed15..a5e1bb9 100644
--- a/src/hals/ESP32_C3.zig
+++ b/src/hals/ESP32_C3.zig
@@ -21,9 +21,9 @@ pub const gpio = struct {
         assertRange(pin);
         GPIO.FUNC_OUT_SEL_CFG[pin].modify(.{
             .OUT_SEL = config.function,
-            .INV_SEL = @boolToInt(config.invert_function),
-            .OEN_SEL = @boolToInt(config.direct_io),
-            .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
+            .INV_SEL = @intFromBool(config.invert_function),
+            .OEN_SEL = @intFromBool(config.direct_io),
+            .OEN_INV_SEL = @intFromBool(config.invert_direct_io),
         });
         switch (config.direction) {
             .input => GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
diff --git a/zpm.zig b/zpm.zig
deleted file mode 100644
index 1dcd7b3..0000000
--- a/zpm.zig
+++ /dev/null
@@ -1,8 +0,0 @@
-//! This file is auto-generated by zpm-update and *should*
-//! not be changed. This file can be checked into your VCS
-//! and is able to work standalone.
-const std = @import("std");
-
-pub const sdks = struct {
-    pub const microzig = @import("vendor/microzig/src/main.zig");
-};

From 82c944b48ceb4814c6dac511f49a89c08a16a3e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 00:29:02 +0200
Subject: [PATCH 25/29] Fixes (#25)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Update to zig-0.11.0

* Removes unnecessary submodule

---------

Co-authored-by: Felix "xq" Queißner 
---
 .gitmodules     | 6 ------
 vendor/microzig | 1 -
 2 files changed, 7 deletions(-)
 delete mode 160000 vendor/microzig

diff --git a/.gitmodules b/.gitmodules
index 911b8cf..e69de29 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +0,0 @@
-[submodule "vendor/microzig"]
-	path = vendor/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/vendor/microzig b/vendor/microzig
deleted file mode 160000
index 0d9721d..0000000
--- a/vendor/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0d9721d9070c356f4ffaf6f4a312bccdb574b8a9

From aceafa110ad6b4555c3850b54aba2392c1ef7d73 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 14:11:07 +0200
Subject: [PATCH 26/29] GitHub CI (#26)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* GitHub CI

* Update CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml     |  4 ----
 .github/workflows/build.yml | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 4 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 create mode 100644 .github/workflows/build.yml

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 7767bbb..0000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-steps:
-  - group: Build
-    steps:
-    - command: zig build
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 0000000..63ea533
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,19 @@
+name: Build
+on:
+  push:
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, windows-latest, macos-latest]
+        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
+    steps:
+      - uses: actions/checkout@v2
+      - uses: goto-bus-stop/setup-zig@v2.1.1
+        with:
+          version: 0.11.0
+
+      - name: Build
+        run: zig build install "-Doptimize=${{matrix.optimize}}"

From 8885309e9c1f22425dca58f67afb315fdeb0e226 Mon Sep 17 00:00:00 2001
From: DEADBLACKCLOVER 
Date: Mon, 28 Aug 2023 00:36:35 +0700
Subject: [PATCH 27/29] Fix perform-flash.sh (#27)

---
 perform-flash.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/perform-flash.sh b/perform-flash.sh
index ce1f5de..f7bc87d 100755
--- a/perform-flash.sh
+++ b/perform-flash.sh
@@ -3,11 +3,11 @@
 set -e
 
 clear
-zig build -Drelease-small
+zig build -Doptimize=ReleaseSmall
 llvm-objdump -S ./zig-out/bin/esp-bringup > /tmp/dump.txt
 esptool.py \
   --port /dev/ttyUSB0 \
   --baud 115200 \
-  write_flash 0x00000000 zig-out/bin/firmware.bin \
+  write_flash 0x00000000 zig-out/firmware/blinky.bin \
   --verify
 picocom --baud 115200 /dev/ttyUSB0
\ No newline at end of file

From e018e7ec6f3a483d3d3baa25506448b8cb532648 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:03:15 +0200
Subject: [PATCH 28/29] Microzig Generation 2 Build Interface  (#28)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Removes old build code.
* Makes basic build work again.
* First build
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .github/FUNDING.yml                   |     1 -
 .github/workflows/build.yml           |    19 -
 build.zig                             |    82 +-
 build.zig.zon                         |     7 +-
 src/chips.zig                         |    23 -
 esp32c3.svd => src/chips/ESP32-C3.svd |     0
 src/chips/ESP32_C3.json               | 33570 ------------------------
 src/chips/ESP32_C3.zig                | 12378 ---------
 src/cpus.zig                          |    23 -
 9 files changed, 64 insertions(+), 46039 deletions(-)
 delete mode 100644 .github/FUNDING.yml
 delete mode 100644 .github/workflows/build.yml
 delete mode 100644 src/chips.zig
 rename esp32c3.svd => src/chips/ESP32-C3.svd (100%)
 delete mode 100644 src/chips/ESP32_C3.json
 delete mode 100644 src/chips/ESP32_C3.zig
 delete mode 100644 src/cpus.zig

diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml
deleted file mode 100644
index 85b5393..0000000
--- a/.github/FUNDING.yml
+++ /dev/null
@@ -1 +0,0 @@
-github: MasterQ32
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 63ea533..0000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: goto-bus-stop/setup-zig@v2.1.1
-        with:
-          version: 0.11.0
-
-      - name: Build
-        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/build.zig b/build.zig
index e04ab94..089066c 100644
--- a/build.zig
+++ b/build.zig
@@ -1,30 +1,74 @@
 const std = @import("std");
-const microzig = @import("microzig");
 
-pub const chips = @import("src/chips.zig");
-pub const cpus = @import("src/cpus.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.Build) void {
-    const optimize = b.standardOptimizeOption(.{});
+const esp_riscv = .{
+    .name = "Espressif RISC-V",
+    .source_file = path("/src/cpus/espressif-riscv.zig"),
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
+
+const hal = .{
+    .source_file = path("/src/hals/ESP32_C3.zig"),
+};
+
+pub const chips = struct {
+    pub const esp32_c3 = .{
+        .preferred_format = .bin, // TODO: Exchange FLAT format with .esp format
+        .chip = .{
+            .name = "ESP32-C3",
+            .url = "https://www.espressif.com/en/products/socs/esp32-c3",
+
+            .cpu = .{ .custom = &esp_riscv },
 
-    var exe = microzig.addEmbeddedExecutable(b, .{
-        .name = "esp-bringup",
-        .source_file = .{
-            .path = "src/example/blinky.zig",
+            .register_definition = .{
+                .svd = path("/src/chips/ESP32-C3.svd"),
+            },
+
+            .memory_regions = &.{
+                .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+                .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+            },
         },
-        .backing = .{ .chip = chips.esp32_c3 },
-        .optimize = optimize,
-    });
+        .hal = hal,
+    };
+};
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+
+    // var exe = microzig.addEmbeddedExecutable(b, .{
+    //     .name = "esp-bringup",
+    //     .source_file = .{
+    //         .path = "src/example/blinky.zig",
+    //     },
+    //     .backing = .{ .chip = chips.esp32_c3 },
+    //     .optimize = optimize,
+    // });
 
-    const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
-        .format = .bin,
-    });
+    // const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+    //     .format = .bin,
+    // });
 
-    const fw_bin = fw_objcopy.getOutput();
+    // const fw_bin = fw_objcopy.getOutput();
 
-    const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
+    // const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
 
-    b.getInstallStep().dependOn(&install_fw_bin.step);
+    // b.getInstallStep().dependOn(&install_fw_bin.step);
 
-    b.installArtifact(exe.inner);
+    // b.installArtifact(exe.inner);
 }
diff --git a/build.zig.zon b/build.zig.zon
index e8787ef..fd45779 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -1,10 +1,5 @@
 .{
     .name = "microzig-espressif-esp",
     .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
-    },
+    .dependencies = .{},
 }
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index 3baa05a..0000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const cpus = @import("cpus.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Chip{
-    .name = "ESP32-C3",
-    .source = .{
-        .path = root_dir() ++ "/chips/ESP32_C3.zig",
-    },
-    .hal = .{
-        .path = root_dir() ++ "/hals/ESP32_C3.zig",
-    },
-
-    .cpu = cpus.esp32_c3,
-    .memory_regions = &.{
-        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-    },
-};
diff --git a/esp32c3.svd b/src/chips/ESP32-C3.svd
similarity index 100%
rename from esp32c3.svd
rename to src/chips/ESP32-C3.svd
diff --git a/src/chips/ESP32_C3.json b/src/chips/ESP32_C3.json
deleted file mode 100644
index 4691dc7..0000000
--- a/src/chips/ESP32_C3.json
+++ /dev/null
@@ -1,33570 +0,0 @@
-{
-  "version": "0.1.0",
-  "types": {
-    "peripherals": {
-      "AES": {
-        "description": "AES (Advanced Encryption Standard) Accelerator",
-        "children": {
-          "registers": {
-            "KEY_0": {
-              "description": "Key material key_0 configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_0": {
-                    "description": "This bits stores key_0 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_1": {
-              "description": "Key material key_1 configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_1": {
-                    "description": "This bits stores key_1 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_2": {
-              "description": "Key material key_2 configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_2": {
-                    "description": "This bits stores key_2 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_3": {
-              "description": "Key material key_3 configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_3": {
-                    "description": "This bits stores key_3 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_4": {
-              "description": "Key material key_4 configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_4": {
-                    "description": "This bits stores key_4 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_5": {
-              "description": "Key material key_5 configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_5": {
-                    "description": "This bits stores key_5 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_6": {
-              "description": "Key material key_6 configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_6": {
-                    "description": "This bits stores key_6 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_7": {
-              "description": "Key material key_7 configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_7": {
-                    "description": "This bits stores key_7 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_0": {
-              "description": "source text material text_in_0 configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_0": {
-                    "description": "This bits stores text_in_0 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_1": {
-              "description": "source text material text_in_1 configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_1": {
-                    "description": "This bits stores text_in_1 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_2": {
-              "description": "source text material text_in_2 configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_2": {
-                    "description": "This bits stores text_in_2 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_3": {
-              "description": "source text material text_in_3 configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_3": {
-                    "description": "This bits stores text_in_3 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_0": {
-              "description": "result text material text_out_0 configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_0": {
-                    "description": "This bits stores text_out_0 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_1": {
-              "description": "result text material text_out_1 configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_1": {
-                    "description": "This bits stores text_out_1 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_2": {
-              "description": "result text material text_out_2 configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_2": {
-                    "description": "This bits stores text_out_2 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_3": {
-              "description": "result text material text_out_3 configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_3": {
-                    "description": "This bits stores text_out_3 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "MODE": {
-              "description": "AES Mode register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "ENDIAN": {
-              "description": "AES Endian configure register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENDIAN": {
-                    "description": "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "TRIGGER": {
-              "description": "AES trigger register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRIGGER": {
-                    "description": "Set this bit to start AES calculation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "AES state register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IV_MEM": {
-              "description": "The memory that stores initialization vector",
-              "offset": 80,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "H_MEM": {
-              "description": "The memory that stores GCM hash subkey",
-              "offset": 96,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "J0_MEM": {
-              "description": "The memory that stores J0",
-              "offset": 112,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "T0_MEM": {
-              "description": "The memory that stores T0",
-              "offset": 128,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "DMA_ENABLE": {
-              "description": "DMA-AES working mode register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_ENABLE": {
-                    "description": "1'b0: typical AES working mode, 1'b1: DMA-AES working mode.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BLOCK_MODE": {
-              "description": "AES cipher block mode register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BLOCK_MODE": {
-                    "description": "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "BLOCK_NUM": {
-              "description": "AES block number register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BLOCK_NUM": {
-                    "description": "Those bits stores the number of Plaintext/ciphertext block.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "INC_SEL": {
-              "description": "Standard incrementing function configure register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INC_SEL": {
-                    "description": "This bit decides the standard incrementing function. 0: INC32. 1: INC128.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "AAD_BLOCK_NUM": {
-              "description": "Additional Authential Data block number register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AAD_BLOCK_NUM": {
-                    "description": "Those bits stores the number of AAD block.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REMAINDER_BIT_NUM": {
-              "description": "AES remainder bit number register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REMAINDER_BIT_NUM": {
-                    "description": "Those bits stores the number of remainder bit.",
-                    "offset": 0,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "CONTINUE": {
-              "description": "AES continue register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONTINUE": {
-                    "description": "Set this bit to continue GCM operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_CLEAR": {
-              "description": "AES Interrupt clear register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_CLEAR": {
-                    "description": "Set this bit to clear the AES interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "AES Interrupt enable register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_ENA": {
-                    "description": "Set this bit to enable interrupt that occurs when DMA-AES calculation is done.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "AES version control register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 538513936,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "This bits stores the version information of AES.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "DMA_EXIT": {
-              "description": "AES-DMA exit config",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_EXIT": {
-                    "description": "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "APB_CTRL": {
-        "description": "Advanced Peripheral Bus Controller",
-        "children": {
-          "registers": {
-            "SYSCLK_CONF": {
-              "description": "APB_CTRL_SYSCLK_CONF_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_DIV_CNT": {
-                    "description": "reg_pre_div_cnt",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "CLK_320M_EN": {
-                    "description": "reg_clk_320m_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RST_TICK_CNT": {
-                    "description": "reg_rst_tick_cnt",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TICK_CONF": {
-              "description": "APB_CTRL_TICK_CONF_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 67367,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL_TICK_NUM": {
-                    "description": "reg_xtal_tick_num",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CK8M_TICK_NUM": {
-                    "description": "reg_ck8m_tick_num",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "TICK_ENABLE": {
-                    "description": "reg_tick_enable",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLK_OUT_EN": {
-              "description": "APB_CTRL_CLK_OUT_EN_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2047,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK20_OEN": {
-                    "description": "reg_clk20_oen",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CLK22_OEN": {
-                    "description": "reg_clk22_oen",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CLK44_OEN": {
-                    "description": "reg_clk44_oen",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CLK_BB_OEN": {
-                    "description": "reg_clk_bb_oen",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CLK80_OEN": {
-                    "description": "reg_clk80_oen",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CLK160_OEN": {
-                    "description": "reg_clk160_oen",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CLK_320M_OEN": {
-                    "description": "reg_clk_320m_oen",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CLK_ADC_INF_OEN": {
-                    "description": "reg_clk_adc_inf_oen",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CLK_DAC_CPU_OEN": {
-                    "description": "reg_clk_dac_cpu_oen",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CLK40X_BB_OEN": {
-                    "description": "reg_clk40x_bb_oen",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CLK_XTAL_OEN": {
-                    "description": "reg_clk_xtal_oen",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WIFI_BB_CFG": {
-              "description": "APB_CTRL_WIFI_BB_CFG_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_BB_CFG": {
-                    "description": "reg_wifi_bb_cfg",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_BB_CFG_2": {
-              "description": "APB_CTRL_WIFI_BB_CFG_2_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_BB_CFG_2": {
-                    "description": "reg_wifi_bb_cfg_2",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_CLK_EN": {
-              "description": "APB_CTRL_WIFI_CLK_EN_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 4294762544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_CLK_EN": {
-                    "description": "reg_wifi_clk_en",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_RST_EN": {
-              "description": "APB_CTRL_WIFI_RST_EN_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_RST": {
-                    "description": "reg_wifi_rst",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "HOST_INF_SEL": {
-              "description": "APB_CTRL_HOST_INF_SEL_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IO_SWAP": {
-                    "description": "reg_peri_io_swap",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "EXT_MEM_PMS_LOCK": {
-              "description": "APB_CTRL_EXT_MEM_PMS_LOCK_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EXT_MEM_PMS_LOCK": {
-                    "description": "reg_ext_mem_pms_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE0_ATTR_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE0_ATTR": {
-                    "description": "reg_flash_ace0_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE1_ATTR_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE1_ATTR": {
-                    "description": "reg_flash_ace1_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE2_ATTR_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE2_ATTR": {
-                    "description": "reg_flash_ace2_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE3_ATTR_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE3_ATTR": {
-                    "description": "reg_flash_ace3_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE0_ADDR_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace0_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE1_ADDR_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 4194304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace1_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE2_ADDR_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace2_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE3_ADDR_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 12582912,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace3_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE0_SIZE_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE0_SIZE": {
-                    "description": "reg_flash_ace0_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE1_SIZE_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE1_SIZE": {
-                    "description": "reg_flash_ace1_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE2_SIZE_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE2_SIZE": {
-                    "description": "reg_flash_ace2_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE3_SIZE_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE3_SIZE": {
-                    "description": "reg_flash_ace3_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "SPI_MEM_PMS_CTRL": {
-              "description": "APB_CTRL_SPI_MEM_PMS_CTRL_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_INT": {
-                    "description": "reg_spi_mem_reject_int",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SPI_MEM_REJECT_CLR": {
-                    "description": "reg_spi_mem_reject_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SPI_MEM_REJECT_CDE": {
-                    "description": "reg_spi_mem_reject_cde",
-                    "offset": 2,
-                    "size": 5,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SPI_MEM_REJECT_ADDR": {
-              "description": "APB_CTRL_SPI_MEM_REJECT_ADDR_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_ADDR": {
-                    "description": "reg_spi_mem_reject_addr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SDIO_CTRL": {
-              "description": "APB_CTRL_SDIO_CTRL_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_WIN_ACCESS_EN": {
-                    "description": "reg_sdio_win_access_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REDCY_SIG0": {
-              "description": "APB_CTRL_REDCY_SIG0_REG",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDCY_SIG0": {
-                    "description": "reg_redcy_sig0",
-                    "offset": 0,
-                    "size": 31
-                  },
-                  "REDCY_ANDOR": {
-                    "description": "reg_redcy_andor",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "REDCY_SIG1": {
-              "description": "APB_CTRL_REDCY_SIG1_REG",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDCY_SIG1": {
-                    "description": "reg_redcy_sig1",
-                    "offset": 0,
-                    "size": 31
-                  },
-                  "REDCY_NANDOR": {
-                    "description": "reg_redcy_nandor",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FRONT_END_MEM_PD": {
-              "description": "APB_CTRL_FRONT_END_MEM_PD_REG",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 21,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AGC_MEM_FORCE_PU": {
-                    "description": "reg_agc_mem_force_pu",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "AGC_MEM_FORCE_PD": {
-                    "description": "reg_agc_mem_force_pd",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PBUS_MEM_FORCE_PU": {
-                    "description": "reg_pbus_mem_force_pu",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PBUS_MEM_FORCE_PD": {
-                    "description": "reg_pbus_mem_force_pd",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "DC_MEM_FORCE_PU": {
-                    "description": "reg_dc_mem_force_pu",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DC_MEM_FORCE_PD": {
-                    "description": "reg_dc_mem_force_pd",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RETENTION_CTRL": {
-              "description": "APB_CTRL_RETENTION_CTRL_REG",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RETENTION_LINK_ADDR": {
-                    "description": "reg_retention_link_addr",
-                    "offset": 0,
-                    "size": 27
-                  },
-                  "NOBYPASS_CPU_ISO_RST": {
-                    "description": "reg_nobypass_cpu_iso_rst",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLKGATE_FORCE_ON": {
-              "description": "APB_CTRL_CLKGATE_FORCE_ON_REG",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_CLKGATE_FORCE_ON": {
-                    "description": "reg_rom_clkgate_force_on",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_CLKGATE_FORCE_ON": {
-                    "description": "reg_sram_clkgate_force_on",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_POWER_DOWN": {
-              "description": "APB_CTRL_MEM_POWER_DOWN_REG",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_POWER_DOWN": {
-                    "description": "reg_rom_power_down",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_POWER_DOWN": {
-                    "description": "reg_sram_power_down",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_POWER_UP": {
-              "description": "APB_CTRL_MEM_POWER_UP_REG",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_POWER_UP": {
-                    "description": "reg_rom_power_up",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_POWER_UP": {
-                    "description": "reg_sram_power_up",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RND_DATA": {
-              "description": "APB_CTRL_RND_DATA_REG",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RND_DATA": {
-                    "description": "reg_rnd_data",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_CONFIG": {
-              "description": "APB_CTRL_PERI_BACKUP_CONFIG_REG",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 25728,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_FLOW_ERR": {
-                    "description": "reg_peri_backup_flow_err",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_BURST_LIMIT": {
-                    "description": "reg_peri_backup_burst_limit",
-                    "offset": 4,
-                    "size": 5
-                  },
-                  "PERI_BACKUP_TOUT_THRES": {
-                    "description": "reg_peri_backup_tout_thres",
-                    "offset": 9,
-                    "size": 10
-                  },
-                  "PERI_BACKUP_SIZE": {
-                    "description": "reg_peri_backup_size",
-                    "offset": 19,
-                    "size": 10
-                  },
-                  "PERI_BACKUP_START": {
-                    "description": "reg_peri_backup_start",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PERI_BACKUP_TO_MEM": {
-                    "description": "reg_peri_backup_to_mem",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "PERI_BACKUP_ENA": {
-                    "description": "reg_peri_backup_ena",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_APB_ADDR": {
-              "description": "APB_CTRL_PERI_BACKUP_APB_ADDR_REG",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_APB_START_ADDR": {
-                    "description": "reg_backup_apb_start_addr",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_MEM_ADDR": {
-              "description": "APB_CTRL_PERI_BACKUP_MEM_ADDR_REG",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_MEM_START_ADDR": {
-                    "description": "reg_backup_mem_start_addr",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_RAW": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_RAW_REG",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_RAW": {
-                    "description": "reg_peri_backup_done_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_RAW": {
-                    "description": "reg_peri_backup_err_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_ST": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_ST_REG",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_ST": {
-                    "description": "reg_peri_backup_done_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_ST": {
-                    "description": "reg_peri_backup_err_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_ENA": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_ENA_REG",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_ENA": {
-                    "description": "reg_peri_backup_done_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PERI_BACKUP_ERR_INT_ENA": {
-                    "description": "reg_peri_backup_err_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_CLR": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_CLR_REG",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_CLR": {
-                    "description": "reg_peri_backup_done_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_CLR": {
-                    "description": "reg_peri_backup_err_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "APB_CTRL_DATE_REG",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583632,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_dateVersion control",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "APB_SARADC": {
-        "description": "Successive Approximation Register Analog to Digital Converter",
-        "children": {
-          "registers": {
-            "CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1073971776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_START_FORCE": {
-                    "description": "select software enable saradc sample",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SARADC_START": {
-                    "description": "software enable saradc sample",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SARADC_SAR_CLK_GATED": {
-                    "description": "SAR clock gated",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SARADC_SAR_CLK_DIV": {
-                    "description": "SAR clock divider",
-                    "offset": 7,
-                    "size": 8
-                  },
-                  "SARADC_SAR_PATT_LEN": {
-                    "description": "0 ~ 15 means length 1 ~ 16",
-                    "offset": 15,
-                    "size": 3
-                  },
-                  "SARADC_SAR_PATT_P_CLEAR": {
-                    "description": "clear the pointer of pattern table for DIG ADC1 CTRL",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "SARADC_XPD_SAR_FORCE": {
-                    "description": "force option to xpd sar blocks",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "SARADC_WAIT_ARB_CYCLE": {
-                    "description": "wait arbit signal stable after sar_done",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "digital saradc configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 41470,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_MEAS_NUM_LIMIT": {
-                    "description": "enable max meas num",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SARADC_MAX_MEAS_NUM": {
-                    "description": "max conversion number",
-                    "offset": 1,
-                    "size": 8
-                  },
-                  "SARADC_SAR1_INV": {
-                    "description": "1: data to DIG ADC1 CTRL is inverted, otherwise not",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SARADC_SAR2_INV": {
-                    "description": "1: data to DIG ADC2 CTRL is inverted, otherwise not",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SARADC_TIMER_TARGET": {
-                    "description": "to set saradc timer target",
-                    "offset": 12,
-                    "size": 12
-                  },
-                  "SARADC_TIMER_EN": {
-                    "description": "to enable saradc timer trigger",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FILTER_CTRL1": {
-              "description": "digital saradc configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_FILTER_FACTOR1": {
-                    "description": "Factor of saradc filter1",
-                    "offset": 26,
-                    "size": 3
-                  },
-                  "APB_SARADC_FILTER_FACTOR0": {
-                    "description": "Factor of saradc filter0",
-                    "offset": 29,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "FSM_WAIT": {
-              "description": "digital saradc configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 16713736,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_XPD_WAIT": {
-                    "description": "saradc_xpd_wait",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SARADC_RSTB_WAIT": {
-                    "description": "saradc_rstb_wait",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "SARADC_STANDBY_WAIT": {
-                    "description": "saradc_standby_wait",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SAR1_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR1_STATUS": {
-                    "description": "saradc1 status about data and channel",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR2_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR2_STATUS": {
-                    "description": "saradc2 status about data and channel",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR_PATT_TAB1": {
-              "description": "digital saradc configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR_PATT_TAB1": {
-                    "description": "item 0 ~ 3 for pattern table 1 (each item one byte)",
-                    "offset": 0,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "SAR_PATT_TAB2": {
-              "description": "digital saradc configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR_PATT_TAB2": {
-                    "description": "Item 4 ~ 7 for pattern table 1 (each item one byte)",
-                    "offset": 0,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "ONETIME_SAMPLE": {
-              "description": "digital saradc configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 436207616,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_ONETIME_ATTEN": {
-                    "description": "configure onetime atten",
-                    "offset": 23,
-                    "size": 2
-                  },
-                  "SARADC_ONETIME_CHANNEL": {
-                    "description": "configure onetime channel",
-                    "offset": 25,
-                    "size": 4
-                  },
-                  "SARADC_ONETIME_START": {
-                    "description": "trigger adc onetime sample",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "SARADC2_ONETIME_SAMPLE": {
-                    "description": "enable adc2 onetime sample",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SARADC1_ONETIME_SAMPLE": {
-                    "description": "enable adc1 onetime sample",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ARB_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 2304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ADC_ARB_APB_FORCE": {
-                    "description": "adc2 arbiter force to enableapb controller",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ADC_ARB_RTC_FORCE": {
-                    "description": "adc2 arbiter force to enable rtc controller",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "ADC_ARB_WIFI_FORCE": {
-                    "description": "adc2 arbiter force to enable wifi controller",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ADC_ARB_GRANT_FORCE": {
-                    "description": "adc2 arbiter force grant",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "ADC_ARB_APB_PRIORITY": {
-                    "description": "Set adc2 arbiterapb priority",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "ADC_ARB_RTC_PRIORITY": {
-                    "description": "Set adc2 arbiter rtc priority",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "ADC_ARB_WIFI_PRIORITY": {
-                    "description": "Set adc2 arbiter wifi priority",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "ADC_ARB_FIX_PRIORITY": {
-                    "description": "adc2 arbiter uses fixed priority",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FILTER_CTRL0": {
-              "description": "digital saradc configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 57933824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_FILTER_CHANNEL1": {
-                    "description": "configure filter1 to adc channel",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "APB_SARADC_FILTER_CHANNEL0": {
-                    "description": "configure filter0 to adc channel",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "APB_SARADC_FILTER_RESET": {
-                    "description": "enable apb_adc1_filter",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SAR1DATA_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC1_DATA": {
-                    "description": "saradc1 data",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR2DATA_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC2_DATA": {
-                    "description": "saradc2 data",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "THRES0_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 262125,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES0_CHANNEL": {
-                    "description": "configure thres0 to adc channel",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "APB_SARADC_THRES0_HIGH": {
-                    "description": "saradc thres0 monitor thres",
-                    "offset": 5,
-                    "size": 13
-                  },
-                  "APB_SARADC_THRES0_LOW": {
-                    "description": "saradc thres0 monitor thres",
-                    "offset": 18,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "THRES1_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 262125,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_CHANNEL": {
-                    "description": "configure thres1 to adc channel",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "APB_SARADC_THRES1_HIGH": {
-                    "description": "saradc thres1 monitor thres",
-                    "offset": 5,
-                    "size": 13
-                  },
-                  "APB_SARADC_THRES1_LOW": {
-                    "description": "saradc thres1 monitor thres",
-                    "offset": 18,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "THRES_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES_ALL_EN": {
-                    "description": "enable thres to all channel",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES1_EN": {
-                    "description": "enable thres1",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_EN": {
-                    "description": "enable thres0",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "digital saradc int register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_ENA": {
-                    "description": "saradc thres1 low  interrupt enable",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_ENA": {
-                    "description": "saradc thres0 low interrupt enable",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_ENA": {
-                    "description": "saradc thres1 high interrupt enable",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_ENA": {
-                    "description": "saradc thres0 high interrupt enable",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "APB_SARADC2_DONE_INT_ENA": {
-                    "description": "saradc2 done interrupt enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_SARADC1_DONE_INT_ENA": {
-                    "description": "saradc1 done interrupt enable",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "digital saradc int register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_RAW": {
-                    "description": "saradc thres1 low  interrupt raw",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_RAW": {
-                    "description": "saradc thres0 low interrupt raw",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_RAW": {
-                    "description": "saradc thres1 high interrupt raw",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_RAW": {
-                    "description": "saradc thres0 high interrupt raw",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC2_DONE_INT_RAW": {
-                    "description": "saradc2 done interrupt raw",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC1_DONE_INT_RAW": {
-                    "description": "saradc1 done interrupt raw",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "digital saradc int register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_ST": {
-                    "description": "saradc thres1 low  interrupt state",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_ST": {
-                    "description": "saradc thres0 low interrupt state",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_ST": {
-                    "description": "saradc thres1 high interrupt state",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_ST": {
-                    "description": "saradc thres0 high interrupt state",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC2_DONE_INT_ST": {
-                    "description": "saradc2 done interrupt state",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC1_DONE_INT_ST": {
-                    "description": "saradc1 done interrupt state",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "digital saradc int register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_CLR": {
-                    "description": "saradc thres1 low  interrupt clear",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_CLR": {
-                    "description": "saradc thres0 low interrupt clear",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_CLR": {
-                    "description": "saradc thres1 high interrupt clear",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_CLR": {
-                    "description": "saradc thres0 high interrupt clear",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC2_DONE_INT_CLR": {
-                    "description": "saradc2 done interrupt clear",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC1_DONE_INT_CLR": {
-                    "description": "saradc1 done interrupt clear",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_CONF": {
-              "description": "digital saradc configure register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_ADC_EOF_NUM": {
-                    "description": "the dma_in_suc_eof gen when sample cnt = spi_eof_num",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "APB_ADC_RESET_FSM": {
-                    "description": "reset_apb_adc_state",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_ADC_TRANS": {
-                    "description": "enable apb_adc use spi_dma",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLKM_CONF": {
-              "description": "digital saradc configure register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 4,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKM_DIV_NUM": {
-                    "description": "Integral I2S clock divider value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKM_DIV_B": {
-                    "description": "Fractional clock divider numerator value",
-                    "offset": 8,
-                    "size": 6
-                  },
-                  "CLKM_DIV_A": {
-                    "description": "Fractional clock divider denominator value",
-                    "offset": 14,
-                    "size": 6
-                  },
-                  "CLK_EN": {
-                    "description": "reg clk en",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "CLK_SEL": {
-                    "description": "Set this bit to enable clk_apll",
-                    "offset": 21,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "APB_TSENS_CTRL": {
-              "description": "digital tsens configure register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 98304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TSENS_OUT": {
-                    "description": "temperature sensor data out",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "read-only"
-                  },
-                  "TSENS_IN_INV": {
-                    "description": "invert temperature sensor data",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TSENS_CLK_DIV": {
-                    "description": "temperature sensor clock divider",
-                    "offset": 14,
-                    "size": 8
-                  },
-                  "TSENS_PU": {
-                    "description": "temperature sensor power up",
-                    "offset": 22,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TSENS_CTRL2": {
-              "description": "digital tsens configure register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 16386,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TSENS_XPD_WAIT": {
-                    "description": "the time that power up tsens need wait",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "TSENS_XPD_FORCE": {
-                    "description": "force power up tsens",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "TSENS_CLK_INV": {
-                    "description": "inv tsens clk",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TSENS_CLK_SEL": {
-                    "description": "tsens clk select",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CALI": {
-              "description": "digital saradc configure register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 32768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_CALI_CFG": {
-                    "description": "saradc cali factor",
-                    "offset": 0,
-                    "size": 17
-                  }
-                }
-              }
-            },
-            "CTRL_DATE": {
-              "description": "version",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583473,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "version",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "ASSIST_DEBUG": {
-        "description": "Debug Assist",
-        "children": {
-          "registers": {
-            "C0RE_0_MONTR_ENA": {
-              "description": "ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_ENA": {
-                    "description": "reg_core_0_area_dram0_0_rd_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_wr_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_ENA": {
-                    "description": "reg_core_0_area_dram0_1_rd_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_wr_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_ENA": {
-                    "description": "reg_core_0_area_pif_0_rd_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_ENA": {
-                    "description": "reg_core_0_area_pif_0_wr_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_ENA": {
-                    "description": "reg_core_0_area_pif_1_rd_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_ENA": {
-                    "description": "reg_core_0_area_pif_1_wr_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_ENA": {
-                    "description": "reg_core_0_sp_spill_min_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_ENA": {
-                    "description": "reg_core_0_sp_spill_max_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_ENA": {
-                    "description": "reg_core_0_iram0_exception_monitor_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_ENA": {
-                    "description": "reg_core_0_dram0_exception_monitor_ena",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_RAW": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_RAW_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_RAW": {
-                    "description": "reg_core_0_area_dram0_0_rd_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_RAW": {
-                    "description": "reg_core_0_area_dram0_0_wr_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_RAW": {
-                    "description": "reg_core_0_area_dram0_1_rd_raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_RAW": {
-                    "description": "reg_core_0_area_dram0_1_wr_raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_0_RD_RAW": {
-                    "description": "reg_core_0_area_pif_0_rd_raw",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_0_WR_RAW": {
-                    "description": "reg_core_0_area_pif_0_wr_raw",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_1_RD_RAW": {
-                    "description": "reg_core_0_area_pif_1_rd_raw",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_1_WR_RAW": {
-                    "description": "reg_core_0_area_pif_1_wr_raw",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_SP_SPILL_MIN_RAW": {
-                    "description": "reg_core_0_sp_spill_min_raw",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_SP_SPILL_MAX_RAW": {
-                    "description": "reg_core_0_sp_spill_max_raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RAW": {
-                    "description": "reg_core_0_iram0_exception_monitor_raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RAW": {
-                    "description": "reg_core_0_dram0_exception_monitor_raw",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_ENA": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_ENA_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_rd_intr_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_wr_intr_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_rd_intr_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_wr_intr_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_0_rd_intr_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_0_wr_intr_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_1_rd_intr_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_1_wr_intr_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_INTR_ENA": {
-                    "description": "reg_core_0_sp_spill_min_intr_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_INTR_ENA": {
-                    "description": "reg_core_0_sp_spill_max_intr_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RLS": {
-                    "description": "reg_core_0_iram0_exception_monitor_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RLS": {
-                    "description": "reg_core_0_dram0_exception_monitor_ena",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_CLR": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_CLR_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_CLR": {
-                    "description": "reg_core_0_area_dram0_0_rd_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_CLR": {
-                    "description": "reg_core_0_area_dram0_0_wr_clr",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_CLR": {
-                    "description": "reg_core_0_area_dram0_1_rd_clr",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_CLR": {
-                    "description": "reg_core_0_area_dram0_1_wr_clr",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_CLR": {
-                    "description": "reg_core_0_area_pif_0_rd_clr",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_CLR": {
-                    "description": "reg_core_0_area_pif_0_wr_clr",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_CLR": {
-                    "description": "reg_core_0_area_pif_1_rd_clr",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_CLR": {
-                    "description": "reg_core_0_area_pif_1_wr_clr",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_CLR": {
-                    "description": "reg_core_0_sp_spill_min_clr",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_CLR": {
-                    "description": "reg_core_0_sp_spill_max_clr",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_CLR": {
-                    "description": "reg_core_0_iram0_exception_monitor_clr",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_CLR": {
-                    "description": "reg_core_0_dram0_exception_monitor_clr",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_0_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_MIN": {
-                    "description": "reg_core_0_area_dram0_0_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_0_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_MAX": {
-                    "description": "reg_core_0_area_dram0_0_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_1_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_1_MIN": {
-                    "description": "reg_core_0_area_dram0_1_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_1_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_1_MAX": {
-                    "description": "reg_core_0_area_dram0_1_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_0_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_0_MIN": {
-                    "description": "reg_core_0_area_pif_0_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_0_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_0_MAX": {
-                    "description": "reg_core_0_area_pif_0_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_1_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_1_MIN": {
-                    "description": "reg_core_0_area_pif_1_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_1_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_1_MAX": {
-                    "description": "reg_core_0_area_pif_1_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PC": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PC_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PC": {
-                    "description": "reg_core_0_area_pc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_SP": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_SP_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_SP": {
-                    "description": "reg_core_0_area_sp",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_MIN_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_MIN": {
-                    "description": "reg_core_0_sp_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_MAX_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_MAX": {
-                    "description": "reg_core_0_sp_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_PC": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_PC_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_PC": {
-                    "description": "reg_core_0_sp_pc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_EN": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_EN_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_RECORDEN": {
-                    "description": "reg_core_0_rcd_recorden",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_RCD_PDEBUGEN": {
-                    "description": "reg_core_0_rcd_pdebugen",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_PDEBUGPC": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_PDEBUGPC": {
-                    "description": "reg_core_0_rcd_pdebugpc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_PDEBUGSP": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_PDEBUGSP": {
-                    "description": "reg_core_0_rcd_pdebugsp",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_RECORDING_ADDR_0": {
-                    "description": "reg_core_0_iram0_recording_addr_0",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_WR_0": {
-                    "description": "reg_core_0_iram0_recording_wr_0",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_LOADSTORE_0": {
-                    "description": "reg_core_0_iram0_recording_loadstore_0",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_RECORDING_ADDR_1": {
-                    "description": "reg_core_0_iram0_recording_addr_1",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_WR_1": {
-                    "description": "reg_core_0_iram0_recording_wr_1",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_LOADSTORE_1": {
-                    "description": "reg_core_0_iram0_recording_loadstore_1",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_ADDR_0": {
-                    "description": "reg_core_0_dram0_recording_addr_0",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_WR_0": {
-                    "description": "reg_core_0_dram0_recording_wr_0",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_BYTEEN_0": {
-                    "description": "reg_core_0_dram0_recording_byteen_0",
-                    "offset": 25,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_PC_0": {
-                    "description": "reg_core_0_dram0_recording_pc_0",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_2": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_ADDR_1": {
-                    "description": "reg_core_0_dram0_recording_addr_1",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_WR_1": {
-                    "description": "reg_core_0_dram0_recording_wr_1",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_BYTEEN_1": {
-                    "description": "reg_core_0_dram0_recording_byteen_1",
-                    "offset": 25,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_3": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_PC_1": {
-                    "description": "reg_core_0_dram0_recording_pc_1",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0": {
-                    "description": "reg_core_x_iram0_dram0_limit_cycle_0",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1": {
-                    "description": "reg_core_x_iram0_dram0_limit_cycle_1",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "LOG_SETTING": {
-              "description": "ASSIST_DEBUG_LOG_SETTING",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 128,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_ENA": {
-                    "description": "reg_log_ena",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "LOG_MODE": {
-                    "description": "reg_log_mode",
-                    "offset": 3,
-                    "size": 4
-                  },
-                  "LOG_MEM_LOOP_ENABLE": {
-                    "description": "reg_log_mem_loop_enable",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LOG_DATA_0": {
-              "description": "ASSIST_DEBUG_LOG_DATA_0_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_DATA_0": {
-                    "description": "reg_log_data_0",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_DATA_MASK": {
-              "description": "ASSIST_DEBUG_LOG_DATA_MASK_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_DATA_SIZE": {
-                    "description": "reg_log_data_size",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "LOG_MIN": {
-              "description": "ASSIST_DEBUG_LOG_MIN_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MIN": {
-                    "description": "reg_log_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MAX": {
-              "description": "ASSIST_DEBUG_LOG_MAX_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MAX": {
-                    "description": "reg_log_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_START": {
-              "description": "ASSIST_DEBUG_LOG_MEM_START_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_START": {
-                    "description": "reg_log_mem_start",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_END": {
-              "description": "ASSIST_DEBUG_LOG_MEM_END_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_END": {
-                    "description": "reg_log_mem_end",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_WRITING_ADDR": {
-              "description": "ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_WRITING_ADDR": {
-                    "description": "reg_log_mem_writing_addr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LOG_MEM_FULL_FLAG": {
-              "description": "ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_FULL_FLAG": {
-                    "description": "reg_log_mem_full_flag",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CLR_LOG_MEM_FULL_FLAG": {
-                    "description": "reg_clr_log_mem_full_flag",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "C0RE_0_LASTPC_BEFORE_EXCEPTION": {
-              "description": "ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_LASTPC_BEFORE_EXC": {
-                    "description": "reg_core_0_lastpc_before_exc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "C0RE_0_DEBUG_MODE": {
-              "description": "ASSIST_DEBUG_C0RE_0_DEBUG_MODE",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DEBUG_MODE": {
-                    "description": "reg_core_0_debug_mode",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DEBUG_MODULE_ACTIVE": {
-                    "description": "reg_core_0_debug_module_active",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "ASSIST_DEBUG_DATE_REG",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33587216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ASSIST_DEBUG_DATE": {
-                    "description": "reg_assist_debug_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "DMA": {
-        "description": "DMA (Direct Memory Access) Controller",
-        "children": {
-          "registers": {
-            "INT_RAW_CH0": {
-              "description": "DMA_INT_RAW_CH0_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH0": {
-              "description": "DMA_INT_ST_CH0_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH0": {
-              "description": "DMA_INT_ENA_CH0_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH0": {
-              "description": "DMA_INT_CLR_CH0_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW_CH1": {
-              "description": "DMA_INT_RAW_CH1_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH1": {
-              "description": "DMA_INT_ST_CH1_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH1": {
-              "description": "DMA_INT_ENA_CH1_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH1": {
-              "description": "DMA_INT_CLR_CH1_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW_CH2": {
-              "description": "DMA_INT_RAW_CH2_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH2": {
-              "description": "DMA_INT_ST_CH2_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH2": {
-              "description": "DMA_INT_ENA_CH2_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH2": {
-              "description": "DMA_INT_CLR_CH2_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "AHB_TEST": {
-              "description": "DMA_AHB_TEST_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AHB_TESTMODE": {
-                    "description": "reserved",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "AHB_TESTADDR": {
-                    "description": "reserved",
-                    "offset": 4,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "MISC_CONF": {
-              "description": "DMA_MISC_CONF_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AHBM_RST_INTER": {
-                    "description": "Set this bit, then clear this bit to reset the internal ahb FSM.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ARB_PRI_DIS": {
-                    "description": "Set this bit to disable priority arbitration function.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "DMA_DATE_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 33587792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "register version.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH0": {
-              "description": "DMA_IN_CONF0_CH0_REG.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH0": {
-                    "description": "This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH0": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH0": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH0": {
-              "description": "DMA_IN_CONF1_CH0_REG.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH0": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH0": {
-              "description": "DMA_INFIFO_STATUS_CH0_REG.",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH0": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH0": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH0": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH0": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH0": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH0": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH0": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH0": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH0": {
-              "description": "DMA_IN_POP_CH0_REG.",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH0": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH0": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH0": {
-              "description": "DMA_IN_LINK_CH0_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH0": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH0": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH0": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH0": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH0": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH0": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH0": {
-              "description": "DMA_IN_STATE_CH0_REG.",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH0": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH0": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH0": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH0": {
-              "description": "DMA_IN_DSCR_CH0_REG.",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH0": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH0": {
-              "description": "DMA_IN_DSCR_BF0_CH0_REG.",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH0": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH0": {
-              "description": "DMA_IN_DSCR_BF1_CH0_REG.",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH0": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH0": {
-              "description": "DMA_IN_PRI_CH0_REG.",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH0": {
-                    "description": "The priority of Rx channel 0. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH0": {
-              "description": "DMA_IN_PERI_SEL_CH0_REG.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH0": {
-                    "description": "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH0": {
-              "description": "DMA_OUT_CONF0_CH0_REG.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH0": {
-                    "description": "This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH0": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH0": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH0": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH0": {
-              "description": "DMA_OUT_CONF1_CH0_REG.",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH0": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH0": {
-              "description": "DMA_OUTFIFO_STATUS_CH0_REG.",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH0": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH0": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH0": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH0": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH0": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH0": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH0": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH0": {
-              "description": "DMA_OUT_PUSH_CH0_REG.",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH0": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH0": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH0": {
-              "description": "DMA_OUT_LINK_CH0_REG.",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH0": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH0": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH0": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH0": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH0": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH0": {
-              "description": "DMA_OUT_STATE_CH0_REG.",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH0": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH0": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH0_REG.",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH0": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH0": {
-              "description": "DMA_OUT_DSCR_CH0_REG.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH0": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH0": {
-              "description": "DMA_OUT_DSCR_BF0_CH0_REG.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH0": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH0": {
-              "description": "DMA_OUT_DSCR_BF1_CH0_REG.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH0": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH0": {
-              "description": "DMA_OUT_PRI_CH0_REG.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH0": {
-                    "description": "The priority of Tx channel 0. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH0": {
-              "description": "DMA_OUT_PERI_SEL_CH0_REG.",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH0": {
-                    "description": "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH1": {
-              "description": "DMA_IN_CONF0_CH1_REG.",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH1": {
-                    "description": "This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH1": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH1": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH1": {
-              "description": "DMA_IN_CONF1_CH1_REG.",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH1": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH1": {
-              "description": "DMA_INFIFO_STATUS_CH1_REG.",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH1": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH1": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH1": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH1": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH1": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH1": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH1": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH1": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH1": {
-              "description": "DMA_IN_POP_CH1_REG.",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH1": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH1": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH1": {
-              "description": "DMA_IN_LINK_CH1_REG.",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH1": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH1": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH1": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH1": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH1": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH1": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH1": {
-              "description": "DMA_IN_STATE_CH1_REG.",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH1": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH1": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH1": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH1": {
-              "description": "DMA_IN_DSCR_CH1_REG.",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH1": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH1": {
-              "description": "DMA_IN_DSCR_BF0_CH1_REG.",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH1": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH1": {
-              "description": "DMA_IN_DSCR_BF1_CH1_REG.",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH1": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH1": {
-              "description": "DMA_IN_PRI_CH1_REG.",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH1": {
-                    "description": "The priority of Rx channel 1. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH1": {
-              "description": "DMA_IN_PERI_SEL_CH1_REG.",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH1": {
-                    "description": "This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH1": {
-              "description": "DMA_OUT_CONF0_CH1_REG.",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH1": {
-                    "description": "This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH1": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH1": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH1": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH1": {
-              "description": "DMA_OUT_CONF1_CH1_REG.",
-              "offset": 404,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH1": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH1": {
-              "description": "DMA_OUTFIFO_STATUS_CH1_REG.",
-              "offset": 408,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH1": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH1": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH1": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH1": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH1": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH1": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH1": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH1": {
-              "description": "DMA_OUT_PUSH_CH1_REG.",
-              "offset": 412,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH1": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH1": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH1": {
-              "description": "DMA_OUT_LINK_CH1_REG.",
-              "offset": 416,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH1": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH1": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH1": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH1": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH1": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH1": {
-              "description": "DMA_OUT_STATE_CH1_REG.",
-              "offset": 420,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH1": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH1": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH1_REG.",
-              "offset": 424,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH1": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.",
-              "offset": 428,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH1": {
-              "description": "DMA_OUT_DSCR_CH1_REG.",
-              "offset": 432,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH1": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH1": {
-              "description": "DMA_OUT_DSCR_BF0_CH1_REG.",
-              "offset": 436,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH1": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH1": {
-              "description": "DMA_OUT_DSCR_BF1_CH1_REG.",
-              "offset": 440,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH1": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH1": {
-              "description": "DMA_OUT_PRI_CH1_REG.",
-              "offset": 444,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH1": {
-                    "description": "The priority of Tx channel 1. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH1": {
-              "description": "DMA_OUT_PERI_SEL_CH1_REG.",
-              "offset": 448,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH1": {
-                    "description": "This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH2": {
-              "description": "DMA_IN_CONF0_CH2_REG.",
-              "offset": 496,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH2": {
-                    "description": "This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH2": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH2": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH2": {
-              "description": "DMA_IN_CONF1_CH2_REG.",
-              "offset": 500,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH2": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH2": {
-              "description": "DMA_INFIFO_STATUS_CH2_REG.",
-              "offset": 504,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH2": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH2": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH2": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH2": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH2": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH2": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH2": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH2": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH2": {
-              "description": "DMA_IN_POP_CH2_REG.",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH2": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH2": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH2": {
-              "description": "DMA_IN_LINK_CH2_REG.",
-              "offset": 512,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH2": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH2": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH2": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH2": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH2": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH2": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH2": {
-              "description": "DMA_IN_STATE_CH2_REG.",
-              "offset": 516,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH2": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH2": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.",
-              "offset": 520,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH2": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.",
-              "offset": 524,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH2": {
-              "description": "DMA_IN_DSCR_CH2_REG.",
-              "offset": 528,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH2": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH2": {
-              "description": "DMA_IN_DSCR_BF0_CH2_REG.",
-              "offset": 532,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH2": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH2": {
-              "description": "DMA_IN_DSCR_BF1_CH2_REG.",
-              "offset": 536,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH2": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH2": {
-              "description": "DMA_IN_PRI_CH2_REG.",
-              "offset": 540,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH2": {
-                    "description": "The priority of Rx channel 2. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH2": {
-              "description": "DMA_IN_PERI_SEL_CH2_REG.",
-              "offset": 544,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH2": {
-                    "description": "This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH2": {
-              "description": "DMA_OUT_CONF0_CH2_REG.",
-              "offset": 592,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH2": {
-                    "description": "This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH2": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH2": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH2": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH2": {
-              "description": "DMA_OUT_CONF1_CH2_REG.",
-              "offset": 596,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH2": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH2": {
-              "description": "DMA_OUTFIFO_STATUS_CH2_REG.",
-              "offset": 600,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH2": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH2": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH2": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH2": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH2": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH2": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH2": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH2": {
-              "description": "DMA_OUT_PUSH_CH2_REG.",
-              "offset": 604,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH2": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH2": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH2": {
-              "description": "DMA_OUT_LINK_CH2_REG.",
-              "offset": 608,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH2": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH2": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH2": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH2": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH2": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH2": {
-              "description": "DMA_OUT_STATE_CH2_REG.",
-              "offset": 612,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH2": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH2": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH2_REG.",
-              "offset": 616,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH2": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.",
-              "offset": 620,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH2": {
-              "description": "DMA_OUT_DSCR_CH2_REG.",
-              "offset": 624,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH2": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH2": {
-              "description": "DMA_OUT_DSCR_BF0_CH2_REG.",
-              "offset": 628,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH2": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH2": {
-              "description": "DMA_OUT_DSCR_BF1_CH2_REG.",
-              "offset": 632,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH2": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH2": {
-              "description": "DMA_OUT_PRI_CH2_REG.",
-              "offset": 636,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH2": {
-                    "description": "The priority of Tx channel 2. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH2": {
-              "description": "DMA_OUT_PERI_SEL_CH2_REG.",
-              "offset": 640,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH2": {
-                    "description": "This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "DS": {
-        "description": "Digital Signature",
-        "children": {
-          "registers": {
-            "Y_MEM": {
-              "description": "memory that stores Y",
-              "offset": 0,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_MEM": {
-              "description": "memory that stores M",
-              "offset": 512,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "RB_MEM": {
-              "description": "memory that stores Rb",
-              "offset": 1024,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "BOX_MEM": {
-              "description": "memory that stores BOX",
-              "offset": 1536,
-              "size": 8,
-              "count": 48,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "X_MEM": {
-              "description": "memory that stores X",
-              "offset": 2048,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Z_MEM": {
-              "description": "memory that stores Z",
-              "offset": 2560,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "SET_START": {
-              "description": "DS start control register",
-              "offset": 3584,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START": {
-                    "description": "set this bit to start DS operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_CONTINUE": {
-              "description": "DS continue control register",
-              "offset": 3588,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_CONTINUE": {
-                    "description": "set this bit to continue DS operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_FINISH": {
-              "description": "DS finish control register",
-              "offset": 3592,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_FINISH": {
-                    "description": "Set this bit to finish DS process.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_BUSY": {
-              "description": "DS query busy register",
-              "offset": 3596,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_BUSY": {
-                    "description": "digital signature state. 1'b0: idle, 1'b1: busy",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_KEY_WRONG": {
-              "description": "DS query key-wrong counter register",
-              "offset": 3600,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_KEY_WRONG": {
-                    "description": "digital signature key wrong counter",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_CHECK": {
-              "description": "DS query check result register",
-              "offset": 3604,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MD_ERROR": {
-                    "description": "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PADDING_BAD": {
-                    "description": "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "DS version control register",
-              "offset": 3616,
-              "size": 32,
-              "reset_value": 538969624,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "ds version information",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "EFUSE": {
-        "description": "eFuse Controller",
-        "children": {
-          "registers": {
-            "PGM_DATA0": {
-              "description": "Register 0 that stores data to be programmed.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_0": {
-                    "description": "The content of the 0th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA1": {
-              "description": "Register 1 that stores data to be programmed.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_1": {
-                    "description": "The content of the 1st 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA2": {
-              "description": "Register 2 that stores data to be programmed.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_2": {
-                    "description": "The content of the 2nd 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA3": {
-              "description": "Register 3 that stores data to be programmed.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_3": {
-                    "description": "The content of the 3rd 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA4": {
-              "description": "Register 4 that stores data to be programmed.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_4": {
-                    "description": "The content of the 4th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA5": {
-              "description": "Register 5 that stores data to be programmed.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_5": {
-                    "description": "The content of the 5th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA6": {
-              "description": "Register 6 that stores data to be programmed.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_6": {
-                    "description": "The content of the 6th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA7": {
-              "description": "Register 7 that stores data to be programmed.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_7": {
-                    "description": "The content of the 7th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE0": {
-              "description": "Register 0 that stores the RS code to be programmed.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_0": {
-                    "description": "The content of the 0th 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE1": {
-              "description": "Register 1 that stores the RS code to be programmed.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_1": {
-                    "description": "The content of the 1st 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE2": {
-              "description": "Register 2 that stores the RS code to be programmed.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_2": {
-                    "description": "The content of the 2nd 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "RD_WR_DIS": {
-              "description": "BLOCK0 data register 0.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_DIS": {
-                    "description": "Disable programming of individual eFuses.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA0": {
-              "description": "BLOCK0 data register 1.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RD_DIS": {
-                    "description": "Set this bit to disable reading from BlOCK4-10.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "DIS_RTC_RAM_BOOT": {
-                    "description": "Set this bit to disable boot from RTC RAM.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_ICACHE": {
-                    "description": "Set this bit to disable Icache.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_JTAG": {
-                    "description": "Set this bit to disable function of usb switch to jtag in module of usb device.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_ICACHE": {
-                    "description": "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DEVICE": {
-                    "description": "Set this bit to disable usb device.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_FORCE_DOWNLOAD": {
-                    "description": "Set this bit to disable the function that forces chip into download mode.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED6": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_CAN": {
-                    "description": "Set this bit to disable CAN function.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_SEL_ENABLE": {
-                    "description": "Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOFT_DIS_JTAG": {
-                    "description": "Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "DIS_PAD_JTAG": {
-                    "description": "Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_MANUAL_ENCRYPT": {
-                    "description": "Set this bit to disable flash encryption when in download boot modes.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_DREFH": {
-                    "description": "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.",
-                    "offset": 21,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_DREFL": {
-                    "description": "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.",
-                    "offset": 23,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_EXCHG_PINS": {
-                    "description": "Set this bit to exchange USB D+ and D- pins.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "VDD_SPI_AS_GPIO": {
-                    "description": "Set this bit to vdd spi pin function as gpio.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BTLC_GPIO_ENABLE": {
-                    "description": "Enable btlc gpio.",
-                    "offset": 27,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "POWERGLITCH_EN": {
-                    "description": "Set this bit to enable power glitch function.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "POWER_GLITCH_DSENSE": {
-                    "description": "Sample delay configuration of power glitch.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA1": {
-              "description": "BLOCK0 data register 2.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED2": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "WDT_DELAY_SEL": {
-                    "description": "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.",
-                    "offset": 16,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "SPI_BOOT_CRYPT_CNT": {
-                    "description": "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.",
-                    "offset": 18,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE0": {
-                    "description": "Set this bit to enable revoking first secure boot key.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE1": {
-                    "description": "Set this bit to enable revoking second secure boot key.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE2": {
-                    "description": "Set this bit to enable revoking third secure boot key.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_0": {
-                    "description": "Purpose of Key0.",
-                    "offset": 24,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_1": {
-                    "description": "Purpose of Key1.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA2": {
-              "description": "BLOCK0 data register 3.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_PURPOSE_2": {
-                    "description": "Purpose of Key2.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_3": {
-                    "description": "Purpose of Key3.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_4": {
-                    "description": "Purpose of Key4.",
-                    "offset": 8,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_5": {
-                    "description": "Purpose of Key5.",
-                    "offset": 12,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED3": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 16,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_EN": {
-                    "description": "Set this bit to enable secure boot.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_AGGRESSIVE_REVOKE": {
-                    "description": "Set this bit to enable revoking aggressive secure boot.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED0": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 22,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "FLASH_TPUW": {
-                    "description": "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA3": {
-              "description": "BLOCK0 data register 4.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIS_DOWNLOAD_MODE": {
-                    "description": "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_LEGACY_SPI_BOOT": {
-                    "description": "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CHANNEL": {
-                    "description": "Selectes the default UART print channel. 0: UART0. 1: UART1.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_MODE": {
-                    "description": "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DOWNLOAD_MODE": {
-                    "description": "Set this bit to disable UART download mode through USB.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ENABLE_SECURITY_DOWNLOAD": {
-                    "description": "Set this bit to enable secure UART download mode.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CONTROL": {
-                    "description": "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PIN_POWER_SELECTION": {
-                    "description": "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_TYPE": {
-                    "description": "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_PAGE_SIZE": {
-                    "description": "Set Flash page size.",
-                    "offset": 10,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_EN": {
-                    "description": "Set 1 to enable ECC for flash boot.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FORCE_SEND_RESUME": {
-                    "description": "Set this bit to force ROM code to send a resume command during SPI boot.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_VERSION": {
-                    "description": "Secure version (used by ESP-IDF anti-rollback feature).",
-                    "offset": 14,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED1": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA4": {
-              "description": "BLOCK0 data register 5.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED4": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_0": {
-              "description": "BLOCK1 data register 0.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_0": {
-                    "description": "Stores the low 32 bits of MAC address.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_1": {
-              "description": "BLOCK1 data register 1.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_1": {
-                    "description": "Stores the high 16 bits of MAC address.",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "SPI_PAD_CONF_0": {
-                    "description": "Stores the zeroth part of SPI_PAD_CONF.",
-                    "offset": 16,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_2": {
-              "description": "BLOCK1 data register 2.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_PAD_CONF_1": {
-                    "description": "Stores the first part of SPI_PAD_CONF.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_3": {
-              "description": "BLOCK1 data register 3.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_PAD_CONF_2": {
-                    "description": "Stores the second part of SPI_PAD_CONF.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "SYS_DATA_PART0_0": {
-                    "description": "Stores the fist 14 bits of the zeroth part of system data.",
-                    "offset": 18,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_4": {
-              "description": "BLOCK1 data register 4.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART0_1": {
-                    "description": "Stores the fist 32 bits of the zeroth part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_5": {
-              "description": "BLOCK1 data register 5.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART0_2": {
-                    "description": "Stores the second 32 bits of the zeroth part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA0": {
-              "description": "Register 0 of BLOCK2 (system).",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_0": {
-                    "description": "Stores the zeroth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA1": {
-              "description": "Register 1 of BLOCK2 (system).",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_1": {
-                    "description": "Stores the first 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA2": {
-              "description": "Register 2 of BLOCK2 (system).",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_2": {
-                    "description": "Stores the second 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA3": {
-              "description": "Register 3 of BLOCK2 (system).",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_3": {
-                    "description": "Stores the third 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA4": {
-              "description": "Register 4 of BLOCK2 (system).",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_4": {
-                    "description": "Stores the fourth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA5": {
-              "description": "Register 5 of BLOCK2 (system).",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_5": {
-                    "description": "Stores the fifth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA6": {
-              "description": "Register 6 of BLOCK2 (system).",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_6": {
-                    "description": "Stores the sixth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA7": {
-              "description": "Register 7 of BLOCK2 (system).",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_7": {
-                    "description": "Stores the seventh 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA0": {
-              "description": "Register 0 of BLOCK3 (user).",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA0": {
-                    "description": "Stores the zeroth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA1": {
-              "description": "Register 1 of BLOCK3 (user).",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA1": {
-                    "description": "Stores the first 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA2": {
-              "description": "Register 2 of BLOCK3 (user).",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA2": {
-                    "description": "Stores the second 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA3": {
-              "description": "Register 3 of BLOCK3 (user).",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA3": {
-                    "description": "Stores the third 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA4": {
-              "description": "Register 4 of BLOCK3 (user).",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA4": {
-                    "description": "Stores the fourth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA5": {
-              "description": "Register 5 of BLOCK3 (user).",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA5": {
-                    "description": "Stores the fifth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA6": {
-              "description": "Register 6 of BLOCK3 (user).",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA6": {
-                    "description": "Stores the sixth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA7": {
-              "description": "Register 7 of BLOCK3 (user).",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA7": {
-                    "description": "Stores the seventh 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA0": {
-              "description": "Register 0 of BLOCK4 (KEY0).",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA1": {
-              "description": "Register 1 of BLOCK4 (KEY0).",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA1": {
-                    "description": "Stores the first 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA2": {
-              "description": "Register 2 of BLOCK4 (KEY0).",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA2": {
-                    "description": "Stores the second 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA3": {
-              "description": "Register 3 of BLOCK4 (KEY0).",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA3": {
-                    "description": "Stores the third 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA4": {
-              "description": "Register 4 of BLOCK4 (KEY0).",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA5": {
-              "description": "Register 5 of BLOCK4 (KEY0).",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA6": {
-              "description": "Register 6 of BLOCK4 (KEY0).",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA7": {
-              "description": "Register 7 of BLOCK4 (KEY0).",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA0": {
-              "description": "Register 0 of BLOCK5 (KEY1).",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA1": {
-              "description": "Register 1 of BLOCK5 (KEY1).",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA1": {
-                    "description": "Stores the first 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA2": {
-              "description": "Register 2 of BLOCK5 (KEY1).",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA2": {
-                    "description": "Stores the second 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA3": {
-              "description": "Register 3 of BLOCK5 (KEY1).",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA3": {
-                    "description": "Stores the third 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA4": {
-              "description": "Register 4 of BLOCK5 (KEY1).",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA5": {
-              "description": "Register 5 of BLOCK5 (KEY1).",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA6": {
-              "description": "Register 6 of BLOCK5 (KEY1).",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA7": {
-              "description": "Register 7 of BLOCK5 (KEY1).",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA0": {
-              "description": "Register 0 of BLOCK6 (KEY2).",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA1": {
-              "description": "Register 1 of BLOCK6 (KEY2).",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA1": {
-                    "description": "Stores the first 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA2": {
-              "description": "Register 2 of BLOCK6 (KEY2).",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA2": {
-                    "description": "Stores the second 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA3": {
-              "description": "Register 3 of BLOCK6 (KEY2).",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA3": {
-                    "description": "Stores the third 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA4": {
-              "description": "Register 4 of BLOCK6 (KEY2).",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA5": {
-              "description": "Register 5 of BLOCK6 (KEY2).",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA6": {
-              "description": "Register 6 of BLOCK6 (KEY2).",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA7": {
-              "description": "Register 7 of BLOCK6 (KEY2).",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA0": {
-              "description": "Register 0 of BLOCK7 (KEY3).",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA1": {
-              "description": "Register 1 of BLOCK7 (KEY3).",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA1": {
-                    "description": "Stores the first 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA2": {
-              "description": "Register 2 of BLOCK7 (KEY3).",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA2": {
-                    "description": "Stores the second 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA3": {
-              "description": "Register 3 of BLOCK7 (KEY3).",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA3": {
-                    "description": "Stores the third 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA4": {
-              "description": "Register 4 of BLOCK7 (KEY3).",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA5": {
-              "description": "Register 5 of BLOCK7 (KEY3).",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA6": {
-              "description": "Register 6 of BLOCK7 (KEY3).",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA7": {
-              "description": "Register 7 of BLOCK7 (KEY3).",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA0": {
-              "description": "Register 0 of BLOCK8 (KEY4).",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA1": {
-              "description": "Register 1 of BLOCK8 (KEY4).",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA1": {
-                    "description": "Stores the first 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA2": {
-              "description": "Register 2 of BLOCK8 (KEY4).",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA2": {
-                    "description": "Stores the second 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA3": {
-              "description": "Register 3 of BLOCK8 (KEY4).",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA3": {
-                    "description": "Stores the third 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA4": {
-              "description": "Register 4 of BLOCK8 (KEY4).",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA5": {
-              "description": "Register 5 of BLOCK8 (KEY4).",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA6": {
-              "description": "Register 6 of BLOCK8 (KEY4).",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA7": {
-              "description": "Register 7 of BLOCK8 (KEY4).",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA0": {
-              "description": "Register 0 of BLOCK9 (KEY5).",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA1": {
-              "description": "Register 1 of BLOCK9 (KEY5).",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA1": {
-                    "description": "Stores the first 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA2": {
-              "description": "Register 2 of BLOCK9 (KEY5).",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA2": {
-                    "description": "Stores the second 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA3": {
-              "description": "Register 3 of BLOCK9 (KEY5).",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA3": {
-                    "description": "Stores the third 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA4": {
-              "description": "Register 4 of BLOCK9 (KEY5).",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA5": {
-              "description": "Register 5 of BLOCK9 (KEY5).",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA6": {
-              "description": "Register 6 of BLOCK9 (KEY5).",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA7": {
-              "description": "Register 7 of BLOCK9 (KEY5).",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA0": {
-              "description": "Register 0 of BLOCK10 (system).",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_0": {
-                    "description": "Stores the 0th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA1": {
-              "description": "Register 1 of BLOCK9 (KEY5).",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_1": {
-                    "description": "Stores the 1st 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA2": {
-              "description": "Register 2 of BLOCK10 (system).",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_2": {
-                    "description": "Stores the 2nd 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA3": {
-              "description": "Register 3 of BLOCK10 (system).",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_3": {
-                    "description": "Stores the 3rd 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA4": {
-              "description": "Register 4 of BLOCK10 (system).",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_4": {
-                    "description": "Stores the 4th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA5": {
-              "description": "Register 5 of BLOCK10 (system).",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_5": {
-                    "description": "Stores the 5th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA6": {
-              "description": "Register 6 of BLOCK10 (system).",
-              "offset": 372,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_6": {
-                    "description": "Stores the 6th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA7": {
-              "description": "Register 7 of BLOCK10 (system).",
-              "offset": 376,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_7": {
-                    "description": "Stores the 7th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR0": {
-              "description": "Programming error record register 0 of BLOCK0.",
-              "offset": 380,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RD_DIS_ERR": {
-                    "description": "If any bit in RD_DIS is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "DIS_RTC_RAM_BOOT_ERR": {
-                    "description": "If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_ICACHE_ERR": {
-                    "description": "If DIS_ICACHE is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_JTAG_ERR": {
-                    "description": "If DIS_USB_JTAG is 1, then it indicates a programming error.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_ICACHE_ERR": {
-                    "description": "If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DEVICE_ERR": {
-                    "description": "If DIS_USB_DEVICE is 1, then it indicates a programming error.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_FORCE_DOWNLOAD_ERR": {
-                    "description": "If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED6_ERR": {
-                    "description": "Reserved.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_CAN_ERR": {
-                    "description": "If DIS_CAN is 1, then it indicates a programming error.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_SEL_ENABLE_ERR": {
-                    "description": "If JTAG_SEL_ENABLE is 1, then it indicates a programming error.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOFT_DIS_JTAG_ERR": {
-                    "description": "If SOFT_DIS_JTAG is 1, then it indicates a programming error.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "DIS_PAD_JTAG_ERR": {
-                    "description": "If DIS_PAD_JTAG is 1, then it indicates a programming error.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR": {
-                    "description": "If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_DREFH_ERR": {
-                    "description": "If any bit in USB_DREFH is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_DREFL_ERR": {
-                    "description": "If any bit in USB_DREFL is 1, then it indicates a programming error.",
-                    "offset": 23,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_EXCHG_PINS_ERR": {
-                    "description": "If USB_EXCHG_PINS is 1, then it indicates a programming error.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "VDD_SPI_AS_GPIO_ERR": {
-                    "description": "If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BTLC_GPIO_ENABLE_ERR": {
-                    "description": "If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.",
-                    "offset": 27,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "POWERGLITCH_EN_ERR": {
-                    "description": "If POWERGLITCH_EN is 1, then it indicates a programming error.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "POWER_GLITCH_DSENSE_ERR": {
-                    "description": "If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR1": {
-              "description": "Programming error record register 1 of BLOCK0.",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED2_ERR": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "WDT_DELAY_SEL_ERR": {
-                    "description": "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.",
-                    "offset": 16,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "SPI_BOOT_CRYPT_CNT_ERR": {
-                    "description": "If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.",
-                    "offset": 18,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE0_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE1_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE2_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_0_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.",
-                    "offset": 24,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_1_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR2": {
-              "description": "Programming error record register 2 of BLOCK0.",
-              "offset": 388,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_PURPOSE_2_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_3_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_4_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_5_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED3_ERR": {
-                    "description": "Reserved.",
-                    "offset": 16,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_EN_ERR": {
-                    "description": "If SECURE_BOOT_EN is 1, then it indicates a programming error.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_AGGRESSIVE_REVOKE_ERR": {
-                    "description": "If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED0_ERR": {
-                    "description": "Reserved.",
-                    "offset": 22,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "FLASH_TPUW_ERR": {
-                    "description": "If any bit in FLASH_TPUM is 1, then it indicates a programming error.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR3": {
-              "description": "Programming error record register 3 of BLOCK0.",
-              "offset": 392,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIS_DOWNLOAD_MODE_ERR": {
-                    "description": "If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_LEGACY_SPI_BOOT_ERR": {
-                    "description": "If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CHANNEL_ERR": {
-                    "description": "If UART_PRINT_CHANNEL is 1, then it indicates a programming error.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_MODE_ERR": {
-                    "description": "If FLASH_ECC_MODE is 1, then it indicates a programming error.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DOWNLOAD_MODE_ERR": {
-                    "description": "If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ENABLE_SECURITY_DOWNLOAD_ERR": {
-                    "description": "If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CONTROL_ERR": {
-                    "description": "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PIN_POWER_SELECTION_ERR": {
-                    "description": "If PIN_POWER_SELECTION is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_TYPE_ERR": {
-                    "description": "If FLASH_TYPE is 1, then it indicates a programming error.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_PAGE_SIZE_ERR": {
-                    "description": "If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.",
-                    "offset": 10,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_EN_ERR": {
-                    "description": "If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FORCE_SEND_RESUME_ERR": {
-                    "description": "If FORCE_SEND_RESUME is 1, then it indicates a programming error.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_VERSION_ERR": {
-                    "description": "If any bit in SECURE_VERSION is 1, then it indicates a programming error.",
-                    "offset": 14,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED1_ERR": {
-                    "description": "Reserved.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR4": {
-              "description": "Programming error record register 4 of BLOCK0.",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED4_ERR": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_RS_ERR0": {
-              "description": "Programming error record register 0 of BLOCK1-10.",
-              "offset": 448,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_SPI_8M_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MAC_SPI_8M_FAIL": {
-                    "description": "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SYS_PART1_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SYS_PART1_FAIL": {
-                    "description": "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USR_DATA_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 8,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "USR_DATA_FAIL": {
-                    "description": "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY0_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 12,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY0_FAIL": {
-                    "description": "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY1_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY1_FAIL": {
-                    "description": "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY2_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY2_FAIL": {
-                    "description": "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY3_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 24,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY3_FAIL": {
-                    "description": "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY4_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 28,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY4_FAIL": {
-                    "description": "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_RS_ERR1": {
-              "description": "Programming error record register 1 of BLOCK1-10.",
-              "offset": 452,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY5_FAIL": {
-                    "description": "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SYS_PART2_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SYS_PART2_FAIL": {
-                    "description": "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLK": {
-              "description": "eFuse clcok configuration register.",
-              "offset": 456,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_MEM_FORCE_PD": {
-                    "description": "Set this bit to force eFuse SRAM into power-saving mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_CLK_FORCE_ON": {
-                    "description": "Set this bit and force to activate clock signal of eFuse SRAM.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EFUSE_MEM_FORCE_PU": {
-                    "description": "Set this bit to force eFuse SRAM into working mode.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "EN": {
-                    "description": "Set this bit and force to enable clock signal of eFuse memory.",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CONF": {
-              "description": "eFuse operation mode configuraiton register;",
-              "offset": 460,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OP_CODE": {
-                    "description": "0x5A5A: Operate programming command 0x5AA5: Operate read command.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "eFuse status register.",
-              "offset": 464,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Indicates the state of the eFuse state machine.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "OTP_LOAD_SW": {
-                    "description": "The value of OTP_LOAD_SW.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_VDDQ_C_SYNC2": {
-                    "description": "The value of OTP_VDDQ_C_SYNC2.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_STROBE_SW": {
-                    "description": "The value of OTP_STROBE_SW.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_CSB_SW": {
-                    "description": "The value of OTP_CSB_SW.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_PGENB_SW": {
-                    "description": "The value of OTP_PGENB_SW.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_VDDQ_IS_SW": {
-                    "description": "The value of OTP_VDDQ_IS_SW.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "REPEAT_ERR_CNT": {
-                    "description": "Indicates the number of error bits during programming BLOCK0.",
-                    "offset": 10,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CMD": {
-              "description": "eFuse command register.",
-              "offset": 468,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_CMD": {
-                    "description": "Set this bit to send read command.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_CMD": {
-                    "description": "Set this bit to send programming command.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "BLK_NUM": {
-                    "description": "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "eFuse raw interrupt register.",
-              "offset": 472,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_RAW": {
-                    "description": "The raw bit signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_DONE_INT_RAW": {
-                    "description": "The raw bit signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "eFuse interrupt status register.",
-              "offset": 476,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_ST": {
-                    "description": "The status signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PGM_DONE_INT_ST": {
-                    "description": "The status signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "eFuse interrupt enable register.",
-              "offset": 480,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_ENA": {
-                    "description": "The enable signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_DONE_INT_ENA": {
-                    "description": "The enable signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "eFuse interrupt clear register.",
-              "offset": 484,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_CLR": {
-                    "description": "The clear signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PGM_DONE_INT_CLR": {
-                    "description": "The clear signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DAC_CONF": {
-              "description": "Controls the eFuse programming voltage.",
-              "offset": 488,
-              "size": 32,
-              "reset_value": 130588,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DAC_CLK_DIV": {
-                    "description": "Controls the division factor of the rising clock of the programming voltage.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "DAC_CLK_PAD_SEL": {
-                    "description": "Don't care.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DAC_NUM": {
-                    "description": "Controls the rising period of the programming voltage.",
-                    "offset": 9,
-                    "size": 8
-                  },
-                  "OE_CLR": {
-                    "description": "Reduces the power supply of the programming voltage.",
-                    "offset": 17,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RD_TIM_CONF": {
-              "description": "Configures read timing parameters.",
-              "offset": 492,
-              "size": 32,
-              "reset_value": 301989888,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_INIT_NUM": {
-                    "description": "Configures the initial read time of eFuse.",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "WR_TIM_CONF1": {
-              "description": "Configurarion register 1 of eFuse programming timing parameters.",
-              "offset": 496,
-              "size": 32,
-              "reset_value": 2654208,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_ON_NUM": {
-                    "description": "Configures the power up time for VDDQ.",
-                    "offset": 8,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "WR_TIM_CONF2": {
-              "description": "Configurarion register 2 of eFuse programming timing parameters.",
-              "offset": 500,
-              "size": 32,
-              "reset_value": 400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_OFF_NUM": {
-                    "description": "Configures the power outage time for VDDQ.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "eFuse version register.",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33583616,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Stores eFuse version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "EXTMEM": {
-        "description": "External Memory",
-        "children": {
-          "registers": {
-            "ICACHE_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_ENABLE": {
-                    "description": "The bit is used to activate the data cache. 0: disable, 1: enable",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_CTRL1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SHUT_IBUS": {
-                    "description": "The bit is used to disable core0 ibus, 0: enable, 1: disable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_SHUT_DBUS": {
-                    "description": "The bit is used to disable core1 ibus, 0: enable, 1: disable",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_TAG_POWER_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_TAG_MEM_FORCE_ON": {
-                    "description": "The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_TAG_MEM_FORCE_PD": {
-                    "description": "The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_TAG_MEM_FORCE_PU": {
-                    "description": "The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT0_EN": {
-                    "description": "The bit is used to enable the first section of prelock function.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOCK_SCT1_EN": {
-                    "description": "The bit is used to enable the second section of prelock function.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT0_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT0_ADDR": {
-                    "description": "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT1_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT1_ADDR": {
-                    "description": "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT1_SIZE": {
-                    "description": "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "ICACHE_PRELOCK_SCT0_SIZE": {
-                    "description": "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 4,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_ENA": {
-                    "description": "The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_UNLOCK_ENA": {
-                    "description": "The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_LOCK_DONE": {
-                    "description": "The bit is used to indicate unlock/lock operation is finished.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_SIZE": {
-                    "description": "The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_INVALIDATE_ENA": {
-                    "description": "The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_SYNC_DONE": {
-                    "description": "The bit is used to indicate invalidate operation is finished.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_SIZE": {
-                    "description": "The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.",
-                    "offset": 0,
-                    "size": 23
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_ENA": {
-                    "description": "The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_DONE": {
-                    "description": "The bit is used to indicate preload operation is finished.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_ORDER": {
-                    "description": "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_SIZE": {
-                    "description": "The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_ENA": {
-                    "description": "The bits are used to enable the first section for autoload operation.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_SCT1_ENA": {
-                    "description": "The bits are used to enable the second section for autoload operation.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_ENA": {
-                    "description": "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_DONE": {
-                    "description": "The bit is used to indicate autoload operation is finished.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_AUTOLOAD_ORDER": {
-                    "description": "The bits are used to configure the direction of autoload. 1: descending, 0: ascending.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_RQST": {
-                    "description": "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.",
-                    "offset": 5,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT0_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_ADDR": {
-                    "description": "The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT0_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_SIZE": {
-                    "description": "The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
-                    "offset": 0,
-                    "size": 27
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT1_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT1_ADDR": {
-                    "description": "The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT1_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT1_SIZE": {
-                    "description": "The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
-                    "offset": 0,
-                    "size": 27
-                  }
-                }
-              }
-            },
-            "IBUS_TO_FLASH_START_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1107296256,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_TO_FLASH_START_VADDR": {
-                    "description": "The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "IBUS_TO_FLASH_END_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1115684863,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_TO_FLASH_END_VADDR": {
-                    "description": "The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "DBUS_TO_FLASH_START_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1006632960,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_TO_FLASH_START_VADDR": {
-                    "description": "The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "DBUS_TO_FLASH_END_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 1015021567,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_TO_FLASH_END_VADDR": {
-                    "description": "The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CACHE_ACS_CNT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_CNT_CLR": {
-                    "description": "The bit is used to clear ibus counter.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DBUS_ACS_CNT_CLR": {
-                    "description": "The bit is used to clear dbus counter.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "IBUS_ACS_MISS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_MISS_CNT": {
-                    "description": "The bits are used to count the number of the cache miss caused by ibus access flash.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IBUS_ACS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_CNT": {
-                    "description": "The bits are used to count the number of ibus access flash through icache.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DBUS_ACS_FLASH_MISS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_ACS_FLASH_MISS_CNT": {
-                    "description": "The bits are used to count the number of the cache miss caused by dbus access flash.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DBUS_ACS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_ACS_CNT": {
-                    "description": "The bits are used to count the number of dbus access flash through icache.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MMU_ENTRY_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "IBUS_CNT_OVF_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by ibus counter overflow.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DBUS_CNT_OVF_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by dbus counter overflow.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MMU_ENTRY_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IBUS_CNT_OVF_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by ibus counter overflow.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DBUS_CNT_OVF_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by dbus counter overflow.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MMU_ENTRY_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IBUS_ACS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IBUS_ACS_MISS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DBUS_ACS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DBUS_ACS_FLASH_MISS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus access flash miss counter overflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE0_IBUS_WR_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE0_IBUS_REJECT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_ACS_MSK_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_REJECT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_WR_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_IBUS_WR_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_IBUS_REJECT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_ACS_MSK_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_REJECT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_WR_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_WR_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_REJECT_ST": {
-                    "description": "The bit is used to indicate interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_ACS_MSK_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_REJECT_ST": {
-                    "description": "The bit is used to indicate interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_WR_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_DBUS_REJECT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_DBUS_ATTR": {
-                    "description": "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_WORLD": {
-                    "description": "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_DBUS_REJECT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_DBUS_VADDR": {
-                    "description": "The bits are used to indicate the virtual address of CPU access dbus when authentication fail.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_IBUS_REJECT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ATTR": {
-                    "description": "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_WORLD": {
-                    "description": "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_IBUS_REJECT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_VADDR": {
-                    "description": "The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_FAULT_CONTENT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_FAULT_CONTENT": {
-                    "description": "The bits are used to indicate the content of mmu entry which cause mmu fault..",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "CACHE_MMU_FAULT_CODE": {
-                    "description": "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.",
-                    "offset": 10,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_FAULT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_FAULT_VADDR": {
-                    "description": "The bits are used to indicate the virtual address which cause mmu fault..",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_WRAP_AROUND_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_FLASH_WRAP_AROUND": {
-                    "description": "The bit is used to enable wrap around mode when read data from flash.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_POWER_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_MEM_FORCE_ON": {
-                    "description": "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_MMU_MEM_FORCE_PD": {
-                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_MMU_MEM_FORCE_PU": {
-                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_STATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_STATE": {
-                    "description": "The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RECORD_DISABLE_DB_ENCRYPT": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RECORD_DISABLE_G0CB_DECRYPT": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON": {
-              "description": "This description will be updated in the near future.",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_FORCE_ON_MANUAL_CRYPT": {
-                    "description": "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CLK_FORCE_ON_AUTO_CRYPT": {
-                    "description": "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CLK_FORCE_ON_CRYPT": {
-                    "description": "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_PRELOAD_INT_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_INT_ST": {
-                    "description": "The bit is used to indicate the interrupt by  icache pre-load done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt by  icache pre-load done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_INT_CLR": {
-                    "description": "The bit is used to clear the interrupt by  icache pre-load done.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_SYNC_INT_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_INT_ST": {
-                    "description": "The bit is used to indicate the interrupt by  icache sync done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_SYNC_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt by  icache sync done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_SYNC_INT_CLR": {
-                    "description": "The bit is used to clear the interrupt by  icache sync done.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_OWNER": {
-              "description": "This description will be updated in the near future.",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_OWNER": {
-                    "description": "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CACHE_CONF_MISC": {
-              "description": "This description will be updated in the near future.",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT": {
-                    "description": "The bit is used to disable checking mmu entry fault by preload operation.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT": {
-                    "description": "The bit is used to disable checking mmu entry fault by sync operation.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_TRACE_ENA": {
-                    "description": "The bit is used to enable cache trace function.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_FREEZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENA": {
-                    "description": "The bit is used to enable icache freeze mode",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MODE": {
-                    "description": "The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DONE": {
-                    "description": "The bit is used to indicate icache freeze success",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_ATOMIC_OPERATE_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_ATOMIC_OPERATE_ENA": {
-                    "description": "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_REQUEST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BYPASS": {
-                    "description": "The bit is used to disable request recording which could cause performance issue",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_LOCK": {
-              "description": "This description will be updated in the near future.",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_LOCK": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY0": {
-              "description": "This description will be updated in the near future.",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY0": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY1": {
-                    "description": "The bit is used to configure the ibus permission control section boundary1",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY2": {
-              "description": "This description will be updated in the near future.",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY2": {
-                    "description": "The bit is used to configure the ibus permission control section boundary2",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_ATTR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_SCT1_ATTR": {
-                    "description": "The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "IBUS_PMS_SCT2_ATTR": {
-                    "description": "The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
-                    "offset": 4,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_LOCK": {
-              "description": "This description will be updated in the near future.",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_LOCK": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY0": {
-              "description": "This description will be updated in the near future.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY0": {
-                    "description": "The bit is used to configure the dbus permission control section boundary0",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY1": {
-                    "description": "The bit is used to configure the dbus permission control section boundary1",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY2": {
-              "description": "This description will be updated in the near future.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY2": {
-                    "description": "The bit is used to configure the dbus permission control section boundary2",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_ATTR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_SCT1_ATTR": {
-                    "description": "The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DBUS_PMS_SCT2_ATTR": {
-                    "description": "The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1",
-                    "offset": 2,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "clock gate enable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REG_DATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583456,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "version information",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "GPIO": {
-        "description": "General Purpose Input/Output",
-        "children": {
-          "registers": {
-            "BT_SELECT": {
-              "description": "GPIO bit select register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_SEL": {
-                    "description": "GPIO bit select register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "OUT": {
-              "description": "GPIO output register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA_ORIG": {
-                    "description": "GPIO output register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "OUT_W1TS": {
-              "description": "GPIO output set register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_W1TS": {
-                    "description": "GPIO output set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "OUT_W1TC": {
-              "description": "GPIO output clear register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_W1TC": {
-                    "description": "GPIO output clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SDIO_SELECT": {
-              "description": "GPIO sdio select register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_SEL": {
-                    "description": "GPIO sdio select register",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "ENABLE": {
-              "description": "GPIO output enable register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "GPIO output enable register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "ENABLE_W1TS": {
-              "description": "GPIO output enable set register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_W1TS": {
-                    "description": "GPIO output enable set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "ENABLE_W1TC": {
-              "description": "GPIO output enable clear register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_W1TC": {
-                    "description": "GPIO output enable clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STRAP": {
-              "description": "pad strapping register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STRAPPING": {
-                    "description": "pad strapping register",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN": {
-              "description": "GPIO input register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA_NEXT": {
-                    "description": "GPIO input register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "GPIO interrupt status register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT": {
-                    "description": "GPIO interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "STATUS_W1TS": {
-              "description": "GPIO interrupt status set register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_W1TS": {
-                    "description": "GPIO interrupt status set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATUS_W1TC": {
-              "description": "GPIO interrupt status clear register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_W1TC": {
-                    "description": "GPIO interrupt status clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "PCPU_INT": {
-              "description": "GPIO PRO_CPU interrupt status register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PROCPU_INT": {
-                    "description": "GPIO PRO_CPU interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PCPU_NMI_INT": {
-              "description": "GPIO PRO_CPU(not shielded) interrupt status register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PROCPU_NMI_INT": {
-                    "description": "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CPUSDIO_INT": {
-              "description": "GPIO CPUSDIO interrupt status register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_INT": {
-                    "description": "GPIO CPUSDIO interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PIN": {
-              "description": "GPIO pin configuration register",
-              "offset": 116,
-              "size": 32,
-              "count": 26,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PIN_SYNC2_BYPASS": {
-                    "description": "set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "PIN_PAD_DRIVER": {
-                    "description": "set this bit to select pad driver. 1:open-drain. :normal.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PIN_SYNC1_BYPASS": {
-                    "description": "set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
-                    "offset": 3,
-                    "size": 2
-                  },
-                  "PIN_INT_TYPE": {
-                    "description": "set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level",
-                    "offset": 7,
-                    "size": 3
-                  },
-                  "PIN_WAKEUP_ENABLE": {
-                    "description": "set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "PIN_CONFIG": {
-                    "description": "reserved",
-                    "offset": 11,
-                    "size": 2
-                  },
-                  "PIN_INT_ENA": {
-                    "description": "set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.",
-                    "offset": 13,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "STATUS_NEXT": {
-              "description": "GPIO interrupt source register",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_INTERRUPT_NEXT": {
-                    "description": "GPIO interrupt source register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FUNC_IN_SEL_CFG": {
-              "description": "GPIO input function configuration register",
-              "offset": 340,
-              "size": 32,
-              "count": 128,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SEL": {
-                    "description": "set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "IN_INV_SEL": {
-                    "description": "set this bit to invert input signal. 1:invert. :not invert.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SEL": {
-                    "description": "set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FUNC_OUT_SEL_CFG": {
-              "description": "GPIO output function select register",
-              "offset": 1364,
-              "size": 32,
-              "count": 26,
-              "reset_value": 128,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_SEL": {
-                    "description": "The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "INV_SEL": {
-                    "description": "set this bit to invert output signal.1:invert.:not invert.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "OEN_SEL": {
-                    "description": "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OEN_INV_SEL": {
-                    "description": "set this bit to invert output enable signal.1:invert.:not invert.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "GPIO clock gate register",
-              "offset": 1580,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "set this bit to enable GPIO clock gate",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REG_DATE": {
-              "description": "GPIO version register",
-              "offset": 1788,
-              "size": 32,
-              "reset_value": 33579312,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_DATE": {
-                    "description": "version register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "GPIOSD": {
-        "description": "Sigma-Delta Modulation",
-        "children": {
-          "registers": {
-            "SIGMADELTA": {
-              "description": "Duty Cycle Configure Register of SDM%s",
-              "offset": 0,
-              "size": 32,
-              "count": 4,
-              "reset_value": 65280,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SD0_IN": {
-                    "description": "This field is used to configure the duty cycle of sigma delta modulation output.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SD0_PRESCALE": {
-                    "description": "This field is used to set a divider value to divide APB clock.",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_CG": {
-              "description": "Clock Gating Configure Register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Clock enable bit of configuration registers for sigma delta modulation.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_MISC": {
-              "description": "MISC Register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FUNCTION_CLK_EN": {
-                    "description": "Clock enable bit of sigma delta modulation.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI_SWAP": {
-                    "description": "Reserved.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_VERSION": {
-              "description": "Version Control Register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 33579568,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_SD_DATE": {
-                    "description": "Version control register.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "HMAC": {
-        "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
-        "children": {
-          "registers": {
-            "SET_START": {
-              "description": "Process control register 0.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START": {
-                    "description": "Start hmac operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_PURPOSE": {
-              "description": "Configure purpose.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PURPOSE_SET": {
-                    "description": "Set hmac parameter purpose.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_KEY": {
-              "description": "Configure key.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_SET": {
-                    "description": "Set hmac parameter key.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_FINISH": {
-              "description": "Finish initial configuration.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_PARA_END": {
-                    "description": "Finish hmac configuration.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_ONE": {
-              "description": "Process control register 1.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_ONE": {
-                    "description": "Call SHA to calculate one message block.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_ING": {
-              "description": "Process control register 2.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_ING": {
-                    "description": "Continue typical hmac.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_END": {
-              "description": "Process control register 3.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_END": {
-                    "description": "Start hardware padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_RESULT_FINISH": {
-              "description": "Process control register 4.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_RESULT_END": {
-                    "description": "After read result from upstream, then let hmac back to idle.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_INVALIDATE_JTAG": {
-              "description": "Invalidate register 0.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_INVALIDATE_JTAG": {
-                    "description": "Clear result from hmac downstream JTAG.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_INVALIDATE_DS": {
-              "description": "Invalidate register 1.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_INVALIDATE_DS": {
-                    "description": "Clear result from hmac downstream DS.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_ERROR": {
-              "description": "Error register.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUREY_CHECK": {
-                    "description": "Hmac configuration state. 0: key are agree with purpose. 1: error",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_BUSY": {
-              "description": "Busy register.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUSY_STATE": {
-                    "description": "Hmac state. 1'b0: idle. 1'b1: busy",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "WR_MESSAGE_MEM": {
-              "description": "Message block memory.",
-              "offset": 128,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "RD_RESULT_MEM": {
-              "description": "Result from upstream.",
-              "offset": 192,
-              "size": 8,
-              "count": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "SET_MESSAGE_PAD": {
-              "description": "Process control register 5.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_PAD": {
-                    "description": "Start software padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "ONE_BLOCK": {
-              "description": "Process control register 6.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_ONE_BLOCK": {
-                    "description": "Don't have to do padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SOFT_JTAG_CTRL": {
-              "description": "Jtag register 0.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SOFT_JTAG_CTRL": {
-                    "description": "Turn on JTAG verification.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WR_JTAG": {
-              "description": "Jtag register 1.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_JTAG": {
-                    "description": "32-bit of key to be compared.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "I2C0": {
-        "description": "I2C (Inter-Integrated Circuit) Controller",
-        "children": {
-          "registers": {
-            "SCL_LOW_PERIOD": {
-              "description": "I2C_SCL_LOW_PERIOD_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_LOW_PERIOD": {
-                    "description": "reg_scl_low_period",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "CTR": {
-              "description": "I2C_CTR_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 523,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDA_FORCE_OUT": {
-                    "description": "reg_sda_force_out",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SCL_FORCE_OUT": {
-                    "description": "reg_scl_force_out",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SAMPLE_SCL_LEVEL": {
-                    "description": "reg_sample_scl_level",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_FULL_ACK_LEVEL": {
-                    "description": "reg_rx_full_ack_level",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MS_MODE": {
-                    "description": "reg_ms_mode",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "TRANS_START": {
-                    "description": "reg_trans_start",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_LSB_FIRST": {
-                    "description": "reg_tx_lsb_first",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RX_LSB_FIRST": {
-                    "description": "reg_rx_lsb_first",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "ARBITRATION_EN": {
-                    "description": "reg_arbitration_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FSM_RST": {
-                    "description": "reg_fsm_rst",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPGATE": {
-                    "description": "reg_conf_upgate",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_TX_AUTO_START_EN": {
-                    "description": "reg_slv_tx_auto_start_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "ADDR_10BIT_RW_CHECK_EN": {
-                    "description": "reg_addr_10bit_rw_check_en",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "ADDR_BROADCASTING_EN": {
-                    "description": "reg_addr_broadcasting_en",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SR": {
-              "description": "I2C_SR_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 49152,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESP_REC": {
-                    "description": "reg_resp_rec",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_RW": {
-                    "description": "reg_slave_rw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARB_LOST": {
-                    "description": "reg_arb_lost",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_BUSY": {
-                    "description": "reg_bus_busy",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_ADDRESSED": {
-                    "description": "reg_slave_addressed",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_CNT": {
-                    "description": "reg_rxfifo_cnt",
-                    "offset": 8,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "STRETCH_CAUSE": {
-                    "description": "reg_stretch_cause",
-                    "offset": 14,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_CNT": {
-                    "description": "reg_txfifo_cnt",
-                    "offset": 18,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_STATE_LAST": {
-                    "description": "reg_scl_main_state_last",
-                    "offset": 24,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SCL_STATE_LAST": {
-                    "description": "reg_scl_state_last",
-                    "offset": 28,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TO": {
-              "description": "I2C_TO_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME_OUT_VALUE": {
-                    "description": "reg_time_out_value",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "TIME_OUT_EN": {
-                    "description": "reg_time_out_en",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLAVE_ADDR": {
-              "description": "I2C_SLAVE_ADDR_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLAVE_ADDR": {
-                    "description": "reg_slave_addr",
-                    "offset": 0,
-                    "size": 15
-                  },
-                  "ADDR_10BIT_EN": {
-                    "description": "reg_addr_10bit_en",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FIFO_ST": {
-              "description": "I2C_FIFO_ST_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_RADDR": {
-                    "description": "reg_rxfifo_raddr",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_WADDR": {
-                    "description": "reg_rxfifo_waddr",
-                    "offset": 5,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_RADDR": {
-                    "description": "reg_txfifo_raddr",
-                    "offset": 10,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WADDR": {
-                    "description": "reg_txfifo_waddr",
-                    "offset": 15,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "SLAVE_RW_POINT": {
-                    "description": "reg_slave_rw_point",
-                    "offset": 22,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FIFO_CONF": {
-              "description": "I2C_FIFO_CONF_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 16523,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_THRHD": {
-                    "description": "reg_rxfifo_wm_thrhd",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "TXFIFO_WM_THRHD": {
-                    "description": "reg_txfifo_wm_thrhd",
-                    "offset": 5,
-                    "size": 5
-                  },
-                  "NONFIFO_EN": {
-                    "description": "reg_nonfifo_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "FIFO_ADDR_CFG_EN": {
-                    "description": "reg_fifo_addr_cfg_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RX_FIFO_RST": {
-                    "description": "reg_rx_fifo_rst",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_FIFO_RST": {
-                    "description": "reg_tx_fifo_rst",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FIFO_PRT_EN": {
-                    "description": "reg_fifo_prt_en",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATA": {
-              "description": "I2C_FIFO_DATA_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FIFO_RDATA": {
-                    "description": "reg_fifo_rdata",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "I2C_INT_RAW_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_RAW": {
-                    "description": "reg_rxfifo_wm_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WM_INT_RAW": {
-                    "description": "reg_txfifo_wm_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_RAW": {
-                    "description": "reg_rxfifo_ovf_int_raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "END_DETECT_INT_RAW": {
-                    "description": "reg_end_detect_int_raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_RAW": {
-                    "description": "reg_byte_trans_done_int_raw",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARBITRATION_LOST_INT_RAW": {
-                    "description": "reg_arbitration_lost_int_raw",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_RAW": {
-                    "description": "reg_mst_txfifo_udf_int_raw",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_COMPLETE_INT_RAW": {
-                    "description": "reg_trans_complete_int_raw",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIME_OUT_INT_RAW": {
-                    "description": "reg_time_out_int_raw",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_START_INT_RAW": {
-                    "description": "reg_trans_start_int_raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "NACK_INT_RAW": {
-                    "description": "reg_nack_int_raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_OVF_INT_RAW": {
-                    "description": "reg_txfifo_ovf_int_raw",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_UDF_INT_RAW": {
-                    "description": "reg_rxfifo_udf_int_raw",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_ST_TO_INT_RAW": {
-                    "description": "reg_scl_st_to_int_raw",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_RAW": {
-                    "description": "reg_scl_main_st_to_int_raw",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DET_START_INT_RAW": {
-                    "description": "reg_det_start_int_raw",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_STRETCH_INT_RAW": {
-                    "description": "reg_slave_stretch_int_raw",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GENERAL_CALL_INT_RAW": {
-                    "description": "reg_general_call_int_raw",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "I2C_INT_CLR_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_CLR": {
-                    "description": "reg_rxfifo_wm_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_WM_INT_CLR": {
-                    "description": "reg_txfifo_wm_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_OVF_INT_CLR": {
-                    "description": "reg_rxfifo_ovf_int_clr",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "END_DETECT_INT_CLR": {
-                    "description": "reg_end_detect_int_clr",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_CLR": {
-                    "description": "reg_byte_trans_done_int_clr",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ARBITRATION_LOST_INT_CLR": {
-                    "description": "reg_arbitration_lost_int_clr",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_CLR": {
-                    "description": "reg_mst_txfifo_udf_int_clr",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_COMPLETE_INT_CLR": {
-                    "description": "reg_trans_complete_int_clr",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TIME_OUT_INT_CLR": {
-                    "description": "reg_time_out_int_clr",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_START_INT_CLR": {
-                    "description": "reg_trans_start_int_clr",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "NACK_INT_CLR": {
-                    "description": "reg_nack_int_clr",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_OVF_INT_CLR": {
-                    "description": "reg_txfifo_ovf_int_clr",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_UDF_INT_CLR": {
-                    "description": "reg_rxfifo_udf_int_clr",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SCL_ST_TO_INT_CLR": {
-                    "description": "reg_scl_st_to_int_clr",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_CLR": {
-                    "description": "reg_scl_main_st_to_int_clr",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DET_START_INT_CLR": {
-                    "description": "reg_det_start_int_clr",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLAVE_STRETCH_INT_CLR": {
-                    "description": "reg_slave_stretch_int_clr",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "GENERAL_CALL_INT_CLR": {
-                    "description": "reg_general_call_int_clr",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "I2C_INT_ENA_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_ENA": {
-                    "description": "reg_rxfifo_wm_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TXFIFO_WM_INT_ENA": {
-                    "description": "reg_txfifo_wm_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RXFIFO_OVF_INT_ENA": {
-                    "description": "reg_rxfifo_ovf_int_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "END_DETECT_INT_ENA": {
-                    "description": "reg_end_detect_int_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "BYTE_TRANS_DONE_INT_ENA": {
-                    "description": "reg_byte_trans_done_int_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ARBITRATION_LOST_INT_ENA": {
-                    "description": "reg_arbitration_lost_int_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "MST_TXFIFO_UDF_INT_ENA": {
-                    "description": "reg_mst_txfifo_udf_int_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TRANS_COMPLETE_INT_ENA": {
-                    "description": "reg_trans_complete_int_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TIME_OUT_INT_ENA": {
-                    "description": "reg_time_out_int_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TRANS_START_INT_ENA": {
-                    "description": "reg_trans_start_int_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "NACK_INT_ENA": {
-                    "description": "reg_nack_int_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TXFIFO_OVF_INT_ENA": {
-                    "description": "reg_txfifo_ovf_int_ena",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RXFIFO_UDF_INT_ENA": {
-                    "description": "reg_rxfifo_udf_int_ena",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "SCL_ST_TO_INT_ENA": {
-                    "description": "reg_scl_st_to_int_ena",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SCL_MAIN_ST_TO_INT_ENA": {
-                    "description": "reg_scl_main_st_to_int_ena",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "DET_START_INT_ENA": {
-                    "description": "reg_det_start_int_ena",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLAVE_STRETCH_INT_ENA": {
-                    "description": "reg_slave_stretch_int_ena",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "GENERAL_CALL_INT_ENA": {
-                    "description": "reg_general_call_int_ena",
-                    "offset": 17,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_STATUS": {
-              "description": "I2C_INT_STATUS_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_ST": {
-                    "description": "reg_rxfifo_wm_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WM_INT_ST": {
-                    "description": "reg_txfifo_wm_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_ST": {
-                    "description": "reg_rxfifo_ovf_int_st",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "END_DETECT_INT_ST": {
-                    "description": "reg_end_detect_int_st",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_ST": {
-                    "description": "reg_byte_trans_done_int_st",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARBITRATION_LOST_INT_ST": {
-                    "description": "reg_arbitration_lost_int_st",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_ST": {
-                    "description": "reg_mst_txfifo_udf_int_st",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_COMPLETE_INT_ST": {
-                    "description": "reg_trans_complete_int_st",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIME_OUT_INT_ST": {
-                    "description": "reg_time_out_int_st",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_START_INT_ST": {
-                    "description": "reg_trans_start_int_st",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "NACK_INT_ST": {
-                    "description": "reg_nack_int_st",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_OVF_INT_ST": {
-                    "description": "reg_txfifo_ovf_int_st",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_UDF_INT_ST": {
-                    "description": "reg_rxfifo_udf_int_st",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_ST_TO_INT_ST": {
-                    "description": "reg_scl_st_to_int_st",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_ST": {
-                    "description": "reg_scl_main_st_to_int_st",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DET_START_INT_ST": {
-                    "description": "reg_det_start_int_st",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_STRETCH_INT_ST": {
-                    "description": "reg_slave_stretch_int_st",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GENERAL_CALL_INT_ST": {
-                    "description": "reg_general_call_int_st",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SDA_HOLD": {
-              "description": "I2C_SDA_HOLD_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_sda_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SDA_SAMPLE": {
-              "description": "I2C_SDA_SAMPLE_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_sda_sample_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_HIGH_PERIOD": {
-              "description": "I2C_SCL_HIGH_PERIOD_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_HIGH_PERIOD": {
-                    "description": "reg_scl_high_period",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "SCL_WAIT_HIGH_PERIOD": {
-                    "description": "reg_scl_wait_high_period",
-                    "offset": 9,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "SCL_START_HOLD": {
-              "description": "I2C_SCL_START_HOLD_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_start_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_RSTART_SETUP": {
-              "description": "I2C_SCL_RSTART_SETUP_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_rstart_setup_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_STOP_HOLD": {
-              "description": "I2C_SCL_STOP_HOLD_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_stop_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_STOP_SETUP": {
-              "description": "I2C_SCL_STOP_SETUP_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_stop_setup_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "FILTER_CFG": {
-              "description": "I2C_FILTER_CFG_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_FILTER_THRES": {
-                    "description": "reg_scl_filter_thres",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "SDA_FILTER_THRES": {
-                    "description": "reg_sda_filter_thres",
-                    "offset": 4,
-                    "size": 4
-                  },
-                  "SCL_FILTER_EN": {
-                    "description": "reg_scl_filter_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SDA_FILTER_EN": {
-                    "description": "reg_sda_filter_en",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "I2C_CLK_CONF_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 2097152,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCLK_DIV_NUM": {
-                    "description": "reg_sclk_div_num",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "reg_sclk_div_a",
-                    "offset": 8,
-                    "size": 6
-                  },
-                  "SCLK_DIV_B": {
-                    "description": "reg_sclk_div_b",
-                    "offset": 14,
-                    "size": 6
-                  },
-                  "SCLK_SEL": {
-                    "description": "reg_sclk_sel",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SCLK_ACTIVE": {
-                    "description": "reg_sclk_active",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMD": {
-              "description": "I2C_COMD%s_REG",
-              "offset": 88,
-              "size": 32,
-              "count": 8,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMMAND": {
-                    "description": "reg_command",
-                    "offset": 0,
-                    "size": 14
-                  },
-                  "COMMAND_DONE": {
-                    "description": "reg_command_done",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SCL_ST_TIME_OUT": {
-              "description": "I2C_SCL_ST_TIME_OUT_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_ST_TO_I2C": {
-                    "description": "reg_scl_st_to_regno more than 23",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SCL_MAIN_ST_TIME_OUT": {
-              "description": "I2C_SCL_MAIN_ST_TIME_OUT_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_MAIN_ST_TO_I2C": {
-                    "description": "reg_scl_main_st_to_regno more than 23",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SCL_SP_CONF": {
-              "description": "I2C_SCL_SP_CONF_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_RST_SLV_EN": {
-                    "description": "reg_scl_rst_slv_en",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SCL_RST_SLV_NUM": {
-                    "description": "reg_scl_rst_slv_num",
-                    "offset": 1,
-                    "size": 5
-                  },
-                  "SCL_PD_EN": {
-                    "description": "reg_scl_pd_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDA_PD_EN": {
-                    "description": "reg_sda_pd_en",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SCL_STRETCH_CONF": {
-              "description": "I2C_SCL_STRETCH_CONF_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STRETCH_PROTECT_NUM": {
-                    "description": "reg_stretch_protect_num",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "SLAVE_SCL_STRETCH_EN": {
-                    "description": "reg_slave_scl_stretch_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLAVE_SCL_STRETCH_CLR": {
-                    "description": "reg_slave_scl_stretch_clr",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLAVE_BYTE_ACK_CTL_EN": {
-                    "description": "reg_slave_byte_ack_ctl_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "SLAVE_BYTE_ACK_LVL": {
-                    "description": "reg_slave_byte_ack_lvl",
-                    "offset": 13,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "I2C_DATE_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 537330177,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TXFIFO_START_ADDR": {
-              "description": "I2C_TXFIFO_START_ADDR_REG",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TXFIFO_START_ADDR": {
-                    "description": "reg_txfifo_start_addr.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RXFIFO_START_ADDR": {
-              "description": "I2C_RXFIFO_START_ADDR_REG",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_START_ADDR": {
-                    "description": "reg_rxfifo_start_addr.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "I2S": {
-        "description": "I2S (Inter-IC Sound) Controller",
-        "children": {
-          "registers": {
-            "INT_RAW": {
-              "description": "I2S interrupt raw register, valid in level.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "I2S interrupt status register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "I2S interrupt enable register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_DONE_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RX_HUNG_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_HUNG_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "I2S interrupt clear register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_HUNG_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_HUNG_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RX_CONF": {
-              "description": "I2S RX configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 38400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_RESET": {
-                    "description": "Set this bit to reset receiver",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_FIFO_RESET": {
-                    "description": "Set this bit to reset Rx AFIFO",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_START": {
-                    "description": "Set this bit to start receiving data",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_SLAVE_MOD": {
-                    "description": "Set this bit to enable slave receiver mode",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_MONO": {
-                    "description": "Set this bit to enable receiver  in mono mode",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RX_BIG_ENDIAN": {
-                    "description": "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RX_UPDATE": {
-                    "description": "Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RX_MONO_FST_VLD": {
-                    "description": "1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RX_PCM_CONF": {
-                    "description": "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "RX_PCM_BYPASS": {
-                    "description": "Set this bit to bypass Compress/Decompress module for received data.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RX_STOP_MODE": {
-                    "description": "0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "RX_LEFT_ALIGN": {
-                    "description": "1: I2S RX left alignment mode. 0: I2S RX right alignment mode.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RX_24_FILL_EN": {
-                    "description": "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RX_WS_IDLE_POL": {
-                    "description": "0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "RX_BIT_ORDER": {
-                    "description": "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RX_TDM_EN": {
-                    "description": "1: Enable I2S TDM Rx mode . 0: Disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RX_PDM_EN": {
-                    "description": "1: Enable I2S PDM Rx mode . 0: Disable.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CONF": {
-              "description": "I2S TX configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 45568,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_RESET": {
-                    "description": "Set this bit to reset transmitter",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_FIFO_RESET": {
-                    "description": "Set this bit to reset Tx AFIFO",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_START": {
-                    "description": "Set this bit to start transmitting data",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_SLAVE_MOD": {
-                    "description": "Set this bit to enable slave transmitter mode",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TX_MONO": {
-                    "description": "Set this bit to enable transmitter in mono mode",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "TX_CHAN_EQUAL": {
-                    "description": "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TX_BIG_ENDIAN": {
-                    "description": "I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TX_UPDATE": {
-                    "description": "Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TX_MONO_FST_VLD": {
-                    "description": "1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TX_PCM_CONF": {
-                    "description": "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "TX_PCM_BYPASS": {
-                    "description": "Set this bit to bypass  Compress/Decompress module for transmitted data.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_STOP_EN": {
-                    "description": "Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_LEFT_ALIGN": {
-                    "description": "1: I2S TX left alignment mode. 0: I2S TX right alignment mode.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "TX_24_FILL_EN": {
-                    "description": "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "TX_WS_IDLE_POL": {
-                    "description": "0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "TX_BIT_ORDER": {
-                    "description": "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "TX_TDM_EN": {
-                    "description": "1: Enable I2S TDM Tx mode . 0: Disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "TX_PDM_EN": {
-                    "description": "1: Enable I2S PDM Tx mode . 0: Disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "TX_CHAN_MOD": {
-                    "description": "I2S transmitter channel mode configuration bits.",
-                    "offset": 24,
-                    "size": 3
-                  },
-                  "SIG_LOOPBACK": {
-                    "description": "Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CONF1": {
-              "description": "I2S RX configure register 1",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 792584960,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_TDM_WS_WIDTH": {
-                    "description": "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck",
-                    "offset": 0,
-                    "size": 7
-                  },
-                  "RX_BCK_DIV_NUM": {
-                    "description": "Bit clock configuration bits in receiver mode.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "RX_BITS_MOD": {
-                    "description": "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
-                    "offset": 13,
-                    "size": 5
-                  },
-                  "RX_HALF_SAMPLE_BITS": {
-                    "description": "I2S Rx half sample bits -1.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "RX_TDM_CHAN_BITS": {
-                    "description": "The Rx bit number for each channel minus 1in TDM mode.",
-                    "offset": 24,
-                    "size": 5
-                  },
-                  "RX_MSB_SHIFT": {
-                    "description": "Set this bit to enable receiver in Phillips standard mode",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CONF1": {
-              "description": "I2S TX configure register 1",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 1866326784,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_TDM_WS_WIDTH": {
-                    "description": "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck",
-                    "offset": 0,
-                    "size": 7
-                  },
-                  "TX_BCK_DIV_NUM": {
-                    "description": "Bit clock configuration bits in transmitter mode.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "TX_BITS_MOD": {
-                    "description": "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
-                    "offset": 13,
-                    "size": 5
-                  },
-                  "TX_HALF_SAMPLE_BITS": {
-                    "description": "I2S Tx half sample bits -1.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "TX_TDM_CHAN_BITS": {
-                    "description": "The Tx bit number for each channel minus 1in TDM mode.",
-                    "offset": 24,
-                    "size": 5
-                  },
-                  "TX_MSB_SHIFT": {
-                    "description": "Set this bit to enable transmitter in Phillips standard mode",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TX_BCK_NO_DLY": {
-                    "description": "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.",
-                    "offset": 30,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CLKM_CONF": {
-              "description": "I2S RX clock configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_CLKM_DIV_NUM": {
-                    "description": "Integral I2S clock divider value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "RX_CLK_ACTIVE": {
-                    "description": "I2S Rx module clock enable signal.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RX_CLK_SEL": {
-                    "description": "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "MCLK_SEL": {
-                    "description": "0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CLKM_CONF": {
-              "description": "I2S TX clock configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_CLKM_DIV_NUM": {
-                    "description": "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "TX_CLK_ACTIVE": {
-                    "description": "I2S Tx module clock enable signal.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TX_CLK_SEL": {
-                    "description": "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "CLK_EN": {
-                    "description": "Set this bit to enable clk gate",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CLKM_DIV_CONF": {
-              "description": "I2S RX module clock divider configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_CLKM_DIV_Z": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_Y": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_X": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.",
-                    "offset": 18,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_YN1": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CLKM_DIV_CONF": {
-              "description": "I2S TX module clock divider configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_CLKM_DIV_Z": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_Y": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_X": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.",
-                    "offset": 18,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_YN1": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_PCM2PDM_CONF": {
-              "description": "I2S TX PCM2PDM configuration register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 4890628,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PDM_HP_BYPASS": {
-                    "description": "I2S TX PDM bypass hp filter or not. The option has been removed.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_PDM_SINC_OSR2": {
-                    "description": "I2S TX PDM OSR2 value",
-                    "offset": 1,
-                    "size": 4
-                  },
-                  "TX_PDM_PRESCALE": {
-                    "description": "I2S TX PDM prescale for sigmadelta",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "TX_PDM_HP_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "TX_PDM_LP_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 15,
-                    "size": 2
-                  },
-                  "TX_PDM_SINC_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 17,
-                    "size": 2
-                  },
-                  "TX_PDM_SIGMADELTA_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 19,
-                    "size": 2
-                  },
-                  "TX_PDM_SIGMADELTA_DITHER2": {
-                    "description": "I2S TX PDM sigmadelta dither2 value",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "TX_PDM_SIGMADELTA_DITHER": {
-                    "description": "I2S TX PDM sigmadelta dither value",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "TX_PDM_DAC_2OUT_EN": {
-                    "description": "I2S TX PDM dac mode enable",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TX_PDM_DAC_MODE_EN": {
-                    "description": "I2S TX PDM dac 2channel enable",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PCM2PDM_CONV_EN": {
-                    "description": "I2S TX PDM Converter enable",
-                    "offset": 25,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_PCM2PDM_CONF1": {
-              "description": "I2S TX PCM2PDM configuration register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 66552768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PDM_FP": {
-                    "description": "I2S TX PDM Fp",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "TX_PDM_FS": {
-                    "description": "I2S TX PDM Fs",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "TX_IIR_HP_MULT12_5": {
-                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "TX_IIR_HP_MULT12_0": {
-                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])",
-                    "offset": 23,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "RX_TDM_CTRL": {
-              "description": "I2S TX TDM mode control register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 65535,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_TDM_PDM_CHAN0_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN1_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN2_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN3_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN4_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN5_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN6_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN7_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN8_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN9_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN10_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN11_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN12_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN13_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN14_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN15_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RX_TDM_TOT_CHAN_NUM": {
-                    "description": "The total channel number of I2S TX TDM mode.",
-                    "offset": 16,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "TX_TDM_CTRL": {
-              "description": "I2S TX TDM mode control register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 65535,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_TDM_CHAN0_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN1_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN2_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN3_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN4_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN5_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN6_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN7_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN8_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN9_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN10_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN11_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN12_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN13_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN14_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN15_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "TX_TDM_TOT_CHAN_NUM": {
-                    "description": "The total channel number of I2S TX TDM mode.",
-                    "offset": 16,
-                    "size": 4
-                  },
-                  "TX_TDM_SKIP_MSK_EN": {
-                    "description": "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_TIMING": {
-              "description": "I2S RX timing control register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_SD_IN_DM": {
-                    "description": "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "RX_WS_OUT_DM": {
-                    "description": "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "RX_BCK_OUT_DM": {
-                    "description": "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "RX_WS_IN_DM": {
-                    "description": "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "RX_BCK_IN_DM": {
-                    "description": "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "TX_TIMING": {
-              "description": "I2S TX timing control register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_SD_OUT_DM": {
-                    "description": "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "TX_SD1_OUT_DM": {
-                    "description": "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "TX_WS_OUT_DM": {
-                    "description": "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "TX_BCK_OUT_DM": {
-                    "description": "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "TX_WS_IN_DM": {
-                    "description": "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "TX_BCK_IN_DM": {
-                    "description": "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "LC_HUNG_CONF": {
-              "description": "I2S HUNG configure register.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 2064,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LC_FIFO_TIMEOUT": {
-                    "description": "the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "LC_FIFO_TIMEOUT_SHIFT": {
-                    "description": "The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift",
-                    "offset": 8,
-                    "size": 3
-                  },
-                  "LC_FIFO_TIMEOUT_ENA": {
-                    "description": "The enable bit for FIFO timeout",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RXEOF_NUM": {
-              "description": "I2S RX data number control register.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 64,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EOF_NUM": {
-                    "description": "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "CONF_SIGLE_DATA": {
-              "description": "I2S signal data register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SINGLE_DATA": {
-                    "description": "The configured constant channel data to be sent out.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "I2S TX status register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_IDLE": {
-                    "description": "1: i2s_tx is idle state. 0: i2s_tx is working.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 33583648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "I2S version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "INTERRUPT_CORE0": {
-        "description": "Interrupt Core",
-        "children": {
-          "registers": {
-            "MAC_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_INTR_MAP": {
-                    "description": "core0_mac_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "MAC_NMI_MAP": {
-              "description": "mac nmi_intr map register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_NMI_MAP": {
-                    "description": "reg_core0_mac_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "PWR_INTR_MAP": {
-              "description": "pwr intr map register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_INTR_MAP": {
-                    "description": "reg_core0_pwr_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BB_INT_MAP": {
-              "description": "bb intr map register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BB_INT_MAP": {
-                    "description": "reg_core0_bb_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_MAC_INT_MAP": {
-              "description": "bt intr map register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_MAC_INT_MAP": {
-                    "description": "reg_core0_bt_mac_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_BB_INT_MAP": {
-              "description": "bb_bt intr map register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_BB_INT_MAP": {
-                    "description": "reg_core0_bt_bb_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_BB_NMI_MAP": {
-              "description": "bb_bt_nmi intr map register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_BB_NMI_MAP": {
-                    "description": "reg_core0_bt_bb_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBT_IRQ_MAP": {
-              "description": "rwbt intr map register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBT_IRQ_MAP": {
-                    "description": "reg_core0_rwbt_irq_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBLE_IRQ_MAP": {
-              "description": "rwble intr map register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBLE_IRQ_MAP": {
-                    "description": "reg_core0_rwble_irq_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBT_NMI_MAP": {
-              "description": "rwbt_nmi intr map register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBT_NMI_MAP": {
-                    "description": "reg_core0_rwbt_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBLE_NMI_MAP": {
-              "description": "rwble_nmi intr map register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBLE_NMI_MAP": {
-                    "description": "reg_core0_rwble_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2C_MST_INT_MAP": {
-              "description": "i2c intr map register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2C_MST_INT_MAP": {
-                    "description": "reg_core0_i2c_mst_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SLC0_INTR_MAP": {
-              "description": "slc0 intr map register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLC0_INTR_MAP": {
-                    "description": "reg_core0_slc0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SLC1_INTR_MAP": {
-              "description": "slc1 intr map register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLC1_INTR_MAP": {
-                    "description": "reg_core0_slc1_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "APB_CTRL_INTR_MAP": {
-              "description": "apb_ctrl intr map register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_CTRL_INTR_MAP": {
-                    "description": "reg_core0_apb_ctrl_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UHCI0_INTR_MAP": {
-              "description": "uchi0 intr map register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UHCI0_INTR_MAP": {
-                    "description": "reg_core0_uhci0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "GPIO_INTERRUPT_PRO_MAP": {
-              "description": "gpio intr map register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_INTERRUPT_PRO_MAP": {
-                    "description": "reg_core0_gpio_interrupt_pro_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "GPIO_INTERRUPT_PRO_NMI_MAP": {
-              "description": "gpio_pro intr map register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_INTERRUPT_PRO_NMI_MAP": {
-                    "description": "reg_core0_gpio_interrupt_pro_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_INTR_1_MAP": {
-              "description": "gpio_pro_nmi intr map register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_INTR_1_MAP": {
-                    "description": "reg_core0_spi_intr_1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_INTR_2_MAP": {
-              "description": "spi1 intr map register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_INTR_2_MAP": {
-                    "description": "reg_core0_spi_intr_2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2S1_INT_MAP": {
-              "description": "spi2 intr map register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2S1_INT_MAP": {
-                    "description": "reg_core0_i2s1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UART_INTR_MAP": {
-              "description": "i2s1 intr map register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UART_INTR_MAP": {
-                    "description": "reg_core0_uart_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UART1_INTR_MAP": {
-              "description": "uart1 intr map register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UART1_INTR_MAP": {
-                    "description": "reg_core0_uart1_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "LEDC_INT_MAP": {
-              "description": "ledc intr map register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LEDC_INT_MAP": {
-                    "description": "reg_core0_ledc_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "EFUSE_INT_MAP": {
-              "description": "efuse intr map register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_INT_MAP": {
-                    "description": "reg_core0_efuse_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CAN_INT_MAP": {
-              "description": "can intr map register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CAN_INT_MAP": {
-                    "description": "reg_core0_can_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "USB_INTR_MAP": {
-              "description": "usb intr map register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USB_INTR_MAP": {
-                    "description": "reg_core0_usb_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RTC_CORE_INTR_MAP": {
-              "description": "rtc intr map register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CORE_INTR_MAP": {
-                    "description": "reg_core0_rtc_core_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RMT_INTR_MAP": {
-              "description": "rmt intr map register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RMT_INTR_MAP": {
-                    "description": "reg_core0_rmt_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2C_EXT0_INTR_MAP": {
-              "description": "i2c intr map register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2C_EXT0_INTR_MAP": {
-                    "description": "reg_core0_i2c_ext0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMER_INT1_MAP": {
-              "description": "timer1 intr map register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_INT1_MAP": {
-                    "description": "reg_core0_timer_int1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMER_INT2_MAP": {
-              "description": "timer2 intr map register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_INT2_MAP": {
-                    "description": "reg_core0_timer_int2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG_T0_INT_MAP": {
-              "description": "tg to intr map register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG_T0_INT_MAP": {
-                    "description": "reg_core0_tg_t0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG_WDT_INT_MAP": {
-              "description": "tg wdt intr map register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG_WDT_INT_MAP": {
-                    "description": "reg_core0_tg_wdt_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG1_T0_INT_MAP": {
-              "description": "tg1 to intr map register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG1_T0_INT_MAP": {
-                    "description": "reg_core0_tg1_t0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG1_WDT_INT_MAP": {
-              "description": "tg1 wdt intr map register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG1_WDT_INT_MAP": {
-                    "description": "reg_core0_tg1_wdt_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CACHE_IA_INT_MAP": {
-              "description": "cache ia intr map register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_IA_INT_MAP": {
-                    "description": "reg_core0_cache_ia_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET0_INT_MAP": {
-              "description": "systimer intr map register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET0_INT_MAP": {
-                    "description": "reg_core0_systimer_target0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET1_INT_MAP": {
-              "description": "systimer target1 intr map register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET1_INT_MAP": {
-                    "description": "reg_core0_systimer_target1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET2_INT_MAP": {
-              "description": "systimer target2 intr map register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET2_INT_MAP": {
-                    "description": "reg_core0_systimer_target2_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_MEM_REJECT_INTR_MAP": {
-              "description": "spi mem reject intr map register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_INTR_MAP": {
-                    "description": "reg_core0_spi_mem_reject_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_INT_MAP": {
-              "description": "icache perload intr map register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_INT_MAP": {
-                    "description": "reg_core0_icache_preload_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_INT_MAP": {
-              "description": "icache sync intr map register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_INT_MAP": {
-                    "description": "reg_core0_icache_sync_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "APB_ADC_INT_MAP": {
-              "description": "adc intr map register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_ADC_INT_MAP": {
-                    "description": "reg_core0_apb_adc_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH0_INT_MAP": {
-              "description": "dma ch0 intr map register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH0_INT_MAP": {
-                    "description": "reg_core0_dma_ch0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH1_INT_MAP": {
-              "description": "dma ch1 intr map register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH1_INT_MAP": {
-                    "description": "reg_core0_dma_ch1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH2_INT_MAP": {
-              "description": "dma ch2 intr map register",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH2_INT_MAP": {
-                    "description": "reg_core0_dma_ch2_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RSA_INT_MAP": {
-              "description": "rsa intr map register",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RSA_INT_MAP": {
-                    "description": "reg_core0_rsa_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "AES_INT_MAP": {
-              "description": "aes intr map register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AES_INT_MAP": {
-                    "description": "reg_core0_aes_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SHA_INT_MAP": {
-              "description": "sha intr map register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SHA_INT_MAP": {
-                    "description": "reg_core0_sha_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_0_MAP": {
-              "description": "cpu from cpu 0 intr map register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_0_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_0_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_1_MAP": {
-              "description": "cpu from cpu 0 intr map register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_1_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_2_MAP": {
-              "description": "cpu from cpu 1 intr map register",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_2_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_3_MAP": {
-              "description": "cpu from cpu 3 intr map register",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_3_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_3_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ASSIST_DEBUG_INTR_MAP": {
-              "description": "assist debug intr map register",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ASSIST_DEBUG_INTR_MAP": {
-                    "description": "reg_core0_assist_debug_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "dma pms violatile intr map register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_dma_apbperi_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "iram0 pms violatile intr map register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_iram0_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_dram0_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_pif_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
-                    "description": "reg_core0_core_0_pif_pms_monitor_violate_size_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BACKUP_PMS_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_PMS_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_backup_pms_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CACHE_CORE0_ACS_INT_MAP": {
-              "description": "mac intr map register",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_CORE0_ACS_INT_MAP": {
-                    "description": "reg_core0_cache_core0_acs_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "INTR_STATUS_REG_0": {
-              "description": "mac intr map register",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTR_STATUS_0": {
-                    "description": "reg_core0_intr_status_0",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INTR_STATUS_REG_1": {
-              "description": "mac intr map register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTR_STATUS_1": {
-                    "description": "reg_core0_intr_status_1",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "mac intr map register",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_CLK_EN": {
-                    "description": "reg_core0_reg_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INT_ENABLE": {
-              "description": "mac intr map register",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_ENABLE": {
-                    "description": "reg_core0_cpu_int_enable",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_TYPE": {
-              "description": "mac intr map register",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_TYPE": {
-                    "description": "reg_core0_cpu_int_type",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_CLEAR": {
-              "description": "mac intr map register",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_CLEAR": {
-                    "description": "reg_core0_cpu_int_clear",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_EIP_STATUS": {
-              "description": "mac intr map register",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_EIP_STATUS": {
-                    "description": "reg_core0_cpu_int_eip_status",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_0": {
-              "description": "mac intr map register",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_0_MAP": {
-                    "description": "reg_core0_cpu_pri_0_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_1": {
-              "description": "mac intr map register",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_1_MAP": {
-                    "description": "reg_core0_cpu_pri_1_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_2": {
-              "description": "mac intr map register",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_2_MAP": {
-                    "description": "reg_core0_cpu_pri_2_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_3": {
-              "description": "mac intr map register",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_3_MAP": {
-                    "description": "reg_core0_cpu_pri_3_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_4": {
-              "description": "mac intr map register",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_4_MAP": {
-                    "description": "reg_core0_cpu_pri_4_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_5": {
-              "description": "mac intr map register",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_5_MAP": {
-                    "description": "reg_core0_cpu_pri_5_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_6": {
-              "description": "mac intr map register",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_6_MAP": {
-                    "description": "reg_core0_cpu_pri_6_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_7": {
-              "description": "mac intr map register",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_7_MAP": {
-                    "description": "reg_core0_cpu_pri_7_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_8": {
-              "description": "mac intr map register",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_8_MAP": {
-                    "description": "reg_core0_cpu_pri_8_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_9": {
-              "description": "mac intr map register",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_9_MAP": {
-                    "description": "reg_core0_cpu_pri_9_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_10": {
-              "description": "mac intr map register",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_10_MAP": {
-                    "description": "reg_core0_cpu_pri_10_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_11": {
-              "description": "mac intr map register",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_11_MAP": {
-                    "description": "reg_core0_cpu_pri_11_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_12": {
-              "description": "mac intr map register",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_12_MAP": {
-                    "description": "reg_core0_cpu_pri_12_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_13": {
-              "description": "mac intr map register",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_13_MAP": {
-                    "description": "reg_core0_cpu_pri_13_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_14": {
-              "description": "mac intr map register",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_14_MAP": {
-                    "description": "reg_core0_cpu_pri_14_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_15": {
-              "description": "mac intr map register",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_15_MAP": {
-                    "description": "reg_core0_cpu_pri_15_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_16": {
-              "description": "mac intr map register",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_16_MAP": {
-                    "description": "reg_core0_cpu_pri_16_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_17": {
-              "description": "mac intr map register",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_17_MAP": {
-                    "description": "reg_core0_cpu_pri_17_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_18": {
-              "description": "mac intr map register",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_18_MAP": {
-                    "description": "reg_core0_cpu_pri_18_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_19": {
-              "description": "mac intr map register",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_19_MAP": {
-                    "description": "reg_core0_cpu_pri_19_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_20": {
-              "description": "mac intr map register",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_20_MAP": {
-                    "description": "reg_core0_cpu_pri_20_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_21": {
-              "description": "mac intr map register",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_21_MAP": {
-                    "description": "reg_core0_cpu_pri_21_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_22": {
-              "description": "mac intr map register",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_22_MAP": {
-                    "description": "reg_core0_cpu_pri_22_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_23": {
-              "description": "mac intr map register",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_23_MAP": {
-                    "description": "reg_core0_cpu_pri_23_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_24": {
-              "description": "mac intr map register",
-              "offset": 372,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_24_MAP": {
-                    "description": "reg_core0_cpu_pri_24_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_25": {
-              "description": "mac intr map register",
-              "offset": 376,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_25_MAP": {
-                    "description": "reg_core0_cpu_pri_25_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_26": {
-              "description": "mac intr map register",
-              "offset": 380,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_26_MAP": {
-                    "description": "reg_core0_cpu_pri_26_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_27": {
-              "description": "mac intr map register",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_27_MAP": {
-                    "description": "reg_core0_cpu_pri_27_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_28": {
-              "description": "mac intr map register",
-              "offset": 388,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_28_MAP": {
-                    "description": "reg_core0_cpu_pri_28_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_29": {
-              "description": "mac intr map register",
-              "offset": 392,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_29_MAP": {
-                    "description": "reg_core0_cpu_pri_29_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_30": {
-              "description": "mac intr map register",
-              "offset": 396,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_30_MAP": {
-                    "description": "reg_core0_cpu_pri_30_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_31": {
-              "description": "mac intr map register",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_31_MAP": {
-                    "description": "reg_core0_cpu_pri_31_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_THRESH": {
-              "description": "mac intr map register",
-              "offset": 404,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_THRESH": {
-                    "description": "reg_core0_cpu_int_thresh",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "INTERRUPT_REG_DATE": {
-              "description": "mac intr map register",
-              "offset": 2044,
-              "size": 32,
-              "reset_value": 33583632,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT_REG_DATE": {
-                    "description": "reg_core0_interrupt_reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "IO_MUX": {
-        "description": "Input/Output Multiplexer",
-        "children": {
-          "registers": {
-            "PIN_CTRL": {
-              "description": "Clock Output Configuration Register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 2047,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_OUT1": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_OUT2": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.",
-                    "offset": 4,
-                    "size": 4
-                  },
-                  "CLK_OUT3": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.",
-                    "offset": 8,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "GPIO": {
-              "description": "IO MUX Configure Register for pad XTAL_32K_P",
-              "offset": 4,
-              "size": 32,
-              "count": 22,
-              "reset_value": 2816,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MCU_OE": {
-                    "description": "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SLP_SEL": {
-                    "description": "Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MCU_WPD": {
-                    "description": "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "MCU_WPU": {
-                    "description": "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MCU_IE": {
-                    "description": "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FUN_WPD": {
-                    "description": "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FUN_WPU": {
-                    "description": "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FUN_IE": {
-                    "description": "Input enable of the pad. 1: input enabled; 0: input disabled.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FUN_DRV": {
-                    "description": "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "MCU_SEL": {
-                    "description": "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "FILTER_EN": {
-                    "description": "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "IO MUX Version Control Register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 33579088,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_DATE": {
-                    "description": "Version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "LEDC": {
-        "description": "LED Control PWM (Pulse Width Modulation)",
-        "children": {
-          "registers": {
-            "LSCH0_CONF0": {
-              "description": "LEDC_LSCH0_CONF0.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH0": {
-                    "description": "reg_timer_sel_lsch0.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH0": {
-                    "description": "reg_sig_out_en_lsch0.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH0": {
-                    "description": "reg_idle_lv_lsch0.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH0": {
-                    "description": "reg_para_up_lsch0.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH0": {
-                    "description": "reg_ovf_num_lsch0.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH0": {
-                    "description": "reg_ovf_cnt_en_lsch0.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH0": {
-                    "description": "reg_ovf_cnt_reset_lsch0.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH0_HPOINT": {
-              "description": "LEDC_LSCH0_HPOINT.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH0": {
-                    "description": "reg_hpoint_lsch0.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH0_DUTY": {
-              "description": "LEDC_LSCH0_DUTY.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH0": {
-                    "description": "reg_duty_lsch0.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH0_CONF1": {
-              "description": "LEDC_LSCH0_CONF1.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH0": {
-                    "description": "reg_duty_scale_lsch0.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH0": {
-                    "description": "reg_duty_cycle_lsch0.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH0": {
-                    "description": "reg_duty_num_lsch0.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH0": {
-                    "description": "reg_duty_inc_lsch0.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH0": {
-                    "description": "reg_duty_start_lsch0.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH0_DUTY_R": {
-              "description": "LEDC_LSCH0_DUTY_R.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH0_R": {
-                    "description": "reg_duty_lsch0_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH1_CONF0": {
-              "description": "LEDC_LSCH1_CONF0.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH1": {
-                    "description": "reg_timer_sel_lsch1.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH1": {
-                    "description": "reg_sig_out_en_lsch1.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH1": {
-                    "description": "reg_idle_lv_lsch1.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH1": {
-                    "description": "reg_para_up_lsch1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH1": {
-                    "description": "reg_ovf_num_lsch1.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH1": {
-                    "description": "reg_ovf_cnt_en_lsch1.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH1": {
-                    "description": "reg_ovf_cnt_reset_lsch1.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH1_HPOINT": {
-              "description": "LEDC_LSCH1_HPOINT.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH1": {
-                    "description": "reg_hpoint_lsch1.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH1_DUTY": {
-              "description": "LEDC_LSCH1_DUTY.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH1": {
-                    "description": "reg_duty_lsch1.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH1_CONF1": {
-              "description": "LEDC_LSCH1_CONF1.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH1": {
-                    "description": "reg_duty_scale_lsch1.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH1": {
-                    "description": "reg_duty_cycle_lsch1.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH1": {
-                    "description": "reg_duty_num_lsch1.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH1": {
-                    "description": "reg_duty_inc_lsch1.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH1": {
-                    "description": "reg_duty_start_lsch1.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH1_DUTY_R": {
-              "description": "LEDC_LSCH1_DUTY_R.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH1_R": {
-                    "description": "reg_duty_lsch1_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH2_CONF0": {
-              "description": "LEDC_LSCH2_CONF0.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH2": {
-                    "description": "reg_timer_sel_lsch2.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH2": {
-                    "description": "reg_sig_out_en_lsch2.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH2": {
-                    "description": "reg_idle_lv_lsch2.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH2": {
-                    "description": "reg_para_up_lsch2.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH2": {
-                    "description": "reg_ovf_num_lsch2.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH2": {
-                    "description": "reg_ovf_cnt_en_lsch2.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH2": {
-                    "description": "reg_ovf_cnt_reset_lsch2.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH2_HPOINT": {
-              "description": "LEDC_LSCH2_HPOINT.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH2": {
-                    "description": "reg_hpoint_lsch2.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH2_DUTY": {
-              "description": "LEDC_LSCH2_DUTY.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH2": {
-                    "description": "reg_duty_lsch2.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH2_CONF1": {
-              "description": "LEDC_LSCH2_CONF1.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH2": {
-                    "description": "reg_duty_scale_lsch2.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH2": {
-                    "description": "reg_duty_cycle_lsch2.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH2": {
-                    "description": "reg_duty_num_lsch2.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH2": {
-                    "description": "reg_duty_inc_lsch2.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH2": {
-                    "description": "reg_duty_start_lsch2.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH2_DUTY_R": {
-              "description": "LEDC_LSCH2_DUTY_R.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH2_R": {
-                    "description": "reg_duty_lsch2_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH3_CONF0": {
-              "description": "LEDC_LSCH3_CONF0.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH3": {
-                    "description": "reg_timer_sel_lsch3.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH3": {
-                    "description": "reg_sig_out_en_lsch3.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH3": {
-                    "description": "reg_idle_lv_lsch3.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH3": {
-                    "description": "reg_para_up_lsch3.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH3": {
-                    "description": "reg_ovf_num_lsch3.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH3": {
-                    "description": "reg_ovf_cnt_en_lsch3.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH3": {
-                    "description": "reg_ovf_cnt_reset_lsch3.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH3_HPOINT": {
-              "description": "LEDC_LSCH3_HPOINT.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH3": {
-                    "description": "reg_hpoint_lsch3.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH3_DUTY": {
-              "description": "LEDC_LSCH3_DUTY.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH3": {
-                    "description": "reg_duty_lsch3.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH3_CONF1": {
-              "description": "LEDC_LSCH3_CONF1.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH3": {
-                    "description": "reg_duty_scale_lsch3.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH3": {
-                    "description": "reg_duty_cycle_lsch3.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH3": {
-                    "description": "reg_duty_num_lsch3.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH3": {
-                    "description": "reg_duty_inc_lsch3.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH3": {
-                    "description": "reg_duty_start_lsch3.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH3_DUTY_R": {
-              "description": "LEDC_LSCH3_DUTY_R.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH3_R": {
-                    "description": "reg_duty_lsch3_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH4_CONF0": {
-              "description": "LEDC_LSCH4_CONF0.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH4": {
-                    "description": "reg_timer_sel_lsch4.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH4": {
-                    "description": "reg_sig_out_en_lsch4.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH4": {
-                    "description": "reg_idle_lv_lsch4.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH4": {
-                    "description": "reg_para_up_lsch4.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH4": {
-                    "description": "reg_ovf_num_lsch4.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH4": {
-                    "description": "reg_ovf_cnt_en_lsch4.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH4": {
-                    "description": "reg_ovf_cnt_reset_lsch4.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH4_HPOINT": {
-              "description": "LEDC_LSCH4_HPOINT.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH4": {
-                    "description": "reg_hpoint_lsch4.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH4_DUTY": {
-              "description": "LEDC_LSCH4_DUTY.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH4": {
-                    "description": "reg_duty_lsch4.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH4_CONF1": {
-              "description": "LEDC_LSCH4_CONF1.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH4": {
-                    "description": "reg_duty_scale_lsch4.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH4": {
-                    "description": "reg_duty_cycle_lsch4.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH4": {
-                    "description": "reg_duty_num_lsch4.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH4": {
-                    "description": "reg_duty_inc_lsch4.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH4": {
-                    "description": "reg_duty_start_lsch4.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH4_DUTY_R": {
-              "description": "LEDC_LSCH4_DUTY_R.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH4_R": {
-                    "description": "reg_duty_lsch4_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH5_CONF0": {
-              "description": "LEDC_LSCH5_CONF0.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH5": {
-                    "description": "reg_timer_sel_lsch5.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH5": {
-                    "description": "reg_sig_out_en_lsch5.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH5": {
-                    "description": "reg_idle_lv_lsch5.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH5": {
-                    "description": "reg_para_up_lsch5.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH5": {
-                    "description": "reg_ovf_num_lsch5.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH5": {
-                    "description": "reg_ovf_cnt_en_lsch5.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH5": {
-                    "description": "reg_ovf_cnt_reset_lsch5.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH5_HPOINT": {
-              "description": "LEDC_LSCH5_HPOINT.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH5": {
-                    "description": "reg_hpoint_lsch5.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH5_DUTY": {
-              "description": "LEDC_LSCH5_DUTY.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH5": {
-                    "description": "reg_duty_lsch5.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH5_CONF1": {
-              "description": "LEDC_LSCH5_CONF1.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH5": {
-                    "description": "reg_duty_scale_lsch5.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH5": {
-                    "description": "reg_duty_cycle_lsch5.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH5": {
-                    "description": "reg_duty_num_lsch5.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH5": {
-                    "description": "reg_duty_inc_lsch5.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH5": {
-                    "description": "reg_duty_start_lsch5.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH5_DUTY_R": {
-              "description": "LEDC_LSCH5_DUTY_R.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH5_R": {
-                    "description": "reg_duty_lsch5_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER0_CONF": {
-              "description": "LEDC_LSTIMER0_CONF.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_DUTY_RES": {
-                    "description": "reg_lstimer0_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER0": {
-                    "description": "reg_clk_div_lstimer0.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER0_PAUSE": {
-                    "description": "reg_lstimer0_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER0_RST": {
-                    "description": "reg_lstimer0_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER0": {
-                    "description": "reg_tick_sel_lstimer0.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER0_PARA_UP": {
-                    "description": "reg_lstimer0_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER0_VALUE": {
-              "description": "LEDC_LSTIMER0_VALUE.",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_CNT": {
-                    "description": "reg_lstimer0_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER1_CONF": {
-              "description": "LEDC_LSTIMER1_CONF.",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER1_DUTY_RES": {
-                    "description": "reg_lstimer1_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER1": {
-                    "description": "reg_clk_div_lstimer1.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER1_PAUSE": {
-                    "description": "reg_lstimer1_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER1_RST": {
-                    "description": "reg_lstimer1_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER1": {
-                    "description": "reg_tick_sel_lstimer1.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER1_PARA_UP": {
-                    "description": "reg_lstimer1_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER1_VALUE": {
-              "description": "LEDC_LSTIMER1_VALUE.",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER1_CNT": {
-                    "description": "reg_lstimer1_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER2_CONF": {
-              "description": "LEDC_LSTIMER2_CONF.",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER2_DUTY_RES": {
-                    "description": "reg_lstimer2_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER2": {
-                    "description": "reg_clk_div_lstimer2.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER2_PAUSE": {
-                    "description": "reg_lstimer2_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER2_RST": {
-                    "description": "reg_lstimer2_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER2": {
-                    "description": "reg_tick_sel_lstimer2.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER2_PARA_UP": {
-                    "description": "reg_lstimer2_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER2_VALUE": {
-              "description": "LEDC_LSTIMER2_VALUE.",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER2_CNT": {
-                    "description": "reg_lstimer2_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER3_CONF": {
-              "description": "LEDC_LSTIMER3_CONF.",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER3_DUTY_RES": {
-                    "description": "reg_lstimer3_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER3": {
-                    "description": "reg_clk_div_lstimer3.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER3_PAUSE": {
-                    "description": "reg_lstimer3_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER3_RST": {
-                    "description": "reg_lstimer3_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER3": {
-                    "description": "reg_tick_sel_lstimer3.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER3_PARA_UP": {
-                    "description": "reg_lstimer3_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER3_VALUE": {
-              "description": "LEDC_LSTIMER3_VALUE.",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER3_CNT": {
-                    "description": "reg_lstimer3_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "LEDC_INT_RAW.",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_RAW": {
-                    "description": "reg_lstimer0_ovf_int_raw.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER1_OVF_INT_RAW": {
-                    "description": "reg_lstimer1_ovf_int_raw.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER2_OVF_INT_RAW": {
-                    "description": "reg_lstimer2_ovf_int_raw.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER3_OVF_INT_RAW": {
-                    "description": "reg_lstimer3_ovf_int_raw.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch0_int_raw.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch1_int_raw.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch2_int_raw.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch3_int_raw.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch4_int_raw.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch5_int_raw.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch0_int_raw.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch1_int_raw.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch2_int_raw.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch3_int_raw.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch4_int_raw.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch5_int_raw.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "LEDC_INT_ST.",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_ST": {
-                    "description": "reg_lstimer0_ovf_int_st.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER1_OVF_INT_ST": {
-                    "description": "reg_lstimer1_ovf_int_st.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER2_OVF_INT_ST": {
-                    "description": "reg_lstimer2_ovf_int_st.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER3_OVF_INT_ST": {
-                    "description": "reg_lstimer3_ovf_int_st.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch0_int_st.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch1_int_st.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch2_int_st.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch3_int_st.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch4_int_st.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch5_int_st.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch0_int_st.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch1_int_st.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch2_int_st.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch3_int_st.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch4_int_st.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch5_int_st.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "LEDC_INT_ENA.",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_ENA": {
-                    "description": "reg_lstimer0_ovf_int_ena.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "LSTIMER1_OVF_INT_ENA": {
-                    "description": "reg_lstimer1_ovf_int_ena.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "LSTIMER2_OVF_INT_ENA": {
-                    "description": "reg_lstimer2_ovf_int_ena.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "LSTIMER3_OVF_INT_ENA": {
-                    "description": "reg_lstimer3_ovf_int_ena.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch0_int_ena.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch1_int_ena.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch2_int_ena.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch3_int_ena.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch4_int_ena.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch5_int_ena.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH0_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch0_int_ena.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH1_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch1_int_ena.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH2_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch2_int_ena.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH3_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch3_int_ena.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH4_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch4_int_ena.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH5_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch5_int_ena.",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "LEDC_INT_CLR.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_CLR": {
-                    "description": "reg_lstimer0_ovf_int_clr.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER1_OVF_INT_CLR": {
-                    "description": "reg_lstimer1_ovf_int_clr.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER2_OVF_INT_CLR": {
-                    "description": "reg_lstimer2_ovf_int_clr.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER3_OVF_INT_CLR": {
-                    "description": "reg_lstimer3_ovf_int_clr.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch0_int_clr.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch1_int_clr.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch2_int_clr.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch3_int_clr.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch4_int_clr.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch5_int_clr.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch0_int_clr.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch1_int_clr.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch2_int_clr.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch3_int_clr.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch4_int_clr.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch5_int_clr.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONF": {
-              "description": "LEDC_CONF.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_CLK_SEL": {
-                    "description": "reg_apb_clk_sel.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "LEDC_DATE.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 419829504,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LEDC_DATE": {
-                    "description": "reg_ledc_date.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RMT": {
-        "description": "Remote Control Peripheral",
-        "children": {
-          "registers": {
-            "CH0DATA": {
-              "description": "RMT_CH0DATA_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH1DATA": {
-              "description": "RMT_CH1DATA_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH2DATA": {
-              "description": "RMT_CH2DATA_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH3DATA": {
-              "description": "RMT_CH3DATA_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH2CONF1": {
-              "description": "RMT_CH2CONF1_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 488,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EN": {
-                    "description": "reg_rx_en_ch2.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_WR_RST": {
-                    "description": "reg_mem_wr_rst_ch2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_MEM_RST": {
-                    "description": "reg_apb_mem_rst_ch2.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MEM_OWNER": {
-                    "description": "reg_mem_owner_ch2.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_FILTER_EN": {
-                    "description": "reg_rx_filter_en_ch2.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_FILTER_THRES": {
-                    "description": "reg_rx_filter_thres_ch2.",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "MEM_RX_WRAP_EN": {
-                    "description": "reg_mem_rx_wrap_en_ch2.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "AFIFO_RST": {
-                    "description": "reg_afifo_rst_ch2.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPDATE": {
-                    "description": "reg_conf_update_ch2.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH3CONF1": {
-              "description": "RMT_CH3CONF1_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 488,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EN": {
-                    "description": "reg_rx_en_ch3.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_WR_RST": {
-                    "description": "reg_mem_wr_rst_ch3.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_MEM_RST": {
-                    "description": "reg_apb_mem_rst_ch3.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MEM_OWNER": {
-                    "description": "reg_mem_owner_ch3.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_FILTER_EN": {
-                    "description": "reg_rx_filter_en_ch3.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_FILTER_THRES": {
-                    "description": "reg_rx_filter_thres_ch3.",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "MEM_RX_WRAP_EN": {
-                    "description": "reg_mem_rx_wrap_en_ch3.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "AFIFO_RST": {
-                    "description": "reg_afifo_rst_ch3.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPDATE": {
-                    "description": "reg_conf_update_ch3.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH0STATUS": {
-              "description": "RMT_CH0STATUS_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_RADDR_EX": {
-                    "description": "reg_mem_raddr_ex_ch0.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch0.",
-                    "offset": 9,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WADDR": {
-                    "description": "reg_apb_mem_waddr_ch0.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch0.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_EMPTY": {
-                    "description": "reg_mem_empty_ch0.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WR_ERR": {
-                    "description": "reg_apb_mem_wr_err_ch0.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch0.",
-                    "offset": 24,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH1STATUS": {
-              "description": "RMT_CH1STATUS_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_RADDR_EX": {
-                    "description": "reg_mem_raddr_ex_ch1.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch1.",
-                    "offset": 9,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WADDR": {
-                    "description": "reg_apb_mem_waddr_ch1.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch1.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_EMPTY": {
-                    "description": "reg_mem_empty_ch1.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WR_ERR": {
-                    "description": "reg_apb_mem_wr_err_ch1.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch1.",
-                    "offset": 24,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH2STATUS": {
-              "description": "RMT_CH2STATUS_REG.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_WADDR_EX": {
-                    "description": "reg_mem_waddr_ex_ch2.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch2.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch2.",
-                    "offset": 22,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MEM_OWNER_ERR": {
-                    "description": "reg_mem_owner_err_ch2.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_FULL": {
-                    "description": "reg_mem_full_ch2.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch2.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH3STATUS": {
-              "description": "RMT_CH3STATUS_REG.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_WADDR_EX": {
-                    "description": "reg_mem_waddr_ex_ch3.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch3.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch3.",
-                    "offset": 22,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MEM_OWNER_ERR": {
-                    "description": "reg_mem_owner_err_ch3.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_FULL": {
-                    "description": "reg_mem_full_ch3.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch3.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "RMT_INT_RAW_REG.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_RAW": {
-                    "description": "reg_ch2_rx_thr_event_int_raw.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_RAW": {
-                    "description": "reg_ch3_rx_thr_event_int_raw.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "RMT_INT_ST_REG.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_ST": {
-                    "description": "reg_ch2_rx_thr_event_int_st.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_ST": {
-                    "description": "reg_ch3_rx_thr_event_int_st.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "RMT_INT_ENA_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_ENA": {
-                    "description": "reg_ch2_rx_thr_event_int_ena.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CH3_RX_THR_EVENT_INT_ENA": {
-                    "description": "reg_ch3_rx_thr_event_int_ena.",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "RMT_INT_CLR_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_CLR": {
-                    "description": "reg_ch2_rx_thr_event_int_clr.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_CLR": {
-                    "description": "reg_ch3_rx_thr_event_int_clr.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH0CARRIER_DUTY": {
-              "description": "RMT_CH0CARRIER_DUTY_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 4194368,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW": {
-                    "description": "reg_carrier_low_ch0.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH": {
-                    "description": "reg_carrier_high_ch0.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH1CARRIER_DUTY": {
-              "description": "RMT_CH1CARRIER_DUTY_REG.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 4194368,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW": {
-                    "description": "reg_carrier_low_ch1.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH": {
-                    "description": "reg_carrier_high_ch1.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH2_RX_CARRIER_RM": {
-              "description": "RMT_CH2_RX_CARRIER_RM_REG.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW_THRES": {
-                    "description": "reg_carrier_low_thres_ch2.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH_THRES": {
-                    "description": "reg_carrier_high_thres_ch2.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH3_RX_CARRIER_RM": {
-              "description": "RMT_CH3_RX_CARRIER_RM_REG.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW_THRES": {
-                    "description": "reg_carrier_low_thres_ch3.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH_THRES": {
-                    "description": "reg_carrier_high_thres_ch3.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "SYS_CONF": {
-              "description": "RMT_SYS_CONF_REG.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 83886096,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_FIFO_MASK": {
-                    "description": "reg_apb_fifo_mask.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_CLK_FORCE_ON": {
-                    "description": "reg_mem_clk_force_on.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PD": {
-                    "description": "reg_rmt_mem_force_pd.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PU": {
-                    "description": "reg_rmt_mem_force_pu.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SCLK_DIV_NUM": {
-                    "description": "reg_rmt_sclk_div_num.",
-                    "offset": 4,
-                    "size": 8
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "reg_rmt_sclk_div_a.",
-                    "offset": 12,
-                    "size": 6
-                  },
-                  "SCLK_DIV_B": {
-                    "description": "reg_rmt_sclk_div_b.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "SCLK_SEL": {
-                    "description": "reg_rmt_sclk_sel.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "SCLK_ACTIVE": {
-                    "description": "reg_rmt_sclk_active.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_SIM": {
-              "description": "RMT_TX_SIM_REG.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_SIM_CH0": {
-                    "description": "reg_rmt_tx_sim_ch0.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_SIM_CH1": {
-                    "description": "reg_rmt_tx_sim_ch1.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_SIM_EN": {
-                    "description": "reg_rmt_tx_sim_en.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REF_CNT_RST": {
-              "description": "RMT_REF_CNT_RST_REG.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH0": {
-                    "description": "reg_ref_cnt_rst_ch0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH1": {
-                    "description": "reg_ref_cnt_rst_ch1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH2": {
-                    "description": "reg_ref_cnt_rst_ch2.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH3": {
-                    "description": "reg_ref_cnt_rst_ch3.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "RMT_DATE_REG.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 33579569,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_rmt_date.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RNG": {
-        "description": "Hardware random number generator",
-        "children": {
-          "registers": {
-            "DATA": {
-              "description": "Random number data",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            }
-          }
-        }
-      },
-      "RSA": {
-        "description": "RSA (Rivest Shamir Adleman) Accelerator",
-        "children": {
-          "registers": {
-            "M_MEM": {
-              "description": "The memory that stores M",
-              "offset": 0,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Z_MEM": {
-              "description": "The memory that stores Z",
-              "offset": 512,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Y_MEM": {
-              "description": "The memory that stores Y",
-              "offset": 1024,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "X_MEM": {
-              "description": "The memory that stores X",
-              "offset": 1536,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_PRIME": {
-              "description": "RSA M_prime register",
-              "offset": 2048,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "M_PRIME": {
-                    "description": "Those bits stores m'",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "MODE": {
-              "description": "RSA mode register",
-              "offset": 2052,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "rsa mode (rsa length).",
-                    "offset": 0,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "QUERY_CLEAN": {
-              "description": "RSA query clean register",
-              "offset": 2056,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_CLEAN": {
-                    "description": "query clean",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MODEXP": {
-              "description": "RSA modular exponentiation trigger register.",
-              "offset": 2060,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MODEXP": {
-                    "description": "start modular exponentiation",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MODMULT": {
-              "description": "RSA modular multiplication trigger register.",
-              "offset": 2064,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MODMULT": {
-                    "description": "start modular multiplication",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MULT": {
-              "description": "RSA normal multiplication trigger register.",
-              "offset": 2068,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MULT": {
-                    "description": "start multiplicaiton",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_IDLE": {
-              "description": "RSA query idle register",
-              "offset": 2072,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_IDLE": {
-                    "description": "query rsa idle. 1'b0: busy, 1'b1: idle",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "RSA interrupt clear register",
-              "offset": 2076,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLEAR_INTERRUPT": {
-                    "description": "set this bit to clear RSA interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONSTANT_TIME": {
-              "description": "RSA constant time option register",
-              "offset": 2080,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONSTANT_TIME": {
-                    "description": "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SEARCH_ENABLE": {
-              "description": "RSA search option",
-              "offset": 2084,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEARCH_ENABLE": {
-                    "description": "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SEARCH_POS": {
-              "description": "RSA search position configure register",
-              "offset": 2088,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEARCH_POS": {
-                    "description": "Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "RSA interrupt enable register",
-              "offset": 2092,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_ENA": {
-                    "description": "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "RSA version control register",
-              "offset": 2096,
-              "size": 32,
-              "reset_value": 538969624,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "rsa version information",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RTC_CNTL": {
-        "description": "Real-Time Clock Control",
-        "children": {
-          "registers": {
-            "OPTIONS0": {
-              "description": "rtc configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 469803008,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_STALL_APPCPU_C0": {
-                    "description": "{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SW_STALL_PROCPU_C0": {
-                    "description": "{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "SW_APPCPU_RST": {
-                    "description": "APP CPU SW reset",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_PROCPU_RST": {
-                    "description": "PRO CPU SW reset",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BB_I2C_FORCE_PD": {
-                    "description": "BB_I2C force power down",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BB_I2C_FORCE_PU": {
-                    "description": "BB_I2C force power up",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "BBPLL_I2C_FORCE_PD": {
-                    "description": "BB_PLL _I2C force power down",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "BBPLL_I2C_FORCE_PU": {
-                    "description": "BB_PLL_I2C force power up",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "BBPLL_FORCE_PD": {
-                    "description": "BB_PLL force power down",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "BBPLL_FORCE_PU": {
-                    "description": "BB_PLL force power up",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "XTL_FORCE_PD": {
-                    "description": "crystall force power down",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "XTL_FORCE_PU": {
-                    "description": "crystall force power up",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "XTL_EN_WAIT": {
-                    "description": "wait bias_sleep and current source wakeup",
-                    "offset": 14,
-                    "size": 4
-                  },
-                  "XTL_EXT_CTR_SEL": {
-                    "description": "analog configure",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "XTL_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PLL_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "ANALOG_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "XTL_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "PLL_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "ANALOG_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_RST": {
-                    "description": "digital wrap force reset in deep sleep",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_NORST": {
-                    "description": "digital core force no reset in deep sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SW_SYS_RST": {
-                    "description": "SW system reset",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SLP_TIMER0": {
-              "description": "rtc configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_VAL_LO": {
-                    "description": "configure the  sleep time",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SLP_TIMER1": {
-              "description": "rtc configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_VAL_HI": {
-                    "description": "RTC sleep timer high 16 bits",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "RTC_MAIN_TIMER_ALARM_EN": {
-                    "description": "timer alarm enable bit",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "TIME_UPDATE": {
-              "description": "rtc configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SYS_STALL": {
-                    "description": "Enable to record system stall time",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "TIMER_XTL_OFF": {
-                    "description": "Enable to record 40M XTAL OFF time",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "TIMER_SYS_RST": {
-                    "description": "enable to record system reset time",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_TIME_UPDATE": {
-                    "description": "Set 1: to update register with RTC timer",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "TIME_LOW0": {
-              "description": "rtc configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE0_LOW": {
-                    "description": "RTC timer low 32 bits",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_HIGH0": {
-              "description": "rtc configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE0_HIGH": {
-                    "description": "RTC timer high 16 bits",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "STATE0": {
-              "description": "rtc configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SW_CPU_INT": {
-                    "description": "rtc software interrupt to main cpu",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SLP_REJECT_CAUSE_CLR": {
-                    "description": "clear rtc sleep reject cause",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB2RTC_BRIDGE_SEL": {
-                    "description": "1: APB to RTC using bridge",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "SDIO_ACTIVE_IND": {
-                    "description": "SDIO active indication",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_WAKEUP": {
-                    "description": "leep wakeup bit",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "SLP_REJECT": {
-                    "description": "leep reject bit",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SLEEP_EN": {
-                    "description": "sleep enable bit",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TIMER1": {
-              "description": "rtc configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 672400387,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_STALL_EN": {
-                    "description": "CPU stall enable bit",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CPU_STALL_WAIT": {
-                    "description": "CPU stall wait cycles in fast_clk_rtc",
-                    "offset": 1,
-                    "size": 5
-                  },
-                  "CK8M_WAIT": {
-                    "description": "CK8M wait cycles in slow_clk_rtc",
-                    "offset": 6,
-                    "size": 8
-                  },
-                  "XTL_BUF_WAIT": {
-                    "description": "XTAL wait cycles in slow_clk_rtc",
-                    "offset": 14,
-                    "size": 10
-                  },
-                  "PLL_BUF_WAIT": {
-                    "description": "PLL wait cycles in slow_clk_rtc",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER2": {
-              "description": "rtc configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 16777216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_TIME_CK8M_OFF": {
-                    "description": "minimal cycles in slow_clk_rtc for CK8M in power down state",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER3": {
-              "description": "rtc configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 168299016,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_WAIT_TIMER": {
-                    "description": "wifi power domain wakeup time",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "WIFI_POWERUP_TIMER": {
-                    "description": "wifi power domain power on time",
-                    "offset": 9,
-                    "size": 7
-                  },
-                  "BT_WAIT_TIMER": {
-                    "description": "bt power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "BT_POWERUP_TIMER": {
-                    "description": "bt power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "TIMER4": {
-              "description": "rtc configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 270535176,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_TOP_WAIT_TIMER": {
-                    "description": "cpu top power domain wakeup time",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "CPU_TOP_POWERUP_TIMER": {
-                    "description": "cpu top power domain power on time",
-                    "offset": 9,
-                    "size": 7
-                  },
-                  "DG_WRAP_WAIT_TIMER": {
-                    "description": "digital wrap power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "DG_WRAP_POWERUP_TIMER": {
-                    "description": "digital wrap power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "TIMER5": {
-              "description": "rtc configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 32768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_SLP_VAL": {
-                    "description": "minimal sleep cycles in slow_clk_rtc",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER6": {
-              "description": "rtc configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 168296448,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DG_PERI_WAIT_TIMER": {
-                    "description": "digital peri power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "DG_PERI_POWERUP_TIMER": {
-                    "description": "digital peri power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "ANA_CONF": {
-              "description": "rtc configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 12845056,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_POR_FORCE_PD": {
-                    "description": "force no bypass i2c power on reset",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RESET_POR_FORCE_PU": {
-                    "description": "force bypass i2c power on reset",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "GLITCH_RST_EN": {
-                    "description": "enable glitch reset",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SAR_I2C_PU": {
-                    "description": "PLLA force power up",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "PLLA_FORCE_PD": {
-                    "description": "PLLA force power down",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PLLA_FORCE_PU": {
-                    "description": "PLLA force power up",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "BBPLL_CAL_SLP_START": {
-                    "description": "start BBPLL calibration during sleep",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PVTMON_PU": {
-                    "description": "1: PVTMON power up",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TXRF_I2C_PU": {
-                    "description": "1: TXRF_I2C power up",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "RFRX_PBUS_PU": {
-                    "description": "1: RFRX_PBUS power up",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CKGEN_I2C_PU": {
-                    "description": "1: CKGEN_I2C power up",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "PLL_I2C_PU": {
-                    "description": "power up pll i2c",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RESET_STATE": {
-              "description": "rtc configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 12288,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_CAUSE_PROCPU": {
-                    "description": "reset cause of PRO CPU",
-                    "offset": 0,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "RESET_CAUSE_APPCPU": {
-                    "description": "reset cause of APP CPU",
-                    "offset": 6,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "STAT_VECTOR_SEL_APPCPU": {
-                    "description": "APP CPU state vector sel",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "STAT_VECTOR_SEL_PROCPU": {
-                    "description": "PRO CPU state vector sel",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "ALL_RESET_FLAG_PROCPU": {
-                    "description": "PRO CPU reset_flag",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ALL_RESET_FLAG_APPCPU": {
-                    "description": "APP CPU reset flag",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ALL_RESET_FLAG_CLR_PROCPU": {
-                    "description": "clear PRO CPU reset_flag",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ALL_RESET_FLAG_CLR_APPCPU": {
-                    "description": "clear APP CPU reset flag",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OCD_HALT_ON_RESET_APPCPU": {
-                    "description": "APPCPU OcdHaltOnReset",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "OCD_HALT_ON_RESET_PROCPU": {
-                    "description": "PROCPU OcdHaltOnReset",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "JTAG_RESET_FLAG_PROCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_RESET_FLAG_APPCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_RESET_FLAG_CLR_PROCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "JTAG_RESET_FLAG_CLR_APPCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_DRESET_MASK_APPCPU": {
-                    "description": "configure dreset configure",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "RTC_DRESET_MASK_PROCPU": {
-                    "description": "configure dreset configure",
-                    "offset": 25,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WAKEUP_STATE": {
-              "description": "rtc configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 393216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_WAKEUP_ENA": {
-                    "description": "wakeup enable bitmap",
-                    "offset": 15,
-                    "size": 17
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC": {
-              "description": "rtc configure register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA": {
-                    "description": "enable sleep wakeup interrupt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SLP_REJECT_INT_ENA": {
-                    "description": "enable sleep reject interrupt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_WDT_INT_ENA": {
-                    "description": "enable RTC WDT interrupt",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_BROWN_OUT_INT_ENA": {
-                    "description": "enable brown out interrupt",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA": {
-                    "description": "enable RTC main timer interrupt",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "RTC_SWD_INT_ENA": {
-                    "description": "enable super watch dog interrupt",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA": {
-                    "description": "enable xtal32k_dead  interrupt",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RTC_GLITCH_DET_INT_ENA": {
-                    "description": "enbale gitch det interrupt",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA": {
-                    "description": "enbale bbpll cal end interrupt",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW_RTC": {
-              "description": "rtc configure register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_RAW": {
-                    "description": "sleep wakeup interrupt raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_REJECT_INT_RAW": {
-                    "description": "sleep reject interrupt raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_WDT_INT_RAW": {
-                    "description": "RTC WDT interrupt raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BROWN_OUT_INT_RAW": {
-                    "description": "brown out interrupt raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_RAW": {
-                    "description": "RTC main timer interrupt raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_SWD_INT_RAW": {
-                    "description": "super watch dog interrupt raw",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_RAW": {
-                    "description": "xtal32k dead detection interrupt raw",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_GLITCH_DET_INT_RAW": {
-                    "description": "glitch_det_interrupt_raw",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_RAW": {
-                    "description": "bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_RTC": {
-              "description": "rtc configure register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ST": {
-                    "description": "sleep wakeup interrupt state",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_REJECT_INT_ST": {
-                    "description": "sleep reject interrupt state",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_WDT_INT_ST": {
-                    "description": "RTC WDT interrupt state",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ST": {
-                    "description": "brown out interrupt state",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ST": {
-                    "description": "RTC main timer interrupt state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_SWD_INT_ST": {
-                    "description": "super watch dog interrupt state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ST": {
-                    "description": "xtal32k dead detection interrupt state",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ST": {
-                    "description": "glitch_det_interrupt state",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ST": {
-                    "description": "bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR_RTC": {
-              "description": "rtc configure register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_CLR": {
-                    "description": "Clear sleep wakeup interrupt state",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_CLR": {
-                    "description": "Clear sleep reject interrupt state",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_CLR": {
-                    "description": "Clear RTC WDT interrupt state",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_CLR": {
-                    "description": "Clear brown out interrupt state",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_CLR": {
-                    "description": "Clear RTC main timer interrupt state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_CLR": {
-                    "description": "Clear super watch dog interrupt state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_CLR": {
-                    "description": "Clear RTC WDT interrupt state",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_CLR": {
-                    "description": "Clear glitch det interrupt state",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_CLR": {
-                    "description": "clear bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STORE0": {
-              "description": "rtc configure register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH0": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE1": {
-              "description": "rtc configure register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH1": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE2": {
-              "description": "rtc configure register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH2": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE3": {
-              "description": "rtc configure register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH3": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "EXT_XTL_CONF": {
-              "description": "rtc configure register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 420992,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_WDT_EN": {
-                    "description": "xtal 32k watch dog enable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "XTAL32K_WDT_CLK_FO": {
-                    "description": "xtal 32k watch dog clock force on",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "XTAL32K_WDT_RESET": {
-                    "description": "xtal 32k watch dog sw reset",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "XTAL32K_EXT_CLK_FO": {
-                    "description": "xtal 32k external xtal clock force on",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_BACKUP": {
-                    "description": "xtal 32k switch to back up clock when xtal is dead",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_RESTART": {
-                    "description": "xtal 32k restart xtal when xtal is dead",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_RETURN": {
-                    "description": "xtal 32k switch back xtal when xtal is restarted",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "XTAL32K_XPD_FORCE": {
-                    "description": "Xtal 32k xpd control by sw or fsm",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "ENCKINIT_XTAL_32K": {
-                    "description": "apply an internal clock to help xtal 32k to start",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DBUF_XTAL_32K": {
-                    "description": "0: single-end buffer 1: differential buffer",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DGM_XTAL_32K": {
-                    "description": "xtal_32k gm control",
-                    "offset": 10,
-                    "size": 3
-                  },
-                  "DRES_XTAL_32K": {
-                    "description": "DRES_XTAL_32K",
-                    "offset": 13,
-                    "size": 3
-                  },
-                  "XPD_XTAL_32K": {
-                    "description": "XPD_XTAL_32K",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "DAC_XTAL_32K": {
-                    "description": "DAC_XTAL_32K",
-                    "offset": 17,
-                    "size": 3
-                  },
-                  "RTC_WDT_STATE": {
-                    "description": "state of 32k_wdt",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_GPIO_SEL": {
-                    "description": "XTAL_32K sel. 0: external XTAL_32K",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "XTL_EXT_CTR_LV": {
-                    "description": "0: power down XTAL at high level",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "XTL_EXT_CTR_EN": {
-                    "description": "enable gpio configure xtal power on",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EXT_WAKEUP_CONF": {
-              "description": "rtc configure register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_WAKEUP_FILTER": {
-                    "description": "enable filter for gpio wakeup event",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_REJECT_CONF": {
-              "description": "rtc configure register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SLEEP_REJECT_ENA": {
-                    "description": "sleep reject enable",
-                    "offset": 12,
-                    "size": 18
-                  },
-                  "LIGHT_SLP_REJECT_EN": {
-                    "description": "enable reject for light sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DEEP_SLP_REJECT_EN": {
-                    "description": "enable reject for deep sleep",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PERIOD_CONF": {
-              "description": "rtc configure register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CPUSEL_CONF": {
-                    "description": "CPU sel option",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_CPUPERIOD_SEL": {
-                    "description": "CPU clk sel option",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "rtc configure register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 290992664,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_CLK_FORCE_GATING": {
-                    "description": "efuse_clk_force_gating",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EFUSE_CLK_FORCE_NOGATING": {
-                    "description": "efuse_clk_force_nogating",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CK8M_DIV_SEL_VLD": {
-                    "description": "used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CK8M_DIV": {
-                    "description": "CK8M_D256_OUT divider. 00: div128",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "ENB_CK8M": {
-                    "description": "disable CK8M and CK8M_D256_OUT",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "ENB_CK8M_DIV": {
-                    "description": "1: CK8M_D256_OUT is actually CK8M",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DIG_XTAL32K_EN": {
-                    "description": "enable CK_XTAL_32K for digital core (no relationship with RTC core)",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DIG_CLK8M_D256_EN": {
-                    "description": "enable CK8M_D256_OUT for digital core (no relationship with RTC core)",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DIG_CLK8M_EN": {
-                    "description": "enable CK8M for digital core (no relationship with RTC core)",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CK8M_DIV_SEL": {
-                    "description": "divider = reg_ck8m_div_sel + 1",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "XTAL_FORCE_NOGATING": {
-                    "description": "XTAL force no gating during sleep",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "CK8M_FORCE_NOGATING": {
-                    "description": "CK8M force no gating during sleep",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "CK8M_DFREQ": {
-                    "description": "CK8M_DFREQ",
-                    "offset": 17,
-                    "size": 8
-                  },
-                  "CK8M_FORCE_PD": {
-                    "description": "CK8M force power down",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "CK8M_FORCE_PU": {
-                    "description": "CK8M force power up",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "XTAL_GLOBAL_FORCE_GATING": {
-                    "description": "force enable xtal clk gating",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "XTAL_GLOBAL_FORCE_NOGATING": {
-                    "description": "force bypass xtal clk gating",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "FAST_CLK_RTC_SEL": {
-                    "description": "fast_clk_rtc sel. 0: XTAL div 4",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ANA_CLK_RTC_SEL": {
-                    "description": "slelect rtc slow clk",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "SLOW_CLK_CONF": {
-              "description": "rtc configure register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 4194304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_ANA_CLK_DIV_VLD": {
-                    "description": "used to sync div bus. clear vld before set reg_rtc_ana_clk_div",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RTC_ANA_CLK_DIV": {
-                    "description": "the clk divider num of RTC_CLK",
-                    "offset": 23,
-                    "size": 8
-                  },
-                  "RTC_SLOW_CLK_NEXT_EDGE": {
-                    "description": "flag rtc_slow_clk_next_edge",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SDIO_CONF": {
-              "description": "rtc configure register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 179355146,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_TIMER_TARGET": {
-                    "description": "timer count to apply reg_sdio_dcap after sdio power on",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SDIO_DTHDRV": {
-                    "description": "Tieh = 1 mode drive ability. Initially set to 0 to limit charge current",
-                    "offset": 9,
-                    "size": 2
-                  },
-                  "SDIO_DCAP": {
-                    "description": "ability to prevent LDO from overshoot",
-                    "offset": 11,
-                    "size": 2
-                  },
-                  "SDIO_INITI": {
-                    "description": "add resistor from ldo output to ground. 0: no res",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "SDIO_EN_INITI": {
-                    "description": "0 to set init[1:0]=0",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SDIO_DCURLIM": {
-                    "description": "tune current limit threshold when tieh = 0. About 800mA/(8+d)",
-                    "offset": 16,
-                    "size": 3
-                  },
-                  "SDIO_MODECURLIM": {
-                    "description": "select current limit mode",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "SDIO_ENCURLIM": {
-                    "description": "enable current limit",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SDIO_REG_PD_EN": {
-                    "description": "power down SDIO_REG in sleep. Only active when reg_sdio_force = 0",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SDIO_FORCE": {
-                    "description": "1: use SW option to control SDIO_REG",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "SDIO_TIEH": {
-                    "description": "SW option for SDIO_TIEH. Only active when reg_sdio_force = 1",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "_1P8_READY": {
-                    "description": "read only register for REG1P8_READY",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DREFL_SDIO": {
-                    "description": "SW option for DREFL_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 25,
-                    "size": 2
-                  },
-                  "DREFM_SDIO": {
-                    "description": "SW option for DREFM_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "DREFH_SDIO": {
-                    "description": "SW option for DREFH_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 29,
-                    "size": 2
-                  },
-                  "XPD_SDIO": {
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BIAS_CONF": {
-              "description": "rtc configure register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 67584,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DG_VDD_DRV_B_SLP": {
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "DG_VDD_DRV_B_SLP_EN": {
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "BIAS_BUF_IDLE": {
-                    "description": "bias buf when rtc in normal work state",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "BIAS_BUF_WAKE": {
-                    "description": "bias buf when rtc in wakeup state",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "BIAS_BUF_DEEP_SLP": {
-                    "description": "bias buf when rtc in sleep state",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "BIAS_BUF_MONITOR": {
-                    "description": "bias buf when rtc in monitor state",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "PD_CUR_DEEP_SLP": {
-                    "description": "xpd cur when rtc in sleep_state",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "PD_CUR_MONITOR": {
-                    "description": "xpd cur when rtc in monitor state",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "BIAS_SLEEP_DEEP_SLP": {
-                    "description": "bias_sleep when rtc in sleep_state",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "BIAS_SLEEP_MONITOR": {
-                    "description": "bias_sleep when rtc in monitor state",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "DBG_ATTEN_DEEP_SLP": {
-                    "description": "DBG_ATTEN when rtc in sleep state",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "DBG_ATTEN_MONITOR": {
-                    "description": "DBG_ATTEN when rtc in monitor state",
-                    "offset": 22,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RTC_CNTL": {
-              "description": "rtc configure register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 2684354560,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIG_REG_CAL_EN": {
-                    "description": "software enable digital regulator cali",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SCK_DCAP": {
-                    "description": "SCK_DCAP",
-                    "offset": 14,
-                    "size": 8
-                  },
-                  "DBOOST_FORCE_PD": {
-                    "description": "RTC_DBOOST force power down",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "DBOOST_FORCE_PU": {
-                    "description": "RTC_DBOOST force power up",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "REGULATOR_FORCE_PD": {
-                    "description": "RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "REGULATOR_FORCE_PU": {
-                    "description": "RTC_REG force power up",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PWC": {
-              "description": "rtc configure register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_PAD_FORCE_HOLD": {
-                    "description": "rtc pad force hold",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_PWC": {
-              "description": "rtc configure register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 5591056,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "VDD_SPI_PWR_DRV": {
-                    "description": "vdd_spi drv's software value",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "VDD_SPI_PWR_FORCE": {
-                    "description": "vdd_spi drv use software value",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "LSLP_MEM_FORCE_PD": {
-                    "description": "memories in digital core force PD in sleep",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "LSLP_MEM_FORCE_PU": {
-                    "description": "memories in digital core force PU in sleep",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "BT_FORCE_PD": {
-                    "description": "bt force power down",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "BT_FORCE_PU": {
-                    "description": "bt force power up",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_PD": {
-                    "description": "digital peri force power down",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_PU": {
-                    "description": "digital peri force power up",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RTC_FASTMEM_FORCE_LPD": {
-                    "description": "fastmemory  retention mode in sleep",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RTC_FASTMEM_FORCE_LPU": {
-                    "description": "fastmemory donlt entry retention mode in sleep",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_PD": {
-                    "description": "wifi force power down",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_PU": {
-                    "description": "wifi force power up",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_PD": {
-                    "description": "digital core force power down",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_PU": {
-                    "description": "digital core force power up",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_PD": {
-                    "description": "cpu core force power down",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_PU": {
-                    "description": "cpu force power up",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "BT_PD_EN": {
-                    "description": "enable power down bt in sleep",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "DG_PERI_PD_EN": {
-                    "description": "enable power down digital peri in sleep",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CPU_TOP_PD_EN": {
-                    "description": "enable power down cpu in sleep",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "WIFI_PD_EN": {
-                    "description": "enable power down wifi in sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DG_WRAP_PD_EN": {
-                    "description": "enable power down digital wrap in sleep",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_ISO": {
-              "description": "rtc configure register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 2860535936,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FORCE_OFF": {
-                    "description": "DIG_ISO force off",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FORCE_ON": {
-                    "description": "DIG_ISO force on",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DG_PAD_AUTOHOLD": {
-                    "description": "read only register to indicate digital pad auto-hold status",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CLR_DG_PAD_AUTOHOLD": {
-                    "description": "wtite only register to clear digital pad auto-hold",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DG_PAD_AUTOHOLD_EN": {
-                    "description": "digital pad enable auto-hold",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_NOISO": {
-                    "description": "digital pad force no ISO",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_ISO": {
-                    "description": "digital pad force ISO",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_UNHOLD": {
-                    "description": "digital pad force un-hold",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_HOLD": {
-                    "description": "digital pad force hold",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "BT_FORCE_ISO": {
-                    "description": "bt force ISO",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "BT_FORCE_NOISO": {
-                    "description": "bt force no ISO",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_ISO": {
-                    "description": "Digital peri force ISO",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_NOISO": {
-                    "description": "digital peri force no ISO",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_ISO": {
-                    "description": "cpu force ISO",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_NOISO": {
-                    "description": "cpu force no ISO",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_ISO": {
-                    "description": "wifi force ISO",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_NOISO": {
-                    "description": "wifi force no ISO",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_ISO": {
-                    "description": "digital core force ISO",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_NOISO": {
-                    "description": "digital core force no ISO",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG0": {
-              "description": "rtc configure register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 78356,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_CHIP_RESET_WIDTH": {
-                    "description": "chip reset siginal pulse width",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "WDT_CHIP_RESET_EN": {
-                    "description": "wdt reset whole chip enable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "WDT_PAUSE_IN_SLP": {
-                    "description": "pause WDT in sleep",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "WDT_APPCPU_RESET_EN": {
-                    "description": "enable WDT reset APP CPU",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "WDT_PROCPU_RESET_EN": {
-                    "description": "enable WDT reset PRO CPU",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "WDT_FLASHBOOT_MOD_EN": {
-                    "description": "enable WDT in flash boot",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "WDT_SYS_RESET_LENGTH": {
-                    "description": "system reset counter length",
-                    "offset": 13,
-                    "size": 3
-                  },
-                  "WDT_CPU_RESET_LENGTH": {
-                    "description": "CPU reset counter length",
-                    "offset": 16,
-                    "size": 3
-                  },
-                  "WDT_STG3": {
-                    "description": "1: interrupt stage en",
-                    "offset": 19,
-                    "size": 3
-                  },
-                  "WDT_STG2": {
-                    "description": "1: interrupt stage en",
-                    "offset": 22,
-                    "size": 3
-                  },
-                  "WDT_STG1": {
-                    "description": "1: interrupt stage en",
-                    "offset": 25,
-                    "size": 3
-                  },
-                  "WDT_STG0": {
-                    "description": "1: interrupt stage en",
-                    "offset": 28,
-                    "size": 3
-                  },
-                  "WDT_EN": {
-                    "description": "enable rtc wdt",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG1": {
-              "description": "rtc configure register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 200000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG0_HOLD": {
-                    "description": "the hold time of stage0",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG2": {
-              "description": "rtc configure register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 80000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG1_HOLD": {
-                    "description": "the hold time of stage1",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG3": {
-              "description": "rtc configure register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG2_HOLD": {
-                    "description": "the hold time of stage2",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG4": {
-              "description": "rtc configure register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG3_HOLD": {
-                    "description": "the hold time of stage3",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTFEED": {
-              "description": "rtc configure register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_WDT_FEED": {
-                    "description": "sw feed rtc wdt",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTWPROTECT": {
-              "description": "rtc configure register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_WKEY": {
-                    "description": "the key of rtc wdt",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SWD_CONF": {
-              "description": "rtc configure register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 78643200,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SWD_RESET_FLAG": {
-                    "description": "swd reset flag",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SWD_FEED_INT": {
-                    "description": "swd interrupt for feeding",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SWD_BYPASS_RST": {
-                    "description": "Bypass swd rst",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "SWD_SIGNAL_WIDTH": {
-                    "description": "adjust signal width send to swd",
-                    "offset": 18,
-                    "size": 10
-                  },
-                  "SWD_RST_FLAG_CLR": {
-                    "description": "reset swd reset flag",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SWD_FEED": {
-                    "description": "Sw feed swd",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SWD_DISABLE": {
-                    "description": "disabel SWD",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SWD_AUTO_FEED_EN": {
-                    "description": "automatically feed swd when int comes",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SWD_WPROTECT": {
-              "description": "rtc configure register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SWD_WKEY": {
-                    "description": "the key of super wdt",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SW_CPU_STALL": {
-              "description": "rtc configure register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_STALL_APPCPU_C1": {
-                    "description": "{reg_sw_stall_appcpu_c1[5:0]",
-                    "offset": 20,
-                    "size": 6
-                  },
-                  "SW_STALL_PROCPU_C1": {
-                    "description": "stall cpu by software",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "STORE4": {
-              "description": "rtc configure register",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH4": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE5": {
-              "description": "rtc configure register",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH5": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE6": {
-              "description": "rtc configure register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH6": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE7": {
-              "description": "rtc configure register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH7": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOW_POWER_ST": {
-              "description": "rtc configure register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XPD_ROM0": {
-                    "description": "rom0 power down",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_DIG_DCDC": {
-                    "description": "External DCDC power down",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_PERI_ISO": {
-                    "description": "rtc peripheral iso",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_RTC_PERI": {
-                    "description": "rtc peripheral power down",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WIFI_ISO": {
-                    "description": "wifi iso",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_WIFI": {
-                    "description": "wifi wrap power down",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIG_ISO": {
-                    "description": "digital wrap iso",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_DIG": {
-                    "description": "digital wrap power down",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_START": {
-                    "description": "touch should start to work",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_SWITCH": {
-                    "description": "touch is about to working. Switch rtc main state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_SLP": {
-                    "description": "touch is in sleep state",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_DONE": {
-                    "description": "touch is done",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_START": {
-                    "description": "ulp/cocpu should start to work",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_SWITCH": {
-                    "description": "ulp/cocpu is about to working. Switch rtc main state",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_SLP": {
-                    "description": "ulp/cocpu is in sleep state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_DONE": {
-                    "description": "ulp/cocpu is done",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_XTAL_ISO": {
-                    "description": "no use any more",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_PLL_ON": {
-                    "description": "rtc main state machine is in states that pll should be running",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_RDY_FOR_WAKEUP": {
-                    "description": "rtc is ready to receive wake up trigger from wake up source",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_WAIT_END": {
-                    "description": "rtc main state machine has been waited for some cycles",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_IN_WAKEUP_STATE": {
-                    "description": "rtc main state machine is in the states of wakeup process",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_IN_LOW_POWER_STATE": {
-                    "description": "rtc main state machine is in the states of low power",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_8M": {
-                    "description": "rtc main state machine is in wait 8m state",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_PLL": {
-                    "description": "rtc main state machine is in wait pll state",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_XTL": {
-                    "description": "rtc main state machine is in wait xtal state",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_SLP": {
-                    "description": "rtc main state machine is in sleep state",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_IDLE": {
-                    "description": "rtc main state machine is in idle state",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE": {
-                    "description": "rtc main state machine status",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DIAG0": {
-              "description": "rtc configure register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_LOW_POWER_DIAG1": {
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PAD_HOLD": {
-              "description": "rtc configure register",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_PIN0_HOLD": {
-                    "description": "the hold configure of rtc gpio0",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_HOLD": {
-                    "description": "the hold configure of rtc gpio1",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_HOLD": {
-                    "description": "the hold configure of rtc gpio2",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_HOLD": {
-                    "description": "the hold configure of rtc gpio3",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_HOLD": {
-                    "description": "the hold configure of rtc gpio4",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_HOLD": {
-                    "description": "the hold configure of rtc gpio5",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_PAD_HOLD": {
-              "description": "rtc configure register",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIG_PAD_HOLD": {
-                    "description": "the configure of digital pad",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "BROWN_OUT": {
-              "description": "rtc configure register",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 1140785168,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_WAIT": {
-                    "description": "brown out interrupt wait cycles",
-                    "offset": 4,
-                    "size": 10
-                  },
-                  "CLOSE_FLASH_ENA": {
-                    "description": "enable close flash when brown out happens",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "PD_RF_ENA": {
-                    "description": "enable power down RF when brown out happens",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RST_WAIT": {
-                    "description": "brown out reset wait cycles",
-                    "offset": 16,
-                    "size": 10
-                  },
-                  "RST_ENA": {
-                    "description": "enable brown out reset",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RST_SEL": {
-                    "description": "1:  4-pos reset",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "ANA_RST_EN": {
-                    "description": "brown_out origin reset enable",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CNT_CLR": {
-                    "description": "clear brown out counter",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ENA": {
-                    "description": "enable brown out",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DET": {
-                    "description": "the flag of brown det from analog",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_LOW1": {
-              "description": "rtc configure register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE1_LOW": {
-                    "description": "RTC timer low 32 bits",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_HIGH1": {
-              "description": "rtc configure register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE1_HIGH": {
-                    "description": "RTC timer high 16 bits",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "XTAL32K_CLK_FACTOR": {
-              "description": "rtc configure register",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_CLK_FACTOR": {
-                    "description": "xtal 32k watch dog backup clock factor",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "XTAL32K_CONF": {
-              "description": "rtc configure register",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 267386880,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_RETURN_WAIT": {
-                    "description": "cycles to wait to return noral xtal 32k",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "XTAL32K_RESTART_WAIT": {
-                    "description": "cycles to wait to repower on xtal 32k",
-                    "offset": 4,
-                    "size": 16
-                  },
-                  "XTAL32K_WDT_TIMEOUT": {
-                    "description": "If no clock detected for this amount of time",
-                    "offset": 20,
-                    "size": 8
-                  },
-                  "XTAL32K_STABLE_THRES": {
-                    "description": "if restarted xtal32k period is smaller than this",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "USB_CONF": {
-              "description": "rtc configure register",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IO_MUX_RESET_DISABLE": {
-                    "description": "disable io_mux reset",
-                    "offset": 18,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_REJECT_CAUSE": {
-              "description": "RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REJECT_CAUSE": {
-                    "description": "sleep reject cause",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OPTION1": {
-              "description": "rtc configure register",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FORCE_DOWNLOAD_BOOT": {
-                    "description": "force chip entry download mode",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_WAKEUP_CAUSE": {
-              "description": "RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WAKEUP_CAUSE": {
-                    "description": "sleep wakeup cause",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ULP_CP_TIMER_1": {
-              "description": "rtc configure register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 51200,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ULP_CP_TIMER_SLP_CYCLE": {
-                    "description": "sleep cycles for ULP-coprocessor timer",
-                    "offset": 8,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC_W1TS": {
-              "description": "rtc configure register",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA_W1TS": {
-                    "description": "enable sleep wakeup interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_ENA_W1TS": {
-                    "description": "enable sleep reject interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_ENA_W1TS": {
-                    "description": "enable RTC WDT interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ENA_W1TS": {
-                    "description": "enable brown out interrupt",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA_W1TS": {
-                    "description": "enable RTC main timer interrupt",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_ENA_W1TS": {
-                    "description": "enable super watch dog interrupt",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA_W1TS": {
-                    "description": "enable xtal32k_dead  interrupt",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ENA_W1TS": {
-                    "description": "enbale gitch det interrupt",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA_W1TS": {
-                    "description": "enbale bbpll cal interrupt",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC_W1TC": {
-              "description": "rtc configure register",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA_W1TC": {
-                    "description": "clear sleep wakeup interrupt enable",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_ENA_W1TC": {
-                    "description": "clear sleep reject interrupt enable",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_ENA_W1TC": {
-                    "description": "clear RTC WDT interrupt enable",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ENA_W1TC": {
-                    "description": "clear brown out interrupt enable",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA_W1TC": {
-                    "description": "Clear RTC main timer interrupt enable",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_ENA_W1TC": {
-                    "description": "clear super watch dog interrupt enable",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA_W1TC": {
-                    "description": "clear xtal32k_dead  interrupt enable",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ENA_W1TC": {
-                    "description": "clear gitch det interrupt enable",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA_W1TC": {
-                    "description": "clear bbpll cal interrupt enable",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RETENTION_CTRL": {
-              "description": "rtc configure register",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 2697986048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RETENTION_CLK_SEL": {
-                    "description": "Retention clk sel",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RETENTION_DONE_WAIT": {
-                    "description": "Retention done wait time",
-                    "offset": 19,
-                    "size": 3
-                  },
-                  "RETENTION_CLKOFF_WAIT": {
-                    "description": "Retention clkoff wait time",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "RETENTION_EN": {
-                    "description": "enable cpu retention when light sleep",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RETENTION_WAIT": {
-                    "description": "wait cycles for rention operation",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "FIB_SEL": {
-              "description": "rtc configure register",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_FIB_SEL": {
-                    "description": "select use analog fib signal",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "GPIO_WAKEUP": {
-              "description": "rtc configure register",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_WAKEUP_STATUS": {
-                    "description": "rtc gpio wakeup flag",
-                    "offset": 0,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "RTC_GPIO_WAKEUP_STATUS_CLR": {
-                    "description": "clear rtc gpio wakeup flag",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN_CLK_GATE": {
-                    "description": "enable rtc io clk gate",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 8,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN4_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 11,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN3_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 14,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN2_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 17,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN1_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN0_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 23,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN5_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio5",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio4",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio3",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio2",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio1",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN0_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio0",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DBG_SEL": {
-              "description": "rtc configure register",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_DEBUG_12M_NO_GATING": {
-                    "description": "use for debug",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_DEBUG_BIT_SEL": {
-                    "description": "use for debug",
-                    "offset": 2,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL0": {
-                    "description": "use for debug",
-                    "offset": 7,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL1": {
-                    "description": "use for debug",
-                    "offset": 12,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL2": {
-                    "description": "use for debug",
-                    "offset": 17,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL3": {
-                    "description": "use for debug",
-                    "offset": 22,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL4": {
-                    "description": "use for debug",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DBG_MAP": {
-              "description": "rtc configure register",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_PIN5_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN0_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 8,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN4_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 12,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN3_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 16,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN2_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 20,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN1_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 24,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN0_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "SENSOR_CTRL": {
-              "description": "rtc configure register",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SAR2_PWDET_CCT": {
-                    "description": "reg_sar2_pwdet_cct",
-                    "offset": 27,
-                    "size": 3
-                  },
-                  "FORCE_XPD_SAR": {
-                    "description": "force power up SAR",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DBG_SAR_SEL": {
-              "description": "rtc configure register",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SAR_DEBUG_SEL": {
-                    "description": "use for debug",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "PG_CTRL": {
-              "description": "rtc configure register",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POWER_GLITCH_DSENSE": {
-                    "description": "power glitch desense",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "POWER_GLITCH_FORCE_PD": {
-                    "description": "force disable power glitch",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_FORCE_PU": {
-                    "description": "force enable power glitch",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_EFUSE_SEL": {
-                    "description": "use efuse value control power glitch enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_EN": {
-                    "description": "enable power glitch",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "rtc configure register",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33583728,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CNTL_DATE": {
-                    "description": "verision",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SENSITIVE": {
-        "description": "Sensitive",
-        "children": {
-          "registers": {
-            "ROM_TABLE_LOCK": {
-              "description": "SENSITIVE_ROM_TABLE_LOCK_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_TABLE_LOCK": {
-                    "description": "rom_table_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ROM_TABLE": {
-              "description": "SENSITIVE_ROM_TABLE_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_TABLE": {
-                    "description": "rom_table",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PRIVILEGE_MODE_SEL_LOCK": {
-              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRIVILEGE_MODE_SEL_LOCK": {
-                    "description": "privilege_mode_sel_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PRIVILEGE_MODE_SEL": {
-              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRIVILEGE_MODE_SEL": {
-                    "description": "privilege_mode_sel",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "APB_PERIPHERAL_ACCESS_0": {
-              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_PERIPHERAL_ACCESS_LOCK": {
-                    "description": "apb_peripheral_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "APB_PERIPHERAL_ACCESS_1": {
-              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_PERIPHERAL_ACCESS_SPLIT_BURST": {
-                    "description": "apb_peripheral_access_split_burst",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_0": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_0_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_LOCK": {
-                    "description": "internal_sram_usage_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_1": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_1_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_CPU_CACHE": {
-                    "description": "internal_sram_usage_cpu_cache",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "INTERNAL_SRAM_USAGE_CPU_SRAM": {
-                    "description": "internal_sram_usage_cpu_sram",
-                    "offset": 1,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_3": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_3_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM": {
-                    "description": "internal_sram_usage_mac_dump_sram",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "INTERNAL_SRAM_ALLOC_MAC_DUMP": {
-                    "description": "internal_sram_alloc_mac_dump",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_4": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_4_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_LOG_SRAM": {
-                    "description": "internal_sram_usage_log_sram",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_TAG_ACCESS_0": {
-              "description": "SENSITIVE_CACHE_TAG_ACCESS_0_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_TAG_ACCESS_LOCK": {
-                    "description": "cache_tag_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_TAG_ACCESS_1": {
-              "description": "SENSITIVE_CACHE_TAG_ACCESS_1_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRO_I_TAG_RD_ACS": {
-                    "description": "pro_i_tag_rd_acs",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PRO_I_TAG_WR_ACS": {
-                    "description": "pro_i_tag_wr_acs",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PRO_D_TAG_RD_ACS": {
-                    "description": "pro_d_tag_rd_acs",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PRO_D_TAG_WR_ACS": {
-                    "description": "pro_d_tag_wr_acs",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_ACCESS_0": {
-              "description": "SENSITIVE_CACHE_MMU_ACCESS_0_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_ACCESS_LOCK": {
-                    "description": "cache_mmu_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_ACCESS_1": {
-              "description": "SENSITIVE_CACHE_MMU_ACCESS_1_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRO_MMU_RD_ACS": {
-                    "description": "pro_mmu_rd_acs",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PRO_MMU_WR_ACS": {
-                    "description": "pro_mmu_wr_acs",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_spi2_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_MAC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_mac_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_MAC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_backup_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_LC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_lc_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_LC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_AES_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_aes_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_AES_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SHA_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_sha_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SHA_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_0": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_LOCK": {
-                    "description": "dma_apbperi_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_1": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "dma_apbperi_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "dma_apbperi_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_2": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "dma_apbperi_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_world",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_addr",
-                    "offset": 3,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_3": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_wr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_byteen",
-                    "offset": 1,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK": {
-                    "description": "core_x_iram0_dram0_dma_split_line_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR": {
-                    "description": "core_x_iram0_dram0_dma_sram_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0": {
-                    "description": "core_x_iram0_sram_line_0_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1": {
-                    "description": "core_x_iram0_sram_line_0_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2": {
-                    "description": "core_x_iram0_sram_line_0_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR": {
-                    "description": "core_x_iram0_sram_line_0_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0": {
-                    "description": "core_x_iram0_sram_line_1_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1": {
-                    "description": "core_x_iram0_sram_line_1_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2": {
-                    "description": "core_x_iram0_sram_line_1_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR": {
-                    "description": "core_x_iram0_sram_line_1_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR": {
-                    "description": "core_x_dram0_dma_sram_line_0_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR": {
-                    "description": "core_x_dram0_dma_sram_line_1_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_x_iram0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 1867775,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 9,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
-                    "description": "core_x_iram0_pms_constrain_rom_world_1_pms",
-                    "offset": 18,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 1867775,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 9,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
-                    "description": "core_x_iram0_pms_constrain_rom_world_0_pms",
-                    "offset": 18,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_LOCK": {
-                    "description": "core_0_iram0_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_iram0_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_iram0_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_iram0_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_wr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_loadstore",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_world",
-                    "offset": 3,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_addr",
-                    "offset": 5,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_DRAM0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_x_dram0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_DRAM0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 252702975,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
-                    "description": "core_x_dram0_pms_constrain_rom_world_0_pms",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
-                    "description": "core_x_dram0_pms_constrain_rom_world_1_pms",
-                    "offset": 26,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_LOCK": {
-                    "description": "core_0_dram0_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_dram0_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_dram0_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_dram0_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_lock",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_world",
-                    "offset": 2,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_addr",
-                    "offset": 4,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_3": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_wr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_byteen",
-                    "offset": 1,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_0_pif_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART": {
-                    "description": "core_0_pif_pms_constrain_world_0_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1": {
-                    "description": "core_0_pif_pms_constrain_world_0_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0": {
-                    "description": "core_0_pif_pms_constrain_world_0_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO": {
-                    "description": "core_0_pif_pms_constrain_world_0_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2": {
-                    "description": "core_0_pif_pms_constrain_world_0_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE": {
-                    "description": "core_0_pif_pms_constrain_world_0_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER": {
-                    "description": "core_0_pif_pms_constrain_world_0_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC": {
-                    "description": "core_0_pif_pms_constrain_world_0_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX": {
-                    "description": "core_0_pif_pms_constrain_world_0_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG": {
-                    "description": "core_0_pif_pms_constrain_world_0_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC": {
-                    "description": "core_0_pif_pms_constrain_world_0_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1": {
-                    "description": "core_0_pif_pms_constrain_world_0_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT": {
-                    "description": "core_0_pif_pms_constrain_world_0_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0": {
-                    "description": "core_0_pif_pms_constrain_world_0_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT": {
-                    "description": "core_0_pif_pms_constrain_world_0_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC": {
-                    "description": "core_0_pif_pms_constrain_world_0_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB": {
-                    "description": "core_0_pif_pms_constrain_world_0_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP": {
-                    "description": "core_0_pif_pms_constrain_world_0_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1": {
-                    "description": "core_0_pif_pms_constrain_world_0_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER": {
-                    "description": "core_0_pif_pms_constrain_world_0_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2": {
-                    "description": "core_0_pif_pms_constrain_world_0_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL": {
-                    "description": "core_0_pif_pms_constrain_world_0_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN": {
-                    "description": "core_0_pif_pms_constrain_world_0_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT": {
-                    "description": "core_0_pif_pms_constrain_world_0_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC": {
-                    "description": "core_0_pif_pms_constrain_world_0_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_0_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 4294964220,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP": {
-                    "description": "core_0_pif_pms_constrain_world_0_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI": {
-                    "description": "core_0_pif_pms_constrain_world_0_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA": {
-                    "description": "core_0_pif_pms_constrain_world_0_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC": {
-                    "description": "core_0_pif_pms_constrain_world_0_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_0_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE": {
-                    "description": "core_0_pif_pms_constrain_world_0_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM": {
-                    "description": "core_0_pif_pms_constrain_world_0_system",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE": {
-                    "description": "core_0_pif_pms_constrain_world_0_sensitive",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT": {
-                    "description": "core_0_pif_pms_constrain_world_0_interrupt",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY": {
-                    "description": "core_0_pif_pms_constrain_world_0_dma_copy",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG": {
-                    "description": "core_0_pif_pms_constrain_world_0_cache_config",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD": {
-                    "description": "core_0_pif_pms_constrain_world_0_ad",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO": {
-                    "description": "core_0_pif_pms_constrain_world_0_dio",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER": {
-                    "description": "core_0_pif_pms_constrain_world_0_world_controller",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_5": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART": {
-                    "description": "core_0_pif_pms_constrain_world_1_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1": {
-                    "description": "core_0_pif_pms_constrain_world_1_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0": {
-                    "description": "core_0_pif_pms_constrain_world_1_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO": {
-                    "description": "core_0_pif_pms_constrain_world_1_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2": {
-                    "description": "core_0_pif_pms_constrain_world_1_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE": {
-                    "description": "core_0_pif_pms_constrain_world_1_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER": {
-                    "description": "core_0_pif_pms_constrain_world_1_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC": {
-                    "description": "core_0_pif_pms_constrain_world_1_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX": {
-                    "description": "core_0_pif_pms_constrain_world_1_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG": {
-                    "description": "core_0_pif_pms_constrain_world_1_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC": {
-                    "description": "core_0_pif_pms_constrain_world_1_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1": {
-                    "description": "core_0_pif_pms_constrain_world_1_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_6": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT": {
-                    "description": "core_0_pif_pms_constrain_world_1_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0": {
-                    "description": "core_0_pif_pms_constrain_world_1_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT": {
-                    "description": "core_0_pif_pms_constrain_world_1_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC": {
-                    "description": "core_0_pif_pms_constrain_world_1_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB": {
-                    "description": "core_0_pif_pms_constrain_world_1_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP": {
-                    "description": "core_0_pif_pms_constrain_world_1_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1": {
-                    "description": "core_0_pif_pms_constrain_world_1_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER": {
-                    "description": "core_0_pif_pms_constrain_world_1_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_7": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2": {
-                    "description": "core_0_pif_pms_constrain_world_1_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL": {
-                    "description": "core_0_pif_pms_constrain_world_1_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN": {
-                    "description": "core_0_pif_pms_constrain_world_1_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT": {
-                    "description": "core_0_pif_pms_constrain_world_1_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC": {
-                    "description": "core_0_pif_pms_constrain_world_1_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_1_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_8": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 4294964220,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP": {
-                    "description": "core_0_pif_pms_constrain_world_1_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI": {
-                    "description": "core_0_pif_pms_constrain_world_1_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA": {
-                    "description": "core_0_pif_pms_constrain_world_1_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC": {
-                    "description": "core_0_pif_pms_constrain_world_1_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_1_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE": {
-                    "description": "core_0_pif_pms_constrain_world_1_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM": {
-                    "description": "core_0_pif_pms_constrain_world_1_system",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE": {
-                    "description": "core_0_pif_pms_constrain_world_1_sensitive",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT": {
-                    "description": "core_0_pif_pms_constrain_world_1_interrupt",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY": {
-                    "description": "core_0_pif_pms_constrain_world_1_dma_copy",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG": {
-                    "description": "core_0_pif_pms_constrain_world_1_cache_config",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD": {
-                    "description": "core_0_pif_pms_constrain_world_1_ad",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO": {
-                    "description": "core_0_pif_pms_constrain_world_1_dio",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER": {
-                    "description": "core_0_pif_pms_constrain_world_1_world_controller",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_9": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 4194303,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
-                    "offset": 0,
-                    "size": 11
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
-                    "offset": 11,
-                    "size": 11
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_10": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_l",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_h",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_l",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_h",
-                    "offset": 9,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_0_REG",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_LOCK": {
-                    "description": "region_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_1_REG",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 16383,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_0": {
-                    "description": "region_pms_constrain_world_0_area_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_1": {
-                    "description": "region_pms_constrain_world_0_area_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_2": {
-                    "description": "region_pms_constrain_world_0_area_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_3": {
-                    "description": "region_pms_constrain_world_0_area_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_4": {
-                    "description": "region_pms_constrain_world_0_area_4",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_5": {
-                    "description": "region_pms_constrain_world_0_area_5",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_6": {
-                    "description": "region_pms_constrain_world_0_area_6",
-                    "offset": 12,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_2_REG",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 16383,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_0": {
-                    "description": "region_pms_constrain_world_1_area_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_1": {
-                    "description": "region_pms_constrain_world_1_area_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_2": {
-                    "description": "region_pms_constrain_world_1_area_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_3": {
-                    "description": "region_pms_constrain_world_1_area_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_4": {
-                    "description": "region_pms_constrain_world_1_area_4",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_5": {
-                    "description": "region_pms_constrain_world_1_area_5",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_6": {
-                    "description": "region_pms_constrain_world_1_area_6",
-                    "offset": 12,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_3_REG",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_0": {
-                    "description": "region_pms_constrain_addr_0",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_4_REG",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_1": {
-                    "description": "region_pms_constrain_addr_1",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_5": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_5_REG",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_2": {
-                    "description": "region_pms_constrain_addr_2",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_6": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_6_REG",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_3": {
-                    "description": "region_pms_constrain_addr_3",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_7": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_7_REG",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_4": {
-                    "description": "region_pms_constrain_addr_4",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_8": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_8_REG",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_5": {
-                    "description": "region_pms_constrain_addr_5",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_9": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_9_REG",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_6": {
-                    "description": "region_pms_constrain_addr_6",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_10": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_10_REG",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_7": {
-                    "description": "region_pms_constrain_addr_7",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_LOCK": {
-                    "description": "core_0_pif_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_pif_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_pif_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_pif_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hport_0",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hsize",
-                    "offset": 2,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hwrite",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hworld",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_3": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR": {
-                    "description": "core_0_pif_pms_monitor_violate_status_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_4": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_5": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hsize",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hworld",
-                    "offset": 3,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_6": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_LOCK": {
-                    "description": "backup_bus_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_UART": {
-                    "description": "backup_bus_pms_constrain_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1": {
-                    "description": "backup_bus_pms_constrain_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0": {
-                    "description": "backup_bus_pms_constrain_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_GPIO": {
-                    "description": "backup_bus_pms_constrain_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_FE2": {
-                    "description": "backup_bus_pms_constrain_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_FE": {
-                    "description": "backup_bus_pms_constrain_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMER": {
-                    "description": "backup_bus_pms_constrain_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RTC": {
-                    "description": "backup_bus_pms_constrain_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_IO_MUX": {
-                    "description": "backup_bus_pms_constrain_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_WDG": {
-                    "description": "backup_bus_pms_constrain_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_MISC": {
-                    "description": "backup_bus_pms_constrain_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2C": {
-                    "description": "backup_bus_pms_constrain_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_UART1": {
-                    "description": "backup_bus_pms_constrain_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_BT": {
-                    "description": "backup_bus_pms_constrain_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0": {
-                    "description": "backup_bus_pms_constrain_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_UHCI0": {
-                    "description": "backup_bus_pms_constrain_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RMT": {
-                    "description": "backup_bus_pms_constrain_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_LEDC": {
-                    "description": "backup_bus_pms_constrain_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_BB": {
-                    "description": "backup_bus_pms_constrain_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP": {
-                    "description": "backup_bus_pms_constrain_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1": {
-                    "description": "backup_bus_pms_constrain_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER": {
-                    "description": "backup_bus_pms_constrain_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_SPI_2": {
-                    "description": "backup_bus_pms_constrain_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL": {
-                    "description": "backup_bus_pms_constrain_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CAN": {
-                    "description": "backup_bus_pms_constrain_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2S1": {
-                    "description": "backup_bus_pms_constrain_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RWBT": {
-                    "description": "backup_bus_pms_constrain_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC": {
-                    "description": "backup_bus_pms_constrain_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_PWR": {
-                    "description": "backup_bus_pms_constrain_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 62460,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP": {
-                    "description": "backup_bus_pms_constrain_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI": {
-                    "description": "backup_bus_pms_constrain_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA": {
-                    "description": "backup_bus_pms_constrain_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_APB_ADC": {
-                    "description": "backup_bus_pms_constrain_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_BT_PWR": {
-                    "description": "backup_bus_pms_constrain_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE": {
-                    "description": "backup_bus_pms_constrain_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_0": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_LOCK": {
-                    "description": "backup_bus_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_1": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "backup_bus_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "backup_bus_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_2": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "backup_bus_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS": {
-                    "description": "backup_bus_pms_monitor_violate_status_htrans",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
-                    "description": "backup_bus_pms_monitor_violate_status_hsize",
-                    "offset": 3,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
-                    "description": "backup_bus_pms_monitor_violate_status_hwrite",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_3": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR": {
-                    "description": "backup_bus_pms_monitor_violate_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SENSITIVE_CLOCK_GATE_REG",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "SENSITIVE_DATE_REG",
-              "offset": 4092,
-              "size": 32,
-              "reset_value": 33620480,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SHA": {
-        "description": "SHA (Secure Hash Algorithm) Accelerator",
-        "children": {
-          "registers": {
-            "MODE": {
-              "description": "Initial configuration register.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "Sha mode.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "T_STRING": {
-              "description": "SHA 512/t configuration register 0.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T_STRING": {
-                    "description": "Sha t_string (used if and only if mode == SHA_512/t).",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T_LENGTH": {
-              "description": "SHA 512/t configuration register 1.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T_LENGTH": {
-                    "description": "Sha t_length (used if and only if mode == SHA_512/t).",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "DMA_BLOCK_NUM": {
-              "description": "DMA configuration register 0.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_BLOCK_NUM": {
-                    "description": "Dma-sha block number.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "START": {
-              "description": "Typical SHA configuration register 0.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "START": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 31,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CONTINUE": {
-              "description": "Typical SHA configuration register 1.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONTINUE": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 31,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BUSY": {
-              "description": "Busy register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Sha busy state. 1'b0: idle. 1'b1: busy.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DMA_START": {
-              "description": "DMA configuration register 1.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_START": {
-                    "description": "Start dma-sha.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_CONTINUE": {
-              "description": "DMA configuration register 2.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CONTINUE": {
-                    "description": "Continue dma-sha.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLEAR_IRQ": {
-              "description": "Interrupt clear register.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLEAR_INTERRUPT": {
-                    "description": "Clear sha interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "IRQ_ENA": {
-              "description": "Interrupt enable register.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT_ENA": {
-                    "description": "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Date register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 538969622,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Sha date information/ sha version information.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "H_MEM": {
-              "description": "Sha H memory which contains intermediate hash or finial hash.",
-              "offset": 64,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_MEM": {
-              "description": "Sha M memory which contains message.",
-              "offset": 128,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            }
-          }
-        }
-      },
-      "SPI0": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CTRL": {
-              "description": "SPI0 control register.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2891776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FDUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FASTRD_MODE": {
-                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "FREAD_DIO": {
-                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FREAD_QIO": {
-                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CTRL1": {
-              "description": "SPI0 control1 register.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "RXFIFO_RST": {
-                    "description": "SPI0 RX FIFO reset signal.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "SPI0 control2 register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 33,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS_SETUP_TIME": {
-                    "description": "(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "CS_HOLD_TIME": {
-                    "description": "Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.",
-                    "offset": 5,
-                    "size": 5
-                  },
-                  "CS_HOLD_DELAY": {
-                    "description": "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.",
-                    "offset": 25,
-                    "size": 6
-                  },
-                  "SYNC_RESET": {
-                    "description": "The FSM will be reset.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI clock division control register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 196867,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
-                    "offset": 16,
-                    "size": 8
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "Set this bit in 1-division mode.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI0 user register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS_HOLD": {
-                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CS_SETUP": {
-                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "spi clock is disable in dummy phase when the bit is enable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation.",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI0 user1 register.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 1543503879,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI0 user2 register.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1879048192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RD_STATUS": {
-              "description": "SPI0 read control register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WB_MODE": {
-                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI0 misc register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRANS_END": {
-                    "description": "The bit is used to indicate the  spi0_mst_st controlled transmitting is done.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TRANS_END_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CSPI_ST_TRANS_END": {
-                    "description": "The bit is used to indicate the  spi0_slv_st controlled transmitting is done.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CSPI_ST_TRANS_END_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_FCTRL": {
-              "description": "SPI0 bit mode control register.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_REQ_EN": {
-                    "description": "For SPI0, Cache access enable, 1: enable, 0:disable.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_USR_ADDR_4BYTE": {
-                    "description": "For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_FLASH_USR_CMD": {
-                    "description": "For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FDIN_DUAL": {
-                    "description": "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FDOUT_DUAL": {
-                    "description": "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FDIN_QUAD": {
-                    "description": "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FDOUT_QUAD": {
-                    "description": "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FSM": {
-              "description": "SPI0 FSM status register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CSPI_ST": {
-                    "description": "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "EM_ST": {
-                    "description": "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CSPI_LOCK_DELAY_TIME": {
-                    "description": "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.",
-                    "offset": 7,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMING_CALI": {
-              "description": "SPI0 timing calibration register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMING_CLK_ENA": {
-                    "description": "The bit is used to enable timing adjust clock for all reading operations.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TIMING_CALI": {
-                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXTRA_DUMMY_CYCLELEN": {
-                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
-                    "offset": 2,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "DIN_MODE": {
-              "description": "SPI0 input delay mode control register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DIN_NUM": {
-              "description": "SPI0 input delay number control register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DOUT_MODE": {
-              "description": "SPI0 output delay mode control register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUT0_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DOUT1_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DOUT2_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DOUT3_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SPI0 clk_gate register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_CLK_SEL": {
-              "description": "SPI0 module clock select register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI01_CLK_SEL": {
-                    "description": "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583408,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "SPI register version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SPI1": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CMD": {
-              "description": "SPI1 memory command register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI1_MST_ST": {
-                    "description": "The current status of SPI1 master FSM.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "MSPI_ST": {
-                    "description": "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "FLASH_PE": {
-                    "description": "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "USR": {
-                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "FLASH_HPM": {
-                    "description": "Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FLASH_RES": {
-                    "description": "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "FLASH_DP": {
-                    "description": "Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "FLASH_CE": {
-                    "description": "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "FLASH_BE": {
-                    "description": "Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FLASH_SE": {
-                    "description": "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "FLASH_PP": {
-                    "description": "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "FLASH_WRSR": {
-                    "description": "Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "FLASH_RDSR": {
-                    "description": "Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "FLASH_RDID": {
-                    "description": "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "FLASH_WRDI": {
-                    "description": "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "FLASH_WREN": {
-                    "description": "Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "FLASH_READ": {
-                    "description": "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ADDR": {
-              "description": "SPI1 address register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_ADDR_VALUE": {
-                    "description": "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CTRL": {
-              "description": "SPI1 control register.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2924544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FDUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FCS_CRC_EN": {
-                    "description": "For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TX_CRC_EN": {
-                    "description": "For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "FASTRD_MODE": {
-                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RESANDRES": {
-                    "description": "The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "WRSR_2B": {
-                    "description": "two bytes data will be written to status register when it is set. 1: enable 0: disable.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "FREAD_DIO": {
-                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FREAD_QIO": {
-                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CTRL1": {
-              "description": "SPI1 control1 register.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 4092,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CS_HOLD_DLY_RES": {
-                    "description": "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.",
-                    "offset": 2,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "SPI1 control2 register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYNC_RESET": {
-                    "description": "The FSM will be reset.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI1 clock division control register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 196867,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
-                    "offset": 16,
-                    "size": 8
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "reserved",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI1 user register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 2147483648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FWRITE_DUAL": {
-                    "description": "In the write operations read-data phase apply 2 signals",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "FWRITE_QUAD": {
-                    "description": "In the write operations read-data phase apply 4 signals",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FWRITE_DIO": {
-                    "description": "In the write operations address phase and read-data phase apply 2 signals.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "FWRITE_QIO": {
-                    "description": "In the write operations address phase and read-data phase apply 4 signals.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "USR_MISO_HIGHPART": {
-                    "description": "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "USR_MOSI_HIGHPART": {
-                    "description": "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "SPI clock is disable in dummy phase when the bit is enable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_MOSI": {
-                    "description": "This bit enable the write-data phase of an operation.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_MISO": {
-                    "description": "This bit enable the read-data phase of an operation.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "USR_ADDR": {
-                    "description": "This bit enable the address phase of an operation.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "USR_COMMAND": {
-                    "description": "This bit enable the command phase of an operation.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI1 user1 register.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 1543503879,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI1 user2 register.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1879048192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MOSI_DLEN": {
-              "description": "SPI1 send data bit length control register.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_MOSI_DBITLEN": {
-                    "description": "The length in bits of write-data. The register value shall be (bit_num-1).",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "MISO_DLEN": {
-              "description": "SPI1 receive data bit length control register.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_MISO_DBITLEN": {
-                    "description": "The length in bits of  read-data. The register value shall be (bit_num-1).",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "RD_STATUS": {
-              "description": "SPI1 status register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS": {
-                    "description": "The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "WB_MODE": {
-                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI1 misc register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS0_DIS": {
-                    "description": "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CS1_DIS": {
-                    "description": "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CRC": {
-              "description": "SPI1 TX CRC data register.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "For SPI1, the value of crc32.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_FCTRL": {
-              "description": "SPI1 bit mode control register.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_USR_ADDR_4BYTE": {
-                    "description": "For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FDIN_DUAL": {
-                    "description": "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FDOUT_DUAL": {
-                    "description": "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FDIN_QUAD": {
-                    "description": "For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FDOUT_QUAD": {
-                    "description": "For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "W0": {
-              "description": "SPI1 memory data buffer0",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF0": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W1": {
-              "description": "SPI1 memory data buffer1",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF1": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W2": {
-              "description": "SPI1 memory data buffer2",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF2": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W3": {
-              "description": "SPI1 memory data buffer3",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF3": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W4": {
-              "description": "SPI1 memory data buffer4",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF4": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W5": {
-              "description": "SPI1 memory data buffer5",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF5": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W6": {
-              "description": "SPI1 memory data buffer6",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF6": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W7": {
-              "description": "SPI1 memory data buffer7",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF7": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W8": {
-              "description": "SPI1 memory data buffer8",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF8": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W9": {
-              "description": "SPI1 memory data buffer9",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF9": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W10": {
-              "description": "SPI1 memory data buffer10",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF10": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W11": {
-              "description": "SPI1 memory data buffer11",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF11": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W12": {
-              "description": "SPI1 memory data buffer12",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF12": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W13": {
-              "description": "SPI1 memory data buffer13",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF13": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W14": {
-              "description": "SPI1 memory data buffer14",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF14": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W15": {
-              "description": "SPI1 memory data buffer15",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF15": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_WAITI_CTRL": {
-              "description": "SPI1 wait idle control register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 20,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WAITI_DUMMY": {
-                    "description": "The dummy phase enable when wait flash idle (RDSR)",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "WAITI_CMD": {
-                    "description": "The command to wait flash idle(RDSR).",
-                    "offset": 2,
-                    "size": 8
-                  },
-                  "WAITI_DUMMY_CYCLELEN": {
-                    "description": "The dummy cycle length when wait flash idle(RDSR).",
-                    "offset": 10,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "FLASH_SUS_CTRL": {
-              "description": "SPI1 flash suspend control register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 134225920,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_PER": {
-                    "description": "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "FLASH_PES": {
-                    "description": "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FLASH_PER_WAIT_EN": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FLASH_PES_WAIT_EN": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PES_PER_EN": {
-                    "description": "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FLASH_PES_EN": {
-                    "description": "Set this bit to enable Auto-suspending function.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "PESR_END_MSK": {
-                    "description": "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].",
-                    "offset": 6,
-                    "size": 16
-                  },
-                  "RD_SUS_2B": {
-                    "description": "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "PER_END_EN": {
-                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PES_END_EN": {
-                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "SUS_TIMEOUT_CNT": {
-                    "description": "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "FLASH_SUS_CMD": {
-              "description": "SPI1 flash suspend command register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 357754,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_PER_COMMAND": {
-                    "description": "Program/Erase resume command.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "FLASH_PES_COMMAND": {
-                    "description": "Program/Erase suspend command.",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "WAIT_PESR_COMMAND": {
-                    "description": "Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "SUS_STATUS": {
-              "description": "SPI1 flash suspend status register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_SUS": {
-                    "description": "The status of flash suspend, only used in SPI1.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "WAIT_PESR_CMD_2B": {
-                    "description": "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FLASH_HPM_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FLASH_RES_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FLASH_DP_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FLASH_PER_DLY_128": {
-                    "description": "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FLASH_PES_DLY_128": {
-                    "description": "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SPI0_LOCK_EN": {
-                    "description": "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TIMING_CALI": {
-              "description": "SPI1 timing control register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMING_CALI": {
-                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXTRA_DUMMY_CYCLELEN": {
-                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
-                    "offset": 2,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "SPI1 interrupt enable register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PES_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "WPE_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_ST_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MST_ST_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "SPI1 interrupt clear register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PES_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WPE_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_ST_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_ST_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "SPI1 interrupt raw register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PES_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WPE_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_ST_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_ST_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "SPI1 interrupt status register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PES_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WPE_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_ST_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_ST_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SPI1 clk_gate register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583472,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SPI2": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CMD": {
-              "description": "Command control register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONF_BITLEN": {
-                    "description": "Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 18
-                  },
-                  "UPDATE": {
-                    "description": "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "USR": {
-                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ADDR": {
-              "description": "Address value register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_ADDR_VALUE": {
-                    "description": "Address to slave. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CTRL": {
-              "description": "SPI control register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 3932160,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "HOLD_POL": {
-                    "description": "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP_POL": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "RD_BIT_ORDER": {
-                    "description": "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "WR_BIT_ORDER": {
-                    "description": "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.",
-                    "offset": 26,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI clock control register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 2147496003,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 6
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.",
-                    "offset": 12,
-                    "size": 6
-                  },
-                  "CLKDIV_PRE": {
-                    "description": "In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI USER control register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 2147483840,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUTDIN": {
-                    "description": "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "QPI_MODE": {
-                    "description": "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TSCK_I_EDGE": {
-                    "description": "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CS_HOLD": {
-                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CS_SETUP": {
-                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RSCK_I_EDGE": {
-                    "description": "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FWRITE_DUAL": {
-                    "description": "In the write operations read-data phase apply 2 signals. Can be configured in CONF state.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "FWRITE_QUAD": {
-                    "description": "In the write operations read-data phase apply 4 signals. Can be configured in CONF state.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "USR_CONF_NXT": {
-                    "description": "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SIO": {
-                    "description": "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "USR_MISO_HIGHPART": {
-                    "description": "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "USR_MOSI_HIGHPART": {
-                    "description": "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_MOSI": {
-                    "description": "This bit enable the write-data phase of an operation. Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_MISO": {
-                    "description": "This bit enable the read-data phase of an operation. Can be configured in CONF state.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation. Can be configured in CONF state.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "USR_ADDR": {
-                    "description": "This bit enable the address phase of an operation. Can be configured in CONF state.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "USR_COMMAND": {
-                    "description": "This bit enable the command phase of an operation. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI USER control register 1",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 3091267591,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "MST_WFULL_ERR_END_EN": {
-                    "description": "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "CS_SETUP_TIME": {
-                    "description": "(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.",
-                    "offset": 17,
-                    "size": 5
-                  },
-                  "CS_HOLD_TIME": {
-                    "description": "delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.",
-                    "offset": 22,
-                    "size": 5
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI USER control register 2",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 2013265920,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "MST_REMPTY_ERR_END_EN": {
-                    "description": "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MS_DLEN": {
-              "description": "SPI data bit length control register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MS_DATA_BITLEN": {
-                    "description": "The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 18
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI misc register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 62,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS0_DIS": {
-                    "description": "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CS1_DIS": {
-                    "description": "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CS2_DIS": {
-                    "description": "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CS3_DIS": {
-                    "description": "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CS4_DIS": {
-                    "description": "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CS5_DIS": {
-                    "description": "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CK_DIS": {
-                    "description": "1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "MASTER_CS_POL": {
-                    "description": "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "SLAVE_CS_POL": {
-                    "description": "spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set. Can be configured in CONF state.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "QUAD_DIN_PIN_SWAP": {
-                    "description": "1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIN_MODE": {
-              "description": "SPI input delay mode configuration",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "TIMING_HCLK_ACTIVE": {
-                    "description": "1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIN_NUM": {
-              "description": "SPI input delay number configuration",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DOUT_MODE": {
-              "description": "SPI output delay mode configuration",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUT0_MODE": {
-                    "description": "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DOUT1_MODE": {
-                    "description": "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DOUT2_MODE": {
-                    "description": "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DOUT3_MODE": {
-                    "description": "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_CONF": {
-              "description": "SPI DMA control register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_SLV_SEG_TRANS_EN": {
-                    "description": "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "SLV_RX_SEG_TRANS_CLR_EN": {
-                    "description": "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "SLV_TX_SEG_TRANS_CLR_EN": {
-                    "description": "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "RX_EOF_EN": {
-                    "description": "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "DMA_RX_ENA": {
-                    "description": "Set this bit to enable SPI DMA controlled receive data mode.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "DMA_TX_ENA": {
-                    "description": "Set this bit to enable SPI DMA controlled send data mode.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "RX_AFIFO_RST": {
-                    "description": "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BUF_AFIFO_RST": {
-                    "description": "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_AFIFO_RST": {
-                    "description": "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_INT_ENA": {
-              "description": "SPI DMA interrupt enable register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SLV_EX_QPI_INT_ENA": {
-                    "description": "The enable bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_EN_QPI_INT_ENA": {
-                    "description": "The enable bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_CMD7_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SLV_CMD8_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SLV_CMD9_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SLV_CMDA_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SLV_RD_DMA_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WR_DMA_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RD_BUF_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WR_BUF_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TRANS_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SEG_MAGIC_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLV_CMD_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "APP2_INT_ENA": {
-                    "description": "The enable bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "APP1_INT_ENA": {
-                    "description": "The enable bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_INT_CLR": {
-              "description": "SPI DMA interrupt clear register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_EX_QPI_INT_CLR": {
-                    "description": "The clear bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_EN_QPI_INT_CLR": {
-                    "description": "The clear bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD7_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD8_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD9_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMDA_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_RD_DMA_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_WR_DMA_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_RD_BUF_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_WR_BUF_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SEG_MAGIC_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP2_INT_CLR": {
-                    "description": "The clear bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP1_INT_CLR": {
-                    "description": "The clear bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_INT_RAW": {
-              "description": "SPI DMA interrupt raw register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_RAW": {
-                    "description": "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_RAW": {
-                    "description": "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SLV_EX_QPI_INT_RAW": {
-                    "description": "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_EN_QPI_INT_RAW": {
-                    "description": "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_CMD7_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SLV_CMD8_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SLV_CMD9_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SLV_CMDA_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SLV_RD_DMA_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WR_DMA_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RD_BUF_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WR_BUF_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TRANS_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SEG_MAGIC_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLV_CMD_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "APP2_INT_RAW": {
-                    "description": "The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "APP1_INT_RAW": {
-                    "description": "The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_INT_ST": {
-              "description": "SPI DMA interrupt status register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_ST": {
-                    "description": "The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_ST": {
-                    "description": "The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_EX_QPI_INT_ST": {
-                    "description": "The status bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_EN_QPI_INT_ST": {
-                    "description": "The status bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD7_INT_ST": {
-                    "description": "The status bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD8_INT_ST": {
-                    "description": "The status bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD9_INT_ST": {
-                    "description": "The status bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMDA_INT_ST": {
-                    "description": "The status bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_RD_DMA_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_WR_DMA_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_RD_BUF_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_WR_BUF_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_DONE_INT_ST": {
-                    "description": "The status bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_ST": {
-                    "description": "The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEG_MAGIC_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_ST": {
-                    "description": "The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_ST": {
-                    "description": "The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP2_INT_ST": {
-                    "description": "The status bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP1_INT_ST": {
-                    "description": "The status bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "W0": {
-              "description": "SPI CPU-controlled buffer0",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF0": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W1": {
-              "description": "SPI CPU-controlled buffer1",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF1": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W2": {
-              "description": "SPI CPU-controlled buffer2",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF2": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W3": {
-              "description": "SPI CPU-controlled buffer3",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF3": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W4": {
-              "description": "SPI CPU-controlled buffer4",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF4": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W5": {
-              "description": "SPI CPU-controlled buffer5",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF5": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W6": {
-              "description": "SPI CPU-controlled buffer6",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF6": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W7": {
-              "description": "SPI CPU-controlled buffer7",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF7": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W8": {
-              "description": "SPI CPU-controlled buffer8",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF8": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W9": {
-              "description": "SPI CPU-controlled buffer9",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF9": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W10": {
-              "description": "SPI CPU-controlled buffer10",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF10": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W11": {
-              "description": "SPI CPU-controlled buffer11",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF11": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W12": {
-              "description": "SPI CPU-controlled buffer12",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF12": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W13": {
-              "description": "SPI CPU-controlled buffer13",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF13": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W14": {
-              "description": "SPI CPU-controlled buffer14",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF14": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W15": {
-              "description": "SPI CPU-controlled buffer15",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF15": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SLAVE": {
-              "description": "SPI slave control register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 41943040,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CLK_MODE_13": {
-                    "description": "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RSCK_DATA_OUT": {
-                    "description": "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_RDDMA_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WRDMA_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RDBUF_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WRBUF_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DMA_SEG_MAGIC_VALUE": {
-                    "description": "The magic value of BM table in master DMA seg-trans.",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "MODE": {
-                    "description": "Set SPI work mode. 1: slave mode 0: master mode.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SOFT_RESET": {
-                    "description": "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "USR_CONF": {
-                    "description": "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLAVE1": {
-              "description": "SPI slave control register 1",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLV_DATA_BITLEN": {
-                    "description": "The transferred data bit length in SPI slave FD and HD mode.",
-                    "offset": 0,
-                    "size": 18
-                  },
-                  "SLV_LAST_COMMAND": {
-                    "description": "In the slave mode it is the value of command.",
-                    "offset": 18,
-                    "size": 8
-                  },
-                  "SLV_LAST_ADDR": {
-                    "description": "In the slave mode it is the value of address.",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "CLK_GATE": {
-              "description": "SPI module clock and register clock control",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Set this bit to enable clk gate",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MST_CLK_ACTIVE": {
-                    "description": "Set this bit to power on the SPI module clock.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MST_CLK_SEL": {
-                    "description": "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 33583648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "SPI register version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SYSTEM": {
-        "description": "System",
-        "children": {
-          "registers": {
-            "CPU_PERI_CLK_EN": {
-              "description": "cpu_peripheral clock gating register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN_ASSIST_DEBUG": {
-                    "description": "reg_clk_en_assist_debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CLK_EN_DEDICATED_GPIO": {
-                    "description": "reg_clk_en_dedicated_gpio",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PERI_RST_EN": {
-              "description": "cpu_peripheral reset register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RST_EN_ASSIST_DEBUG": {
-                    "description": "reg_rst_en_assist_debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RST_EN_DEDICATED_GPIO": {
-                    "description": "reg_rst_en_dedicated_gpio",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PER_CONF": {
-              "description": "cpu clock config register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 12,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPUPERIOD_SEL": {
-                    "description": "reg_cpuperiod_sel",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "PLL_FREQ_SEL": {
-                    "description": "reg_pll_freq_sel",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CPU_WAIT_MODE_FORCE_ON": {
-                    "description": "reg_cpu_wait_mode_force_on",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CPU_WAITI_DELAY_NUM": {
-                    "description": "reg_cpu_waiti_delay_num",
-                    "offset": 4,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_PD_MASK": {
-              "description": "memory power down mask register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSLP_MEM_PD_MASK": {
-                    "description": "reg_lslp_mem_pd_mask",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_CLK_EN0": {
-              "description": "peripheral clock gating register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 4190232687,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMERS_CLK_EN": {
-                    "description": "reg_timers_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SPI01_CLK_EN": {
-                    "description": "reg_spi01_clk_en",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART_CLK_EN": {
-                    "description": "reg_uart_clk_en",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "WDG_CLK_EN": {
-                    "description": "reg_wdg_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "I2S0_CLK_EN": {
-                    "description": "reg_i2s0_clk_en",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "UART1_CLK_EN": {
-                    "description": "reg_uart1_clk_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SPI2_CLK_EN": {
-                    "description": "reg_spi2_clk_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "I2C_EXT0_CLK_EN": {
-                    "description": "reg_ext0_clk_en",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UHCI0_CLK_EN": {
-                    "description": "reg_uhci0_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RMT_CLK_EN": {
-                    "description": "reg_rmt_clk_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "PCNT_CLK_EN": {
-                    "description": "reg_pcnt_clk_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "LEDC_CLK_EN": {
-                    "description": "reg_ledc_clk_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UHCI1_CLK_EN": {
-                    "description": "reg_uhci1_clk_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TIMERGROUP_CLK_EN": {
-                    "description": "reg_timergroup_clk_en",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "EFUSE_CLK_EN": {
-                    "description": "reg_efuse_clk_en",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TIMERGROUP1_CLK_EN": {
-                    "description": "reg_timergroup1_clk_en",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SPI3_CLK_EN": {
-                    "description": "reg_spi3_clk_en",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "PWM0_CLK_EN": {
-                    "description": "reg_pwm0_clk_en",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "EXT1_CLK_EN": {
-                    "description": "reg_ext1_clk_en",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "CAN_CLK_EN": {
-                    "description": "reg_can_clk_en",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "PWM1_CLK_EN": {
-                    "description": "reg_pwm1_clk_en",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "I2S1_CLK_EN": {
-                    "description": "reg_i2s1_clk_en",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SPI2_DMA_CLK_EN": {
-                    "description": "reg_spi2_dma_clk_en",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "USB_DEVICE_CLK_EN": {
-                    "description": "reg_usb_device_clk_en",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "UART_MEM_CLK_EN": {
-                    "description": "reg_uart_mem_clk_en",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PWM2_CLK_EN": {
-                    "description": "reg_pwm2_clk_en",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PWM3_CLK_EN": {
-                    "description": "reg_pwm3_clk_en",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SPI3_DMA_CLK_EN": {
-                    "description": "reg_spi3_dma_clk_en",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_CLK_EN": {
-                    "description": "reg_apb_saradc_clk_en",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "SYSTIMER_CLK_EN": {
-                    "description": "reg_systimer_clk_en",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ADC2_ARB_CLK_EN": {
-                    "description": "reg_adc2_arb_clk_en",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI4_CLK_EN": {
-                    "description": "reg_spi4_clk_en",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_CLK_EN1": {
-              "description": "peripheral clock gating register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CRYPTO_AES_CLK_EN": {
-                    "description": "reg_crypto_aes_clk_en",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CRYPTO_SHA_CLK_EN": {
-                    "description": "reg_crypto_sha_clk_en",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CRYPTO_RSA_CLK_EN": {
-                    "description": "reg_crypto_rsa_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CRYPTO_DS_CLK_EN": {
-                    "description": "reg_crypto_ds_clk_en",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRYPTO_HMAC_CLK_EN": {
-                    "description": "reg_crypto_hmac_clk_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DMA_CLK_EN": {
-                    "description": "reg_dma_clk_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDIO_HOST_CLK_EN": {
-                    "description": "reg_sdio_host_clk_en",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "LCD_CAM_CLK_EN": {
-                    "description": "reg_lcd_cam_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "UART2_CLK_EN": {
-                    "description": "reg_uart2_clk_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TSENS_CLK_EN": {
-                    "description": "reg_tsens_clk_en",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_RST_EN0": {
-              "description": "reserved",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMERS_RST": {
-                    "description": "reg_timers_rst",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SPI01_RST": {
-                    "description": "reg_spi01_rst",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART_RST": {
-                    "description": "reg_uart_rst",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "WDG_RST": {
-                    "description": "reg_wdg_rst",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "I2S0_RST": {
-                    "description": "reg_i2s0_rst",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "UART1_RST": {
-                    "description": "reg_uart1_rst",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SPI2_RST": {
-                    "description": "reg_spi2_rst",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "I2C_EXT0_RST": {
-                    "description": "reg_ext0_rst",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UHCI0_RST": {
-                    "description": "reg_uhci0_rst",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RMT_RST": {
-                    "description": "reg_rmt_rst",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "PCNT_RST": {
-                    "description": "reg_pcnt_rst",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "LEDC_RST": {
-                    "description": "reg_ledc_rst",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UHCI1_RST": {
-                    "description": "reg_uhci1_rst",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TIMERGROUP_RST": {
-                    "description": "reg_timergroup_rst",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "EFUSE_RST": {
-                    "description": "reg_efuse_rst",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TIMERGROUP1_RST": {
-                    "description": "reg_timergroup1_rst",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SPI3_RST": {
-                    "description": "reg_spi3_rst",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "PWM0_RST": {
-                    "description": "reg_pwm0_rst",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "EXT1_RST": {
-                    "description": "reg_ext1_rst",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "CAN_RST": {
-                    "description": "reg_can_rst",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "PWM1_RST": {
-                    "description": "reg_pwm1_rst",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "I2S1_RST": {
-                    "description": "reg_i2s1_rst",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SPI2_DMA_RST": {
-                    "description": "reg_spi2_dma_rst",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "USB_DEVICE_RST": {
-                    "description": "reg_usb_device_rst",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "UART_MEM_RST": {
-                    "description": "reg_uart_mem_rst",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PWM2_RST": {
-                    "description": "reg_pwm2_rst",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PWM3_RST": {
-                    "description": "reg_pwm3_rst",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SPI3_DMA_RST": {
-                    "description": "reg_spi3_dma_rst",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_RST": {
-                    "description": "reg_apb_saradc_rst",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "SYSTIMER_RST": {
-                    "description": "reg_systimer_rst",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ADC2_ARB_RST": {
-                    "description": "reg_adc2_arb_rst",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI4_RST": {
-                    "description": "reg_spi4_rst",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_RST_EN1": {
-              "description": "peripheral reset register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 510,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CRYPTO_AES_RST": {
-                    "description": "reg_crypto_aes_rst",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CRYPTO_SHA_RST": {
-                    "description": "reg_crypto_sha_rst",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CRYPTO_RSA_RST": {
-                    "description": "reg_crypto_rsa_rst",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CRYPTO_DS_RST": {
-                    "description": "reg_crypto_ds_rst",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRYPTO_HMAC_RST": {
-                    "description": "reg_crypto_hmac_rst",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DMA_RST": {
-                    "description": "reg_dma_rst",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDIO_HOST_RST": {
-                    "description": "reg_sdio_host_rst",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "LCD_CAM_RST": {
-                    "description": "reg_lcd_cam_rst",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "UART2_RST": {
-                    "description": "reg_uart2_rst",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TSENS_RST": {
-                    "description": "reg_tsens_rst",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BT_LPCK_DIV_INT": {
-              "description": "clock config register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_LPCK_DIV_NUM": {
-                    "description": "reg_bt_lpck_div_num",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "BT_LPCK_DIV_FRAC": {
-              "description": "clock config register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 33558529,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_LPCK_DIV_B": {
-                    "description": "reg_bt_lpck_div_b",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "BT_LPCK_DIV_A": {
-                    "description": "reg_bt_lpck_div_a",
-                    "offset": 12,
-                    "size": 12
-                  },
-                  "LPCLK_SEL_RTC_SLOW": {
-                    "description": "reg_lpclk_sel_rtc_slow",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_8M": {
-                    "description": "reg_lpclk_sel_8m",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_XTAL": {
-                    "description": "reg_lpclk_sel_xtal",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_XTAL32K": {
-                    "description": "reg_lpclk_sel_xtal32k",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "LPCLK_RTC_EN": {
-                    "description": "reg_lpclk_rtc_en",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_0": {
-              "description": "interrupt generate register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_0": {
-                    "description": "reg_cpu_intr_from_cpu_0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_1": {
-              "description": "interrupt generate register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_1": {
-                    "description": "reg_cpu_intr_from_cpu_1",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_2": {
-              "description": "interrupt generate register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_2": {
-                    "description": "reg_cpu_intr_from_cpu_2",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_3": {
-              "description": "interrupt generate register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_3": {
-                    "description": "reg_cpu_intr_from_cpu_3",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RSA_PD_CTRL": {
-              "description": "rsa memory power control register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RSA_MEM_PD": {
-                    "description": "reg_rsa_mem_pd",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RSA_MEM_FORCE_PU": {
-                    "description": "reg_rsa_mem_force_pu",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RSA_MEM_FORCE_PD": {
-                    "description": "reg_rsa_mem_force_pd",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EDMA_CTRL": {
-              "description": "edma clcok and reset register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EDMA_CLK_ON": {
-                    "description": "reg_edma_clk_on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "EDMA_RESET": {
-                    "description": "reg_edma_reset",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_CONTROL": {
-              "description": "cache control register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_CLK_ON": {
-                    "description": "reg_icache_clk_on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_RESET": {
-                    "description": "reg_icache_reset",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DCACHE_CLK_ON": {
-                    "description": "reg_dcache_clk_on",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DCACHE_RESET": {
-                    "description": "reg_dcache_reset",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL": {
-              "description": "SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_SPI_MANUAL_ENCRYPT": {
-                    "description": "reg_enable_spi_manual_encrypt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_DB_ENCRYPT": {
-                    "description": "reg_enable_download_db_encrypt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_G0CB_DECRYPT": {
-                    "description": "reg_enable_download_g0cb_decrypt",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_MANUAL_ENCRYPT": {
-                    "description": "reg_enable_download_manual_encrypt",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RTC_FASTMEM_CONFIG": {
-              "description": "fast memory config register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 2146435072,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_MEM_CRC_START": {
-                    "description": "reg_rtc_mem_crc_start",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RTC_MEM_CRC_ADDR": {
-                    "description": "reg_rtc_mem_crc_addr",
-                    "offset": 9,
-                    "size": 11
-                  },
-                  "RTC_MEM_CRC_LEN": {
-                    "description": "reg_rtc_mem_crc_len",
-                    "offset": 20,
-                    "size": 11
-                  },
-                  "RTC_MEM_CRC_FINISH": {
-                    "description": "reg_rtc_mem_crc_finish",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RTC_FASTMEM_CRC": {
-              "description": "reserved",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_MEM_CRC_RES": {
-                    "description": "reg_rtc_mem_crc_res",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "REDUNDANT_ECO_CTRL": {
-              "description": "eco register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDUNDANT_ECO_DRIVE": {
-                    "description": "reg_redundant_eco_drive",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "REDUNDANT_ECO_RESULT": {
-                    "description": "reg_redundant_eco_result",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "clock gating register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SYSCLK_CONF": {
-              "description": "system clock config register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_DIV_CNT": {
-                    "description": "reg_pre_div_cnt",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "SOC_CLK_SEL": {
-                    "description": "reg_soc_clk_sel",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CLK_XTAL_FREQ": {
-                    "description": "reg_clk_xtal_freq",
-                    "offset": 12,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "CLK_DIV_EN": {
-                    "description": "reg_clk_div_en",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MEM_PVT": {
-              "description": "mem pvt register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_PATH_LEN": {
-                    "description": "reg_mem_path_len",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "MEM_ERR_CNT_CLR": {
-                    "description": "reg_mem_err_cnt_clr",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MONITOR_EN": {
-                    "description": "reg_mem_pvt_monitor_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "MEM_TIMING_ERR_CNT": {
-                    "description": "reg_mem_timing_err_cnt",
-                    "offset": 6,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "MEM_VT_SEL": {
-                    "description": "reg_mem_vt_sel",
-                    "offset": 22,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "COMB_PVT_LVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_LVT": {
-                    "description": "reg_comb_path_len_lvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_LVT": {
-                    "description": "reg_comb_err_cnt_clr_lvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_LVT": {
-                    "description": "reg_comb_pvt_monitor_en_lvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_NVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_NVT": {
-                    "description": "reg_comb_path_len_nvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_NVT": {
-                    "description": "reg_comb_err_cnt_clr_nvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_NVT": {
-                    "description": "reg_comb_pvt_monitor_en_nvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_HVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_HVT": {
-                    "description": "reg_comb_path_len_hvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_HVT": {
-                    "description": "reg_comb_err_cnt_clr_hvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_HVT": {
-                    "description": "reg_comb_pvt_monitor_en_hvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SYSTEM_REG_DATE": {
-              "description": "Version register",
-              "offset": 4092,
-              "size": 32,
-              "reset_value": 33583440,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTEM_REG_DATE": {
-                    "description": "reg_system_reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SYSTIMER": {
-        "description": "System Timer",
-        "children": {
-          "registers": {
-            "CONF": {
-              "description": "SYSTIMER_CONF.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1174405120,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_CLK_FO": {
-                    "description": "systimer clock force on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TARGET2_WORK_EN": {
-                    "description": "target2 work enable",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "TARGET1_WORK_EN": {
-                    "description": "target1 work enable",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TARGET0_WORK_EN": {
-                    "description": "target0 work enable",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_CORE1_STALL_EN": {
-                    "description": "If timer unit1 is stalled when core1 stalled",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_CORE0_STALL_EN": {
-                    "description": "If timer unit1 is stalled when core0 stalled",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_CORE1_STALL_EN": {
-                    "description": "If timer unit0 is stalled when core1 stalled",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_CORE0_STALL_EN": {
-                    "description": "If timer unit0 is stalled when core0 stalled",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_WORK_EN": {
-                    "description": "timer unit1 work enable",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_WORK_EN": {
-                    "description": "timer unit0 work enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "register file clk gating",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "UNIT0_OP": {
-              "description": "SYSTIMER_UNIT0_OP.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_VALID": {
-                    "description": "reg_timer_unit0_value_valid",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIMER_UNIT0_UPDATE": {
-                    "description": "update timer_unit0",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_OP": {
-              "description": "SYSTIMER_UNIT1_OP.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_VALID": {
-                    "description": "timer value is sync and valid",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIMER_UNIT1_UPDATE": {
-                    "description": "update timer unit1",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD_HI": {
-              "description": "SYSTIMER_UNIT0_LOAD_HI.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD_HI": {
-                    "description": "timer unit0 load high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD_LO": {
-              "description": "SYSTIMER_UNIT0_LOAD_LO.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD_LO": {
-                    "description": "timer unit0 load low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD_HI": {
-              "description": "SYSTIMER_UNIT1_LOAD_HI.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD_HI": {
-                    "description": "timer unit1 load high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD_LO": {
-              "description": "SYSTIMER_UNIT1_LOAD_LO.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD_LO": {
-                    "description": "timer unit1 load low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET0_HI": {
-              "description": "SYSTIMER_TARGET0_HI.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET0_HI": {
-                    "description": "timer taget0 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET0_LO": {
-              "description": "SYSTIMER_TARGET0_LO.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET0_LO": {
-                    "description": "timer taget0 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET1_HI": {
-              "description": "SYSTIMER_TARGET1_HI.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET1_HI": {
-                    "description": "timer taget1 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET1_LO": {
-              "description": "SYSTIMER_TARGET1_LO.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET1_LO": {
-                    "description": "timer taget1 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET2_HI": {
-              "description": "SYSTIMER_TARGET2_HI.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET2_HI": {
-                    "description": "timer taget2 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET2_LO": {
-              "description": "SYSTIMER_TARGET2_LO.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET2_LO": {
-                    "description": "timer taget2 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET0_CONF": {
-              "description": "SYSTIMER_TARGET0_CONF.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_PERIOD": {
-                    "description": "target0 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET0_PERIOD_MODE": {
-                    "description": "Set target0 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET0_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TARGET1_CONF": {
-              "description": "SYSTIMER_TARGET1_CONF.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET1_PERIOD": {
-                    "description": "target1 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET1_PERIOD_MODE": {
-                    "description": "Set target1 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET1_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TARGET2_CONF": {
-              "description": "SYSTIMER_TARGET2_CONF.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET2_PERIOD": {
-                    "description": "target2 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET2_PERIOD_MODE": {
-                    "description": "Set target2 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET2_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "UNIT0_VALUE_HI": {
-              "description": "SYSTIMER_UNIT0_VALUE_HI.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_HI": {
-                    "description": "timer read value high 32bit",
-                    "offset": 0,
-                    "size": 20,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_VALUE_LO": {
-              "description": "SYSTIMER_UNIT0_VALUE_LO.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_LO": {
-                    "description": "timer read value low 32bit",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_VALUE_HI": {
-              "description": "SYSTIMER_UNIT1_VALUE_HI.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_HI": {
-                    "description": "timer read value high 32bit",
-                    "offset": 0,
-                    "size": 20,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_VALUE_LO": {
-              "description": "SYSTIMER_UNIT1_VALUE_LO.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_LO": {
-                    "description": "timer read value low 32bit",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMP0_LOAD": {
-              "description": "SYSTIMER_COMP0_LOAD.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP0_LOAD": {
-                    "description": "timer comp0 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "COMP1_LOAD": {
-              "description": "SYSTIMER_COMP1_LOAD.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP1_LOAD": {
-                    "description": "timer comp1 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "COMP2_LOAD": {
-              "description": "SYSTIMER_COMP2_LOAD.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP2_LOAD": {
-                    "description": "timer comp2 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD": {
-              "description": "SYSTIMER_UNIT0_LOAD.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD": {
-                    "description": "timer unit0 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD": {
-              "description": "SYSTIMER_UNIT1_LOAD.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD": {
-                    "description": "timer unit1 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "SYSTIMER_INT_ENA.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_ENA": {
-                    "description": "interupt0 enable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TARGET1_INT_ENA": {
-                    "description": "interupt1 enable",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TARGET2_INT_ENA": {
-                    "description": "interupt2 enable",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "SYSTIMER_INT_RAW.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_RAW": {
-                    "description": "interupt0 raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET1_INT_RAW": {
-                    "description": "interupt1 raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET2_INT_RAW": {
-                    "description": "interupt2 raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "SYSTIMER_INT_CLR.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_CLR": {
-                    "description": "interupt0 clear",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TARGET1_INT_CLR": {
-                    "description": "interupt1 clear",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TARGET2_INT_CLR": {
-                    "description": "interupt2 clear",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "SYSTIMER_INT_ST.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_ST": {
-                    "description": "reg_target0_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET1_INT_ST": {
-                    "description": "reg_target1_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET2_INT_ST": {
-                    "description": "reg_target2_int_st",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "SYSTIMER_DATE.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 33579377,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "TIMG0": {
-        "description": "Timer Group",
-        "children": {
-          "registers": {
-            "T0CONFIG": {
-              "description": "TIMG_T0CONFIG_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1610620928,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_USE_XTAL": {
-                    "description": "reg_t0_use_xtal.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "T0_ALARM_EN": {
-                    "description": "reg_t0_alarm_en.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "T0_DIVCNT_RST": {
-                    "description": "reg_t0_divcnt_rst.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "T0_DIVIDER": {
-                    "description": "reg_t0_divider.",
-                    "offset": 13,
-                    "size": 16
-                  },
-                  "T0_AUTORELOAD": {
-                    "description": "reg_t0_autoreload.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "T0_INCREASE": {
-                    "description": "reg_t0_increase.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "T0_EN": {
-                    "description": "reg_t0_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "T0LO": {
-              "description": "TIMG_T0LO_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LO": {
-                    "description": "t0_lo",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "T0HI": {
-              "description": "TIMG_T0HI_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_HI": {
-                    "description": "t0_hi",
-                    "offset": 0,
-                    "size": 22,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "T0UPDATE": {
-              "description": "TIMG_T0UPDATE_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_UPDATE": {
-                    "description": "t0_update",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "T0ALARMLO": {
-              "description": "TIMG_T0ALARMLO_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_ALARM_LO": {
-                    "description": "reg_t0_alarm_lo.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T0ALARMHI": {
-              "description": "TIMG_T0ALARMHI_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_ALARM_HI": {
-                    "description": "reg_t0_alarm_hi.",
-                    "offset": 0,
-                    "size": 22
-                  }
-                }
-              }
-            },
-            "T0LOADLO": {
-              "description": "TIMG_T0LOADLO_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD_LO": {
-                    "description": "reg_t0_load_lo.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T0LOADHI": {
-              "description": "TIMG_T0LOADHI_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD_HI": {
-                    "description": "reg_t0_load_hi.",
-                    "offset": 0,
-                    "size": 22
-                  }
-                }
-              }
-            },
-            "T0LOAD": {
-              "description": "TIMG_T0LOAD_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD": {
-                    "description": "t0_load",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTCONFIG0": {
-              "description": "TIMG_WDTCONFIG0_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 311296,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_APPCPU_RESET_EN": {
-                    "description": "reg_wdt_appcpu_reset_en.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "WDT_PROCPU_RESET_EN": {
-                    "description": "reg_wdt_procpu_reset_en.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "WDT_FLASHBOOT_MOD_EN": {
-                    "description": "reg_wdt_flashboot_mod_en.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "WDT_SYS_RESET_LENGTH": {
-                    "description": "reg_wdt_sys_reset_length.",
-                    "offset": 15,
-                    "size": 3
-                  },
-                  "WDT_CPU_RESET_LENGTH": {
-                    "description": "reg_wdt_cpu_reset_length.",
-                    "offset": 18,
-                    "size": 3
-                  },
-                  "WDT_USE_XTAL": {
-                    "description": "reg_wdt_use_xtal.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "WDT_CONF_UPDATE_EN": {
-                    "description": "reg_wdt_conf_update_en.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_STG3": {
-                    "description": "reg_wdt_stg3.",
-                    "offset": 23,
-                    "size": 2
-                  },
-                  "WDT_STG2": {
-                    "description": "reg_wdt_stg2.",
-                    "offset": 25,
-                    "size": 2
-                  },
-                  "WDT_STG1": {
-                    "description": "reg_wdt_stg1.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "WDT_STG0": {
-                    "description": "reg_wdt_stg0.",
-                    "offset": 29,
-                    "size": 2
-                  },
-                  "WDT_EN": {
-                    "description": "reg_wdt_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG1": {
-              "description": "TIMG_WDTCONFIG1_REG.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 65536,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_DIVCNT_RST": {
-                    "description": "reg_wdt_divcnt_rst.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_CLK_PRESCALE": {
-                    "description": "reg_wdt_clk_prescale.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "WDTCONFIG2": {
-              "description": "TIMG_WDTCONFIG2_REG.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 26000000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG0_HOLD": {
-                    "description": "reg_wdt_stg0_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG3": {
-              "description": "TIMG_WDTCONFIG3_REG.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 134217727,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG1_HOLD": {
-                    "description": "reg_wdt_stg1_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG4": {
-              "description": "TIMG_WDTCONFIG4_REG.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1048575,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG2_HOLD": {
-                    "description": "reg_wdt_stg2_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG5": {
-              "description": "TIMG_WDTCONFIG5_REG.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1048575,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG3_HOLD": {
-                    "description": "reg_wdt_stg3_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTFEED": {
-              "description": "TIMG_WDTFEED_REG.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_FEED": {
-                    "description": "wdt_feed",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTWPROTECT": {
-              "description": "TIMG_WDTWPROTECT_REG.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 1356348065,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_WKEY": {
-                    "description": "reg_wdt_wkey.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "RTCCALICFG": {
-              "description": "TIMG_RTCCALICFG_REG.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 77824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_START_CYCLING": {
-                    "description": "reg_rtc_cali_start_cycling.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RTC_CALI_CLK_SEL": {
-                    "description": "reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "RTC_CALI_RDY": {
-                    "description": "rtc_cali_rdy",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_MAX": {
-                    "description": "reg_rtc_cali_max.",
-                    "offset": 16,
-                    "size": 15
-                  },
-                  "RTC_CALI_START": {
-                    "description": "reg_rtc_cali_start.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RTCCALICFG1": {
-              "description": "TIMG_RTCCALICFG1_REG.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_CYCLING_DATA_VLD": {
-                    "description": "rtc_cali_cycling_data_vld",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_VALUE": {
-                    "description": "rtc_cali_value",
-                    "offset": 7,
-                    "size": 25,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_TIMERS": {
-              "description": "INT_ENA_TIMG_REG",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_ENA": {
-                    "description": "t0_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "WDT_INT_ENA": {
-                    "description": "wdt_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW_TIMERS": {
-              "description": "INT_RAW_TIMG_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_RAW": {
-                    "description": "t0_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WDT_INT_RAW": {
-                    "description": "wdt_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_TIMERS": {
-              "description": "INT_ST_TIMG_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_ST": {
-                    "description": "t0_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WDT_INT_ST": {
-                    "description": "wdt_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR_TIMERS": {
-              "description": "INT_CLR_TIMG_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_CLR": {
-                    "description": "t0_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_INT_CLR": {
-                    "description": "wdt_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RTCCALICFG2": {
-              "description": "TIMG_RTCCALICFG2_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 4294967192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_TIMEOUT": {
-                    "description": "timeoutindicator",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_TIMEOUT_RST_CNT": {
-                    "description": "reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset",
-                    "offset": 3,
-                    "size": 4
-                  },
-                  "RTC_CALI_TIMEOUT_THRES": {
-                    "description": "reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold",
-                    "offset": 7,
-                    "size": 25
-                  }
-                }
-              }
-            },
-            "NTIMG_DATE": {
-              "description": "TIMG_NTIMG_DATE_REG.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 33579409,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "NTIMGS_DATE": {
-                    "description": "reg_ntimers_date.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            },
-            "REGCLK": {
-              "description": "TIMG_REGCLK_REG.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 1610612736,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_CLK_IS_ACTIVE": {
-                    "description": "reg_wdt_clk_is_active.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TIMER_CLK_IS_ACTIVE": {
-                    "description": "reg_timer_clk_is_active.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "XTS_AES": {
-        "description": "XTS-AES-128 Flash Encryption",
-        "children": {
-          "registers": {
-            "PLAIN_MEM": {
-              "description": "The memory that stores plaintext",
-              "offset": 0,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "LINESIZE": {
-              "description": "XTS-AES line-size register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LINESIZE": {
-                    "description": "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DESTINATION": {
-              "description": "XTS-AES destination register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DESTINATION": {
-                    "description": "This bit stores the destination. 0: flash(default). 1: reserved.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PHYSICAL_ADDRESS": {
-              "description": "XTS-AES physical address register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PHYSICAL_ADDRESS": {
-                    "description": "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "TRIGGER": {
-              "description": "XTS-AES trigger register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRIGGER": {
-                    "description": "Set this bit to start manual encryption calculation",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RELEASE": {
-              "description": "XTS-AES release register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RELEASE": {
-                    "description": "Set this bit to release the manual encrypted result, after that the result will be visible to spi",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DESTROY": {
-              "description": "XTS-AES destroy register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DESTROY": {
-                    "description": "Set this bit to destroy XTS-AES result.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "XTS-AES status register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "XTS-AES version control register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 538969635,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Those bits stores the version information of XTS-AES.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "TWAI": {
-        "description": "Two-Wire Automotive Interface",
-        "children": {
-          "registers": {
-            "MODE": {
-              "description": "Mode Register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_MODE": {
-                    "description": "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "LISTEN_ONLY_MODE": {
-                    "description": "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SELF_TEST_MODE": {
-                    "description": "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_FILTER_MODE": {
-                    "description": "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CMD": {
-              "description": "Command Register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_REQ": {
-                    "description": "Set the bit to 1 to allow the driving nodes start transmission.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ABORT_TX": {
-                    "description": "Set the bit to 1 to cancel a pending transmission request.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RELEASE_BUF": {
-                    "description": "Set the bit to 1 to release the RX buffer.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CLR_OVERRUN": {
-                    "description": "Set the bit to 1 to clear the data overrun status bit.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SELF_RX_REQ": {
-                    "description": "Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "Status register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_BUF_ST": {
-                    "description": "1: The data in the RX buffer is not empty, with at least one received data packet.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVERRUN_ST": {
-                    "description": "1: The RX FIFO is full and data overrun has occurred.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BUF_ST": {
-                    "description": "1: The TX buffer is empty, the CPU may write a message into it.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_COMPLETE": {
-                    "description": "1: The TWAI controller has successfully received a packet from the bus.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_ST": {
-                    "description": "1: The TWAI Controller is receiving a message from the bus.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_ST": {
-                    "description": "1: The TWAI Controller is transmitting a message to the bus.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_ST": {
-                    "description": "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_OFF_ST": {
-                    "description": "1: In bus-off status, the TWAI Controller is no longer involved in bus activities.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MISS_ST": {
-                    "description": "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "Interrupt Register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_INT_ST": {
-                    "description": "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_INT_ST": {
-                    "description": "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_WARN_INT_ST": {
-                    "description": "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVERRUN_INT_ST": {
-                    "description": "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_PASSIVE_INT_ST": {
-                    "description": "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARB_LOST_INT_ST": {
-                    "description": "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_ERR_INT_ST": {
-                    "description": "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "Interrupt Enable Register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_INT_ENA": {
-                    "description": "Set this bit to 1 to enable receive interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_INT_ENA": {
-                    "description": "Set this bit to 1 to enable transmit interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ERR_WARN_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error warning interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OVERRUN_INT_ENA": {
-                    "description": "Set this bit to 1 to enable data overrun interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "ERR_PASSIVE_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error passive interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "ARB_LOST_INT_ENA": {
-                    "description": "Set this bit to 1 to enable arbitration lost interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BUS_ERR_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BUS_TIMING_0": {
-              "description": "Bus Timing Register 0",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BAUD_PRESC": {
-                    "description": "Baud Rate Prescaler, determines the frequency dividing ratio.",
-                    "offset": 0,
-                    "size": 13
-                  },
-                  "SYNC_JUMP_WIDTH": {
-                    "description": "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide.",
-                    "offset": 14,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BUS_TIMING_1": {
-              "description": "Bus Timing Register 1",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME_SEG1": {
-                    "description": "The width of PBS1.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "TIME_SEG2": {
-                    "description": "The width of PBS2.",
-                    "offset": 4,
-                    "size": 3
-                  },
-                  "TIME_SAMP": {
-                    "description": "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ARB_LOST_CAP": {
-              "description": "Arbitration Lost Capture Register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ARB_LOST_CAP": {
-                    "description": "This register contains information about the bit position of lost arbitration.",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ERR_CODE_CAP": {
-              "description": "Error Code Capture Register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ECC_SEGMENT": {
-                    "description": "This register contains information about the location of errors, see Table 181 for details.",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "ECC_DIRECTION": {
-                    "description": "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ECC_TYPE": {
-                    "description": "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ERR_WARNING_LIMIT": {
-              "description": "Error Warning Limit Register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 96,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ERR_WARNING_LIMIT": {
-                    "description": "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "RX_ERR_CNT": {
-              "description": "Receive Error Counter Register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_ERR_CNT": {
-                    "description": "The RX error counter register, reflects value changes under reception status.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TX_ERR_CNT": {
-              "description": "Transmit Error Counter Register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_ERR_CNT": {
-                    "description": "The TX error counter register, reflects value changes under transmission status.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "DATA_0": {
-              "description": "Data register 0",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_0": {
-                    "description": "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_1": {
-              "description": "Data register 1",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_1": {
-                    "description": "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_2": {
-              "description": "Data register 2",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_2": {
-                    "description": "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_3": {
-              "description": "Data register 3",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_3": {
-                    "description": "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_4": {
-              "description": "Data register 4",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_4": {
-                    "description": "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_5": {
-              "description": "Data register 5",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_5": {
-                    "description": "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_6": {
-              "description": "Data register 6",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_6": {
-                    "description": "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_7": {
-              "description": "Data register 7",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_7": {
-                    "description": "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_8": {
-              "description": "Data register 8",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_8": {
-                    "description": "Stored the 8th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_9": {
-              "description": "Data register 9",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_9": {
-                    "description": "Stored the 9th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_10": {
-              "description": "Data register 10",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_10": {
-                    "description": "Stored the 10th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_11": {
-              "description": "Data register 11",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_11": {
-                    "description": "Stored the 11th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_12": {
-              "description": "Data register 12",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_12": {
-                    "description": "Stored the 12th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RX_MESSAGE_CNT": {
-              "description": "Receive Message Counter Register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_MESSAGE_COUNTER": {
-                    "description": "This register reflects the number of messages available within the RX FIFO.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_DIVIDER": {
-              "description": "Clock Divider register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CD": {
-                    "description": "These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLOCK_OFF": {
-                    "description": "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "UART0": {
-        "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-        "children": {
-          "registers": {
-            "FIFO": {
-              "description": "FIFO data register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_RD_BYTE": {
-                    "description": "UART 0 accesses FIFO via this register.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "Raw interrupt status",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_EMPTY_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PARITY_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error in the data.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FRM_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error .",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DSR_CHG_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTS_CHG_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BRK_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_TOUT_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XON_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XOFF_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GLITCH_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_PARITY_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_FRM_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_CLASH_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WAKEUP_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "Masked interrupt status",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_ST": {
-                    "description": "This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_EMPTY_INT_ST": {
-                    "description": "This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PARITY_ERR_INT_ST": {
-                    "description": "This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FRM_ERR_INT_ST": {
-                    "description": "This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_ST": {
-                    "description": "This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DSR_CHG_INT_ST": {
-                    "description": "This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTS_CHG_INT_ST": {
-                    "description": "This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BRK_DET_INT_ST": {
-                    "description": "This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_TOUT_INT_ST": {
-                    "description": "This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XON_INT_ST": {
-                    "description": "This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XOFF_INT_ST": {
-                    "description": "This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GLITCH_DET_INT_ST": {
-                    "description": "This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_DONE_INT_ST": {
-                    "description": "This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_ST": {
-                    "description": "This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_ST": {
-                    "description": "This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_PARITY_ERR_INT_ST": {
-                    "description": "This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_FRM_ERR_INT_ST": {
-                    "description": "This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_CLASH_INT_ST": {
-                    "description": "This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_ST": {
-                    "description": "This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WAKEUP_INT_ST": {
-                    "description": "This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "Interrupt enable bits",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_full_int_st register.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TXFIFO_EMPTY_INT_ENA": {
-                    "description": "This is the enable bit for txfifo_empty_int_st register.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PARITY_ERR_INT_ENA": {
-                    "description": "This is the enable bit for parity_err_int_st register.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FRM_ERR_INT_ENA": {
-                    "description": "This is the enable bit for frm_err_int_st register.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RXFIFO_OVF_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_ovf_int_st register.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DSR_CHG_INT_ENA": {
-                    "description": "This is the enable bit for dsr_chg_int_st register.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CTS_CHG_INT_ENA": {
-                    "description": "This is the enable bit for cts_chg_int_st register.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BRK_DET_INT_ENA": {
-                    "description": "This is the enable bit for brk_det_int_st register.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RXFIFO_TOUT_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_tout_int_st register.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SW_XON_INT_ENA": {
-                    "description": "This is the enable bit for sw_xon_int_st register.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SW_XOFF_INT_ENA": {
-                    "description": "This is the enable bit for sw_xoff_int_st register.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "GLITCH_DET_INT_ENA": {
-                    "description": "This is the enable bit for glitch_det_int_st register.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TX_BRK_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_brk_done_int_st register.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_BRK_IDLE_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_brk_idle_done_int_st register.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_done_int_st register.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RS485_PARITY_ERR_INT_ENA": {
-                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RS485_FRM_ERR_INT_ENA": {
-                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RS485_CLASH_INT_ENA": {
-                    "description": "This is the enable bit for rs485_clash_int_st register.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "AT_CMD_CHAR_DET_INT_ENA": {
-                    "description": "This is the enable bit for at_cmd_char_det_int_st register.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "WAKEUP_INT_ENA": {
-                    "description": "This is the enable bit for uart_wakeup_int_st register.",
-                    "offset": 19,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "Interrupt clear bits",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_CLR": {
-                    "description": "Set this bit to clear the rxfifo_full_int_raw interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_EMPTY_INT_CLR": {
-                    "description": "Set this bit to clear txfifo_empty_int_raw interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PARITY_ERR_INT_CLR": {
-                    "description": "Set this bit to clear parity_err_int_raw interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "FRM_ERR_INT_CLR": {
-                    "description": "Set this bit to clear frm_err_int_raw interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_OVF_INT_CLR": {
-                    "description": "Set this bit to clear rxfifo_ovf_int_raw interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DSR_CHG_INT_CLR": {
-                    "description": "Set this bit to clear the dsr_chg_int_raw interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CTS_CHG_INT_CLR": {
-                    "description": "Set this bit to clear the cts_chg_int_raw interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BRK_DET_INT_CLR": {
-                    "description": "Set this bit to clear the brk_det_int_raw interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_TOUT_INT_CLR": {
-                    "description": "Set this bit to clear the rxfifo_tout_int_raw interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_XON_INT_CLR": {
-                    "description": "Set this bit to clear the sw_xon_int_raw interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_XOFF_INT_CLR": {
-                    "description": "Set this bit to clear the sw_xoff_int_raw interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "GLITCH_DET_INT_CLR": {
-                    "description": "Set this bit to clear the glitch_det_int_raw interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_BRK_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_brk_done_int_raw interrupt..",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_brk_idle_done_int_raw interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_done_int_raw interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_PARITY_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_parity_err_int_raw interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_FRM_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_frm_err_int_raw interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_CLASH_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_clash_int_raw interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_CLR": {
-                    "description": "Set this bit to clear the at_cmd_char_det_int_raw interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WAKEUP_INT_CLR": {
-                    "description": "Set this bit to clear the uart_wakeup_int_raw interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLKDIV": {
-              "description": "Clock divider configuration",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 694,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKDIV": {
-                    "description": "The integral part of the frequency divider factor.",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "FRAG": {
-                    "description": "The decimal part of the frequency divider factor.",
-                    "offset": 20,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RX_FILT": {
-              "description": "Rx Filter configuration",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GLITCH_FILT": {
-                    "description": "when input pulse width is lower than this value, the pulse is ignored.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "GLITCH_FILT_EN": {
-                    "description": "Set this bit to enable Rx signal filter.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "UART status register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 3758145536,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_CNT": {
-                    "description": "Stores the byte number of valid data in Rx-FIFO.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "DSRN": {
-                    "description": "The register represent the level value of the internal uart dsr signal.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTSN": {
-                    "description": "This register represent the level value of the internal uart cts signal.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXD": {
-                    "description": "This register represent the  level value of the internal uart rxd signal.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_CNT": {
-                    "description": "Stores the byte number of data in Tx-FIFO.",
-                    "offset": 16,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "DTRN": {
-                    "description": "This bit represents the level of the internal uart dtr signal.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTSN": {
-                    "description": "This bit represents the level of the internal uart rts signal.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXD": {
-                    "description": "This bit represents the  level of the internal uart txd signal.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CONF0": {
-              "description": "a",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 268435484,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PARITY": {
-                    "description": "This register is used to configure the parity check mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PARITY_EN": {
-                    "description": "Set this bit to enable uart parity check.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "BIT_NUM": {
-                    "description": "This register is used to set the length of data.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "STOP_BIT_NUM": {
-                    "description": "This register is used to set the length of  stop bit.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "SW_RTS": {
-                    "description": "This register is used to configure the software rts signal which is used in software flow control.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SW_DTR": {
-                    "description": "This register is used to configure the software dtr signal which is used in software flow control.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TXD_BRK": {
-                    "description": "Set this bit to enbale transmitter to  send NULL when the process of sending data is done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "IRDA_DPLX": {
-                    "description": "Set this bit to enable IrDA loopback mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "IRDA_TX_EN": {
-                    "description": "This is the start enable bit for IrDA transmitter.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "IRDA_WCTL": {
-                    "description": "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "IRDA_TX_INV": {
-                    "description": "Set this bit to invert the level of  IrDA transmitter.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "IRDA_RX_INV": {
-                    "description": "Set this bit to invert the level of IrDA receiver.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "LOOPBACK": {
-                    "description": "Set this bit to enable uart loopback test mode.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TX_FLOW_EN": {
-                    "description": "Set this bit to enable flow control function for transmitter.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "IRDA_EN": {
-                    "description": "Set this bit to enable IrDA protocol.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RXFIFO_RST": {
-                    "description": "Set this bit to reset the uart receive-FIFO.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "TXFIFO_RST": {
-                    "description": "Set this bit to reset the uart transmit-FIFO.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RXD_INV": {
-                    "description": "Set this bit to inverse the level value of uart rxd signal.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "CTS_INV": {
-                    "description": "Set this bit to inverse the level value of uart cts signal.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "DSR_INV": {
-                    "description": "Set this bit to inverse the level value of uart dsr signal.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "TXD_INV": {
-                    "description": "Set this bit to inverse the level value of uart txd signal.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RTS_INV": {
-                    "description": "Set this bit to inverse the level value of uart rts signal.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "DTR_INV": {
-                    "description": "Set this bit to inverse the level value of uart dtr signal.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "ERR_WR_MASK": {
-                    "description": "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "AUTOBAUD_EN": {
-                    "description": "This is the enable bit for detecting baudrate.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "MEM_CLK_EN": {
-                    "description": "UART memory clock gate enable signal.",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CONF1": {
-              "description": "Configuration register 1",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 49248,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_THRHD": {
-                    "description": "It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "TXFIFO_EMPTY_THRHD": {
-                    "description": "It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "DIS_RX_DAT_OVF": {
-                    "description": "Disable UART Rx data overflow detect.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RX_TOUT_FLOW_DIS": {
-                    "description": "Set this bit to stop accumulating idle_cnt when hardware flow control works.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RX_FLOW_EN": {
-                    "description": "This is the flow enable bit for UART receiver.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "RX_TOUT_EN": {
-                    "description": "This is the enble bit for uart receiver's timeout function.",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LOWPULSE": {
-              "description": "Autobaud minimum low pulse duration register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_CNT": {
-                    "description": "This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "HIGHPULSE": {
-              "description": "Autobaud minimum high pulse duration register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_CNT": {
-                    "description": "This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RXD_CNT": {
-              "description": "Autobaud edge change count register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXD_EDGE_CNT": {
-                    "description": "This register stores the count of rxd edge change. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FLOW_CONF": {
-              "description": "Software flow-control configuration",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_FLOW_CON_EN": {
-                    "description": "Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "XONOFF_DEL": {
-                    "description": "Set this bit to remove flow control char from the received data.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FORCE_XON": {
-                    "description": "Set this bit to enable the transmitter to go on sending data.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FORCE_XOFF": {
-                    "description": "Set this bit to stop the  transmitter from sending data.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SEND_XON": {
-                    "description": "Set this bit to send Xon char. It is cleared by hardware automatically.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SEND_XOFF": {
-                    "description": "Set this bit to send Xoff char. It is cleared by hardware automatically.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLEEP_CONF": {
-              "description": "Sleep-mode configuration",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 240,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ACTIVE_THRESHOLD": {
-                    "description": "The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "SWFC_CONF0": {
-              "description": "Software flow-control character configuration",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 9952,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XOFF_THRESHOLD": {
-                    "description": "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "XOFF_CHAR": {
-                    "description": "This register stores the Xoff flow control char.",
-                    "offset": 9,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SWFC_CONF1": {
-              "description": "Software flow-control character configuration",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8704,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XON_THRESHOLD": {
-                    "description": "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "XON_CHAR": {
-                    "description": "This register stores the Xon flow control char.",
-                    "offset": 9,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TXBRK_CONF": {
-              "description": "Tx Break character configuration",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 10,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BRK_NUM": {
-                    "description": "This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "IDLE_CONF": {
-              "description": "Frame-end idle configuration",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 262400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_IDLE_THRHD": {
-                    "description": "It will produce frame end signal when receiver takes more time to receive one byte data than this register value.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "TX_IDLE_NUM": {
-                    "description": "This register is used to configure the duration time between transfers.",
-                    "offset": 10,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "RS485_CONF": {
-              "description": "RS485 mode configuration",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RS485_EN": {
-                    "description": "Set this bit to choose the rs485 mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DL0_EN": {
-                    "description": "Set this bit to delay the stop bit by 1 bit.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DL1_EN": {
-                    "description": "Set this bit to delay the stop bit by 1 bit.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RS485TX_RX_EN": {
-                    "description": "Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RS485RXBY_TX_EN": {
-                    "description": "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RS485_RX_DLY_NUM": {
-                    "description": "This register is used to delay the receiver's internal data signal.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RS485_TX_DLY_NUM": {
-                    "description": "This register is used to delay the transmitter's internal data signal.",
-                    "offset": 6,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "AT_CMD_PRECNT": {
-              "description": "Pre-sequence timing configuration",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 2305,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_IDLE_NUM": {
-                    "description": "This register is used to configure the idle duration time before the first at_cmd is received by receiver.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_POSTCNT": {
-              "description": "Post-sequence timing configuration",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 2305,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POST_IDLE_NUM": {
-                    "description": "This register is used to configure the duration time between the last at_cmd and the next data.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_GAPTOUT": {
-              "description": "Timeout configuration",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 11,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_GAP_TOUT": {
-                    "description": "This register is used to configure the duration time between the at_cmd chars.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_CHAR": {
-              "description": "AT escape sequence detection configuration",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 811,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AT_CMD_CHAR": {
-                    "description": "This register is used to configure the content of at_cmd char.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CHAR_NUM": {
-                    "description": "This register is used to configure the num of continuous at_cmd chars received by receiver.",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MEM_CONF": {
-              "description": "UART threshold and allocation configuration",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 655378,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_SIZE": {
-                    "description": "This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.",
-                    "offset": 1,
-                    "size": 3
-                  },
-                  "TX_SIZE": {
-                    "description": "This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.",
-                    "offset": 4,
-                    "size": 3
-                  },
-                  "RX_FLOW_THRHD": {
-                    "description": "This register is used to configure the maximum amount of data that can be received  when hardware flow control works.",
-                    "offset": 7,
-                    "size": 9
-                  },
-                  "RX_TOUT_THRHD": {
-                    "description": "This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.",
-                    "offset": 16,
-                    "size": 10
-                  },
-                  "MEM_FORCE_PD": {
-                    "description": "Set this bit to force power down UART memory.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PU": {
-                    "description": "Set this bit to force power up UART memory.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "MEM_TX_STATUS": {
-              "description": "Tx-FIFO write and read offset address.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_TX_WADDR": {
-                    "description": "This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "TX_RADDR": {
-                    "description": "This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.",
-                    "offset": 11,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MEM_RX_STATUS": {
-              "description": "Rx-FIFO write and read offset address.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 524544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_RX_RADDR": {
-                    "description": "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "RX_WADDR": {
-                    "description": "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.",
-                    "offset": 11,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FSM_STATUS": {
-              "description": "UART transmit and receive status.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ST_URX_OUT": {
-                    "description": "This is the status register of receiver.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "ST_UTX_OUT": {
-                    "description": "This is the status register of transmitter.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "POSPULSE": {
-              "description": "Autobaud high pulse register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POSEDGE_MIN_CNT": {
-                    "description": "This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "NEGPULSE": {
-              "description": "Autobaud low pulse register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "NEGEDGE_MIN_CNT": {
-                    "description": "This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "UART core clock configuration",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 57675776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCLK_DIV_B": {
-                    "description": "The  denominator of the frequency divider factor.",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "The numerator of the frequency divider factor.",
-                    "offset": 6,
-                    "size": 6
-                  },
-                  "SCLK_DIV_NUM": {
-                    "description": "The integral part of the frequency divider factor.",
-                    "offset": 12,
-                    "size": 8
-                  },
-                  "SCLK_SEL": {
-                    "description": "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "SCLK_EN": {
-                    "description": "Set this bit to enable UART Tx/Rx clock.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Tx/Rx.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TX_SCLK_EN": {
-                    "description": "Set this bit to enable UART Tx clock.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "RX_SCLK_EN": {
-                    "description": "Set this bit to enable UART Rx clock.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "TX_RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Tx.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RX_RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Rx.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "UART Version register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 33587824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "This is the version register.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ID": {
-              "description": "UART ID register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 1073743104,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ID": {
-                    "description": "This register is used to configure the uart_id.",
-                    "offset": 0,
-                    "size": 30
-                  },
-                  "HIGH_SPEED": {
-                    "description": "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "REG_UPDATE": {
-                    "description": "Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "USB_DEVICE": {
-        "description": "Full-speed USB Serial/JTAG Controller",
-        "children": {
-          "registers": {
-            "EP1": {
-              "description": "USB_DEVICE_EP1_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RDWR_BYTE": {
-                    "description": "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "EP1_CONF": {
-              "description": "USB_DEVICE_EP1_CONF_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_DONE": {
-                    "description": "Set this bit to indicate writing byte data to UART Tx FIFO is done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_IN_EP_DATA_FREE": {
-                    "description": "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_EP_DATA_AVAIL": {
-                    "description": "1'b1: Indicate there is data in UART Rx FIFO.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "USB_DEVICE_INT_RAW_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOF_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when SOF frame is received.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PID_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when pid error is detected.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC5_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when CRC5 error is detected.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC16_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when CRC16 error is detected.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "STUFF_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when stuff error is detected.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_BUS_RESET_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when usb bus reset is detected.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "USB_DEVICE_INT_ST_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOF_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PID_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC5_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC16_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "STUFF_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_BUS_RESET_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "USB_DEVICE_INT_ENA_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SOF_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SERIAL_IN_EMPTY_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PID_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRC5_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CRC16_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "STUFF_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "USB_BUS_RESET_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "USB_DEVICE_INT_CLR_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SOF_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PID_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CRC5_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CRC16_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "STUFF_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "USB_BUS_RESET_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONF0": {
-              "description": "USB_DEVICE_CONF0_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 16896,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PHY_SEL": {
-                    "description": "Select internal/external PHY",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "EXCHG_PINS_OVERRIDE": {
-                    "description": "Enable software control USB D+ D- exchange",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXCHG_PINS": {
-                    "description": "USB D+ D- exchange",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "VREFH": {
-                    "description": "Control single-end input high threshold,1.76V to 2V, step 80mV",
-                    "offset": 3,
-                    "size": 2
-                  },
-                  "VREFL": {
-                    "description": "Control single-end input low threshold,0.8V to 1.04V, step 80mV",
-                    "offset": 5,
-                    "size": 2
-                  },
-                  "VREF_OVERRIDE": {
-                    "description": "Enable software control input  threshold",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "PAD_PULL_OVERRIDE": {
-                    "description": "Enable software control USB D+ D- pullup pulldown",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DP_PULLUP": {
-                    "description": "Control USB D+ pull up.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DP_PULLDOWN": {
-                    "description": "Control USB D+ pull down.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "DM_PULLUP": {
-                    "description": "Control USB D- pull up.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DM_PULLDOWN": {
-                    "description": "Control USB D- pull down.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "PULLUP_VALUE": {
-                    "description": "Control pull up value.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "USB_PAD_ENABLE": {
-                    "description": "Enable USB pad function.",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TEST": {
-              "description": "USB_DEVICE_TEST_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE": {
-                    "description": "Enable test of the USB pad",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "USB_OE": {
-                    "description": "USB pad oen in test",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_DP": {
-                    "description": "USB D+ tx value in test",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_DM": {
-                    "description": "USB D- tx value in test",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "JFIFO_ST": {
-              "description": "USB_DEVICE_JFIFO_ST_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 68,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_FIFO_CNT": {
-                    "description": "JTAT in fifo counter.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_EMPTY": {
-                    "description": "1: JTAG in fifo is empty.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_FULL": {
-                    "description": "1: JTAG in fifo is full.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_CNT": {
-                    "description": "JTAT out fifo counter.",
-                    "offset": 4,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_EMPTY": {
-                    "description": "1: JTAG out fifo is empty.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_FULL": {
-                    "description": "1: JTAG out fifo is full.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_RESET": {
-                    "description": "Write 1 to reset JTAG in fifo.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "OUT_FIFO_RESET": {
-                    "description": "Write 1 to reset JTAG out fifo.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FRAM_NUM": {
-              "description": "USB_DEVICE_FRAM_NUM_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SOF_FRAME_INDEX": {
-                    "description": "Frame index of received SOF frame.",
-                    "offset": 0,
-                    "size": 11,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP0_ST": {
-              "description": "USB_DEVICE_IN_EP0_ST_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP0_STATE": {
-                    "description": "State of IN Endpoint 0.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP0_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 0.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP0_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 0.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP1_ST": {
-              "description": "USB_DEVICE_IN_EP1_ST_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP1_STATE": {
-                    "description": "State of IN Endpoint 1.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP1_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 1.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP1_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 1.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP2_ST": {
-              "description": "USB_DEVICE_IN_EP2_ST_REG.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP2_STATE": {
-                    "description": "State of IN Endpoint 2.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP2_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 2.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP2_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 2.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP3_ST": {
-              "description": "USB_DEVICE_IN_EP3_ST_REG.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP3_STATE": {
-                    "description": "State of IN Endpoint 3.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP3_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 3.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP3_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 3.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP0_ST": {
-              "description": "USB_DEVICE_OUT_EP0_ST_REG.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP0_STATE": {
-                    "description": "State of OUT Endpoint 0.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP0_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP0_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 0.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP1_ST": {
-              "description": "USB_DEVICE_OUT_EP1_ST_REG.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP1_STATE": {
-                    "description": "State of OUT Endpoint 1.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 1.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_REC_DATA_CNT": {
-                    "description": "Data count in OUT endpoint 1 when one packet is received.",
-                    "offset": 16,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP2_ST": {
-              "description": "USB_DEVICE_OUT_EP2_ST_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP2_STATE": {
-                    "description": "State of OUT Endpoint 2.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 2.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MISC_CONF": {
-              "description": "USB_DEVICE_MISC_CONF_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "MEM_CONF": {
-              "description": "USB_DEVICE_MEM_CONF_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USB_MEM_PD": {
-                    "description": "1: power down usb memory.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "USB_MEM_CLK_EN": {
-                    "description": "1: Force clock on for usb memory.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "USB_DEVICE_DATE_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 33583872,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "register version.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "UHCI0": {
-        "description": "Universal Host Controller Interface",
-        "children": {
-          "registers": {
-            "CONF0": {
-              "description": "a",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1760,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_RST": {
-                    "description": "Write 1, then write 0 to this bit to reset decode state machine.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RX_RST": {
-                    "description": "Write 1, then write 0 to this bit to reset encode state machine.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART0_CE": {
-                    "description": "Set this bit to link up HCI and UART0.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "UART1_CE": {
-                    "description": "Set this bit to link up HCI and UART1.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SEPER_EN": {
-                    "description": "Set this bit to separate the data frame using a special char.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "HEAD_EN": {
-                    "description": "Set this bit to encode the data packet with a formatting header.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CRC_REC_EN": {
-                    "description": "Set this bit to enable UHCI to receive the 16 bit CRC.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UART_IDLE_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "LEN_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "ENCODE_CRC_EN": {
-                    "description": "Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UART_RX_BRK_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "a",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_RAW": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_START_INT_RAW": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_RAW": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_RAW": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_S_REG_Q_INT_RAW": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_A_REG_Q_INT_RAW": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_INT_RAW": {
-                    "description": "This is the interrupt raw bit. Triggered when there are some errors in EOF in the",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP_CTRL0_INT_RAW": {
-                    "description": "Soft control int raw bit.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "APP_CTRL1_INT_RAW": {
-                    "description": "Soft control int raw bit.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "a",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_ST": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_START_INT_ST": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_ST": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_ST": {
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-        },
-        "peripheral_instances": {
-          "AES": {
-            "description": "AES (Advanced Encryption Standard) Accelerator",
-            "offset": 1610850304,
-            "type": "types.peripherals.AES"
-          },
-          "APB_CTRL": {
-            "description": "Advanced Peripheral Bus Controller",
-            "offset": 1610768384,
-            "type": "types.peripherals.APB_CTRL"
-          },
-          "APB_SARADC": {
-            "description": "Successive Approximation Register Analog to Digital Converter",
-            "offset": 1610874880,
-            "type": "types.peripherals.APB_SARADC"
-          },
-          "ASSIST_DEBUG": {
-            "description": "Debug Assist",
-            "offset": 1611456512,
-            "type": "types.peripherals.ASSIST_DEBUG"
-          },
-          "DMA": {
-            "description": "DMA (Direct Memory Access) Controller",
-            "offset": 1610870784,
-            "type": "types.peripherals.DMA"
-          },
-          "DS": {
-            "description": "Digital Signature",
-            "offset": 1610862592,
-            "type": "types.peripherals.DS"
-          },
-          "EFUSE": {
-            "description": "eFuse Controller",
-            "offset": 1610647552,
-            "type": "types.peripherals.EFUSE"
-          },
-          "EXTMEM": {
-            "description": "External Memory",
-            "offset": 1611415552,
-            "type": "types.peripherals.EXTMEM"
-          },
-          "GPIO": {
-            "description": "General Purpose Input/Output",
-            "offset": 1610629120,
-            "type": "types.peripherals.GPIO"
-          },
-          "GPIOSD": {
-            "description": "Sigma-Delta Modulation",
-            "offset": 1610632960,
-            "type": "types.peripherals.GPIOSD"
-          },
-          "HMAC": {
-            "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
-            "offset": 1610866688,
-            "type": "types.peripherals.HMAC"
-          },
-          "I2C0": {
-            "description": "I2C (Inter-Integrated Circuit) Controller",
-            "offset": 1610690560,
-            "type": "types.peripherals.I2C0"
-          },
-          "I2S": {
-            "description": "I2S (Inter-IC Sound) Controller",
-            "offset": 1610797056,
-            "type": "types.peripherals.I2S"
-          },
-          "INTERRUPT_CORE0": {
-            "description": "Interrupt Core",
-            "offset": 1611407360,
-            "type": "types.peripherals.INTERRUPT_CORE0"
-          },
-          "IO_MUX": {
-            "description": "Input/Output Multiplexer",
-            "offset": 1610649600,
-            "type": "types.peripherals.IO_MUX"
-          },
-          "LEDC": {
-            "description": "LED Control PWM (Pulse Width Modulation)",
-            "offset": 1610715136,
-            "type": "types.peripherals.LEDC"
-          },
-          "RMT": {
-            "description": "Remote Control Peripheral",
-            "offset": 1610702848,
-            "type": "types.peripherals.RMT"
-          },
-          "RNG": {
-            "description": "Hardware random number generator",
-            "offset": 1610768384,
-            "type": "types.peripherals.RNG"
-          },
-          "RSA": {
-            "description": "RSA (Rivest Shamir Adleman) Accelerator",
-            "offset": 1610858496,
-            "type": "types.peripherals.RSA"
-          },
-          "RTC_CNTL": {
-            "description": "Real-Time Clock Control",
-            "offset": 1610645504,
-            "type": "types.peripherals.RTC_CNTL"
-          },
-          "SENSITIVE": {
-            "description": "Sensitive",
-            "offset": 1611403264,
-            "type": "types.peripherals.SENSITIVE"
-          },
-          "SHA": {
-            "description": "SHA (Secure Hash Algorithm) Accelerator",
-            "offset": 1610854400,
-            "type": "types.peripherals.SHA"
-          },
-          "SPI0": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610625024,
-            "type": "types.peripherals.SPI0"
-          },
-          "SPI1": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610620928,
-            "type": "types.peripherals.SPI1"
-          },
-          "SPI2": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610760192,
-            "type": "types.peripherals.SPI2"
-          },
-          "SYSTEM": {
-            "description": "System",
-            "offset": 1611399168,
-            "type": "types.peripherals.SYSTEM"
-          },
-          "SYSTIMER": {
-            "description": "System Timer",
-            "offset": 1610756096,
-            "type": "types.peripherals.SYSTIMER"
-          },
-          "TIMG0": {
-            "description": "Timer Group",
-            "offset": 1610739712,
-            "type": "types.peripherals.TIMG0"
-          },
-          "TIMG1": {
-            "description": "Timer Group",
-            "offset": 1610743808,
-            "type": "types.peripherals.TIMG0"
-          },
-          "TWAI": {
-            "description": "Two-Wire Automotive Interface",
-            "offset": 1610788864,
-            "type": "types.peripherals.TWAI"
-          },
-          "UART0": {
-            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-            "offset": 1610612736,
-            "type": "types.peripherals.UART0"
-          },
-          "UART1": {
-            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-            "offset": 1610678272,
-            "type": "types.peripherals.UART0"
-          },
-          "UHCI0": {
-            "description": "Universal Host Controller Interface",
-            "offset": 1610694656,
-            "type": "types.peripherals.UHCI0"
-          },
-          "UHCI1": {
-            "description": "Universal Host Controller Interface",
-            "offset": 1610661888,
-            "type": "types.peripherals.UHCI0"
-          },
-          "USB_DEVICE": {
-            "description": "Full-speed USB Serial/JTAG Controller",
-            "offset": 1610887168,
-            "type": "types.peripherals.USB_DEVICE"
-          },
-          "XTS_AES": {
-            "description": "XTS-AES-128 Flash Encryption",
-            "offset": 1611448320,
-            "type": "types.peripherals.XTS_AES"
-          }
-        }
-      }
-    }
-  }
-}
\ No newline at end of file
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
deleted file mode 100644
index 8a632a0..0000000
--- a/src/chips/ESP32_C3.zig
+++ /dev/null
@@ -1,12378 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
-    pub const @"ESP32-C3" = struct {
-        pub const properties = struct {
-            pub const @"cpu.mpuPresent" = "false";
-            pub const @"cpu.nvicPrioBits" = "4";
-            pub const @"cpu.vendorSystickConfig" = "false";
-            pub const @"cpu.revision" = "r0p0";
-            pub const @"cpu.endian" = "little";
-            pub const license =
-                \\
-                \\    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
-                \\
-                \\    Licensed under the Apache License, Version 2.0 (the "License");
-                \\    you may not use this file except in compliance with the License.
-                \\    You may obtain a copy of the License at
-                \\
-                \\        http://www.apache.org/licenses/LICENSE-2.0
-                \\
-                \\    Unless required by applicable law or agreed to in writing, software
-                \\    distributed under the License is distributed on an "AS IS" BASIS,
-                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-                \\    See the License for the specific language governing permissions and
-                \\    limitations under the License.
-                \\
-            ;
-            pub const @"cpu.name" = "RV32IMC";
-            pub const @"cpu.fpuPresent" = "false";
-        };
-
-        pub const peripherals = struct {
-            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60000000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI1 = @as(*volatile types.peripherals.SPI1, @ptrFromInt(0x60002000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x60003000));
-            ///  General Purpose Input/Output
-            pub const GPIO = @as(*volatile types.peripherals.GPIO, @ptrFromInt(0x60004000));
-            ///  Sigma-Delta Modulation
-            pub const GPIOSD = @as(*volatile types.peripherals.GPIOSD, @ptrFromInt(0x60004f00));
-            ///  Real-Time Clock Control
-            pub const RTC_CNTL = @as(*volatile types.peripherals.RTC_CNTL, @ptrFromInt(0x60008000));
-            ///  eFuse Controller
-            pub const EFUSE = @as(*volatile types.peripherals.EFUSE, @ptrFromInt(0x60008800));
-            ///  Input/Output Multiplexer
-            pub const IO_MUX = @as(*volatile types.peripherals.IO_MUX, @ptrFromInt(0x60009000));
-            ///  Universal Host Controller Interface
-            pub const UHCI1 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x6000c000));
-            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60010000));
-            ///  I2C (Inter-Integrated Circuit) Controller
-            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x60013000));
-            ///  Universal Host Controller Interface
-            pub const UHCI0 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x60014000));
-            ///  Remote Control Peripheral
-            pub const RMT = @as(*volatile types.peripherals.RMT, @ptrFromInt(0x60016000));
-            ///  LED Control PWM (Pulse Width Modulation)
-            pub const LEDC = @as(*volatile types.peripherals.LEDC, @ptrFromInt(0x60019000));
-            ///  Timer Group
-            pub const TIMG0 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x6001f000));
-            ///  Timer Group
-            pub const TIMG1 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x60020000));
-            ///  System Timer
-            pub const SYSTIMER = @as(*volatile types.peripherals.SYSTIMER, @ptrFromInt(0x60023000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI2 = @as(*volatile types.peripherals.SPI2, @ptrFromInt(0x60024000));
-            ///  Advanced Peripheral Bus Controller
-            pub const APB_CTRL = @as(*volatile types.peripherals.APB_CTRL, @ptrFromInt(0x60026000));
-            ///  Hardware random number generator
-            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x60026000));
-            ///  Two-Wire Automotive Interface
-            pub const TWAI = @as(*volatile types.peripherals.TWAI, @ptrFromInt(0x6002b000));
-            ///  I2S (Inter-IC Sound) Controller
-            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x6002d000));
-            ///  AES (Advanced Encryption Standard) Accelerator
-            pub const AES = @as(*volatile types.peripherals.AES, @ptrFromInt(0x6003a000));
-            ///  SHA (Secure Hash Algorithm) Accelerator
-            pub const SHA = @as(*volatile types.peripherals.SHA, @ptrFromInt(0x6003b000));
-            ///  RSA (Rivest Shamir Adleman) Accelerator
-            pub const RSA = @as(*volatile types.peripherals.RSA, @ptrFromInt(0x6003c000));
-            ///  Digital Signature
-            pub const DS = @as(*volatile types.peripherals.DS, @ptrFromInt(0x6003d000));
-            ///  HMAC (Hash-based Message Authentication Code) Accelerator
-            pub const HMAC = @as(*volatile types.peripherals.HMAC, @ptrFromInt(0x6003e000));
-            ///  DMA (Direct Memory Access) Controller
-            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x6003f000));
-            ///  Successive Approximation Register Analog to Digital Converter
-            pub const APB_SARADC = @as(*volatile types.peripherals.APB_SARADC, @ptrFromInt(0x60040000));
-            ///  Full-speed USB Serial/JTAG Controller
-            pub const USB_DEVICE = @as(*volatile types.peripherals.USB_DEVICE, @ptrFromInt(0x60043000));
-            ///  System
-            pub const SYSTEM = @as(*volatile types.peripherals.SYSTEM, @ptrFromInt(0x600c0000));
-            ///  Sensitive
-            pub const SENSITIVE = @as(*volatile types.peripherals.SENSITIVE, @ptrFromInt(0x600c1000));
-            ///  Interrupt Core
-            pub const INTERRUPT_CORE0 = @as(*volatile types.peripherals.INTERRUPT_CORE0, @ptrFromInt(0x600c2000));
-            ///  External Memory
-            pub const EXTMEM = @as(*volatile types.peripherals.EXTMEM, @ptrFromInt(0x600c4000));
-            ///  XTS-AES-128 Flash Encryption
-            pub const XTS_AES = @as(*volatile types.peripherals.XTS_AES, @ptrFromInt(0x600cc000));
-            ///  Debug Assist
-            pub const ASSIST_DEBUG = @as(*volatile types.peripherals.ASSIST_DEBUG, @ptrFromInt(0x600ce000));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  AES (Advanced Encryption Standard) Accelerator
-        pub const AES = extern struct {
-            ///  Key material key_0 configure register
-            KEY_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_0 that is a part of key material.
-                KEY_0: u32,
-            }),
-            ///  Key material key_1 configure register
-            KEY_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_1 that is a part of key material.
-                KEY_1: u32,
-            }),
-            ///  Key material key_2 configure register
-            KEY_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_2 that is a part of key material.
-                KEY_2: u32,
-            }),
-            ///  Key material key_3 configure register
-            KEY_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_3 that is a part of key material.
-                KEY_3: u32,
-            }),
-            ///  Key material key_4 configure register
-            KEY_4: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_4 that is a part of key material.
-                KEY_4: u32,
-            }),
-            ///  Key material key_5 configure register
-            KEY_5: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_5 that is a part of key material.
-                KEY_5: u32,
-            }),
-            ///  Key material key_6 configure register
-            KEY_6: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_6 that is a part of key material.
-                KEY_6: u32,
-            }),
-            ///  Key material key_7 configure register
-            KEY_7: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_7 that is a part of key material.
-                KEY_7: u32,
-            }),
-            ///  source text material text_in_0 configure register
-            TEXT_IN_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_0 that is a part of source text material.
-                TEXT_IN_0: u32,
-            }),
-            ///  source text material text_in_1 configure register
-            TEXT_IN_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_1 that is a part of source text material.
-                TEXT_IN_1: u32,
-            }),
-            ///  source text material text_in_2 configure register
-            TEXT_IN_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_2 that is a part of source text material.
-                TEXT_IN_2: u32,
-            }),
-            ///  source text material text_in_3 configure register
-            TEXT_IN_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_3 that is a part of source text material.
-                TEXT_IN_3: u32,
-            }),
-            ///  result text material text_out_0 configure register
-            TEXT_OUT_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_0 that is a part of result text material.
-                TEXT_OUT_0: u32,
-            }),
-            ///  result text material text_out_1 configure register
-            TEXT_OUT_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_1 that is a part of result text material.
-                TEXT_OUT_1: u32,
-            }),
-            ///  result text material text_out_2 configure register
-            TEXT_OUT_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_2 that is a part of result text material.
-                TEXT_OUT_2: u32,
-            }),
-            ///  result text material text_out_3 configure register
-            TEXT_OUT_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_3 that is a part of result text material.
-                TEXT_OUT_3: u32,
-            }),
-            ///  AES Mode register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
-                MODE: u3,
-                padding: u29,
-            }),
-            ///  AES Endian configure register
-            ENDIAN: mmio.Mmio(packed struct(u32) {
-                ///  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian
-                ENDIAN: u6,
-                padding: u26,
-            }),
-            ///  AES trigger register
-            TRIGGER: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to start AES calculation.
-                TRIGGER: u1,
-                padding: u31,
-            }),
-            ///  AES state register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
-                STATE: u2,
-                padding: u30,
-            }),
-            ///  The memory that stores initialization vector
-            IV_MEM: [16]u8,
-            ///  The memory that stores GCM hash subkey
-            H_MEM: [16]u8,
-            ///  The memory that stores J0
-            J0_MEM: [16]u8,
-            ///  The memory that stores T0
-            T0_MEM: [16]u8,
-            ///  DMA-AES working mode register
-            DMA_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
-                DMA_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  AES cipher block mode register
-            BLOCK_MODE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
-                BLOCK_MODE: u3,
-                padding: u29,
-            }),
-            ///  AES block number register
-            BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of Plaintext/ciphertext block.
-                BLOCK_NUM: u32,
-            }),
-            ///  Standard incrementing function configure register
-            INC_SEL: mmio.Mmio(packed struct(u32) {
-                ///  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
-                INC_SEL: u1,
-                padding: u31,
-            }),
-            ///  Additional Authential Data block number register
-            AAD_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of AAD block.
-                AAD_BLOCK_NUM: u32,
-            }),
-            ///  AES remainder bit number register
-            REMAINDER_BIT_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of remainder bit.
-                REMAINDER_BIT_NUM: u7,
-                padding: u25,
-            }),
-            ///  AES continue register
-            CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to continue GCM operation.
-                CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  AES Interrupt clear register
-            INT_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the AES interrupt.
-                INT_CLEAR: u1,
-                padding: u31,
-            }),
-            ///  AES Interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
-                INT_ENA: u1,
-                padding: u31,
-            }),
-            ///  AES version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores the version information of AES.
-                DATE: u30,
-                padding: u2,
-            }),
-            ///  AES-DMA exit config
-            DMA_EXIT: mmio.Mmio(packed struct(u32) {
-                ///  Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
-                DMA_EXIT: u1,
-                padding: u31,
-            }),
-        };
-
-        ///  Advanced Peripheral Bus Controller
-        pub const APB_CTRL = extern struct {
-            ///  APB_CTRL_SYSCLK_CONF_REG
-            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_pre_div_cnt
-                PRE_DIV_CNT: u10,
-                ///  reg_clk_320m_en
-                CLK_320M_EN: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                ///  reg_rst_tick_cnt
-                RST_TICK_CNT: u1,
-                padding: u19,
-            }),
-            ///  APB_CTRL_TICK_CONF_REG
-            TICK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_xtal_tick_num
-                XTAL_TICK_NUM: u8,
-                ///  reg_ck8m_tick_num
-                CK8M_TICK_NUM: u8,
-                ///  reg_tick_enable
-                TICK_ENABLE: u1,
-                padding: u15,
-            }),
-            ///  APB_CTRL_CLK_OUT_EN_REG
-            CLK_OUT_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_clk20_oen
-                CLK20_OEN: u1,
-                ///  reg_clk22_oen
-                CLK22_OEN: u1,
-                ///  reg_clk44_oen
-                CLK44_OEN: u1,
-                ///  reg_clk_bb_oen
-                CLK_BB_OEN: u1,
-                ///  reg_clk80_oen
-                CLK80_OEN: u1,
-                ///  reg_clk160_oen
-                CLK160_OEN: u1,
-                ///  reg_clk_320m_oen
-                CLK_320M_OEN: u1,
-                ///  reg_clk_adc_inf_oen
-                CLK_ADC_INF_OEN: u1,
-                ///  reg_clk_dac_cpu_oen
-                CLK_DAC_CPU_OEN: u1,
-                ///  reg_clk40x_bb_oen
-                CLK40X_BB_OEN: u1,
-                ///  reg_clk_xtal_oen
-                CLK_XTAL_OEN: u1,
-                padding: u21,
-            }),
-            ///  APB_CTRL_WIFI_BB_CFG_REG
-            WIFI_BB_CFG: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_bb_cfg
-                WIFI_BB_CFG: u32,
-            }),
-            ///  APB_CTRL_WIFI_BB_CFG_2_REG
-            WIFI_BB_CFG_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_bb_cfg_2
-                WIFI_BB_CFG_2: u32,
-            }),
-            ///  APB_CTRL_WIFI_CLK_EN_REG
-            WIFI_CLK_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_clk_en
-                WIFI_CLK_EN: u32,
-            }),
-            ///  APB_CTRL_WIFI_RST_EN_REG
-            WIFI_RST_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_rst
-                WIFI_RST: u32,
-            }),
-            ///  APB_CTRL_HOST_INF_SEL_REG
-            HOST_INF_SEL: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_io_swap
-                PERI_IO_SWAP: u8,
-                padding: u24,
-            }),
-            ///  APB_CTRL_EXT_MEM_PMS_LOCK_REG
-            EXT_MEM_PMS_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  reg_ext_mem_pms_lock
-                EXT_MEM_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            reserved40: [4]u8,
-            ///  APB_CTRL_FLASH_ACE0_ATTR_REG
-            FLASH_ACE0_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_attr
-                FLASH_ACE0_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_ATTR_REG
-            FLASH_ACE1_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_attr
-                FLASH_ACE1_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_ATTR_REG
-            FLASH_ACE2_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_attr
-                FLASH_ACE2_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_ATTR_REG
-            FLASH_ACE3_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_attr
-                FLASH_ACE3_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE0_ADDR_REG
-            FLASH_ACE0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_ADDR_REG
-            FLASH_ACE1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_ADDR_REG
-            FLASH_ACE2_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_ADDR_REG
-            FLASH_ACE3_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE0_SIZE_REG
-            FLASH_ACE0_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_size
-                FLASH_ACE0_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_SIZE_REG
-            FLASH_ACE1_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_size
-                FLASH_ACE1_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_SIZE_REG
-            FLASH_ACE2_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_size
-                FLASH_ACE2_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_SIZE_REG
-            FLASH_ACE3_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_size
-                FLASH_ACE3_SIZE: u13,
-                padding: u19,
-            }),
-            reserved136: [48]u8,
-            ///  APB_CTRL_SPI_MEM_PMS_CTRL_REG
-            SPI_MEM_PMS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_spi_mem_reject_int
-                SPI_MEM_REJECT_INT: u1,
-                ///  reg_spi_mem_reject_clr
-                SPI_MEM_REJECT_CLR: u1,
-                ///  reg_spi_mem_reject_cde
-                SPI_MEM_REJECT_CDE: u5,
-                padding: u25,
-            }),
-            ///  APB_CTRL_SPI_MEM_REJECT_ADDR_REG
-            SPI_MEM_REJECT_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_spi_mem_reject_addr
-                SPI_MEM_REJECT_ADDR: u32,
-            }),
-            ///  APB_CTRL_SDIO_CTRL_REG
-            SDIO_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_sdio_win_access_en
-                SDIO_WIN_ACCESS_EN: u1,
-                padding: u31,
-            }),
-            ///  APB_CTRL_REDCY_SIG0_REG
-            REDCY_SIG0: mmio.Mmio(packed struct(u32) {
-                ///  reg_redcy_sig0
-                REDCY_SIG0: u31,
-                ///  reg_redcy_andor
-                REDCY_ANDOR: u1,
-            }),
-            ///  APB_CTRL_REDCY_SIG1_REG
-            REDCY_SIG1: mmio.Mmio(packed struct(u32) {
-                ///  reg_redcy_sig1
-                REDCY_SIG1: u31,
-                ///  reg_redcy_nandor
-                REDCY_NANDOR: u1,
-            }),
-            ///  APB_CTRL_FRONT_END_MEM_PD_REG
-            FRONT_END_MEM_PD: mmio.Mmio(packed struct(u32) {
-                ///  reg_agc_mem_force_pu
-                AGC_MEM_FORCE_PU: u1,
-                ///  reg_agc_mem_force_pd
-                AGC_MEM_FORCE_PD: u1,
-                ///  reg_pbus_mem_force_pu
-                PBUS_MEM_FORCE_PU: u1,
-                ///  reg_pbus_mem_force_pd
-                PBUS_MEM_FORCE_PD: u1,
-                ///  reg_dc_mem_force_pu
-                DC_MEM_FORCE_PU: u1,
-                ///  reg_dc_mem_force_pd
-                DC_MEM_FORCE_PD: u1,
-                padding: u26,
-            }),
-            ///  APB_CTRL_RETENTION_CTRL_REG
-            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_retention_link_addr
-                RETENTION_LINK_ADDR: u27,
-                ///  reg_nobypass_cpu_iso_rst
-                NOBYPASS_CPU_ISO_RST: u1,
-                padding: u4,
-            }),
-            ///  APB_CTRL_CLKGATE_FORCE_ON_REG
-            CLKGATE_FORCE_ON: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_clkgate_force_on
-                ROM_CLKGATE_FORCE_ON: u2,
-                ///  reg_sram_clkgate_force_on
-                SRAM_CLKGATE_FORCE_ON: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_MEM_POWER_DOWN_REG
-            MEM_POWER_DOWN: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_power_down
-                ROM_POWER_DOWN: u2,
-                ///  reg_sram_power_down
-                SRAM_POWER_DOWN: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_MEM_POWER_UP_REG
-            MEM_POWER_UP: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_power_up
-                ROM_POWER_UP: u2,
-                ///  reg_sram_power_up
-                SRAM_POWER_UP: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_RND_DATA_REG
-            RND_DATA: mmio.Mmio(packed struct(u32) {
-                ///  reg_rnd_data
-                RND_DATA: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_CONFIG_REG
-            PERI_BACKUP_CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_peri_backup_flow_err
-                PERI_BACKUP_FLOW_ERR: u2,
-                reserved4: u1,
-                ///  reg_peri_backup_burst_limit
-                PERI_BACKUP_BURST_LIMIT: u5,
-                ///  reg_peri_backup_tout_thres
-                PERI_BACKUP_TOUT_THRES: u10,
-                ///  reg_peri_backup_size
-                PERI_BACKUP_SIZE: u10,
-                ///  reg_peri_backup_start
-                PERI_BACKUP_START: u1,
-                ///  reg_peri_backup_to_mem
-                PERI_BACKUP_TO_MEM: u1,
-                ///  reg_peri_backup_ena
-                PERI_BACKUP_ENA: u1,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_APB_ADDR_REG
-            PERI_BACKUP_APB_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_backup_apb_start_addr
-                BACKUP_APB_START_ADDR: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
-            PERI_BACKUP_MEM_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_backup_mem_start_addr
-                BACKUP_MEM_START_ADDR: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_RAW_REG
-            PERI_BACKUP_INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_raw
-                PERI_BACKUP_DONE_INT_RAW: u1,
-                ///  reg_peri_backup_err_int_raw
-                PERI_BACKUP_ERR_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_ST_REG
-            PERI_BACKUP_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_st
-                PERI_BACKUP_DONE_INT_ST: u1,
-                ///  reg_peri_backup_err_int_st
-                PERI_BACKUP_ERR_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_ENA_REG
-            PERI_BACKUP_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_ena
-                PERI_BACKUP_DONE_INT_ENA: u1,
-                ///  reg_peri_backup_err_int_ena
-                PERI_BACKUP_ERR_INT_ENA: u1,
-                padding: u30,
-            }),
-            reserved208: [4]u8,
-            ///  APB_CTRL_PERI_BACKUP_INT_CLR_REG
-            PERI_BACKUP_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_clr
-                PERI_BACKUP_DONE_INT_CLR: u1,
-                ///  reg_peri_backup_err_int_clr
-                PERI_BACKUP_ERR_INT_CLR: u1,
-                padding: u30,
-            }),
-            reserved1020: [808]u8,
-            ///  APB_CTRL_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_dateVersion control
-                DATE: u32,
-            }),
-        };
-
-        ///  Successive Approximation Register Analog to Digital Converter
-        pub const APB_SARADC = extern struct {
-            ///  digital saradc configure register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  select software enable saradc sample
-                SARADC_START_FORCE: u1,
-                ///  software enable saradc sample
-                SARADC_START: u1,
-                reserved6: u4,
-                ///  SAR clock gated
-                SARADC_SAR_CLK_GATED: u1,
-                ///  SAR clock divider
-                SARADC_SAR_CLK_DIV: u8,
-                ///  0 ~ 15 means length 1 ~ 16
-                SARADC_SAR_PATT_LEN: u3,
-                reserved23: u5,
-                ///  clear the pointer of pattern table for DIG ADC1 CTRL
-                SARADC_SAR_PATT_P_CLEAR: u1,
-                reserved27: u3,
-                ///  force option to xpd sar blocks
-                SARADC_XPD_SAR_FORCE: u2,
-                reserved30: u1,
-                ///  wait arbit signal stable after sar_done
-                SARADC_WAIT_ARB_CYCLE: u2,
-            }),
-            ///  digital saradc configure register
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  enable max meas num
-                SARADC_MEAS_NUM_LIMIT: u1,
-                ///  max conversion number
-                SARADC_MAX_MEAS_NUM: u8,
-                ///  1: data to DIG ADC1 CTRL is inverted, otherwise not
-                SARADC_SAR1_INV: u1,
-                ///  1: data to DIG ADC2 CTRL is inverted, otherwise not
-                SARADC_SAR2_INV: u1,
-                reserved12: u1,
-                ///  to set saradc timer target
-                SARADC_TIMER_TARGET: u12,
-                ///  to enable saradc timer trigger
-                SARADC_TIMER_EN: u1,
-                padding: u7,
-            }),
-            ///  digital saradc configure register
-            FILTER_CTRL1: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  Factor of saradc filter1
-                APB_SARADC_FILTER_FACTOR1: u3,
-                ///  Factor of saradc filter0
-                APB_SARADC_FILTER_FACTOR0: u3,
-            }),
-            ///  digital saradc configure register
-            FSM_WAIT: mmio.Mmio(packed struct(u32) {
-                ///  saradc_xpd_wait
-                SARADC_XPD_WAIT: u8,
-                ///  saradc_rstb_wait
-                SARADC_RSTB_WAIT: u8,
-                ///  saradc_standby_wait
-                SARADC_STANDBY_WAIT: u8,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            SAR1_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc1 status about data and channel
-                SARADC_SAR1_STATUS: u32,
-            }),
-            ///  digital saradc configure register
-            SAR2_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc2 status about data and channel
-                SARADC_SAR2_STATUS: u32,
-            }),
-            ///  digital saradc configure register
-            SAR_PATT_TAB1: mmio.Mmio(packed struct(u32) {
-                ///  item 0 ~ 3 for pattern table 1 (each item one byte)
-                SARADC_SAR_PATT_TAB1: u24,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            SAR_PATT_TAB2: mmio.Mmio(packed struct(u32) {
-                ///  Item 4 ~ 7 for pattern table 1 (each item one byte)
-                SARADC_SAR_PATT_TAB2: u24,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            ONETIME_SAMPLE: mmio.Mmio(packed struct(u32) {
-                reserved23: u23,
-                ///  configure onetime atten
-                SARADC_ONETIME_ATTEN: u2,
-                ///  configure onetime channel
-                SARADC_ONETIME_CHANNEL: u4,
-                ///  trigger adc onetime sample
-                SARADC_ONETIME_START: u1,
-                ///  enable adc2 onetime sample
-                SARADC2_ONETIME_SAMPLE: u1,
-                ///  enable adc1 onetime sample
-                SARADC1_ONETIME_SAMPLE: u1,
-            }),
-            ///  digital saradc configure register
-            ARB_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  adc2 arbiter force to enableapb controller
-                ADC_ARB_APB_FORCE: u1,
-                ///  adc2 arbiter force to enable rtc controller
-                ADC_ARB_RTC_FORCE: u1,
-                ///  adc2 arbiter force to enable wifi controller
-                ADC_ARB_WIFI_FORCE: u1,
-                ///  adc2 arbiter force grant
-                ADC_ARB_GRANT_FORCE: u1,
-                ///  Set adc2 arbiterapb priority
-                ADC_ARB_APB_PRIORITY: u2,
-                ///  Set adc2 arbiter rtc priority
-                ADC_ARB_RTC_PRIORITY: u2,
-                ///  Set adc2 arbiter wifi priority
-                ADC_ARB_WIFI_PRIORITY: u2,
-                ///  adc2 arbiter uses fixed priority
-                ADC_ARB_FIX_PRIORITY: u1,
-                padding: u19,
-            }),
-            ///  digital saradc configure register
-            FILTER_CTRL0: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  configure filter1 to adc channel
-                APB_SARADC_FILTER_CHANNEL1: u4,
-                ///  configure filter0 to adc channel
-                APB_SARADC_FILTER_CHANNEL0: u4,
-                reserved31: u5,
-                ///  enable apb_adc1_filter
-                APB_SARADC_FILTER_RESET: u1,
-            }),
-            ///  digital saradc configure register
-            SAR1DATA_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc1 data
-                APB_SARADC1_DATA: u17,
-                padding: u15,
-            }),
-            ///  digital saradc configure register
-            SAR2DATA_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc2 data
-                APB_SARADC2_DATA: u17,
-                padding: u15,
-            }),
-            ///  digital saradc configure register
-            THRES0_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  configure thres0 to adc channel
-                APB_SARADC_THRES0_CHANNEL: u4,
-                reserved5: u1,
-                ///  saradc thres0 monitor thres
-                APB_SARADC_THRES0_HIGH: u13,
-                ///  saradc thres0 monitor thres
-                APB_SARADC_THRES0_LOW: u13,
-                padding: u1,
-            }),
-            ///  digital saradc configure register
-            THRES1_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  configure thres1 to adc channel
-                APB_SARADC_THRES1_CHANNEL: u4,
-                reserved5: u1,
-                ///  saradc thres1 monitor thres
-                APB_SARADC_THRES1_HIGH: u13,
-                ///  saradc thres1 monitor thres
-                APB_SARADC_THRES1_LOW: u13,
-                padding: u1,
-            }),
-            ///  digital saradc configure register
-            THRES_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  enable thres to all channel
-                APB_SARADC_THRES_ALL_EN: u1,
-                reserved30: u2,
-                ///  enable thres1
-                APB_SARADC_THRES1_EN: u1,
-                ///  enable thres0
-                APB_SARADC_THRES0_EN: u1,
-            }),
-            ///  digital saradc int register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt enable
-                APB_SARADC_THRES1_LOW_INT_ENA: u1,
-                ///  saradc thres0 low interrupt enable
-                APB_SARADC_THRES0_LOW_INT_ENA: u1,
-                ///  saradc thres1 high interrupt enable
-                APB_SARADC_THRES1_HIGH_INT_ENA: u1,
-                ///  saradc thres0 high interrupt enable
-                APB_SARADC_THRES0_HIGH_INT_ENA: u1,
-                ///  saradc2 done interrupt enable
-                APB_SARADC2_DONE_INT_ENA: u1,
-                ///  saradc1 done interrupt enable
-                APB_SARADC1_DONE_INT_ENA: u1,
-            }),
-            ///  digital saradc int register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt raw
-                APB_SARADC_THRES1_LOW_INT_RAW: u1,
-                ///  saradc thres0 low interrupt raw
-                APB_SARADC_THRES0_LOW_INT_RAW: u1,
-                ///  saradc thres1 high interrupt raw
-                APB_SARADC_THRES1_HIGH_INT_RAW: u1,
-                ///  saradc thres0 high interrupt raw
-                APB_SARADC_THRES0_HIGH_INT_RAW: u1,
-                ///  saradc2 done interrupt raw
-                APB_SARADC2_DONE_INT_RAW: u1,
-                ///  saradc1 done interrupt raw
-                APB_SARADC1_DONE_INT_RAW: u1,
-            }),
-            ///  digital saradc int register
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt state
-                APB_SARADC_THRES1_LOW_INT_ST: u1,
-                ///  saradc thres0 low interrupt state
-                APB_SARADC_THRES0_LOW_INT_ST: u1,
-                ///  saradc thres1 high interrupt state
-                APB_SARADC_THRES1_HIGH_INT_ST: u1,
-                ///  saradc thres0 high interrupt state
-                APB_SARADC_THRES0_HIGH_INT_ST: u1,
-                ///  saradc2 done interrupt state
-                APB_SARADC2_DONE_INT_ST: u1,
-                ///  saradc1 done interrupt state
-                APB_SARADC1_DONE_INT_ST: u1,
-            }),
-            ///  digital saradc int register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt clear
-                APB_SARADC_THRES1_LOW_INT_CLR: u1,
-                ///  saradc thres0 low interrupt clear
-                APB_SARADC_THRES0_LOW_INT_CLR: u1,
-                ///  saradc thres1 high interrupt clear
-                APB_SARADC_THRES1_HIGH_INT_CLR: u1,
-                ///  saradc thres0 high interrupt clear
-                APB_SARADC_THRES0_HIGH_INT_CLR: u1,
-                ///  saradc2 done interrupt clear
-                APB_SARADC2_DONE_INT_CLR: u1,
-                ///  saradc1 done interrupt clear
-                APB_SARADC1_DONE_INT_CLR: u1,
-            }),
-            ///  digital saradc configure register
-            DMA_CONF: mmio.Mmio(packed struct(u32) {
-                ///  the dma_in_suc_eof gen when sample cnt = spi_eof_num
-                APB_ADC_EOF_NUM: u16,
-                reserved30: u14,
-                ///  reset_apb_adc_state
-                APB_ADC_RESET_FSM: u1,
-                ///  enable apb_adc use spi_dma
-                APB_ADC_TRANS: u1,
-            }),
-            ///  digital saradc configure register
-            CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S clock divider value
-                CLKM_DIV_NUM: u8,
-                ///  Fractional clock divider numerator value
-                CLKM_DIV_B: u6,
-                ///  Fractional clock divider denominator value
-                CLKM_DIV_A: u6,
-                ///  reg clk en
-                CLK_EN: u1,
-                ///  Set this bit to enable clk_apll
-                CLK_SEL: u2,
-                padding: u9,
-            }),
-            ///  digital tsens configure register
-            APB_TSENS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  temperature sensor data out
-                TSENS_OUT: u8,
-                reserved13: u5,
-                ///  invert temperature sensor data
-                TSENS_IN_INV: u1,
-                ///  temperature sensor clock divider
-                TSENS_CLK_DIV: u8,
-                ///  temperature sensor power up
-                TSENS_PU: u1,
-                padding: u9,
-            }),
-            ///  digital tsens configure register
-            TSENS_CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  the time that power up tsens need wait
-                TSENS_XPD_WAIT: u12,
-                ///  force power up tsens
-                TSENS_XPD_FORCE: u2,
-                ///  inv tsens clk
-                TSENS_CLK_INV: u1,
-                ///  tsens clk select
-                TSENS_CLK_SEL: u1,
-                padding: u16,
-            }),
-            ///  digital saradc configure register
-            CALI: mmio.Mmio(packed struct(u32) {
-                ///  saradc cali factor
-                APB_SARADC_CALI_CFG: u17,
-                padding: u15,
-            }),
-            reserved1020: [920]u8,
-            ///  version
-            CTRL_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version
-                DATE: u32,
-            }),
-        };
-
-        ///  Debug Assist
-        pub const ASSIST_DEBUG = extern struct {
-            ///  ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
-            C0RE_0_MONTR_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_ena
-                CORE_0_AREA_DRAM0_0_RD_ENA: u1,
-                ///  reg_core_0_area_dram0_0_wr_ena
-                CORE_0_AREA_DRAM0_0_WR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_rd_ena
-                CORE_0_AREA_DRAM0_1_RD_ENA: u1,
-                ///  reg_core_0_area_dram0_1_wr_ena
-                CORE_0_AREA_DRAM0_1_WR_ENA: u1,
-                ///  reg_core_0_area_pif_0_rd_ena
-                CORE_0_AREA_PIF_0_RD_ENA: u1,
-                ///  reg_core_0_area_pif_0_wr_ena
-                CORE_0_AREA_PIF_0_WR_ENA: u1,
-                ///  reg_core_0_area_pif_1_rd_ena
-                CORE_0_AREA_PIF_1_RD_ENA: u1,
-                ///  reg_core_0_area_pif_1_wr_ena
-                CORE_0_AREA_PIF_1_WR_ENA: u1,
-                ///  reg_core_0_sp_spill_min_ena
-                CORE_0_SP_SPILL_MIN_ENA: u1,
-                ///  reg_core_0_sp_spill_max_ena
-                CORE_0_SP_SPILL_MAX_ENA: u1,
-                ///  reg_core_0_iram0_exception_monitor_ena
-                CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
-                ///  reg_core_0_dram0_exception_monitor_ena
-                CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_RAW_REG
-            CORE_0_INTR_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_raw
-                CORE_0_AREA_DRAM0_0_RD_RAW: u1,
-                ///  reg_core_0_area_dram0_0_wr_raw
-                CORE_0_AREA_DRAM0_0_WR_RAW: u1,
-                ///  reg_core_0_area_dram0_1_rd_raw
-                CORE_0_AREA_DRAM0_1_RD_RAW: u1,
-                ///  reg_core_0_area_dram0_1_wr_raw
-                CORE_0_AREA_DRAM0_1_WR_RAW: u1,
-                ///  reg_core_0_area_pif_0_rd_raw
-                CORE_0_AREA_PIF_0_RD_RAW: u1,
-                ///  reg_core_0_area_pif_0_wr_raw
-                CORE_0_AREA_PIF_0_WR_RAW: u1,
-                ///  reg_core_0_area_pif_1_rd_raw
-                CORE_0_AREA_PIF_1_RD_RAW: u1,
-                ///  reg_core_0_area_pif_1_wr_raw
-                CORE_0_AREA_PIF_1_WR_RAW: u1,
-                ///  reg_core_0_sp_spill_min_raw
-                CORE_0_SP_SPILL_MIN_RAW: u1,
-                ///  reg_core_0_sp_spill_max_raw
-                CORE_0_SP_SPILL_MAX_RAW: u1,
-                ///  reg_core_0_iram0_exception_monitor_raw
-                CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
-                ///  reg_core_0_dram0_exception_monitor_raw
-                CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
-            CORE_0_INTR_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_intr_ena
-                CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_0_wr_intr_ena
-                CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_rd_intr_ena
-                CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_wr_intr_ena
-                CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_0_rd_intr_ena
-                CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_0_wr_intr_ena
-                CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_1_rd_intr_ena
-                CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_1_wr_intr_ena
-                CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
-                ///  reg_core_0_sp_spill_min_intr_ena
-                CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
-                ///  reg_core_0_sp_spill_max_intr_ena
-                CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
-                ///  reg_core_0_iram0_exception_monitor_ena
-                CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
-                ///  reg_core_0_dram0_exception_monitor_ena
-                CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_CLR_REG
-            CORE_0_INTR_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_clr
-                CORE_0_AREA_DRAM0_0_RD_CLR: u1,
-                ///  reg_core_0_area_dram0_0_wr_clr
-                CORE_0_AREA_DRAM0_0_WR_CLR: u1,
-                ///  reg_core_0_area_dram0_1_rd_clr
-                CORE_0_AREA_DRAM0_1_RD_CLR: u1,
-                ///  reg_core_0_area_dram0_1_wr_clr
-                CORE_0_AREA_DRAM0_1_WR_CLR: u1,
-                ///  reg_core_0_area_pif_0_rd_clr
-                CORE_0_AREA_PIF_0_RD_CLR: u1,
-                ///  reg_core_0_area_pif_0_wr_clr
-                CORE_0_AREA_PIF_0_WR_CLR: u1,
-                ///  reg_core_0_area_pif_1_rd_clr
-                CORE_0_AREA_PIF_1_RD_CLR: u1,
-                ///  reg_core_0_area_pif_1_wr_clr
-                CORE_0_AREA_PIF_1_WR_CLR: u1,
-                ///  reg_core_0_sp_spill_min_clr
-                CORE_0_SP_SPILL_MIN_CLR: u1,
-                ///  reg_core_0_sp_spill_max_clr
-                CORE_0_SP_SPILL_MAX_CLR: u1,
-                ///  reg_core_0_iram0_exception_monitor_clr
-                CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
-                ///  reg_core_0_dram0_exception_monitor_clr
-                CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
-            CORE_0_AREA_DRAM0_0_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_min
-                CORE_0_AREA_DRAM0_0_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
-            CORE_0_AREA_DRAM0_0_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_max
-                CORE_0_AREA_DRAM0_0_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
-            CORE_0_AREA_DRAM0_1_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_1_min
-                CORE_0_AREA_DRAM0_1_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
-            CORE_0_AREA_DRAM0_1_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_1_max
-                CORE_0_AREA_DRAM0_1_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
-            CORE_0_AREA_PIF_0_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_0_min
-                CORE_0_AREA_PIF_0_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
-            CORE_0_AREA_PIF_0_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_0_max
-                CORE_0_AREA_PIF_0_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
-            CORE_0_AREA_PIF_1_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_1_min
-                CORE_0_AREA_PIF_1_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
-            CORE_0_AREA_PIF_1_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_1_max
-                CORE_0_AREA_PIF_1_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PC_REG
-            CORE_0_AREA_PC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pc
-                CORE_0_AREA_PC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_SP_REG
-            CORE_0_AREA_SP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_sp
-                CORE_0_AREA_SP: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_MIN_REG
-            CORE_0_SP_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_min
-                CORE_0_SP_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_MAX_REG
-            CORE_0_SP_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_max
-                CORE_0_SP_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_PC_REG
-            CORE_0_SP_PC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_pc
-                CORE_0_SP_PC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_EN_REG
-            CORE_0_RCD_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_recorden
-                CORE_0_RCD_RECORDEN: u1,
-                ///  reg_core_0_rcd_pdebugen
-                CORE_0_RCD_PDEBUGEN: u1,
-                padding: u30,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
-            CORE_0_RCD_PDEBUGPC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_pdebugpc
-                CORE_0_RCD_PDEBUGPC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-            CORE_0_RCD_PDEBUGSP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_pdebugsp
-                CORE_0_RCD_PDEBUGSP: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-            CORE_0_IRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_iram0_recording_addr_0
-                CORE_0_IRAM0_RECORDING_ADDR_0: u24,
-                ///  reg_core_0_iram0_recording_wr_0
-                CORE_0_IRAM0_RECORDING_WR_0: u1,
-                ///  reg_core_0_iram0_recording_loadstore_0
-                CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
-                padding: u6,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_IRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_iram0_recording_addr_1
-                CORE_0_IRAM0_RECORDING_ADDR_1: u24,
-                ///  reg_core_0_iram0_recording_wr_1
-                CORE_0_IRAM0_RECORDING_WR_1: u1,
-                ///  reg_core_0_iram0_recording_loadstore_1
-                CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
-                padding: u6,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_addr_0
-                CORE_0_DRAM0_RECORDING_ADDR_0: u24,
-                ///  reg_core_0_dram0_recording_wr_0
-                CORE_0_DRAM0_RECORDING_WR_0: u1,
-                ///  reg_core_0_dram0_recording_byteen_0
-                CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
-                padding: u3,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_pc_0
-                CORE_0_DRAM0_RECORDING_PC_0: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_addr_1
-                CORE_0_DRAM0_RECORDING_ADDR_1: u24,
-                ///  reg_core_0_dram0_recording_wr_1
-                CORE_0_DRAM0_RECORDING_WR_1: u1,
-                ///  reg_core_0_dram0_recording_byteen_1
-                CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
-                padding: u3,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_pc_1
-                CORE_0_DRAM0_RECORDING_PC_1: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
-            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_x_iram0_dram0_limit_cycle_0
-                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
-                padding: u12,
-            }),
-            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_x_iram0_dram0_limit_cycle_1
-                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
-                padding: u12,
-            }),
-            ///  ASSIST_DEBUG_LOG_SETTING
-            LOG_SETTING: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_ena
-                LOG_ENA: u3,
-                ///  reg_log_mode
-                LOG_MODE: u4,
-                ///  reg_log_mem_loop_enable
-                LOG_MEM_LOOP_ENABLE: u1,
-                padding: u24,
-            }),
-            ///  ASSIST_DEBUG_LOG_DATA_0_REG
-            LOG_DATA_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_data_0
-                LOG_DATA_0: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_DATA_MASK_REG
-            LOG_DATA_MASK: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_data_size
-                LOG_DATA_SIZE: u16,
-                padding: u16,
-            }),
-            ///  ASSIST_DEBUG_LOG_MIN_REG
-            LOG_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_min
-                LOG_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MAX_REG
-            LOG_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_max
-                LOG_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_START_REG
-            LOG_MEM_START: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_start
-                LOG_MEM_START: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_END_REG
-            LOG_MEM_END: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_end
-                LOG_MEM_END: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
-            LOG_MEM_WRITING_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_writing_addr
-                LOG_MEM_WRITING_ADDR: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
-            LOG_MEM_FULL_FLAG: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_full_flag
-                LOG_MEM_FULL_FLAG: u1,
-                ///  reg_clr_log_mem_full_flag
-                CLR_LOG_MEM_FULL_FLAG: u1,
-                padding: u30,
-            }),
-            ///  ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
-            C0RE_0_LASTPC_BEFORE_EXCEPTION: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_lastpc_before_exc
-                CORE_0_LASTPC_BEFORE_EXC: u32,
-            }),
-            ///  ASSIST_DEBUG_C0RE_0_DEBUG_MODE
-            C0RE_0_DEBUG_MODE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_debug_mode
-                CORE_0_DEBUG_MODE: u1,
-                ///  reg_core_0_debug_module_active
-                CORE_0_DEBUG_MODULE_ACTIVE: u1,
-                padding: u30,
-            }),
-            reserved508: [352]u8,
-            ///  ASSIST_DEBUG_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_assist_debug_date
-                ASSIST_DEBUG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  DMA (Direct Memory Access) Controller
-        pub const DMA = extern struct {
-            ///  DMA_INT_RAW_CH0_REG.
-            INT_RAW_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
-                IN_DONE_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
-                IN_SUC_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
-                OUT_DONE_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
-                OUT_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
-                IN_DSCR_ERR_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
-                OUT_DSCR_ERR_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
-                IN_DSCR_EMPTY_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
-                OUT_TOTAL_EOF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
-                INFIFO_OVF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
-                INFIFO_UDF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
-                OUTFIFO_OVF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
-                OUTFIFO_UDF_CH0_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH0_REG.
-            INT_ST_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH0_REG.
-            INT_ENA_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH0_REG.
-            INT_CLR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_CLR: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_RAW_CH1_REG.
-            INT_RAW_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
-                IN_DONE_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
-                IN_SUC_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
-                OUT_DONE_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
-                OUT_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
-                IN_DSCR_ERR_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
-                OUT_DSCR_ERR_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
-                IN_DSCR_EMPTY_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
-                OUT_TOTAL_EOF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
-                INFIFO_OVF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
-                INFIFO_UDF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
-                OUTFIFO_OVF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
-                OUTFIFO_UDF_CH1_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH1_REG.
-            INT_ST_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH1_REG.
-            INT_ENA_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH1_REG.
-            INT_CLR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_CLR: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_RAW_CH2_REG.
-            INT_RAW_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
-                IN_DONE_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
-                IN_SUC_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
-                OUT_DONE_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
-                OUT_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
-                IN_DSCR_ERR_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
-                OUT_DSCR_ERR_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
-                IN_DSCR_EMPTY_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
-                OUT_TOTAL_EOF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
-                INFIFO_OVF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
-                INFIFO_UDF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
-                OUTFIFO_OVF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
-                OUTFIFO_UDF_CH2_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH2_REG.
-            INT_ST_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH2_REG.
-            INT_ENA_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH2_REG.
-            INT_CLR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_CLR: u1,
-                padding: u19,
-            }),
-            reserved64: [16]u8,
-            ///  DMA_AHB_TEST_REG.
-            AHB_TEST: mmio.Mmio(packed struct(u32) {
-                ///  reserved
-                AHB_TESTMODE: u3,
-                reserved4: u1,
-                ///  reserved
-                AHB_TESTADDR: u2,
-                padding: u26,
-            }),
-            ///  DMA_MISC_CONF_REG.
-            MISC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit, then clear this bit to reset the internal ahb FSM.
-                AHBM_RST_INTER: u1,
-                reserved2: u1,
-                ///  Set this bit to disable priority arbitration function.
-                ARB_PRI_DIS: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                padding: u28,
-            }),
-            ///  DMA_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  register version.
-                DATE: u32,
-            }),
-            reserved112: [36]u8,
-            ///  DMA_IN_CONF0_CH0_REG.
-            IN_CONF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH0: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH0: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH0: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH0_REG.
-            IN_CONF1_CH0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH0_REG.
-            INFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 0.
-                INFIFO_FULL_CH0: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 0.
-                INFIFO_EMPTY_CH0: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
-                INFIFO_CNT_CH0: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH0: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH0: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH0_REG.
-            IN_POP_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH0: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH0_REG.
-            IN_LINK_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH0: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH0: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH0: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH0: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH0: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH0: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH0_REG.
-            IN_STATE_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH0: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH0: u2,
-                ///  reserved
-                IN_STATE_CH0: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
-            IN_SUC_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
-            IN_ERR_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_CH0_REG.
-            IN_DSCR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH0_REG.
-            IN_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH0_REG.
-            IN_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH0: u32,
-            }),
-            ///  DMA_IN_PRI_CH0_REG.
-            IN_PRI_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 0. The larger of the value, the higher of the priority.
-                RX_PRI_CH0: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH0_REG.
-            IN_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH0: u6,
-                padding: u26,
-            }),
-            reserved208: [44]u8,
-            ///  DMA_OUT_CONF0_CH0_REG.
-            OUT_CONF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH0: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH0: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH0: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH0: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH0_REG.
-            OUT_CONF1_CH0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH0_REG.
-            OUTFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 0.
-                OUTFIFO_FULL_CH0: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 0.
-                OUTFIFO_EMPTY_CH0: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
-                OUTFIFO_CNT_CH0: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH0: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH0_REG.
-            OUT_PUSH_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH0: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH0: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH0_REG.
-            OUT_LINK_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH0: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH0: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH0: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH0: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH0: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH0_REG.
-            OUT_STATE_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH0: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH0: u2,
-                ///  reserved
-                OUT_STATE_CH0: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH0_REG.
-            OUT_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
-            OUT_EOF_BFR_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH0_REG.
-            OUT_DSCR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH0_REG.
-            OUT_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH0_REG.
-            OUT_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH0: u32,
-            }),
-            ///  DMA_OUT_PRI_CH0_REG.
-            OUT_PRI_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 0. The larger of the value, the higher of the priority.
-                TX_PRI_CH0: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH0_REG.
-            OUT_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH0: u6,
-                padding: u26,
-            }),
-            reserved304: [44]u8,
-            ///  DMA_IN_CONF0_CH1_REG.
-            IN_CONF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH1: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH1: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH1: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH1_REG.
-            IN_CONF1_CH1: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH1_REG.
-            INFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 1.
-                INFIFO_FULL_CH1: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 1.
-                INFIFO_EMPTY_CH1: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
-                INFIFO_CNT_CH1: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH1: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH1: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH1_REG.
-            IN_POP_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH1: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH1_REG.
-            IN_LINK_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH1: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH1: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH1: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH1: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH1: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH1: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH1_REG.
-            IN_STATE_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH1: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH1: u2,
-                ///  reserved
-                IN_STATE_CH1: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
-            IN_SUC_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
-            IN_ERR_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_CH1_REG.
-            IN_DSCR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH1_REG.
-            IN_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH1_REG.
-            IN_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH1: u32,
-            }),
-            ///  DMA_IN_PRI_CH1_REG.
-            IN_PRI_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 1. The larger of the value, the higher of the priority.
-                RX_PRI_CH1: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH1_REG.
-            IN_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH1: u6,
-                padding: u26,
-            }),
-            reserved400: [44]u8,
-            ///  DMA_OUT_CONF0_CH1_REG.
-            OUT_CONF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH1: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH1: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH1: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH1: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH1_REG.
-            OUT_CONF1_CH1: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH1_REG.
-            OUTFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 1.
-                OUTFIFO_FULL_CH1: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 1.
-                OUTFIFO_EMPTY_CH1: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
-                OUTFIFO_CNT_CH1: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH1: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH1_REG.
-            OUT_PUSH_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH1: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH1: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH1_REG.
-            OUT_LINK_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH1: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH1: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH1: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH1: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH1: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH1_REG.
-            OUT_STATE_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH1: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH1: u2,
-                ///  reserved
-                OUT_STATE_CH1: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH1_REG.
-            OUT_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
-            OUT_EOF_BFR_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH1_REG.
-            OUT_DSCR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH1_REG.
-            OUT_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH1_REG.
-            OUT_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH1: u32,
-            }),
-            ///  DMA_OUT_PRI_CH1_REG.
-            OUT_PRI_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 1. The larger of the value, the higher of the priority.
-                TX_PRI_CH1: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH1_REG.
-            OUT_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH1: u6,
-                padding: u26,
-            }),
-            reserved496: [44]u8,
-            ///  DMA_IN_CONF0_CH2_REG.
-            IN_CONF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH2: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH2: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH2: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH2_REG.
-            IN_CONF1_CH2: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH2_REG.
-            INFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 2.
-                INFIFO_FULL_CH2: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 2.
-                INFIFO_EMPTY_CH2: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
-                INFIFO_CNT_CH2: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH2: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH2: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH2_REG.
-            IN_POP_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH2: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH2_REG.
-            IN_LINK_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH2: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH2: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH2: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH2: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH2: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH2: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH2_REG.
-            IN_STATE_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH2: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH2: u2,
-                ///  reserved
-                IN_STATE_CH2: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
-            IN_SUC_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
-            IN_ERR_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_CH2_REG.
-            IN_DSCR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH2_REG.
-            IN_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH2_REG.
-            IN_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH2: u32,
-            }),
-            ///  DMA_IN_PRI_CH2_REG.
-            IN_PRI_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 2. The larger of the value, the higher of the priority.
-                RX_PRI_CH2: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH2_REG.
-            IN_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH2: u6,
-                padding: u26,
-            }),
-            reserved592: [44]u8,
-            ///  DMA_OUT_CONF0_CH2_REG.
-            OUT_CONF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH2: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH2: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH2: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH2: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH2_REG.
-            OUT_CONF1_CH2: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH2_REG.
-            OUTFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 2.
-                OUTFIFO_FULL_CH2: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 2.
-                OUTFIFO_EMPTY_CH2: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
-                OUTFIFO_CNT_CH2: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH2: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH2_REG.
-            OUT_PUSH_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH2: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH2: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH2_REG.
-            OUT_LINK_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH2: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH2: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH2: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH2: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH2: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH2_REG.
-            OUT_STATE_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH2: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH2: u2,
-                ///  reserved
-                OUT_STATE_CH2: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH2_REG.
-            OUT_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
-            OUT_EOF_BFR_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH2_REG.
-            OUT_DSCR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH2_REG.
-            OUT_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH2_REG.
-            OUT_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH2: u32,
-            }),
-            ///  DMA_OUT_PRI_CH2_REG.
-            OUT_PRI_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 2. The larger of the value, the higher of the priority.
-                TX_PRI_CH2: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH2_REG.
-            OUT_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH2: u6,
-                padding: u26,
-            }),
-        };
-
-        ///  Digital Signature
-        pub const DS = extern struct {
-            ///  memory that stores Y
-            Y_MEM: [512]u8,
-            ///  memory that stores M
-            M_MEM: [512]u8,
-            ///  memory that stores Rb
-            RB_MEM: [512]u8,
-            ///  memory that stores BOX
-            BOX_MEM: [48]u8,
-            reserved2048: [464]u8,
-            ///  memory that stores X
-            X_MEM: [512]u8,
-            ///  memory that stores Z
-            Z_MEM: [512]u8,
-            reserved3584: [512]u8,
-            ///  DS start control register
-            SET_START: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to start DS operation.
-                SET_START: u1,
-                padding: u31,
-            }),
-            ///  DS continue control register
-            SET_CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to continue DS operation.
-                SET_CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  DS finish control register
-            SET_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to finish DS process.
-                SET_FINISH: u1,
-                padding: u31,
-            }),
-            ///  DS query busy register
-            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
-                ///  digital signature state. 1'b0: idle, 1'b1: busy
-                QUERY_BUSY: u1,
-                padding: u31,
-            }),
-            ///  DS query key-wrong counter register
-            QUERY_KEY_WRONG: mmio.Mmio(packed struct(u32) {
-                ///  digital signature key wrong counter
-                QUERY_KEY_WRONG: u4,
-                padding: u28,
-            }),
-            ///  DS query check result register
-            QUERY_CHECK: mmio.Mmio(packed struct(u32) {
-                ///  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
-                MD_ERROR: u1,
-                ///  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
-                PADDING_BAD: u1,
-                padding: u30,
-            }),
-            reserved3616: [8]u8,
-            ///  DS version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  ds version information
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  eFuse Controller
-        pub const EFUSE = extern struct {
-            ///  Register 0 that stores data to be programmed.
-            PGM_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 0th 32-bit data to be programmed.
-                PGM_DATA_0: u32,
-            }),
-            ///  Register 1 that stores data to be programmed.
-            PGM_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 1st 32-bit data to be programmed.
-                PGM_DATA_1: u32,
-            }),
-            ///  Register 2 that stores data to be programmed.
-            PGM_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 2nd 32-bit data to be programmed.
-                PGM_DATA_2: u32,
-            }),
-            ///  Register 3 that stores data to be programmed.
-            PGM_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 3rd 32-bit data to be programmed.
-                PGM_DATA_3: u32,
-            }),
-            ///  Register 4 that stores data to be programmed.
-            PGM_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 4th 32-bit data to be programmed.
-                PGM_DATA_4: u32,
-            }),
-            ///  Register 5 that stores data to be programmed.
-            PGM_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 5th 32-bit data to be programmed.
-                PGM_DATA_5: u32,
-            }),
-            ///  Register 6 that stores data to be programmed.
-            PGM_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 6th 32-bit data to be programmed.
-                PGM_DATA_6: u32,
-            }),
-            ///  Register 7 that stores data to be programmed.
-            PGM_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 7th 32-bit data to be programmed.
-                PGM_DATA_7: u32,
-            }),
-            ///  Register 0 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE0: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 0th 32-bit RS code to be programmed.
-                PGM_RS_DATA_0: u32,
-            }),
-            ///  Register 1 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE1: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 1st 32-bit RS code to be programmed.
-                PGM_RS_DATA_1: u32,
-            }),
-            ///  Register 2 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE2: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 2nd 32-bit RS code to be programmed.
-                PGM_RS_DATA_2: u32,
-            }),
-            ///  BLOCK0 data register 0.
-            RD_WR_DIS: mmio.Mmio(packed struct(u32) {
-                ///  Disable programming of individual eFuses.
-                WR_DIS: u32,
-            }),
-            ///  BLOCK0 data register 1.
-            RD_REPEAT_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to disable reading from BlOCK4-10.
-                RD_DIS: u7,
-                ///  Set this bit to disable boot from RTC RAM.
-                DIS_RTC_RAM_BOOT: u1,
-                ///  Set this bit to disable Icache.
-                DIS_ICACHE: u1,
-                ///  Set this bit to disable function of usb switch to jtag in module of usb device.
-                DIS_USB_JTAG: u1,
-                ///  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
-                DIS_DOWNLOAD_ICACHE: u1,
-                ///  Set this bit to disable usb device.
-                DIS_USB_DEVICE: u1,
-                ///  Set this bit to disable the function that forces chip into download mode.
-                DIS_FORCE_DOWNLOAD: u1,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED6: u1,
-                ///  Set this bit to disable CAN function.
-                DIS_CAN: u1,
-                ///  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-                JTAG_SEL_ENABLE: u1,
-                ///  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
-                SOFT_DIS_JTAG: u3,
-                ///  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-                DIS_PAD_JTAG: u1,
-                ///  Set this bit to disable flash encryption when in download boot modes.
-                DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
-                ///  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
-                USB_DREFH: u2,
-                ///  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
-                USB_DREFL: u2,
-                ///  Set this bit to exchange USB D+ and D- pins.
-                USB_EXCHG_PINS: u1,
-                ///  Set this bit to vdd spi pin function as gpio.
-                VDD_SPI_AS_GPIO: u1,
-                ///  Enable btlc gpio.
-                BTLC_GPIO_ENABLE: u2,
-                ///  Set this bit to enable power glitch function.
-                POWERGLITCH_EN: u1,
-                ///  Sample delay configuration of power glitch.
-                POWER_GLITCH_DSENSE: u2,
-            }),
-            ///  BLOCK0 data register 2.
-            RD_REPEAT_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED2: u16,
-                ///  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
-                WDT_DELAY_SEL: u2,
-                ///  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
-                SPI_BOOT_CRYPT_CNT: u3,
-                ///  Set this bit to enable revoking first secure boot key.
-                SECURE_BOOT_KEY_REVOKE0: u1,
-                ///  Set this bit to enable revoking second secure boot key.
-                SECURE_BOOT_KEY_REVOKE1: u1,
-                ///  Set this bit to enable revoking third secure boot key.
-                SECURE_BOOT_KEY_REVOKE2: u1,
-                ///  Purpose of Key0.
-                KEY_PURPOSE_0: u4,
-                ///  Purpose of Key1.
-                KEY_PURPOSE_1: u4,
-            }),
-            ///  BLOCK0 data register 3.
-            RD_REPEAT_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Purpose of Key2.
-                KEY_PURPOSE_2: u4,
-                ///  Purpose of Key3.
-                KEY_PURPOSE_3: u4,
-                ///  Purpose of Key4.
-                KEY_PURPOSE_4: u4,
-                ///  Purpose of Key5.
-                KEY_PURPOSE_5: u4,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED3: u4,
-                ///  Set this bit to enable secure boot.
-                SECURE_BOOT_EN: u1,
-                ///  Set this bit to enable revoking aggressive secure boot.
-                SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED0: u6,
-                ///  Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
-                FLASH_TPUW: u4,
-            }),
-            ///  BLOCK0 data register 4.
-            RD_REPEAT_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-                DIS_DOWNLOAD_MODE: u1,
-                ///  Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
-                DIS_LEGACY_SPI_BOOT: u1,
-                ///  Selectes the default UART print channel. 0: UART0. 1: UART1.
-                UART_PRINT_CHANNEL: u1,
-                ///  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
-                FLASH_ECC_MODE: u1,
-                ///  Set this bit to disable UART download mode through USB.
-                DIS_USB_DOWNLOAD_MODE: u1,
-                ///  Set this bit to enable secure UART download mode.
-                ENABLE_SECURITY_DOWNLOAD: u1,
-                ///  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-                UART_PRINT_CONTROL: u2,
-                ///  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-                PIN_POWER_SELECTION: u1,
-                ///  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-                FLASH_TYPE: u1,
-                ///  Set Flash page size.
-                FLASH_PAGE_SIZE: u2,
-                ///  Set 1 to enable ECC for flash boot.
-                FLASH_ECC_EN: u1,
-                ///  Set this bit to force ROM code to send a resume command during SPI boot.
-                FORCE_SEND_RESUME: u1,
-                ///  Secure version (used by ESP-IDF anti-rollback feature).
-                SECURE_VERSION: u16,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED1: u2,
-            }),
-            ///  BLOCK0 data register 5.
-            RD_REPEAT_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED4: u24,
-                padding: u8,
-            }),
-            ///  BLOCK1 data register 0.
-            RD_MAC_SPI_SYS_0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the low 32 bits of MAC address.
-                MAC_0: u32,
-            }),
-            ///  BLOCK1 data register 1.
-            RD_MAC_SPI_SYS_1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the high 16 bits of MAC address.
-                MAC_1: u16,
-                ///  Stores the zeroth part of SPI_PAD_CONF.
-                SPI_PAD_CONF_0: u16,
-            }),
-            ///  BLOCK1 data register 2.
-            RD_MAC_SPI_SYS_2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first part of SPI_PAD_CONF.
-                SPI_PAD_CONF_1: u32,
-            }),
-            ///  BLOCK1 data register 3.
-            RD_MAC_SPI_SYS_3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second part of SPI_PAD_CONF.
-                SPI_PAD_CONF_2: u18,
-                ///  Stores the fist 14 bits of the zeroth part of system data.
-                SYS_DATA_PART0_0: u14,
-            }),
-            ///  BLOCK1 data register 4.
-            RD_MAC_SPI_SYS_4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fist 32 bits of the zeroth part of system data.
-                SYS_DATA_PART0_1: u32,
-            }),
-            ///  BLOCK1 data register 5.
-            RD_MAC_SPI_SYS_5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of the zeroth part of system data.
-                SYS_DATA_PART0_2: u32,
-            }),
-            ///  Register 0 of BLOCK2 (system).
-            RD_SYS_PART1_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of the first part of system data.
-                SYS_DATA_PART1_0: u32,
-            }),
-            ///  Register 1 of BLOCK2 (system).
-            RD_SYS_PART1_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of the first part of system data.
-                SYS_DATA_PART1_1: u32,
-            }),
-            ///  Register 2 of BLOCK2 (system).
-            RD_SYS_PART1_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of the first part of system data.
-                SYS_DATA_PART1_2: u32,
-            }),
-            ///  Register 3 of BLOCK2 (system).
-            RD_SYS_PART1_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of the first part of system data.
-                SYS_DATA_PART1_3: u32,
-            }),
-            ///  Register 4 of BLOCK2 (system).
-            RD_SYS_PART1_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of the first part of system data.
-                SYS_DATA_PART1_4: u32,
-            }),
-            ///  Register 5 of BLOCK2 (system).
-            RD_SYS_PART1_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of the first part of system data.
-                SYS_DATA_PART1_5: u32,
-            }),
-            ///  Register 6 of BLOCK2 (system).
-            RD_SYS_PART1_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of the first part of system data.
-                SYS_DATA_PART1_6: u32,
-            }),
-            ///  Register 7 of BLOCK2 (system).
-            RD_SYS_PART1_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of the first part of system data.
-                SYS_DATA_PART1_7: u32,
-            }),
-            ///  Register 0 of BLOCK3 (user).
-            RD_USR_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of BLOCK3 (user).
-                USR_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK3 (user).
-            RD_USR_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of BLOCK3 (user).
-                USR_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK3 (user).
-            RD_USR_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of BLOCK3 (user).
-                USR_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK3 (user).
-            RD_USR_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of BLOCK3 (user).
-                USR_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK3 (user).
-            RD_USR_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of BLOCK3 (user).
-                USR_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK3 (user).
-            RD_USR_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of BLOCK3 (user).
-                USR_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK3 (user).
-            RD_USR_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of BLOCK3 (user).
-                USR_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK3 (user).
-            RD_USR_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of BLOCK3 (user).
-                USR_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK4 (KEY0).
-            RD_KEY0_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY0.
-                KEY0_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK4 (KEY0).
-            RD_KEY0_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY0.
-                KEY0_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK4 (KEY0).
-            RD_KEY0_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY0.
-                KEY0_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK4 (KEY0).
-            RD_KEY0_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY0.
-                KEY0_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK4 (KEY0).
-            RD_KEY0_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY0.
-                KEY0_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK4 (KEY0).
-            RD_KEY0_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY0.
-                KEY0_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK4 (KEY0).
-            RD_KEY0_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY0.
-                KEY0_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK4 (KEY0).
-            RD_KEY0_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY0.
-                KEY0_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK5 (KEY1).
-            RD_KEY1_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY1.
-                KEY1_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK5 (KEY1).
-            RD_KEY1_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY1.
-                KEY1_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK5 (KEY1).
-            RD_KEY1_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY1.
-                KEY1_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK5 (KEY1).
-            RD_KEY1_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY1.
-                KEY1_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK5 (KEY1).
-            RD_KEY1_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY1.
-                KEY1_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK5 (KEY1).
-            RD_KEY1_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY1.
-                KEY1_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK5 (KEY1).
-            RD_KEY1_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY1.
-                KEY1_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK5 (KEY1).
-            RD_KEY1_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY1.
-                KEY1_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK6 (KEY2).
-            RD_KEY2_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY2.
-                KEY2_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK6 (KEY2).
-            RD_KEY2_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY2.
-                KEY2_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK6 (KEY2).
-            RD_KEY2_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY2.
-                KEY2_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK6 (KEY2).
-            RD_KEY2_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY2.
-                KEY2_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK6 (KEY2).
-            RD_KEY2_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY2.
-                KEY2_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK6 (KEY2).
-            RD_KEY2_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY2.
-                KEY2_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK6 (KEY2).
-            RD_KEY2_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY2.
-                KEY2_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK6 (KEY2).
-            RD_KEY2_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY2.
-                KEY2_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK7 (KEY3).
-            RD_KEY3_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY3.
-                KEY3_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK7 (KEY3).
-            RD_KEY3_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY3.
-                KEY3_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK7 (KEY3).
-            RD_KEY3_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY3.
-                KEY3_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK7 (KEY3).
-            RD_KEY3_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY3.
-                KEY3_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK7 (KEY3).
-            RD_KEY3_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY3.
-                KEY3_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK7 (KEY3).
-            RD_KEY3_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY3.
-                KEY3_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK7 (KEY3).
-            RD_KEY3_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY3.
-                KEY3_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK7 (KEY3).
-            RD_KEY3_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY3.
-                KEY3_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK8 (KEY4).
-            RD_KEY4_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY4.
-                KEY4_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK8 (KEY4).
-            RD_KEY4_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY4.
-                KEY4_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK8 (KEY4).
-            RD_KEY4_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY4.
-                KEY4_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK8 (KEY4).
-            RD_KEY4_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY4.
-                KEY4_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK8 (KEY4).
-            RD_KEY4_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY4.
-                KEY4_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK8 (KEY4).
-            RD_KEY4_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY4.
-                KEY4_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK8 (KEY4).
-            RD_KEY4_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY4.
-                KEY4_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK8 (KEY4).
-            RD_KEY4_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY4.
-                KEY4_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK9 (KEY5).
-            RD_KEY5_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY5.
-                KEY5_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK9 (KEY5).
-            RD_KEY5_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY5.
-                KEY5_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK9 (KEY5).
-            RD_KEY5_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY5.
-                KEY5_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK9 (KEY5).
-            RD_KEY5_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY5.
-                KEY5_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK9 (KEY5).
-            RD_KEY5_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY5.
-                KEY5_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK9 (KEY5).
-            RD_KEY5_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY5.
-                KEY5_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK9 (KEY5).
-            RD_KEY5_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY5.
-                KEY5_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK9 (KEY5).
-            RD_KEY5_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY5.
-                KEY5_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK10 (system).
-            RD_SYS_PART2_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 0th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_0: u32,
-            }),
-            ///  Register 1 of BLOCK9 (KEY5).
-            RD_SYS_PART2_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 1st 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_1: u32,
-            }),
-            ///  Register 2 of BLOCK10 (system).
-            RD_SYS_PART2_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 2nd 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_2: u32,
-            }),
-            ///  Register 3 of BLOCK10 (system).
-            RD_SYS_PART2_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 3rd 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_3: u32,
-            }),
-            ///  Register 4 of BLOCK10 (system).
-            RD_SYS_PART2_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 4th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_4: u32,
-            }),
-            ///  Register 5 of BLOCK10 (system).
-            RD_SYS_PART2_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 5th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_5: u32,
-            }),
-            ///  Register 6 of BLOCK10 (system).
-            RD_SYS_PART2_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 6th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_6: u32,
-            }),
-            ///  Register 7 of BLOCK10 (system).
-            RD_SYS_PART2_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 7th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_7: u32,
-            }),
-            ///  Programming error record register 0 of BLOCK0.
-            RD_REPEAT_ERR0: mmio.Mmio(packed struct(u32) {
-                ///  If any bit in RD_DIS is 1, then it indicates a programming error.
-                RD_DIS_ERR: u7,
-                ///  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
-                DIS_RTC_RAM_BOOT_ERR: u1,
-                ///  If DIS_ICACHE is 1, then it indicates a programming error.
-                DIS_ICACHE_ERR: u1,
-                ///  If DIS_USB_JTAG is 1, then it indicates a programming error.
-                DIS_USB_JTAG_ERR: u1,
-                ///  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_ICACHE_ERR: u1,
-                ///  If DIS_USB_DEVICE is 1, then it indicates a programming error.
-                DIS_USB_DEVICE_ERR: u1,
-                ///  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
-                DIS_FORCE_DOWNLOAD_ERR: u1,
-                ///  Reserved.
-                RPT4_RESERVED6_ERR: u1,
-                ///  If DIS_CAN is 1, then it indicates a programming error.
-                DIS_CAN_ERR: u1,
-                ///  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
-                JTAG_SEL_ENABLE_ERR: u1,
-                ///  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
-                SOFT_DIS_JTAG_ERR: u3,
-                ///  If DIS_PAD_JTAG is 1, then it indicates a programming error.
-                DIS_PAD_JTAG_ERR: u1,
-                ///  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
-                ///  If any bit in USB_DREFH is 1, then it indicates a programming error.
-                USB_DREFH_ERR: u2,
-                ///  If any bit in USB_DREFL is 1, then it indicates a programming error.
-                USB_DREFL_ERR: u2,
-                ///  If USB_EXCHG_PINS is 1, then it indicates a programming error.
-                USB_EXCHG_PINS_ERR: u1,
-                ///  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
-                VDD_SPI_AS_GPIO_ERR: u1,
-                ///  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
-                BTLC_GPIO_ENABLE_ERR: u2,
-                ///  If POWERGLITCH_EN is 1, then it indicates a programming error.
-                POWERGLITCH_EN_ERR: u1,
-                ///  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
-                POWER_GLITCH_DSENSE_ERR: u2,
-            }),
-            ///  Programming error record register 1 of BLOCK0.
-            RD_REPEAT_ERR1: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RPT4_RESERVED2_ERR: u16,
-                ///  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-                WDT_DELAY_SEL_ERR: u2,
-                ///  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
-                SPI_BOOT_CRYPT_CNT_ERR: u3,
-                ///  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE0_ERR: u1,
-                ///  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE1_ERR: u1,
-                ///  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE2_ERR: u1,
-                ///  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
-                KEY_PURPOSE_0_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
-                KEY_PURPOSE_1_ERR: u4,
-            }),
-            ///  Programming error record register 2 of BLOCK0.
-            RD_REPEAT_ERR2: mmio.Mmio(packed struct(u32) {
-                ///  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
-                KEY_PURPOSE_2_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
-                KEY_PURPOSE_3_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
-                KEY_PURPOSE_4_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
-                KEY_PURPOSE_5_ERR: u4,
-                ///  Reserved.
-                RPT4_RESERVED3_ERR: u4,
-                ///  If SECURE_BOOT_EN is 1, then it indicates a programming error.
-                SECURE_BOOT_EN_ERR: u1,
-                ///  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
-                SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
-                ///  Reserved.
-                RPT4_RESERVED0_ERR: u6,
-                ///  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
-                FLASH_TPUW_ERR: u4,
-            }),
-            ///  Programming error record register 3 of BLOCK0.
-            RD_REPEAT_ERR3: mmio.Mmio(packed struct(u32) {
-                ///  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_MODE_ERR: u1,
-                ///  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
-                DIS_LEGACY_SPI_BOOT_ERR: u1,
-                ///  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
-                UART_PRINT_CHANNEL_ERR: u1,
-                ///  If FLASH_ECC_MODE is 1, then it indicates a programming error.
-                FLASH_ECC_MODE_ERR: u1,
-                ///  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
-                DIS_USB_DOWNLOAD_MODE_ERR: u1,
-                ///  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
-                ENABLE_SECURITY_DOWNLOAD_ERR: u1,
-                ///  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-                UART_PRINT_CONTROL_ERR: u2,
-                ///  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
-                PIN_POWER_SELECTION_ERR: u1,
-                ///  If FLASH_TYPE is 1, then it indicates a programming error.
-                FLASH_TYPE_ERR: u1,
-                ///  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
-                FLASH_PAGE_SIZE_ERR: u2,
-                ///  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
-                FLASH_ECC_EN_ERR: u1,
-                ///  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
-                FORCE_SEND_RESUME_ERR: u1,
-                ///  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
-                SECURE_VERSION_ERR: u16,
-                ///  Reserved.
-                RPT4_RESERVED1_ERR: u2,
-            }),
-            reserved400: [4]u8,
-            ///  Programming error record register 4 of BLOCK0.
-            RD_REPEAT_ERR4: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RPT4_RESERVED4_ERR: u24,
-                padding: u8,
-            }),
-            reserved448: [44]u8,
-            ///  Programming error record register 0 of BLOCK1-10.
-            RD_RS_ERR0: mmio.Mmio(packed struct(u32) {
-                ///  The value of this signal means the number of error bytes.
-                MAC_SPI_8M_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                MAC_SPI_8M_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                SYS_PART1_NUM: u3,
-                ///  0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                SYS_PART1_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                USR_DATA_ERR_NUM: u3,
-                ///  0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                USR_DATA_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY0_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
-                KEY0_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY1_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
-                KEY1_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY2_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
-                KEY2_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY3_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
-                KEY3_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY4_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
-                KEY4_FAIL: u1,
-            }),
-            ///  Programming error record register 1 of BLOCK1-10.
-            RD_RS_ERR1: mmio.Mmio(packed struct(u32) {
-                ///  The value of this signal means the number of error bytes.
-                KEY5_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                KEY5_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                SYS_PART2_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                SYS_PART2_FAIL: u1,
-                padding: u24,
-            }),
-            ///  eFuse clcok configuration register.
-            CLK: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to force eFuse SRAM into power-saving mode.
-                EFUSE_MEM_FORCE_PD: u1,
-                ///  Set this bit and force to activate clock signal of eFuse SRAM.
-                MEM_CLK_FORCE_ON: u1,
-                ///  Set this bit to force eFuse SRAM into working mode.
-                EFUSE_MEM_FORCE_PU: u1,
-                reserved16: u13,
-                ///  Set this bit and force to enable clock signal of eFuse memory.
-                EN: u1,
-                padding: u15,
-            }),
-            ///  eFuse operation mode configuraiton register;
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  0x5A5A: Operate programming command 0x5AA5: Operate read command.
-                OP_CODE: u16,
-                padding: u16,
-            }),
-            ///  eFuse status register.
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the state of the eFuse state machine.
-                STATE: u4,
-                ///  The value of OTP_LOAD_SW.
-                OTP_LOAD_SW: u1,
-                ///  The value of OTP_VDDQ_C_SYNC2.
-                OTP_VDDQ_C_SYNC2: u1,
-                ///  The value of OTP_STROBE_SW.
-                OTP_STROBE_SW: u1,
-                ///  The value of OTP_CSB_SW.
-                OTP_CSB_SW: u1,
-                ///  The value of OTP_PGENB_SW.
-                OTP_PGENB_SW: u1,
-                ///  The value of OTP_VDDQ_IS_SW.
-                OTP_VDDQ_IS_SW: u1,
-                ///  Indicates the number of error bits during programming BLOCK0.
-                REPEAT_ERR_CNT: u8,
-                padding: u14,
-            }),
-            ///  eFuse command register.
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to send read command.
-                READ_CMD: u1,
-                ///  Set this bit to send programming command.
-                PGM_CMD: u1,
-                ///  The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
-                BLK_NUM: u4,
-                padding: u26,
-            }),
-            ///  eFuse raw interrupt register.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw bit signal for read_done interrupt.
-                READ_DONE_INT_RAW: u1,
-                ///  The raw bit signal for pgm_done interrupt.
-                PGM_DONE_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt status register.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status signal for read_done interrupt.
-                READ_DONE_INT_ST: u1,
-                ///  The status signal for pgm_done interrupt.
-                PGM_DONE_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt enable register.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable signal for read_done interrupt.
-                READ_DONE_INT_ENA: u1,
-                ///  The enable signal for pgm_done interrupt.
-                PGM_DONE_INT_ENA: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt clear register.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear signal for read_done interrupt.
-                READ_DONE_INT_CLR: u1,
-                ///  The clear signal for pgm_done interrupt.
-                PGM_DONE_INT_CLR: u1,
-                padding: u30,
-            }),
-            ///  Controls the eFuse programming voltage.
-            DAC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Controls the division factor of the rising clock of the programming voltage.
-                DAC_CLK_DIV: u8,
-                ///  Don't care.
-                DAC_CLK_PAD_SEL: u1,
-                ///  Controls the rising period of the programming voltage.
-                DAC_NUM: u8,
-                ///  Reduces the power supply of the programming voltage.
-                OE_CLR: u1,
-                padding: u14,
-            }),
-            ///  Configures read timing parameters.
-            RD_TIM_CONF: mmio.Mmio(packed struct(u32) {
-                reserved24: u24,
-                ///  Configures the initial read time of eFuse.
-                READ_INIT_NUM: u8,
-            }),
-            ///  Configurarion register 1 of eFuse programming timing parameters.
-            WR_TIM_CONF1: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Configures the power up time for VDDQ.
-                PWR_ON_NUM: u16,
-                padding: u8,
-            }),
-            ///  Configurarion register 2 of eFuse programming timing parameters.
-            WR_TIM_CONF2: mmio.Mmio(packed struct(u32) {
-                ///  Configures the power outage time for VDDQ.
-                PWR_OFF_NUM: u16,
-                padding: u16,
-            }),
-            reserved508: [4]u8,
-            ///  eFuse version register.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Stores eFuse version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  External Memory
-        pub const EXTMEM = extern struct {
-            ///  This description will be updated in the near future.
-            ICACHE_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to activate the data cache. 0: disable, 1: enable
-                ICACHE_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable core0 ibus, 0: enable, 1: disable
-                ICACHE_SHUT_IBUS: u1,
-                ///  The bit is used to disable core1 ibus, 0: enable, 1: disable
-                ICACHE_SHUT_DBUS: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_TAG_POWER_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.
-                ICACHE_TAG_MEM_FORCE_ON: u1,
-                ///  The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down
-                ICACHE_TAG_MEM_FORCE_PD: u1,
-                ///  The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
-                ICACHE_TAG_MEM_FORCE_PU: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable the first section of prelock function.
-                ICACHE_PRELOCK_SCT0_EN: u1,
-                ///  The bit is used to enable the second section of prelock function.
-                ICACHE_PRELOCK_SCT1_EN: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
-                ICACHE_PRELOCK_SCT0_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
-                ICACHE_PRELOCK_SCT1_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
-                ICACHE_PRELOCK_SCT1_SIZE: u16,
-                ///  The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
-                ICACHE_PRELOCK_SCT0_SIZE: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
-                ICACHE_LOCK_ENA: u1,
-                ///  The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
-                ICACHE_UNLOCK_ENA: u1,
-                ///  The bit is used to indicate unlock/lock operation is finished.
-                ICACHE_LOCK_DONE: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
-                ICACHE_LOCK_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
-                ICACHE_LOCK_SIZE: u16,
-                padding: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
-                ICACHE_INVALIDATE_ENA: u1,
-                ///  The bit is used to indicate invalidate operation is finished.
-                ICACHE_SYNC_DONE: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
-                ICACHE_SYNC_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
-                ICACHE_SYNC_SIZE: u23,
-                padding: u9,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
-                ICACHE_PRELOAD_ENA: u1,
-                ///  The bit is used to indicate preload operation is finished.
-                ICACHE_PRELOAD_DONE: u1,
-                ///  The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
-                ICACHE_PRELOAD_ORDER: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
-                ICACHE_PRELOAD_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
-                ICACHE_PRELOAD_SIZE: u16,
-                padding: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to enable the first section for autoload operation.
-                ICACHE_AUTOLOAD_SCT0_ENA: u1,
-                ///  The bits are used to enable the second section for autoload operation.
-                ICACHE_AUTOLOAD_SCT1_ENA: u1,
-                ///  The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
-                ICACHE_AUTOLOAD_ENA: u1,
-                ///  The bit is used to indicate autoload operation is finished.
-                ICACHE_AUTOLOAD_DONE: u1,
-                ///  The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
-                ICACHE_AUTOLOAD_ORDER: u1,
-                ///  The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
-                ICACHE_AUTOLOAD_RQST: u2,
-                padding: u25,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
-                ICACHE_AUTOLOAD_SCT0_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT0_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
-                ICACHE_AUTOLOAD_SCT0_SIZE: u27,
-                padding: u5,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
-                ICACHE_AUTOLOAD_SCT1_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT1_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
-                ICACHE_AUTOLOAD_SCT1_SIZE: u27,
-                padding: u5,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
-                IBUS_TO_FLASH_START_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
-                IBUS_TO_FLASH_END_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
-                DBUS_TO_FLASH_START_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
-                DBUS_TO_FLASH_END_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ACS_CNT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear ibus counter.
-                IBUS_ACS_CNT_CLR: u1,
-                ///  The bit is used to clear dbus counter.
-                DBUS_ACS_CNT_CLR: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_ACS_MISS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of the cache miss caused by ibus access flash.
-                IBUS_ACS_MISS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of ibus access flash through icache.
-                IBUS_ACS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_ACS_FLASH_MISS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of the cache miss caused by dbus access flash.
-                DBUS_ACS_FLASH_MISS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of dbus access flash through icache.
-                DBUS_ACS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
-                reserved5: u3,
-                ///  The bit is used to enable interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_INT_ENA: u1,
-                reserved7: u1,
-                ///  The bit is used to enable interrupt by ibus counter overflow.
-                IBUS_CNT_OVF_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by dbus counter overflow.
-                DBUS_CNT_OVF_INT_ENA: u1,
-                padding: u23,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
-                reserved5: u3,
-                ///  The bit is used to clear interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_INT_CLR: u1,
-                reserved7: u1,
-                ///  The bit is used to clear interrupt by ibus counter overflow.
-                IBUS_CNT_OVF_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by dbus counter overflow.
-                DBUS_CNT_OVF_INT_CLR: u1,
-                padding: u23,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_ST: u1,
-                ///  The bit is used to indicate interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_ST: u1,
-                reserved5: u3,
-                ///  The bit is used to indicate interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_ST: u1,
-                reserved7: u1,
-                ///  The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
-                IBUS_ACS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
-                IBUS_ACS_MISS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
-                DBUS_ACS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus access flash miss counter overflow.
-                DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
-                padding: u21,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by authentication fail.
-                CORE0_IBUS_REJECT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by authentication fail.
-                CORE0_DBUS_REJECT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_IC_INT_ENA: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by authentication fail.
-                CORE0_IBUS_REJECT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by authentication fail.
-                CORE0_DBUS_REJECT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_IC_INT_CLR: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by authentication fail.
-                CORE0_IBUS_REJECT_ST: u1,
-                ///  The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by authentication fail.
-                CORE0_DBUS_REJECT_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_ICACHE_ST: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_DBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
-                CORE0_DBUS_ATTR: u3,
-                ///  The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
-                CORE0_DBUS_WORLD: u1,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_DBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
-                CORE0_DBUS_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_IBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
-                CORE0_IBUS_ATTR: u3,
-                ///  The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
-                CORE0_IBUS_WORLD: u1,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_IBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address of CPU access ibus when authentication fail.
-                CORE0_IBUS_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_FAULT_CONTENT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the content of mmu entry which cause mmu fault..
-                CACHE_MMU_FAULT_CONTENT: u10,
-                ///  The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
-                CACHE_MMU_FAULT_CODE: u4,
-                padding: u18,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_FAULT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address which cause mmu fault..
-                CACHE_MMU_FAULT_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_WRAP_AROUND_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable wrap around mode when read data from flash.
-                CACHE_FLASH_WRAP_AROUND: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_POWER_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
-                CACHE_MMU_MEM_FORCE_ON: u1,
-                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
-                CACHE_MMU_MEM_FORCE_PD: u1,
-                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
-                CACHE_MMU_MEM_FORCE_PU: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_STATE: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
-                ICACHE_STATE: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RECORD_DISABLE_DB_ENCRYPT: u1,
-                ///  Reserved.
-                RECORD_DISABLE_G0CB_DECRYPT: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_MANUAL_CRYPT: u1,
-                ///  The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_AUTO_CRYPT: u1,
-                ///  The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_CRYPT: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_PRELOAD_INT_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_ST: u1,
-                ///  The bit is used to enable the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_ENA: u1,
-                ///  The bit is used to clear the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_SYNC_INT_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate the interrupt by icache sync done.
-                ICACHE_SYNC_INT_ST: u1,
-                ///  The bit is used to enable the interrupt by icache sync done.
-                ICACHE_SYNC_INT_ENA: u1,
-                ///  The bit is used to clear the interrupt by icache sync done.
-                ICACHE_SYNC_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_OWNER: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
-                CACHE_MMU_OWNER: u4,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_CONF_MISC: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable checking mmu entry fault by preload operation.
-                CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
-                ///  The bit is used to disable checking mmu entry fault by sync operation.
-                CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
-                ///  The bit is used to enable cache trace function.
-                CACHE_TRACE_ENA: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_FREEZE: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable icache freeze mode
-                ENA: u1,
-                ///  The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
-                MODE: u1,
-                ///  The bit is used to indicate icache freeze success
-                DONE: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_ATOMIC_OPERATE_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
-                ICACHE_ATOMIC_OPERATE_ENA: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_REQUEST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable request recording which could cause performance issue
-                BYPASS: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                IBUS_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                IBUS_PMS_BOUNDARY0: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary1
-                IBUS_PMS_BOUNDARY1: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary2
-                IBUS_PMS_BOUNDARY2: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
-                IBUS_PMS_SCT1_ATTR: u4,
-                ///  The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
-                IBUS_PMS_SCT2_ATTR: u4,
-                padding: u24,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                DBUS_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary0
-                DBUS_PMS_BOUNDARY0: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary1
-                DBUS_PMS_BOUNDARY1: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary2
-                DBUS_PMS_BOUNDARY2: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
-                DBUS_PMS_SCT1_ATTR: u2,
-                ///  The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
-                DBUS_PMS_SCT2_ATTR: u2,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  clock gate enable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1020: [760]u8,
-            ///  This description will be updated in the near future.
-            REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version information
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  General Purpose Input/Output
-        pub const GPIO = extern struct {
-            ///  GPIO bit select register
-            BT_SELECT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO bit select register
-                BT_SEL: u32,
-            }),
-            ///  GPIO output register
-            OUT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output register for GPIO0-25
-                DATA_ORIG: u26,
-                padding: u6,
-            }),
-            ///  GPIO output set register
-            OUT_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output set register for GPIO0-25
-                OUT_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO output clear register
-            OUT_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output clear register for GPIO0-25
-                OUT_W1TC: u26,
-                padding: u6,
-            }),
-            reserved28: [12]u8,
-            ///  GPIO sdio select register
-            SDIO_SELECT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO sdio select register
-                SDIO_SEL: u8,
-                padding: u24,
-            }),
-            ///  GPIO output enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable register for GPIO0-25
-                DATA: u26,
-                padding: u6,
-            }),
-            ///  GPIO output enable set register
-            ENABLE_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable set register for GPIO0-25
-                ENABLE_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO output enable clear register
-            ENABLE_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable clear register for GPIO0-25
-                ENABLE_W1TC: u26,
-                padding: u6,
-            }),
-            reserved56: [12]u8,
-            ///  pad strapping register
-            STRAP: mmio.Mmio(packed struct(u32) {
-                ///  pad strapping register
-                STRAPPING: u16,
-                padding: u16,
-            }),
-            ///  GPIO input register
-            IN: mmio.Mmio(packed struct(u32) {
-                ///  GPIO input register for GPIO0-25
-                DATA_NEXT: u26,
-                padding: u6,
-            }),
-            reserved68: [4]u8,
-            ///  GPIO interrupt status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status register for GPIO0-25
-                INTERRUPT: u26,
-                padding: u6,
-            }),
-            ///  GPIO interrupt status set register
-            STATUS_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status set register for GPIO0-25
-                STATUS_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO interrupt status clear register
-            STATUS_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status clear register for GPIO0-25
-                STATUS_W1TC: u26,
-                padding: u6,
-            }),
-            reserved92: [12]u8,
-            ///  GPIO PRO_CPU interrupt status register
-            PCPU_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO PRO_CPU interrupt status register for GPIO0-25
-                PROCPU_INT: u26,
-                padding: u6,
-            }),
-            ///  GPIO PRO_CPU(not shielded) interrupt status register
-            PCPU_NMI_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
-                PROCPU_NMI_INT: u26,
-                padding: u6,
-            }),
-            ///  GPIO CPUSDIO interrupt status register
-            CPUSDIO_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO CPUSDIO interrupt status register for GPIO0-25
-                SDIO_INT: u26,
-                padding: u6,
-            }),
-            reserved116: [12]u8,
-            ///  GPIO pin configuration register
-            PIN: [26]mmio.Mmio(packed struct(u32) {
-                ///  set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
-                PIN_SYNC2_BYPASS: u2,
-                ///  set this bit to select pad driver. 1:open-drain. :normal.
-                PIN_PAD_DRIVER: u1,
-                ///  set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
-                PIN_SYNC1_BYPASS: u2,
-                reserved7: u2,
-                ///  set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
-                PIN_INT_TYPE: u3,
-                ///  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-                PIN_WAKEUP_ENABLE: u1,
-                ///  reserved
-                PIN_CONFIG: u2,
-                ///  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
-                PIN_INT_ENA: u5,
-                padding: u14,
-            }),
-            reserved332: [112]u8,
-            ///  GPIO interrupt source register
-            STATUS_NEXT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt source register for GPIO0-25
-                STATUS_INTERRUPT_NEXT: u26,
-                padding: u6,
-            }),
-            reserved340: [4]u8,
-            ///  GPIO input function configuration register
-            FUNC_IN_SEL_CFG: [128]mmio.Mmio(packed struct(u32) {
-                ///  set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
-                IN_SEL: u5,
-                ///  set this bit to invert input signal. 1:invert. :not invert.
-                IN_INV_SEL: u1,
-                ///  set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-                SEL: u1,
-                padding: u25,
-            }),
-            reserved1364: [512]u8,
-            ///  GPIO output function select register
-            FUNC_OUT_SEL_CFG: [26]mmio.Mmio(packed struct(u32) {
-                ///  The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
-                OUT_SEL: u8,
-                ///  set this bit to invert output signal.1:invert.:not invert.
-                INV_SEL: u1,
-                ///  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
-                OEN_SEL: u1,
-                ///  set this bit to invert output enable signal.1:invert.:not invert.
-                OEN_INV_SEL: u1,
-                padding: u21,
-            }),
-            reserved1580: [112]u8,
-            ///  GPIO clock gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to enable GPIO clock gate
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1788: [204]u8,
-            ///  GPIO version register
-            REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version register
-                REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Sigma-Delta Modulation
-        pub const GPIOSD = extern struct {
-            ///  Duty Cycle Configure Register of SDM%s
-            SIGMADELTA: [4]mmio.Mmio(packed struct(u32) {
-                ///  This field is used to configure the duty cycle of sigma delta modulation output.
-                SD0_IN: u8,
-                ///  This field is used to set a divider value to divide APB clock.
-                SD0_PRESCALE: u8,
-                padding: u16,
-            }),
-            reserved32: [16]u8,
-            ///  Clock Gating Configure Register
-            SIGMADELTA_CG: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  Clock enable bit of configuration registers for sigma delta modulation.
-                CLK_EN: u1,
-            }),
-            ///  MISC Register
-            SIGMADELTA_MISC: mmio.Mmio(packed struct(u32) {
-                reserved30: u30,
-                ///  Clock enable bit of sigma delta modulation.
-                FUNCTION_CLK_EN: u1,
-                ///  Reserved.
-                SPI_SWAP: u1,
-            }),
-            ///  Version Control Register
-            SIGMADELTA_VERSION: mmio.Mmio(packed struct(u32) {
-                ///  Version control register.
-                GPIO_SD_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  HMAC (Hash-based Message Authentication Code) Accelerator
-        pub const HMAC = extern struct {
-            reserved64: [64]u8,
-            ///  Process control register 0.
-            SET_START: mmio.Mmio(packed struct(u32) {
-                ///  Start hmac operation.
-                SET_START: u1,
-                padding: u31,
-            }),
-            ///  Configure purpose.
-            SET_PARA_PURPOSE: mmio.Mmio(packed struct(u32) {
-                ///  Set hmac parameter purpose.
-                PURPOSE_SET: u4,
-                padding: u28,
-            }),
-            ///  Configure key.
-            SET_PARA_KEY: mmio.Mmio(packed struct(u32) {
-                ///  Set hmac parameter key.
-                KEY_SET: u3,
-                padding: u29,
-            }),
-            ///  Finish initial configuration.
-            SET_PARA_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  Finish hmac configuration.
-                SET_PARA_END: u1,
-                padding: u31,
-            }),
-            ///  Process control register 1.
-            SET_MESSAGE_ONE: mmio.Mmio(packed struct(u32) {
-                ///  Call SHA to calculate one message block.
-                SET_TEXT_ONE: u1,
-                padding: u31,
-            }),
-            ///  Process control register 2.
-            SET_MESSAGE_ING: mmio.Mmio(packed struct(u32) {
-                ///  Continue typical hmac.
-                SET_TEXT_ING: u1,
-                padding: u31,
-            }),
-            ///  Process control register 3.
-            SET_MESSAGE_END: mmio.Mmio(packed struct(u32) {
-                ///  Start hardware padding.
-                SET_TEXT_END: u1,
-                padding: u31,
-            }),
-            ///  Process control register 4.
-            SET_RESULT_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  After read result from upstream, then let hmac back to idle.
-                SET_RESULT_END: u1,
-                padding: u31,
-            }),
-            ///  Invalidate register 0.
-            SET_INVALIDATE_JTAG: mmio.Mmio(packed struct(u32) {
-                ///  Clear result from hmac downstream JTAG.
-                SET_INVALIDATE_JTAG: u1,
-                padding: u31,
-            }),
-            ///  Invalidate register 1.
-            SET_INVALIDATE_DS: mmio.Mmio(packed struct(u32) {
-                ///  Clear result from hmac downstream DS.
-                SET_INVALIDATE_DS: u1,
-                padding: u31,
-            }),
-            ///  Error register.
-            QUERY_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  Hmac configuration state. 0: key are agree with purpose. 1: error
-                QUREY_CHECK: u1,
-                padding: u31,
-            }),
-            ///  Busy register.
-            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
-                ///  Hmac state. 1'b0: idle. 1'b1: busy
-                BUSY_STATE: u1,
-                padding: u31,
-            }),
-            reserved128: [16]u8,
-            ///  Message block memory.
-            WR_MESSAGE_MEM: [64]u8,
-            ///  Result from upstream.
-            RD_RESULT_MEM: [32]u8,
-            reserved240: [16]u8,
-            ///  Process control register 5.
-            SET_MESSAGE_PAD: mmio.Mmio(packed struct(u32) {
-                ///  Start software padding.
-                SET_TEXT_PAD: u1,
-                padding: u31,
-            }),
-            ///  Process control register 6.
-            ONE_BLOCK: mmio.Mmio(packed struct(u32) {
-                ///  Don't have to do padding.
-                SET_ONE_BLOCK: u1,
-                padding: u31,
-            }),
-            ///  Jtag register 0.
-            SOFT_JTAG_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Turn on JTAG verification.
-                SOFT_JTAG_CTRL: u1,
-                padding: u31,
-            }),
-            ///  Jtag register 1.
-            WR_JTAG: mmio.Mmio(packed struct(u32) {
-                ///  32-bit of key to be compared.
-                WR_JTAG: u32,
-            }),
-        };
-
-        ///  I2C (Inter-Integrated Circuit) Controller
-        pub const I2C0 = extern struct {
-            ///  I2C_SCL_LOW_PERIOD_REG
-            SCL_LOW_PERIOD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_low_period
-                SCL_LOW_PERIOD: u9,
-                padding: u23,
-            }),
-            ///  I2C_CTR_REG
-            CTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_force_out
-                SDA_FORCE_OUT: u1,
-                ///  reg_scl_force_out
-                SCL_FORCE_OUT: u1,
-                ///  reg_sample_scl_level
-                SAMPLE_SCL_LEVEL: u1,
-                ///  reg_rx_full_ack_level
-                RX_FULL_ACK_LEVEL: u1,
-                ///  reg_ms_mode
-                MS_MODE: u1,
-                ///  reg_trans_start
-                TRANS_START: u1,
-                ///  reg_tx_lsb_first
-                TX_LSB_FIRST: u1,
-                ///  reg_rx_lsb_first
-                RX_LSB_FIRST: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                ///  reg_arbitration_en
-                ARBITRATION_EN: u1,
-                ///  reg_fsm_rst
-                FSM_RST: u1,
-                ///  reg_conf_upgate
-                CONF_UPGATE: u1,
-                ///  reg_slv_tx_auto_start_en
-                SLV_TX_AUTO_START_EN: u1,
-                ///  reg_addr_10bit_rw_check_en
-                ADDR_10BIT_RW_CHECK_EN: u1,
-                ///  reg_addr_broadcasting_en
-                ADDR_BROADCASTING_EN: u1,
-                padding: u17,
-            }),
-            ///  I2C_SR_REG
-            SR: mmio.Mmio(packed struct(u32) {
-                ///  reg_resp_rec
-                RESP_REC: u1,
-                ///  reg_slave_rw
-                SLAVE_RW: u1,
-                reserved3: u1,
-                ///  reg_arb_lost
-                ARB_LOST: u1,
-                ///  reg_bus_busy
-                BUS_BUSY: u1,
-                ///  reg_slave_addressed
-                SLAVE_ADDRESSED: u1,
-                reserved8: u2,
-                ///  reg_rxfifo_cnt
-                RXFIFO_CNT: u6,
-                ///  reg_stretch_cause
-                STRETCH_CAUSE: u2,
-                reserved18: u2,
-                ///  reg_txfifo_cnt
-                TXFIFO_CNT: u6,
-                ///  reg_scl_main_state_last
-                SCL_MAIN_STATE_LAST: u3,
-                reserved28: u1,
-                ///  reg_scl_state_last
-                SCL_STATE_LAST: u3,
-                padding: u1,
-            }),
-            ///  I2C_TO_REG
-            TO: mmio.Mmio(packed struct(u32) {
-                ///  reg_time_out_value
-                TIME_OUT_VALUE: u5,
-                ///  reg_time_out_en
-                TIME_OUT_EN: u1,
-                padding: u26,
-            }),
-            ///  I2C_SLAVE_ADDR_REG
-            SLAVE_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_slave_addr
-                SLAVE_ADDR: u15,
-                reserved31: u16,
-                ///  reg_addr_10bit_en
-                ADDR_10BIT_EN: u1,
-            }),
-            ///  I2C_FIFO_ST_REG
-            FIFO_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_raddr
-                RXFIFO_RADDR: u5,
-                ///  reg_rxfifo_waddr
-                RXFIFO_WADDR: u5,
-                ///  reg_txfifo_raddr
-                TXFIFO_RADDR: u5,
-                ///  reg_txfifo_waddr
-                TXFIFO_WADDR: u5,
-                reserved22: u2,
-                ///  reg_slave_rw_point
-                SLAVE_RW_POINT: u8,
-                padding: u2,
-            }),
-            ///  I2C_FIFO_CONF_REG
-            FIFO_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_thrhd
-                RXFIFO_WM_THRHD: u5,
-                ///  reg_txfifo_wm_thrhd
-                TXFIFO_WM_THRHD: u5,
-                ///  reg_nonfifo_en
-                NONFIFO_EN: u1,
-                ///  reg_fifo_addr_cfg_en
-                FIFO_ADDR_CFG_EN: u1,
-                ///  reg_rx_fifo_rst
-                RX_FIFO_RST: u1,
-                ///  reg_tx_fifo_rst
-                TX_FIFO_RST: u1,
-                ///  reg_fifo_prt_en
-                FIFO_PRT_EN: u1,
-                padding: u17,
-            }),
-            ///  I2C_FIFO_DATA_REG
-            DATA: mmio.Mmio(packed struct(u32) {
-                ///  reg_fifo_rdata
-                FIFO_RDATA: u8,
-                padding: u24,
-            }),
-            ///  I2C_INT_RAW_REG
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_raw
-                RXFIFO_WM_INT_RAW: u1,
-                ///  reg_txfifo_wm_int_raw
-                TXFIFO_WM_INT_RAW: u1,
-                ///  reg_rxfifo_ovf_int_raw
-                RXFIFO_OVF_INT_RAW: u1,
-                ///  reg_end_detect_int_raw
-                END_DETECT_INT_RAW: u1,
-                ///  reg_byte_trans_done_int_raw
-                BYTE_TRANS_DONE_INT_RAW: u1,
-                ///  reg_arbitration_lost_int_raw
-                ARBITRATION_LOST_INT_RAW: u1,
-                ///  reg_mst_txfifo_udf_int_raw
-                MST_TXFIFO_UDF_INT_RAW: u1,
-                ///  reg_trans_complete_int_raw
-                TRANS_COMPLETE_INT_RAW: u1,
-                ///  reg_time_out_int_raw
-                TIME_OUT_INT_RAW: u1,
-                ///  reg_trans_start_int_raw
-                TRANS_START_INT_RAW: u1,
-                ///  reg_nack_int_raw
-                NACK_INT_RAW: u1,
-                ///  reg_txfifo_ovf_int_raw
-                TXFIFO_OVF_INT_RAW: u1,
-                ///  reg_rxfifo_udf_int_raw
-                RXFIFO_UDF_INT_RAW: u1,
-                ///  reg_scl_st_to_int_raw
-                SCL_ST_TO_INT_RAW: u1,
-                ///  reg_scl_main_st_to_int_raw
-                SCL_MAIN_ST_TO_INT_RAW: u1,
-                ///  reg_det_start_int_raw
-                DET_START_INT_RAW: u1,
-                ///  reg_slave_stretch_int_raw
-                SLAVE_STRETCH_INT_RAW: u1,
-                ///  reg_general_call_int_raw
-                GENERAL_CALL_INT_RAW: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_CLR_REG
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_clr
-                RXFIFO_WM_INT_CLR: u1,
-                ///  reg_txfifo_wm_int_clr
-                TXFIFO_WM_INT_CLR: u1,
-                ///  reg_rxfifo_ovf_int_clr
-                RXFIFO_OVF_INT_CLR: u1,
-                ///  reg_end_detect_int_clr
-                END_DETECT_INT_CLR: u1,
-                ///  reg_byte_trans_done_int_clr
-                BYTE_TRANS_DONE_INT_CLR: u1,
-                ///  reg_arbitration_lost_int_clr
-                ARBITRATION_LOST_INT_CLR: u1,
-                ///  reg_mst_txfifo_udf_int_clr
-                MST_TXFIFO_UDF_INT_CLR: u1,
-                ///  reg_trans_complete_int_clr
-                TRANS_COMPLETE_INT_CLR: u1,
-                ///  reg_time_out_int_clr
-                TIME_OUT_INT_CLR: u1,
-                ///  reg_trans_start_int_clr
-                TRANS_START_INT_CLR: u1,
-                ///  reg_nack_int_clr
-                NACK_INT_CLR: u1,
-                ///  reg_txfifo_ovf_int_clr
-                TXFIFO_OVF_INT_CLR: u1,
-                ///  reg_rxfifo_udf_int_clr
-                RXFIFO_UDF_INT_CLR: u1,
-                ///  reg_scl_st_to_int_clr
-                SCL_ST_TO_INT_CLR: u1,
-                ///  reg_scl_main_st_to_int_clr
-                SCL_MAIN_ST_TO_INT_CLR: u1,
-                ///  reg_det_start_int_clr
-                DET_START_INT_CLR: u1,
-                ///  reg_slave_stretch_int_clr
-                SLAVE_STRETCH_INT_CLR: u1,
-                ///  reg_general_call_int_clr
-                GENERAL_CALL_INT_CLR: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_ENA_REG
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_ena
-                RXFIFO_WM_INT_ENA: u1,
-                ///  reg_txfifo_wm_int_ena
-                TXFIFO_WM_INT_ENA: u1,
-                ///  reg_rxfifo_ovf_int_ena
-                RXFIFO_OVF_INT_ENA: u1,
-                ///  reg_end_detect_int_ena
-                END_DETECT_INT_ENA: u1,
-                ///  reg_byte_trans_done_int_ena
-                BYTE_TRANS_DONE_INT_ENA: u1,
-                ///  reg_arbitration_lost_int_ena
-                ARBITRATION_LOST_INT_ENA: u1,
-                ///  reg_mst_txfifo_udf_int_ena
-                MST_TXFIFO_UDF_INT_ENA: u1,
-                ///  reg_trans_complete_int_ena
-                TRANS_COMPLETE_INT_ENA: u1,
-                ///  reg_time_out_int_ena
-                TIME_OUT_INT_ENA: u1,
-                ///  reg_trans_start_int_ena
-                TRANS_START_INT_ENA: u1,
-                ///  reg_nack_int_ena
-                NACK_INT_ENA: u1,
-                ///  reg_txfifo_ovf_int_ena
-                TXFIFO_OVF_INT_ENA: u1,
-                ///  reg_rxfifo_udf_int_ena
-                RXFIFO_UDF_INT_ENA: u1,
-                ///  reg_scl_st_to_int_ena
-                SCL_ST_TO_INT_ENA: u1,
-                ///  reg_scl_main_st_to_int_ena
-                SCL_MAIN_ST_TO_INT_ENA: u1,
-                ///  reg_det_start_int_ena
-                DET_START_INT_ENA: u1,
-                ///  reg_slave_stretch_int_ena
-                SLAVE_STRETCH_INT_ENA: u1,
-                ///  reg_general_call_int_ena
-                GENERAL_CALL_INT_ENA: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_STATUS_REG
-            INT_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_st
-                RXFIFO_WM_INT_ST: u1,
-                ///  reg_txfifo_wm_int_st
-                TXFIFO_WM_INT_ST: u1,
-                ///  reg_rxfifo_ovf_int_st
-                RXFIFO_OVF_INT_ST: u1,
-                ///  reg_end_detect_int_st
-                END_DETECT_INT_ST: u1,
-                ///  reg_byte_trans_done_int_st
-                BYTE_TRANS_DONE_INT_ST: u1,
-                ///  reg_arbitration_lost_int_st
-                ARBITRATION_LOST_INT_ST: u1,
-                ///  reg_mst_txfifo_udf_int_st
-                MST_TXFIFO_UDF_INT_ST: u1,
-                ///  reg_trans_complete_int_st
-                TRANS_COMPLETE_INT_ST: u1,
-                ///  reg_time_out_int_st
-                TIME_OUT_INT_ST: u1,
-                ///  reg_trans_start_int_st
-                TRANS_START_INT_ST: u1,
-                ///  reg_nack_int_st
-                NACK_INT_ST: u1,
-                ///  reg_txfifo_ovf_int_st
-                TXFIFO_OVF_INT_ST: u1,
-                ///  reg_rxfifo_udf_int_st
-                RXFIFO_UDF_INT_ST: u1,
-                ///  reg_scl_st_to_int_st
-                SCL_ST_TO_INT_ST: u1,
-                ///  reg_scl_main_st_to_int_st
-                SCL_MAIN_ST_TO_INT_ST: u1,
-                ///  reg_det_start_int_st
-                DET_START_INT_ST: u1,
-                ///  reg_slave_stretch_int_st
-                SLAVE_STRETCH_INT_ST: u1,
-                ///  reg_general_call_int_st
-                GENERAL_CALL_INT_ST: u1,
-                padding: u14,
-            }),
-            ///  I2C_SDA_HOLD_REG
-            SDA_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SDA_SAMPLE_REG
-            SDA_SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_sample_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_HIGH_PERIOD_REG
-            SCL_HIGH_PERIOD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_high_period
-                SCL_HIGH_PERIOD: u9,
-                ///  reg_scl_wait_high_period
-                SCL_WAIT_HIGH_PERIOD: u7,
-                padding: u16,
-            }),
-            reserved64: [4]u8,
-            ///  I2C_SCL_START_HOLD_REG
-            SCL_START_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_start_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_RSTART_SETUP_REG
-            SCL_RSTART_SETUP: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_rstart_setup_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_STOP_HOLD_REG
-            SCL_STOP_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_stop_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_STOP_SETUP_REG
-            SCL_STOP_SETUP: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_stop_setup_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_FILTER_CFG_REG
-            FILTER_CFG: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_filter_thres
-                SCL_FILTER_THRES: u4,
-                ///  reg_sda_filter_thres
-                SDA_FILTER_THRES: u4,
-                ///  reg_scl_filter_en
-                SCL_FILTER_EN: u1,
-                ///  reg_sda_filter_en
-                SDA_FILTER_EN: u1,
-                padding: u22,
-            }),
-            ///  I2C_CLK_CONF_REG
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_sclk_div_num
-                SCLK_DIV_NUM: u8,
-                ///  reg_sclk_div_a
-                SCLK_DIV_A: u6,
-                ///  reg_sclk_div_b
-                SCLK_DIV_B: u6,
-                ///  reg_sclk_sel
-                SCLK_SEL: u1,
-                ///  reg_sclk_active
-                SCLK_ACTIVE: u1,
-                padding: u10,
-            }),
-            ///  I2C_COMD%s_REG
-            COMD: [8]mmio.Mmio(packed struct(u32) {
-                ///  reg_command
-                COMMAND: u14,
-                reserved31: u17,
-                ///  reg_command_done
-                COMMAND_DONE: u1,
-            }),
-            ///  I2C_SCL_ST_TIME_OUT_REG
-            SCL_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_st_to_regno more than 23
-                SCL_ST_TO_I2C: u5,
-                padding: u27,
-            }),
-            ///  I2C_SCL_MAIN_ST_TIME_OUT_REG
-            SCL_MAIN_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_main_st_to_regno more than 23
-                SCL_MAIN_ST_TO_I2C: u5,
-                padding: u27,
-            }),
-            ///  I2C_SCL_SP_CONF_REG
-            SCL_SP_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_rst_slv_en
-                SCL_RST_SLV_EN: u1,
-                ///  reg_scl_rst_slv_num
-                SCL_RST_SLV_NUM: u5,
-                ///  reg_scl_pd_en
-                SCL_PD_EN: u1,
-                ///  reg_sda_pd_en
-                SDA_PD_EN: u1,
-                padding: u24,
-            }),
-            ///  I2C_SCL_STRETCH_CONF_REG
-            SCL_STRETCH_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_stretch_protect_num
-                STRETCH_PROTECT_NUM: u10,
-                ///  reg_slave_scl_stretch_en
-                SLAVE_SCL_STRETCH_EN: u1,
-                ///  reg_slave_scl_stretch_clr
-                SLAVE_SCL_STRETCH_CLR: u1,
-                ///  reg_slave_byte_ack_ctl_en
-                SLAVE_BYTE_ACK_CTL_EN: u1,
-                ///  reg_slave_byte_ack_lvl
-                SLAVE_BYTE_ACK_LVL: u1,
-                padding: u18,
-            }),
-            reserved248: [112]u8,
-            ///  I2C_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u32,
-            }),
-            reserved256: [4]u8,
-            ///  I2C_TXFIFO_START_ADDR_REG
-            TXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_txfifo_start_addr.
-                TXFIFO_START_ADDR: u32,
-            }),
-            reserved384: [124]u8,
-            ///  I2C_RXFIFO_START_ADDR_REG
-            RXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_start_addr.
-                RXFIFO_START_ADDR: u32,
-            }),
-        };
-
-        ///  I2S (Inter-IC Sound) Controller
-        pub const I2S = extern struct {
-            reserved12: [12]u8,
-            ///  I2S interrupt raw register, valid in level.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_RAW: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt status register.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The masked interrupt status bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_ST: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt enable register.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_ENA: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt clear register.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the i2s_rx_done_int interrupt
-                RX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_tx_done_int interrupt
-                TX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_CLR: u1,
-                padding: u28,
-            }),
-            reserved32: [4]u8,
-            ///  I2S RX configure register
-            RX_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to reset receiver
-                RX_RESET: u1,
-                ///  Set this bit to reset Rx AFIFO
-                RX_FIFO_RESET: u1,
-                ///  Set this bit to start receiving data
-                RX_START: u1,
-                ///  Set this bit to enable slave receiver mode
-                RX_SLAVE_MOD: u1,
-                reserved5: u1,
-                ///  Set this bit to enable receiver in mono mode
-                RX_MONO: u1,
-                reserved7: u1,
-                ///  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-                RX_BIG_ENDIAN: u1,
-                ///  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
-                RX_UPDATE: u1,
-                ///  1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
-                RX_MONO_FST_VLD: u1,
-                ///  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-                RX_PCM_CONF: u2,
-                ///  Set this bit to bypass Compress/Decompress module for received data.
-                RX_PCM_BYPASS: u1,
-                ///  0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-                RX_STOP_MODE: u2,
-                ///  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-                RX_LEFT_ALIGN: u1,
-                ///  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-                RX_24_FILL_EN: u1,
-                ///  0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-                RX_WS_IDLE_POL: u1,
-                ///  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
-                RX_BIT_ORDER: u1,
-                ///  1: Enable I2S TDM Rx mode . 0: Disable.
-                RX_TDM_EN: u1,
-                ///  1: Enable I2S PDM Rx mode . 0: Disable.
-                RX_PDM_EN: u1,
-                padding: u11,
-            }),
-            ///  I2S TX configure register
-            TX_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to reset transmitter
-                TX_RESET: u1,
-                ///  Set this bit to reset Tx AFIFO
-                TX_FIFO_RESET: u1,
-                ///  Set this bit to start transmitting data
-                TX_START: u1,
-                ///  Set this bit to enable slave transmitter mode
-                TX_SLAVE_MOD: u1,
-                reserved5: u1,
-                ///  Set this bit to enable transmitter in mono mode
-                TX_MONO: u1,
-                ///  1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-                TX_CHAN_EQUAL: u1,
-                ///  I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-                TX_BIG_ENDIAN: u1,
-                ///  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
-                TX_UPDATE: u1,
-                ///  1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
-                TX_MONO_FST_VLD: u1,
-                ///  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-                TX_PCM_CONF: u2,
-                ///  Set this bit to bypass Compress/Decompress module for transmitted data.
-                TX_PCM_BYPASS: u1,
-                ///  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-                TX_STOP_EN: u1,
-                reserved15: u1,
-                ///  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-                TX_LEFT_ALIGN: u1,
-                ///  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-                TX_24_FILL_EN: u1,
-                ///  0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
-                TX_WS_IDLE_POL: u1,
-                ///  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
-                TX_BIT_ORDER: u1,
-                ///  1: Enable I2S TDM Tx mode . 0: Disable.
-                TX_TDM_EN: u1,
-                ///  1: Enable I2S PDM Tx mode . 0: Disable.
-                TX_PDM_EN: u1,
-                reserved24: u3,
-                ///  I2S transmitter channel mode configuration bits.
-                TX_CHAN_MOD: u3,
-                ///  Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
-                SIG_LOOPBACK: u1,
-                padding: u4,
-            }),
-            ///  I2S RX configure register 1
-            RX_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
-                RX_TDM_WS_WIDTH: u7,
-                ///  Bit clock configuration bits in receiver mode.
-                RX_BCK_DIV_NUM: u6,
-                ///  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
-                RX_BITS_MOD: u5,
-                ///  I2S Rx half sample bits -1.
-                RX_HALF_SAMPLE_BITS: u6,
-                ///  The Rx bit number for each channel minus 1in TDM mode.
-                RX_TDM_CHAN_BITS: u5,
-                ///  Set this bit to enable receiver in Phillips standard mode
-                RX_MSB_SHIFT: u1,
-                padding: u2,
-            }),
-            ///  I2S TX configure register 1
-            TX_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
-                TX_TDM_WS_WIDTH: u7,
-                ///  Bit clock configuration bits in transmitter mode.
-                TX_BCK_DIV_NUM: u6,
-                ///  Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
-                TX_BITS_MOD: u5,
-                ///  I2S Tx half sample bits -1.
-                TX_HALF_SAMPLE_BITS: u6,
-                ///  The Tx bit number for each channel minus 1in TDM mode.
-                TX_TDM_CHAN_BITS: u5,
-                ///  Set this bit to enable transmitter in Phillips standard mode
-                TX_MSB_SHIFT: u1,
-                ///  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
-                TX_BCK_NO_DLY: u1,
-                padding: u1,
-            }),
-            ///  I2S RX clock configure register
-            RX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S clock divider value
-                RX_CLKM_DIV_NUM: u8,
-                reserved26: u18,
-                ///  I2S Rx module clock enable signal.
-                RX_CLK_ACTIVE: u1,
-                ///  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-                RX_CLK_SEL: u2,
-                ///  0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.
-                MCLK_SEL: u1,
-                padding: u2,
-            }),
-            ///  I2S TX clock configure register
-            TX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
-                TX_CLKM_DIV_NUM: u8,
-                reserved26: u18,
-                ///  I2S Tx module clock enable signal.
-                TX_CLK_ACTIVE: u1,
-                ///  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-                TX_CLK_SEL: u2,
-                ///  Set this bit to enable clk gate
-                CLK_EN: u1,
-                padding: u2,
-            }),
-            ///  I2S RX module clock divider configure register
-            RX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
-                RX_CLKM_DIV_Z: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-                RX_CLKM_DIV_Y: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-                RX_CLKM_DIV_X: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
-                RX_CLKM_DIV_YN1: u1,
-                padding: u4,
-            }),
-            ///  I2S TX module clock divider configure register
-            TX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
-                TX_CLKM_DIV_Z: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-                TX_CLKM_DIV_Y: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-                TX_CLKM_DIV_X: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
-                TX_CLKM_DIV_YN1: u1,
-                padding: u4,
-            }),
-            ///  I2S TX PCM2PDM configuration register
-            TX_PCM2PDM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  I2S TX PDM bypass hp filter or not. The option has been removed.
-                TX_PDM_HP_BYPASS: u1,
-                ///  I2S TX PDM OSR2 value
-                TX_PDM_SINC_OSR2: u4,
-                ///  I2S TX PDM prescale for sigmadelta
-                TX_PDM_PRESCALE: u8,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_HP_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_LP_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_SINC_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_SIGMADELTA_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta dither2 value
-                TX_PDM_SIGMADELTA_DITHER2: u1,
-                ///  I2S TX PDM sigmadelta dither value
-                TX_PDM_SIGMADELTA_DITHER: u1,
-                ///  I2S TX PDM dac mode enable
-                TX_PDM_DAC_2OUT_EN: u1,
-                ///  I2S TX PDM dac 2channel enable
-                TX_PDM_DAC_MODE_EN: u1,
-                ///  I2S TX PDM Converter enable
-                PCM2PDM_CONV_EN: u1,
-                padding: u6,
-            }),
-            ///  I2S TX PCM2PDM configuration register
-            TX_PCM2PDM_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  I2S TX PDM Fp
-                TX_PDM_FP: u10,
-                ///  I2S TX PDM Fs
-                TX_PDM_FS: u10,
-                ///  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
-                TX_IIR_HP_MULT12_5: u3,
-                ///  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
-                TX_IIR_HP_MULT12_0: u3,
-                padding: u6,
-            }),
-            reserved80: [8]u8,
-            ///  I2S TX TDM mode control register
-            RX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN0_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN1_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN2_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN3_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN4_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN5_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN6_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN7_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN8_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN9_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN10_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN11_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN12_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN13_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN14_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN15_EN: u1,
-                ///  The total channel number of I2S TX TDM mode.
-                RX_TDM_TOT_CHAN_NUM: u4,
-                padding: u12,
-            }),
-            ///  I2S TX TDM mode control register
-            TX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN0_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN1_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN2_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN3_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN4_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN5_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN6_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN7_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN8_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN9_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN10_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN11_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN12_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN13_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN14_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN15_EN: u1,
-                ///  The total channel number of I2S TX TDM mode.
-                TX_TDM_TOT_CHAN_NUM: u4,
-                ///  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
-                TX_TDM_SKIP_MSK_EN: u1,
-                padding: u11,
-            }),
-            ///  I2S RX timing control register
-            RX_TIMING: mmio.Mmio(packed struct(u32) {
-                ///  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_SD_IN_DM: u2,
-                reserved16: u14,
-                ///  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_WS_OUT_DM: u2,
-                reserved20: u2,
-                ///  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_BCK_OUT_DM: u2,
-                reserved24: u2,
-                ///  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_WS_IN_DM: u2,
-                reserved28: u2,
-                ///  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_BCK_IN_DM: u2,
-                padding: u2,
-            }),
-            ///  I2S TX timing control register
-            TX_TIMING: mmio.Mmio(packed struct(u32) {
-                ///  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_SD_OUT_DM: u2,
-                reserved4: u2,
-                ///  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_SD1_OUT_DM: u2,
-                reserved16: u10,
-                ///  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_WS_OUT_DM: u2,
-                reserved20: u2,
-                ///  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_BCK_OUT_DM: u2,
-                reserved24: u2,
-                ///  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_WS_IN_DM: u2,
-                reserved28: u2,
-                ///  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_BCK_IN_DM: u2,
-                padding: u2,
-            }),
-            ///  I2S HUNG configure register.
-            LC_HUNG_CONF: mmio.Mmio(packed struct(u32) {
-                ///  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
-                LC_FIFO_TIMEOUT: u8,
-                ///  The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-                LC_FIFO_TIMEOUT_SHIFT: u3,
-                ///  The enable bit for FIFO timeout
-                LC_FIFO_TIMEOUT_ENA: u1,
-                padding: u20,
-            }),
-            ///  I2S RX data number control register.
-            RXEOF_NUM: mmio.Mmio(packed struct(u32) {
-                ///  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-                RX_EOF_NUM: u12,
-                padding: u20,
-            }),
-            ///  I2S signal data register
-            CONF_SIGLE_DATA: mmio.Mmio(packed struct(u32) {
-                ///  The configured constant channel data to be sent out.
-                SINGLE_DATA: u32,
-            }),
-            ///  I2S TX status register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  1: i2s_tx is idle state. 0: i2s_tx is working.
-                TX_IDLE: u1,
-                padding: u31,
-            }),
-            reserved128: [16]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  I2S version control register
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Interrupt Core
-        pub const INTERRUPT_CORE0 = extern struct {
-            ///  mac intr map register
-            MAC_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  core0_mac_intr_map
-                MAC_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac nmi_intr map register
-            MAC_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_mac_nmi_map
-                MAC_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  pwr intr map register
-            PWR_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_pwr_intr_map
-                PWR_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb intr map register
-            BB_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bb_int_map
-                BB_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bt intr map register
-            BT_MAC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_mac_int_map
-                BT_MAC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb_bt intr map register
-            BT_BB_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_bb_int_map
-                BT_BB_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb_bt_nmi intr map register
-            BT_BB_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_bb_nmi_map
-                BT_BB_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwbt intr map register
-            RWBT_IRQ_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwbt_irq_map
-                RWBT_IRQ_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwble intr map register
-            RWBLE_IRQ_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwble_irq_map
-                RWBLE_IRQ_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwbt_nmi intr map register
-            RWBT_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwbt_nmi_map
-                RWBT_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwble_nmi intr map register
-            RWBLE_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwble_nmi_map
-                RWBLE_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2c intr map register
-            I2C_MST_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2c_mst_int_map
-                I2C_MST_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  slc0 intr map register
-            SLC0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_slc0_intr_map
-                SLC0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  slc1 intr map register
-            SLC1_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_slc1_intr_map
-                SLC1_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  apb_ctrl intr map register
-            APB_CTRL_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_apb_ctrl_intr_map
-                APB_CTRL_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  uchi0 intr map register
-            UHCI0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uhci0_intr_map
-                UHCI0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio intr map register
-            GPIO_INTERRUPT_PRO_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_gpio_interrupt_pro_map
-                GPIO_INTERRUPT_PRO_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio_pro intr map register
-            GPIO_INTERRUPT_PRO_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_gpio_interrupt_pro_nmi_map
-                GPIO_INTERRUPT_PRO_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio_pro_nmi intr map register
-            SPI_INTR_1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_intr_1_map
-                SPI_INTR_1_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi1 intr map register
-            SPI_INTR_2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_intr_2_map
-                SPI_INTR_2_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi2 intr map register
-            I2S1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2s1_int_map
-                I2S1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2s1 intr map register
-            UART_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uart_intr_map
-                UART_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  uart1 intr map register
-            UART1_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uart1_intr_map
-                UART1_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  ledc intr map register
-            LEDC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_ledc_int_map
-                LEDC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  efuse intr map register
-            EFUSE_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_efuse_int_map
-                EFUSE_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  can intr map register
-            CAN_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_can_int_map
-                CAN_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  usb intr map register
-            USB_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_usb_intr_map
-                USB_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  rtc intr map register
-            RTC_CORE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rtc_core_intr_map
-                RTC_CORE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  rmt intr map register
-            RMT_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rmt_intr_map
-                RMT_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2c intr map register
-            I2C_EXT0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2c_ext0_intr_map
-                I2C_EXT0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  timer1 intr map register
-            TIMER_INT1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_timer_int1_map
-                TIMER_INT1_MAP: u5,
-                padding: u27,
-            }),
-            ///  timer2 intr map register
-            TIMER_INT2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_timer_int2_map
-                TIMER_INT2_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg to intr map register
-            TG_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg_t0_int_map
-                TG_T0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg wdt intr map register
-            TG_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg_wdt_int_map
-                TG_WDT_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg1 to intr map register
-            TG1_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg1_t0_int_map
-                TG1_T0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg1 wdt intr map register
-            TG1_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg1_wdt_int_map
-                TG1_WDT_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  cache ia intr map register
-            CACHE_IA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cache_ia_int_map
-                CACHE_IA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer intr map register
-            SYSTIMER_TARGET0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target0_int_map
-                SYSTIMER_TARGET0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer target1 intr map register
-            SYSTIMER_TARGET1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target1_int_map
-                SYSTIMER_TARGET1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer target2 intr map register
-            SYSTIMER_TARGET2_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target2_int_map
-                SYSTIMER_TARGET2_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi mem reject intr map register
-            SPI_MEM_REJECT_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_mem_reject_intr_map
-                SPI_MEM_REJECT_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  icache perload intr map register
-            ICACHE_PRELOAD_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_icache_preload_int_map
-                ICACHE_PRELOAD_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  icache sync intr map register
-            ICACHE_SYNC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_icache_sync_int_map
-                ICACHE_SYNC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  adc intr map register
-            APB_ADC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_apb_adc_int_map
-                APB_ADC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch0 intr map register
-            DMA_CH0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch0_int_map
-                DMA_CH0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch1 intr map register
-            DMA_CH1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch1_int_map
-                DMA_CH1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch2 intr map register
-            DMA_CH2_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch2_int_map
-                DMA_CH2_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  rsa intr map register
-            RSA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rsa_int_map
-                RSA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  aes intr map register
-            AES_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_aes_int_map
-                AES_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  sha intr map register
-            SHA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_sha_int_map
-                SHA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 0 intr map register
-            CPU_INTR_FROM_CPU_0_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_0_map
-                CPU_INTR_FROM_CPU_0_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 0 intr map register
-            CPU_INTR_FROM_CPU_1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_1_map
-                CPU_INTR_FROM_CPU_1_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 1 intr map register
-            CPU_INTR_FROM_CPU_2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_2_map
-                CPU_INTR_FROM_CPU_2_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 3 intr map register
-            CPU_INTR_FROM_CPU_3_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_3_map
-                CPU_INTR_FROM_CPU_3_MAP: u5,
-                padding: u27,
-            }),
-            ///  assist debug intr map register
-            ASSIST_DEBUG_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_assist_debug_intr_map
-                ASSIST_DEBUG_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma pms violatile intr map register
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_apbperi_pms_monitor_violate_intr_map
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  iram0 pms violatile intr map register
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_iram0_pms_monitor_violate_intr_map
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_dram0_pms_monitor_violate_intr_map
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_pif_pms_monitor_violate_intr_map
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            BACKUP_PMS_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_backup_pms_violate_intr_map
-                BACKUP_PMS_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CACHE_CORE0_ACS_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cache_core0_acs_int_map
-                CACHE_CORE0_ACS_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            INTR_STATUS_REG_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_intr_status_0
-                INTR_STATUS_0: u32,
-            }),
-            ///  mac intr map register
-            INTR_STATUS_REG_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_intr_status_1
-                INTR_STATUS_1: u32,
-            }),
-            ///  mac intr map register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_reg_clk_en
-                REG_CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  mac intr map register
-            CPU_INT_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_enable
-                CPU_INT_ENABLE: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_TYPE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_type
-                CPU_INT_TYPE: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_clear
-                CPU_INT_CLEAR: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_EIP_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_eip_status
-                CPU_INT_EIP_STATUS: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_0_map
-                CPU_PRI_0_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_1_map
-                CPU_PRI_1_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_2_map
-                CPU_PRI_2_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_3_map
-                CPU_PRI_3_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_4: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_4_map
-                CPU_PRI_4_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_5: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_5_map
-                CPU_PRI_5_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_6: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_6_map
-                CPU_PRI_6_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_7: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_7_map
-                CPU_PRI_7_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_8: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_8_map
-                CPU_PRI_8_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_9: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_9_map
-                CPU_PRI_9_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_10: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_10_map
-                CPU_PRI_10_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_11: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_11_map
-                CPU_PRI_11_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_12: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_12_map
-                CPU_PRI_12_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_13: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_13_map
-                CPU_PRI_13_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_14: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_14_map
-                CPU_PRI_14_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_15: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_15_map
-                CPU_PRI_15_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_16: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_16_map
-                CPU_PRI_16_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_17: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_17_map
-                CPU_PRI_17_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_18: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_18_map
-                CPU_PRI_18_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_19: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_19_map
-                CPU_PRI_19_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_20: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_20_map
-                CPU_PRI_20_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_21: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_21_map
-                CPU_PRI_21_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_22: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_22_map
-                CPU_PRI_22_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_23: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_23_map
-                CPU_PRI_23_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_24: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_24_map
-                CPU_PRI_24_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_25: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_25_map
-                CPU_PRI_25_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_26: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_26_map
-                CPU_PRI_26_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_27: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_27_map
-                CPU_PRI_27_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_28: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_28_map
-                CPU_PRI_28_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_29: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_29_map
-                CPU_PRI_29_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_30: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_30_map
-                CPU_PRI_30_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_31: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_31_map
-                CPU_PRI_31_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_THRESH: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_thresh
-                CPU_INT_THRESH: u4,
-                padding: u28,
-            }),
-            reserved2044: [1636]u8,
-            ///  mac intr map register
-            INTERRUPT_REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_interrupt_reg_date
-                INTERRUPT_REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Input/Output Multiplexer
-        pub const IO_MUX = extern struct {
-            ///  Clock Output Configuration Register
-            PIN_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
-                CLK_OUT1: u4,
-                ///  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
-                CLK_OUT2: u4,
-                ///  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
-                CLK_OUT3: u4,
-                padding: u20,
-            }),
-            ///  IO MUX Configure Register for pad XTAL_32K_P
-            GPIO: [22]mmio.Mmio(packed struct(u32) {
-                ///  Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-                MCU_OE: u1,
-                ///  Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-                SLP_SEL: u1,
-                ///  Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
-                MCU_WPD: u1,
-                ///  Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
-                MCU_WPU: u1,
-                ///  Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-                MCU_IE: u1,
-                reserved7: u2,
-                ///  Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
-                FUN_WPD: u1,
-                ///  Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
-                FUN_WPU: u1,
-                ///  Input enable of the pad. 1: input enabled; 0: input disabled.
-                FUN_IE: u1,
-                ///  Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-                FUN_DRV: u2,
-                ///  Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
-                MCU_SEL: u3,
-                ///  Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-                FILTER_EN: u1,
-                padding: u16,
-            }),
-            reserved252: [160]u8,
-            ///  IO MUX Version Control Register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Version control register
-                REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  LED Control PWM (Pulse Width Modulation)
-        pub const LEDC = extern struct {
-            ///  LEDC_LSCH0_CONF0.
-            LSCH0_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch0.
-                TIMER_SEL_LSCH0: u2,
-                ///  reg_sig_out_en_lsch0.
-                SIG_OUT_EN_LSCH0: u1,
-                ///  reg_idle_lv_lsch0.
-                IDLE_LV_LSCH0: u1,
-                ///  reg_para_up_lsch0.
-                PARA_UP_LSCH0: u1,
-                ///  reg_ovf_num_lsch0.
-                OVF_NUM_LSCH0: u10,
-                ///  reg_ovf_cnt_en_lsch0.
-                OVF_CNT_EN_LSCH0: u1,
-                ///  reg_ovf_cnt_reset_lsch0.
-                OVF_CNT_RESET_LSCH0: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH0_HPOINT.
-            LSCH0_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch0.
-                HPOINT_LSCH0: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH0_DUTY.
-            LSCH0_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch0.
-                DUTY_LSCH0: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH0_CONF1.
-            LSCH0_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch0.
-                DUTY_SCALE_LSCH0: u10,
-                ///  reg_duty_cycle_lsch0.
-                DUTY_CYCLE_LSCH0: u10,
-                ///  reg_duty_num_lsch0.
-                DUTY_NUM_LSCH0: u10,
-                ///  reg_duty_inc_lsch0.
-                DUTY_INC_LSCH0: u1,
-                ///  reg_duty_start_lsch0.
-                DUTY_START_LSCH0: u1,
-            }),
-            ///  LEDC_LSCH0_DUTY_R.
-            LSCH0_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch0_r.
-                DUTY_LSCH0_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH1_CONF0.
-            LSCH1_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch1.
-                TIMER_SEL_LSCH1: u2,
-                ///  reg_sig_out_en_lsch1.
-                SIG_OUT_EN_LSCH1: u1,
-                ///  reg_idle_lv_lsch1.
-                IDLE_LV_LSCH1: u1,
-                ///  reg_para_up_lsch1.
-                PARA_UP_LSCH1: u1,
-                ///  reg_ovf_num_lsch1.
-                OVF_NUM_LSCH1: u10,
-                ///  reg_ovf_cnt_en_lsch1.
-                OVF_CNT_EN_LSCH1: u1,
-                ///  reg_ovf_cnt_reset_lsch1.
-                OVF_CNT_RESET_LSCH1: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH1_HPOINT.
-            LSCH1_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch1.
-                HPOINT_LSCH1: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH1_DUTY.
-            LSCH1_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch1.
-                DUTY_LSCH1: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH1_CONF1.
-            LSCH1_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch1.
-                DUTY_SCALE_LSCH1: u10,
-                ///  reg_duty_cycle_lsch1.
-                DUTY_CYCLE_LSCH1: u10,
-                ///  reg_duty_num_lsch1.
-                DUTY_NUM_LSCH1: u10,
-                ///  reg_duty_inc_lsch1.
-                DUTY_INC_LSCH1: u1,
-                ///  reg_duty_start_lsch1.
-                DUTY_START_LSCH1: u1,
-            }),
-            ///  LEDC_LSCH1_DUTY_R.
-            LSCH1_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch1_r.
-                DUTY_LSCH1_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH2_CONF0.
-            LSCH2_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch2.
-                TIMER_SEL_LSCH2: u2,
-                ///  reg_sig_out_en_lsch2.
-                SIG_OUT_EN_LSCH2: u1,
-                ///  reg_idle_lv_lsch2.
-                IDLE_LV_LSCH2: u1,
-                ///  reg_para_up_lsch2.
-                PARA_UP_LSCH2: u1,
-                ///  reg_ovf_num_lsch2.
-                OVF_NUM_LSCH2: u10,
-                ///  reg_ovf_cnt_en_lsch2.
-                OVF_CNT_EN_LSCH2: u1,
-                ///  reg_ovf_cnt_reset_lsch2.
-                OVF_CNT_RESET_LSCH2: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH2_HPOINT.
-            LSCH2_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch2.
-                HPOINT_LSCH2: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH2_DUTY.
-            LSCH2_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch2.
-                DUTY_LSCH2: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH2_CONF1.
-            LSCH2_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch2.
-                DUTY_SCALE_LSCH2: u10,
-                ///  reg_duty_cycle_lsch2.
-                DUTY_CYCLE_LSCH2: u10,
-                ///  reg_duty_num_lsch2.
-                DUTY_NUM_LSCH2: u10,
-                ///  reg_duty_inc_lsch2.
-                DUTY_INC_LSCH2: u1,
-                ///  reg_duty_start_lsch2.
-                DUTY_START_LSCH2: u1,
-            }),
-            ///  LEDC_LSCH2_DUTY_R.
-            LSCH2_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch2_r.
-                DUTY_LSCH2_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH3_CONF0.
-            LSCH3_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch3.
-                TIMER_SEL_LSCH3: u2,
-                ///  reg_sig_out_en_lsch3.
-                SIG_OUT_EN_LSCH3: u1,
-                ///  reg_idle_lv_lsch3.
-                IDLE_LV_LSCH3: u1,
-                ///  reg_para_up_lsch3.
-                PARA_UP_LSCH3: u1,
-                ///  reg_ovf_num_lsch3.
-                OVF_NUM_LSCH3: u10,
-                ///  reg_ovf_cnt_en_lsch3.
-                OVF_CNT_EN_LSCH3: u1,
-                ///  reg_ovf_cnt_reset_lsch3.
-                OVF_CNT_RESET_LSCH3: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH3_HPOINT.
-            LSCH3_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch3.
-                HPOINT_LSCH3: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH3_DUTY.
-            LSCH3_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch3.
-                DUTY_LSCH3: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH3_CONF1.
-            LSCH3_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch3.
-                DUTY_SCALE_LSCH3: u10,
-                ///  reg_duty_cycle_lsch3.
-                DUTY_CYCLE_LSCH3: u10,
-                ///  reg_duty_num_lsch3.
-                DUTY_NUM_LSCH3: u10,
-                ///  reg_duty_inc_lsch3.
-                DUTY_INC_LSCH3: u1,
-                ///  reg_duty_start_lsch3.
-                DUTY_START_LSCH3: u1,
-            }),
-            ///  LEDC_LSCH3_DUTY_R.
-            LSCH3_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch3_r.
-                DUTY_LSCH3_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH4_CONF0.
-            LSCH4_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch4.
-                TIMER_SEL_LSCH4: u2,
-                ///  reg_sig_out_en_lsch4.
-                SIG_OUT_EN_LSCH4: u1,
-                ///  reg_idle_lv_lsch4.
-                IDLE_LV_LSCH4: u1,
-                ///  reg_para_up_lsch4.
-                PARA_UP_LSCH4: u1,
-                ///  reg_ovf_num_lsch4.
-                OVF_NUM_LSCH4: u10,
-                ///  reg_ovf_cnt_en_lsch4.
-                OVF_CNT_EN_LSCH4: u1,
-                ///  reg_ovf_cnt_reset_lsch4.
-                OVF_CNT_RESET_LSCH4: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH4_HPOINT.
-            LSCH4_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch4.
-                HPOINT_LSCH4: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH4_DUTY.
-            LSCH4_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch4.
-                DUTY_LSCH4: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH4_CONF1.
-            LSCH4_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch4.
-                DUTY_SCALE_LSCH4: u10,
-                ///  reg_duty_cycle_lsch4.
-                DUTY_CYCLE_LSCH4: u10,
-                ///  reg_duty_num_lsch4.
-                DUTY_NUM_LSCH4: u10,
-                ///  reg_duty_inc_lsch4.
-                DUTY_INC_LSCH4: u1,
-                ///  reg_duty_start_lsch4.
-                DUTY_START_LSCH4: u1,
-            }),
-            ///  LEDC_LSCH4_DUTY_R.
-            LSCH4_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch4_r.
-                DUTY_LSCH4_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH5_CONF0.
-            LSCH5_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch5.
-                TIMER_SEL_LSCH5: u2,
-                ///  reg_sig_out_en_lsch5.
-                SIG_OUT_EN_LSCH5: u1,
-                ///  reg_idle_lv_lsch5.
-                IDLE_LV_LSCH5: u1,
-                ///  reg_para_up_lsch5.
-                PARA_UP_LSCH5: u1,
-                ///  reg_ovf_num_lsch5.
-                OVF_NUM_LSCH5: u10,
-                ///  reg_ovf_cnt_en_lsch5.
-                OVF_CNT_EN_LSCH5: u1,
-                ///  reg_ovf_cnt_reset_lsch5.
-                OVF_CNT_RESET_LSCH5: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH5_HPOINT.
-            LSCH5_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch5.
-                HPOINT_LSCH5: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH5_DUTY.
-            LSCH5_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch5.
-                DUTY_LSCH5: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH5_CONF1.
-            LSCH5_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch5.
-                DUTY_SCALE_LSCH5: u10,
-                ///  reg_duty_cycle_lsch5.
-                DUTY_CYCLE_LSCH5: u10,
-                ///  reg_duty_num_lsch5.
-                DUTY_NUM_LSCH5: u10,
-                ///  reg_duty_inc_lsch5.
-                DUTY_INC_LSCH5: u1,
-                ///  reg_duty_start_lsch5.
-                DUTY_START_LSCH5: u1,
-            }),
-            ///  LEDC_LSCH5_DUTY_R.
-            LSCH5_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch5_r.
-                DUTY_LSCH5_R: u19,
-                padding: u13,
-            }),
-            reserved160: [40]u8,
-            ///  LEDC_LSTIMER0_CONF.
-            LSTIMER0_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_duty_res.
-                LSTIMER0_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer0.
-                CLK_DIV_LSTIMER0: u18,
-                ///  reg_lstimer0_pause.
-                LSTIMER0_PAUSE: u1,
-                ///  reg_lstimer0_rst.
-                LSTIMER0_RST: u1,
-                ///  reg_tick_sel_lstimer0.
-                TICK_SEL_LSTIMER0: u1,
-                ///  reg_lstimer0_para_up.
-                LSTIMER0_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER0_VALUE.
-            LSTIMER0_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_cnt.
-                LSTIMER0_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER1_CONF.
-            LSTIMER1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer1_duty_res.
-                LSTIMER1_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer1.
-                CLK_DIV_LSTIMER1: u18,
-                ///  reg_lstimer1_pause.
-                LSTIMER1_PAUSE: u1,
-                ///  reg_lstimer1_rst.
-                LSTIMER1_RST: u1,
-                ///  reg_tick_sel_lstimer1.
-                TICK_SEL_LSTIMER1: u1,
-                ///  reg_lstimer1_para_up.
-                LSTIMER1_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER1_VALUE.
-            LSTIMER1_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer1_cnt.
-                LSTIMER1_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER2_CONF.
-            LSTIMER2_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer2_duty_res.
-                LSTIMER2_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer2.
-                CLK_DIV_LSTIMER2: u18,
-                ///  reg_lstimer2_pause.
-                LSTIMER2_PAUSE: u1,
-                ///  reg_lstimer2_rst.
-                LSTIMER2_RST: u1,
-                ///  reg_tick_sel_lstimer2.
-                TICK_SEL_LSTIMER2: u1,
-                ///  reg_lstimer2_para_up.
-                LSTIMER2_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER2_VALUE.
-            LSTIMER2_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer2_cnt.
-                LSTIMER2_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER3_CONF.
-            LSTIMER3_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer3_duty_res.
-                LSTIMER3_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer3.
-                CLK_DIV_LSTIMER3: u18,
-                ///  reg_lstimer3_pause.
-                LSTIMER3_PAUSE: u1,
-                ///  reg_lstimer3_rst.
-                LSTIMER3_RST: u1,
-                ///  reg_tick_sel_lstimer3.
-                TICK_SEL_LSTIMER3: u1,
-                ///  reg_lstimer3_para_up.
-                LSTIMER3_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER3_VALUE.
-            LSTIMER3_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer3_cnt.
-                LSTIMER3_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_INT_RAW.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_raw.
-                LSTIMER0_OVF_INT_RAW: u1,
-                ///  reg_lstimer1_ovf_int_raw.
-                LSTIMER1_OVF_INT_RAW: u1,
-                ///  reg_lstimer2_ovf_int_raw.
-                LSTIMER2_OVF_INT_RAW: u1,
-                ///  reg_lstimer3_ovf_int_raw.
-                LSTIMER3_OVF_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch0_int_raw.
-                DUTY_CHNG_END_LSCH0_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch1_int_raw.
-                DUTY_CHNG_END_LSCH1_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch2_int_raw.
-                DUTY_CHNG_END_LSCH2_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch3_int_raw.
-                DUTY_CHNG_END_LSCH3_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch4_int_raw.
-                DUTY_CHNG_END_LSCH4_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch5_int_raw.
-                DUTY_CHNG_END_LSCH5_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch0_int_raw.
-                OVF_CNT_LSCH0_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch1_int_raw.
-                OVF_CNT_LSCH1_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch2_int_raw.
-                OVF_CNT_LSCH2_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch3_int_raw.
-                OVF_CNT_LSCH3_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch4_int_raw.
-                OVF_CNT_LSCH4_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch5_int_raw.
-                OVF_CNT_LSCH5_INT_RAW: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_ST.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_st.
-                LSTIMER0_OVF_INT_ST: u1,
-                ///  reg_lstimer1_ovf_int_st.
-                LSTIMER1_OVF_INT_ST: u1,
-                ///  reg_lstimer2_ovf_int_st.
-                LSTIMER2_OVF_INT_ST: u1,
-                ///  reg_lstimer3_ovf_int_st.
-                LSTIMER3_OVF_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch0_int_st.
-                DUTY_CHNG_END_LSCH0_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch1_int_st.
-                DUTY_CHNG_END_LSCH1_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch2_int_st.
-                DUTY_CHNG_END_LSCH2_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch3_int_st.
-                DUTY_CHNG_END_LSCH3_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch4_int_st.
-                DUTY_CHNG_END_LSCH4_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch5_int_st.
-                DUTY_CHNG_END_LSCH5_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch0_int_st.
-                OVF_CNT_LSCH0_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch1_int_st.
-                OVF_CNT_LSCH1_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch2_int_st.
-                OVF_CNT_LSCH2_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch3_int_st.
-                OVF_CNT_LSCH3_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch4_int_st.
-                OVF_CNT_LSCH4_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch5_int_st.
-                OVF_CNT_LSCH5_INT_ST: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_ENA.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_ena.
-                LSTIMER0_OVF_INT_ENA: u1,
-                ///  reg_lstimer1_ovf_int_ena.
-                LSTIMER1_OVF_INT_ENA: u1,
-                ///  reg_lstimer2_ovf_int_ena.
-                LSTIMER2_OVF_INT_ENA: u1,
-                ///  reg_lstimer3_ovf_int_ena.
-                LSTIMER3_OVF_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch0_int_ena.
-                DUTY_CHNG_END_LSCH0_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch1_int_ena.
-                DUTY_CHNG_END_LSCH1_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch2_int_ena.
-                DUTY_CHNG_END_LSCH2_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch3_int_ena.
-                DUTY_CHNG_END_LSCH3_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch4_int_ena.
-                DUTY_CHNG_END_LSCH4_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch5_int_ena.
-                DUTY_CHNG_END_LSCH5_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch0_int_ena.
-                OVF_CNT_LSCH0_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch1_int_ena.
-                OVF_CNT_LSCH1_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch2_int_ena.
-                OVF_CNT_LSCH2_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch3_int_ena.
-                OVF_CNT_LSCH3_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch4_int_ena.
-                OVF_CNT_LSCH4_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch5_int_ena.
-                OVF_CNT_LSCH5_INT_ENA: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_CLR.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_clr.
-                LSTIMER0_OVF_INT_CLR: u1,
-                ///  reg_lstimer1_ovf_int_clr.
-                LSTIMER1_OVF_INT_CLR: u1,
-                ///  reg_lstimer2_ovf_int_clr.
-                LSTIMER2_OVF_INT_CLR: u1,
-                ///  reg_lstimer3_ovf_int_clr.
-                LSTIMER3_OVF_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch0_int_clr.
-                DUTY_CHNG_END_LSCH0_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch1_int_clr.
-                DUTY_CHNG_END_LSCH1_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch2_int_clr.
-                DUTY_CHNG_END_LSCH2_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch3_int_clr.
-                DUTY_CHNG_END_LSCH3_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch4_int_clr.
-                DUTY_CHNG_END_LSCH4_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch5_int_clr.
-                DUTY_CHNG_END_LSCH5_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch0_int_clr.
-                OVF_CNT_LSCH0_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch1_int_clr.
-                OVF_CNT_LSCH1_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch2_int_clr.
-                OVF_CNT_LSCH2_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch3_int_clr.
-                OVF_CNT_LSCH3_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch4_int_clr.
-                OVF_CNT_LSCH4_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch5_int_clr.
-                OVF_CNT_LSCH5_INT_CLR: u1,
-                padding: u16,
-            }),
-            ///  LEDC_CONF.
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_apb_clk_sel.
-                APB_CLK_SEL: u2,
-                reserved31: u29,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-            reserved252: [40]u8,
-            ///  LEDC_DATE.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_ledc_date.
-                LEDC_DATE: u32,
-            }),
-        };
-
-        ///  Remote Control Peripheral
-        pub const RMT = extern struct {
-            ///  RMT_CH0DATA_REG.
-            CH0DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH1DATA_REG.
-            CH1DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH2DATA_REG.
-            CH2DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH3DATA_REG.
-            CH3DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            reserved28: [12]u8,
-            ///  RMT_CH2CONF1_REG.
-            CH2CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_rx_en_ch2.
-                RX_EN: u1,
-                ///  reg_mem_wr_rst_ch2.
-                MEM_WR_RST: u1,
-                ///  reg_apb_mem_rst_ch2.
-                APB_MEM_RST: u1,
-                ///  reg_mem_owner_ch2.
-                MEM_OWNER: u1,
-                ///  reg_rx_filter_en_ch2.
-                RX_FILTER_EN: u1,
-                ///  reg_rx_filter_thres_ch2.
-                RX_FILTER_THRES: u8,
-                ///  reg_mem_rx_wrap_en_ch2.
-                MEM_RX_WRAP_EN: u1,
-                ///  reg_afifo_rst_ch2.
-                AFIFO_RST: u1,
-                ///  reg_conf_update_ch2.
-                CONF_UPDATE: u1,
-                padding: u16,
-            }),
-            reserved36: [4]u8,
-            ///  RMT_CH3CONF1_REG.
-            CH3CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_rx_en_ch3.
-                RX_EN: u1,
-                ///  reg_mem_wr_rst_ch3.
-                MEM_WR_RST: u1,
-                ///  reg_apb_mem_rst_ch3.
-                APB_MEM_RST: u1,
-                ///  reg_mem_owner_ch3.
-                MEM_OWNER: u1,
-                ///  reg_rx_filter_en_ch3.
-                RX_FILTER_EN: u1,
-                ///  reg_rx_filter_thres_ch3.
-                RX_FILTER_THRES: u8,
-                ///  reg_mem_rx_wrap_en_ch3.
-                MEM_RX_WRAP_EN: u1,
-                ///  reg_afifo_rst_ch3.
-                AFIFO_RST: u1,
-                ///  reg_conf_update_ch3.
-                CONF_UPDATE: u1,
-                padding: u16,
-            }),
-            ///  RMT_CH0STATUS_REG.
-            CH0STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_raddr_ex_ch0.
-                MEM_RADDR_EX: u9,
-                ///  reg_state_ch0.
-                STATE: u3,
-                ///  reg_apb_mem_waddr_ch0.
-                APB_MEM_WADDR: u9,
-                ///  reg_apb_mem_rd_err_ch0.
-                APB_MEM_RD_ERR: u1,
-                ///  reg_mem_empty_ch0.
-                MEM_EMPTY: u1,
-                ///  reg_apb_mem_wr_err_ch0.
-                APB_MEM_WR_ERR: u1,
-                ///  reg_apb_mem_raddr_ch0.
-                APB_MEM_RADDR: u8,
-            }),
-            ///  RMT_CH1STATUS_REG.
-            CH1STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_raddr_ex_ch1.
-                MEM_RADDR_EX: u9,
-                ///  reg_state_ch1.
-                STATE: u3,
-                ///  reg_apb_mem_waddr_ch1.
-                APB_MEM_WADDR: u9,
-                ///  reg_apb_mem_rd_err_ch1.
-                APB_MEM_RD_ERR: u1,
-                ///  reg_mem_empty_ch1.
-                MEM_EMPTY: u1,
-                ///  reg_apb_mem_wr_err_ch1.
-                APB_MEM_WR_ERR: u1,
-                ///  reg_apb_mem_raddr_ch1.
-                APB_MEM_RADDR: u8,
-            }),
-            ///  RMT_CH2STATUS_REG.
-            CH2STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_waddr_ex_ch2.
-                MEM_WADDR_EX: u9,
-                reserved12: u3,
-                ///  reg_apb_mem_raddr_ch2.
-                APB_MEM_RADDR: u9,
-                reserved22: u1,
-                ///  reg_state_ch2.
-                STATE: u3,
-                ///  reg_mem_owner_err_ch2.
-                MEM_OWNER_ERR: u1,
-                ///  reg_mem_full_ch2.
-                MEM_FULL: u1,
-                ///  reg_apb_mem_rd_err_ch2.
-                APB_MEM_RD_ERR: u1,
-                padding: u4,
-            }),
-            ///  RMT_CH3STATUS_REG.
-            CH3STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_waddr_ex_ch3.
-                MEM_WADDR_EX: u9,
-                reserved12: u3,
-                ///  reg_apb_mem_raddr_ch3.
-                APB_MEM_RADDR: u9,
-                reserved22: u1,
-                ///  reg_state_ch3.
-                STATE: u3,
-                ///  reg_mem_owner_err_ch3.
-                MEM_OWNER_ERR: u1,
-                ///  reg_mem_full_ch3.
-                MEM_FULL: u1,
-                ///  reg_apb_mem_rd_err_ch3.
-                APB_MEM_RD_ERR: u1,
-                padding: u4,
-            }),
-            ///  RMT_INT_RAW_REG.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_raw.
-                CH2_RX_THR_EVENT_INT_RAW: u1,
-                ///  reg_ch3_rx_thr_event_int_raw.
-                CH3_RX_THR_EVENT_INT_RAW: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_ST_REG.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_st.
-                CH2_RX_THR_EVENT_INT_ST: u1,
-                ///  reg_ch3_rx_thr_event_int_st.
-                CH3_RX_THR_EVENT_INT_ST: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_ENA_REG.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_ena.
-                CH2_RX_THR_EVENT_INT_ENA: u1,
-                ///  reg_ch3_rx_thr_event_int_ena.
-                CH3_RX_THR_EVENT_INT_ENA: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_CLR_REG.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_clr.
-                CH2_RX_THR_EVENT_INT_CLR: u1,
-                ///  reg_ch3_rx_thr_event_int_clr.
-                CH3_RX_THR_EVENT_INT_CLR: u1,
-                padding: u20,
-            }),
-            ///  RMT_CH0CARRIER_DUTY_REG.
-            CH0CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_ch0.
-                CARRIER_LOW: u16,
-                ///  reg_carrier_high_ch0.
-                CARRIER_HIGH: u16,
-            }),
-            ///  RMT_CH1CARRIER_DUTY_REG.
-            CH1CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_ch1.
-                CARRIER_LOW: u16,
-                ///  reg_carrier_high_ch1.
-                CARRIER_HIGH: u16,
-            }),
-            ///  RMT_CH2_RX_CARRIER_RM_REG.
-            CH2_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_thres_ch2.
-                CARRIER_LOW_THRES: u16,
-                ///  reg_carrier_high_thres_ch2.
-                CARRIER_HIGH_THRES: u16,
-            }),
-            ///  RMT_CH3_RX_CARRIER_RM_REG.
-            CH3_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_thres_ch3.
-                CARRIER_LOW_THRES: u16,
-                ///  reg_carrier_high_thres_ch3.
-                CARRIER_HIGH_THRES: u16,
-            }),
-            reserved104: [16]u8,
-            ///  RMT_SYS_CONF_REG.
-            SYS_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_apb_fifo_mask.
-                APB_FIFO_MASK: u1,
-                ///  reg_mem_clk_force_on.
-                MEM_CLK_FORCE_ON: u1,
-                ///  reg_rmt_mem_force_pd.
-                MEM_FORCE_PD: u1,
-                ///  reg_rmt_mem_force_pu.
-                MEM_FORCE_PU: u1,
-                ///  reg_rmt_sclk_div_num.
-                SCLK_DIV_NUM: u8,
-                ///  reg_rmt_sclk_div_a.
-                SCLK_DIV_A: u6,
-                ///  reg_rmt_sclk_div_b.
-                SCLK_DIV_B: u6,
-                ///  reg_rmt_sclk_sel.
-                SCLK_SEL: u2,
-                ///  reg_rmt_sclk_active.
-                SCLK_ACTIVE: u1,
-                reserved31: u4,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-            ///  RMT_TX_SIM_REG.
-            TX_SIM: mmio.Mmio(packed struct(u32) {
-                ///  reg_rmt_tx_sim_ch0.
-                TX_SIM_CH0: u1,
-                ///  reg_rmt_tx_sim_ch1.
-                TX_SIM_CH1: u1,
-                ///  reg_rmt_tx_sim_en.
-                TX_SIM_EN: u1,
-                padding: u29,
-            }),
-            ///  RMT_REF_CNT_RST_REG.
-            REF_CNT_RST: mmio.Mmio(packed struct(u32) {
-                ///  reg_ref_cnt_rst_ch0.
-                CH0: u1,
-                ///  reg_ref_cnt_rst_ch1.
-                CH1: u1,
-                ///  reg_ref_cnt_rst_ch2.
-                CH2: u1,
-                ///  reg_ref_cnt_rst_ch3.
-                CH3: u1,
-                padding: u28,
-            }),
-            reserved204: [88]u8,
-            ///  RMT_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_rmt_date.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Hardware random number generator
-        pub const RNG = extern struct {
-            reserved176: [176]u8,
-            ///  Random number data
-            DATA: u32,
-        };
-
-        ///  RSA (Rivest Shamir Adleman) Accelerator
-        pub const RSA = extern struct {
-            ///  The memory that stores M
-            M_MEM: [16]u8,
-            reserved512: [496]u8,
-            ///  The memory that stores Z
-            Z_MEM: [16]u8,
-            reserved1024: [496]u8,
-            ///  The memory that stores Y
-            Y_MEM: [16]u8,
-            reserved1536: [496]u8,
-            ///  The memory that stores X
-            X_MEM: [16]u8,
-            reserved2048: [496]u8,
-            ///  RSA M_prime register
-            M_PRIME: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores m'
-                M_PRIME: u32,
-            }),
-            ///  RSA mode register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  rsa mode (rsa length).
-                MODE: u7,
-                padding: u25,
-            }),
-            ///  RSA query clean register
-            QUERY_CLEAN: mmio.Mmio(packed struct(u32) {
-                ///  query clean
-                QUERY_CLEAN: u1,
-                padding: u31,
-            }),
-            ///  RSA modular exponentiation trigger register.
-            SET_START_MODEXP: mmio.Mmio(packed struct(u32) {
-                ///  start modular exponentiation
-                SET_START_MODEXP: u1,
-                padding: u31,
-            }),
-            ///  RSA modular multiplication trigger register.
-            SET_START_MODMULT: mmio.Mmio(packed struct(u32) {
-                ///  start modular multiplication
-                SET_START_MODMULT: u1,
-                padding: u31,
-            }),
-            ///  RSA normal multiplication trigger register.
-            SET_START_MULT: mmio.Mmio(packed struct(u32) {
-                ///  start multiplicaiton
-                SET_START_MULT: u1,
-                padding: u31,
-            }),
-            ///  RSA query idle register
-            QUERY_IDLE: mmio.Mmio(packed struct(u32) {
-                ///  query rsa idle. 1'b0: busy, 1'b1: idle
-                QUERY_IDLE: u1,
-                padding: u31,
-            }),
-            ///  RSA interrupt clear register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to clear RSA interrupt.
-                CLEAR_INTERRUPT: u1,
-                padding: u31,
-            }),
-            ///  RSA constant time option register
-            CONSTANT_TIME: mmio.Mmio(packed struct(u32) {
-                ///  Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
-                CONSTANT_TIME: u1,
-                padding: u31,
-            }),
-            ///  RSA search option
-            SEARCH_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
-                SEARCH_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  RSA search position configure register
-            SEARCH_POS: mmio.Mmio(packed struct(u32) {
-                ///  Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
-                SEARCH_POS: u12,
-                padding: u20,
-            }),
-            ///  RSA interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
-                INT_ENA: u1,
-                padding: u31,
-            }),
-            ///  RSA version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  rsa version information
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  Real-Time Clock Control
-        pub const RTC_CNTL = extern struct {
-            ///  rtc configure register
-            OPTIONS0: mmio.Mmio(packed struct(u32) {
-                ///  {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
-                SW_STALL_APPCPU_C0: u2,
-                ///  {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
-                SW_STALL_PROCPU_C0: u2,
-                ///  APP CPU SW reset
-                SW_APPCPU_RST: u1,
-                ///  PRO CPU SW reset
-                SW_PROCPU_RST: u1,
-                ///  BB_I2C force power down
-                BB_I2C_FORCE_PD: u1,
-                ///  BB_I2C force power up
-                BB_I2C_FORCE_PU: u1,
-                ///  BB_PLL _I2C force power down
-                BBPLL_I2C_FORCE_PD: u1,
-                ///  BB_PLL_I2C force power up
-                BBPLL_I2C_FORCE_PU: u1,
-                ///  BB_PLL force power down
-                BBPLL_FORCE_PD: u1,
-                ///  BB_PLL force power up
-                BBPLL_FORCE_PU: u1,
-                ///  crystall force power down
-                XTL_FORCE_PD: u1,
-                ///  crystall force power up
-                XTL_FORCE_PU: u1,
-                ///  wait bias_sleep and current source wakeup
-                XTL_EN_WAIT: u4,
-                reserved20: u2,
-                ///  analog configure
-                XTL_EXT_CTR_SEL: u3,
-                ///  analog configure
-                XTL_FORCE_ISO: u1,
-                ///  analog configure
-                PLL_FORCE_ISO: u1,
-                ///  analog configure
-                ANALOG_FORCE_ISO: u1,
-                ///  analog configure
-                XTL_FORCE_NOISO: u1,
-                ///  analog configure
-                PLL_FORCE_NOISO: u1,
-                ///  analog configure
-                ANALOG_FORCE_NOISO: u1,
-                ///  digital wrap force reset in deep sleep
-                DG_WRAP_FORCE_RST: u1,
-                ///  digital core force no reset in deep sleep
-                DG_WRAP_FORCE_NORST: u1,
-                ///  SW system reset
-                SW_SYS_RST: u1,
-            }),
-            ///  rtc configure register
-            SLP_TIMER0: mmio.Mmio(packed struct(u32) {
-                ///  configure the sleep time
-                SLP_VAL_LO: u32,
-            }),
-            ///  rtc configure register
-            SLP_TIMER1: mmio.Mmio(packed struct(u32) {
-                ///  RTC sleep timer high 16 bits
-                SLP_VAL_HI: u16,
-                ///  timer alarm enable bit
-                RTC_MAIN_TIMER_ALARM_EN: u1,
-                padding: u15,
-            }),
-            ///  rtc configure register
-            TIME_UPDATE: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  Enable to record system stall time
-                TIMER_SYS_STALL: u1,
-                ///  Enable to record 40M XTAL OFF time
-                TIMER_XTL_OFF: u1,
-                ///  enable to record system reset time
-                TIMER_SYS_RST: u1,
-                reserved31: u1,
-                ///  Set 1: to update register with RTC timer
-                RTC_TIME_UPDATE: u1,
-            }),
-            ///  rtc configure register
-            TIME_LOW0: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer low 32 bits
-                RTC_TIMER_VALUE0_LOW: u32,
-            }),
-            ///  rtc configure register
-            TIME_HIGH0: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer high 16 bits
-                RTC_TIMER_VALUE0_HIGH: u16,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            STATE0: mmio.Mmio(packed struct(u32) {
-                ///  rtc software interrupt to main cpu
-                RTC_SW_CPU_INT: u1,
-                ///  clear rtc sleep reject cause
-                RTC_SLP_REJECT_CAUSE_CLR: u1,
-                reserved22: u20,
-                ///  1: APB to RTC using bridge
-                APB2RTC_BRIDGE_SEL: u1,
-                reserved28: u5,
-                ///  SDIO active indication
-                SDIO_ACTIVE_IND: u1,
-                ///  leep wakeup bit
-                SLP_WAKEUP: u1,
-                ///  leep reject bit
-                SLP_REJECT: u1,
-                ///  sleep enable bit
-                SLEEP_EN: u1,
-            }),
-            ///  rtc configure register
-            TIMER1: mmio.Mmio(packed struct(u32) {
-                ///  CPU stall enable bit
-                CPU_STALL_EN: u1,
-                ///  CPU stall wait cycles in fast_clk_rtc
-                CPU_STALL_WAIT: u5,
-                ///  CK8M wait cycles in slow_clk_rtc
-                CK8M_WAIT: u8,
-                ///  XTAL wait cycles in slow_clk_rtc
-                XTL_BUF_WAIT: u10,
-                ///  PLL wait cycles in slow_clk_rtc
-                PLL_BUF_WAIT: u8,
-            }),
-            ///  rtc configure register
-            TIMER2: mmio.Mmio(packed struct(u32) {
-                reserved24: u24,
-                ///  minimal cycles in slow_clk_rtc for CK8M in power down state
-                MIN_TIME_CK8M_OFF: u8,
-            }),
-            ///  rtc configure register
-            TIMER3: mmio.Mmio(packed struct(u32) {
-                ///  wifi power domain wakeup time
-                WIFI_WAIT_TIMER: u9,
-                ///  wifi power domain power on time
-                WIFI_POWERUP_TIMER: u7,
-                ///  bt power domain wakeup time
-                BT_WAIT_TIMER: u9,
-                ///  bt power domain power on time
-                BT_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            TIMER4: mmio.Mmio(packed struct(u32) {
-                ///  cpu top power domain wakeup time
-                CPU_TOP_WAIT_TIMER: u9,
-                ///  cpu top power domain power on time
-                CPU_TOP_POWERUP_TIMER: u7,
-                ///  digital wrap power domain wakeup time
-                DG_WRAP_WAIT_TIMER: u9,
-                ///  digital wrap power domain power on time
-                DG_WRAP_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            TIMER5: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  minimal sleep cycles in slow_clk_rtc
-                MIN_SLP_VAL: u8,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            TIMER6: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  digital peri power domain wakeup time
-                DG_PERI_WAIT_TIMER: u9,
-                ///  digital peri power domain power on time
-                DG_PERI_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            ANA_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  force no bypass i2c power on reset
-                RESET_POR_FORCE_PD: u1,
-                ///  force bypass i2c power on reset
-                RESET_POR_FORCE_PU: u1,
-                ///  enable glitch reset
-                GLITCH_RST_EN: u1,
-                reserved22: u1,
-                ///  PLLA force power up
-                SAR_I2C_PU: u1,
-                ///  PLLA force power down
-                PLLA_FORCE_PD: u1,
-                ///  PLLA force power up
-                PLLA_FORCE_PU: u1,
-                ///  start BBPLL calibration during sleep
-                BBPLL_CAL_SLP_START: u1,
-                ///  1: PVTMON power up
-                PVTMON_PU: u1,
-                ///  1: TXRF_I2C power up
-                TXRF_I2C_PU: u1,
-                ///  1: RFRX_PBUS power up
-                RFRX_PBUS_PU: u1,
-                reserved30: u1,
-                ///  1: CKGEN_I2C power up
-                CKGEN_I2C_PU: u1,
-                ///  power up pll i2c
-                PLL_I2C_PU: u1,
-            }),
-            ///  rtc configure register
-            RESET_STATE: mmio.Mmio(packed struct(u32) {
-                ///  reset cause of PRO CPU
-                RESET_CAUSE_PROCPU: u6,
-                ///  reset cause of APP CPU
-                RESET_CAUSE_APPCPU: u6,
-                ///  APP CPU state vector sel
-                STAT_VECTOR_SEL_APPCPU: u1,
-                ///  PRO CPU state vector sel
-                STAT_VECTOR_SEL_PROCPU: u1,
-                ///  PRO CPU reset_flag
-                ALL_RESET_FLAG_PROCPU: u1,
-                ///  APP CPU reset flag
-                ALL_RESET_FLAG_APPCPU: u1,
-                ///  clear PRO CPU reset_flag
-                ALL_RESET_FLAG_CLR_PROCPU: u1,
-                ///  clear APP CPU reset flag
-                ALL_RESET_FLAG_CLR_APPCPU: u1,
-                ///  APPCPU OcdHaltOnReset
-                OCD_HALT_ON_RESET_APPCPU: u1,
-                ///  PROCPU OcdHaltOnReset
-                OCD_HALT_ON_RESET_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_APPCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_CLR_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_CLR_APPCPU: u1,
-                ///  configure dreset configure
-                RTC_DRESET_MASK_APPCPU: u1,
-                ///  configure dreset configure
-                RTC_DRESET_MASK_PROCPU: u1,
-                padding: u6,
-            }),
-            ///  rtc configure register
-            WAKEUP_STATE: mmio.Mmio(packed struct(u32) {
-                reserved15: u15,
-                ///  wakeup enable bitmap
-                RTC_WAKEUP_ENA: u17,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC: mmio.Mmio(packed struct(u32) {
-                ///  enable sleep wakeup interrupt
-                SLP_WAKEUP_INT_ENA: u1,
-                ///  enable sleep reject interrupt
-                SLP_REJECT_INT_ENA: u1,
-                reserved3: u1,
-                ///  enable RTC WDT interrupt
-                RTC_WDT_INT_ENA: u1,
-                reserved9: u5,
-                ///  enable brown out interrupt
-                RTC_BROWN_OUT_INT_ENA: u1,
-                ///  enable RTC main timer interrupt
-                RTC_MAIN_TIMER_INT_ENA: u1,
-                reserved15: u4,
-                ///  enable super watch dog interrupt
-                RTC_SWD_INT_ENA: u1,
-                ///  enable xtal32k_dead interrupt
-                RTC_XTAL32K_DEAD_INT_ENA: u1,
-                reserved19: u2,
-                ///  enbale gitch det interrupt
-                RTC_GLITCH_DET_INT_ENA: u1,
-                ///  enbale bbpll cal end interrupt
-                RTC_BBPLL_CAL_INT_ENA: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_RAW_RTC: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup interrupt raw
-                SLP_WAKEUP_INT_RAW: u1,
-                ///  sleep reject interrupt raw
-                SLP_REJECT_INT_RAW: u1,
-                reserved3: u1,
-                ///  RTC WDT interrupt raw
-                RTC_WDT_INT_RAW: u1,
-                reserved9: u5,
-                ///  brown out interrupt raw
-                RTC_BROWN_OUT_INT_RAW: u1,
-                ///  RTC main timer interrupt raw
-                RTC_MAIN_TIMER_INT_RAW: u1,
-                reserved15: u4,
-                ///  super watch dog interrupt raw
-                RTC_SWD_INT_RAW: u1,
-                ///  xtal32k dead detection interrupt raw
-                RTC_XTAL32K_DEAD_INT_RAW: u1,
-                reserved19: u2,
-                ///  glitch_det_interrupt_raw
-                RTC_GLITCH_DET_INT_RAW: u1,
-                ///  bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_RAW: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_ST_RTC: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup interrupt state
-                SLP_WAKEUP_INT_ST: u1,
-                ///  sleep reject interrupt state
-                SLP_REJECT_INT_ST: u1,
-                reserved3: u1,
-                ///  RTC WDT interrupt state
-                RTC_WDT_INT_ST: u1,
-                reserved9: u5,
-                ///  brown out interrupt state
-                RTC_BROWN_OUT_INT_ST: u1,
-                ///  RTC main timer interrupt state
-                RTC_MAIN_TIMER_INT_ST: u1,
-                reserved15: u4,
-                ///  super watch dog interrupt state
-                RTC_SWD_INT_ST: u1,
-                ///  xtal32k dead detection interrupt state
-                RTC_XTAL32K_DEAD_INT_ST: u1,
-                reserved19: u2,
-                ///  glitch_det_interrupt state
-                RTC_GLITCH_DET_INT_ST: u1,
-                ///  bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_ST: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_CLR_RTC: mmio.Mmio(packed struct(u32) {
-                ///  Clear sleep wakeup interrupt state
-                SLP_WAKEUP_INT_CLR: u1,
-                ///  Clear sleep reject interrupt state
-                SLP_REJECT_INT_CLR: u1,
-                reserved3: u1,
-                ///  Clear RTC WDT interrupt state
-                RTC_WDT_INT_CLR: u1,
-                reserved9: u5,
-                ///  Clear brown out interrupt state
-                RTC_BROWN_OUT_INT_CLR: u1,
-                ///  Clear RTC main timer interrupt state
-                RTC_MAIN_TIMER_INT_CLR: u1,
-                reserved15: u4,
-                ///  Clear super watch dog interrupt state
-                RTC_SWD_INT_CLR: u1,
-                ///  Clear RTC WDT interrupt state
-                RTC_XTAL32K_DEAD_INT_CLR: u1,
-                reserved19: u2,
-                ///  Clear glitch det interrupt state
-                RTC_GLITCH_DET_INT_CLR: u1,
-                ///  clear bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_CLR: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            STORE0: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH0: u32,
-            }),
-            ///  rtc configure register
-            STORE1: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH1: u32,
-            }),
-            ///  rtc configure register
-            STORE2: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH2: u32,
-            }),
-            ///  rtc configure register
-            STORE3: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH3: u32,
-            }),
-            ///  rtc configure register
-            EXT_XTL_CONF: mmio.Mmio(packed struct(u32) {
-                ///  xtal 32k watch dog enable
-                XTAL32K_WDT_EN: u1,
-                ///  xtal 32k watch dog clock force on
-                XTAL32K_WDT_CLK_FO: u1,
-                ///  xtal 32k watch dog sw reset
-                XTAL32K_WDT_RESET: u1,
-                ///  xtal 32k external xtal clock force on
-                XTAL32K_EXT_CLK_FO: u1,
-                ///  xtal 32k switch to back up clock when xtal is dead
-                XTAL32K_AUTO_BACKUP: u1,
-                ///  xtal 32k restart xtal when xtal is dead
-                XTAL32K_AUTO_RESTART: u1,
-                ///  xtal 32k switch back xtal when xtal is restarted
-                XTAL32K_AUTO_RETURN: u1,
-                ///  Xtal 32k xpd control by sw or fsm
-                XTAL32K_XPD_FORCE: u1,
-                ///  apply an internal clock to help xtal 32k to start
-                ENCKINIT_XTAL_32K: u1,
-                ///  0: single-end buffer 1: differential buffer
-                DBUF_XTAL_32K: u1,
-                ///  xtal_32k gm control
-                DGM_XTAL_32K: u3,
-                ///  DRES_XTAL_32K
-                DRES_XTAL_32K: u3,
-                ///  XPD_XTAL_32K
-                XPD_XTAL_32K: u1,
-                ///  DAC_XTAL_32K
-                DAC_XTAL_32K: u3,
-                ///  state of 32k_wdt
-                RTC_WDT_STATE: u3,
-                ///  XTAL_32K sel. 0: external XTAL_32K
-                RTC_XTAL32K_GPIO_SEL: u1,
-                reserved30: u6,
-                ///  0: power down XTAL at high level
-                XTL_EXT_CTR_LV: u1,
-                ///  enable gpio configure xtal power on
-                XTL_EXT_CTR_EN: u1,
-            }),
-            ///  rtc configure register
-            EXT_WAKEUP_CONF: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  enable filter for gpio wakeup event
-                GPIO_WAKEUP_FILTER: u1,
-            }),
-            ///  rtc configure register
-            SLP_REJECT_CONF: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  sleep reject enable
-                RTC_SLEEP_REJECT_ENA: u18,
-                ///  enable reject for light sleep
-                LIGHT_SLP_REJECT_EN: u1,
-                ///  enable reject for deep sleep
-                DEEP_SLP_REJECT_EN: u1,
-            }),
-            ///  rtc configure register
-            CPU_PERIOD_CONF: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  CPU sel option
-                RTC_CPUSEL_CONF: u1,
-                ///  CPU clk sel option
-                RTC_CPUPERIOD_SEL: u2,
-            }),
-            ///  rtc configure register
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  efuse_clk_force_gating
-                EFUSE_CLK_FORCE_GATING: u1,
-                ///  efuse_clk_force_nogating
-                EFUSE_CLK_FORCE_NOGATING: u1,
-                ///  used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
-                CK8M_DIV_SEL_VLD: u1,
-                ///  CK8M_D256_OUT divider. 00: div128
-                CK8M_DIV: u2,
-                ///  disable CK8M and CK8M_D256_OUT
-                ENB_CK8M: u1,
-                ///  1: CK8M_D256_OUT is actually CK8M
-                ENB_CK8M_DIV: u1,
-                ///  enable CK_XTAL_32K for digital core (no relationship with RTC core)
-                DIG_XTAL32K_EN: u1,
-                ///  enable CK8M_D256_OUT for digital core (no relationship with RTC core)
-                DIG_CLK8M_D256_EN: u1,
-                ///  enable CK8M for digital core (no relationship with RTC core)
-                DIG_CLK8M_EN: u1,
-                reserved12: u1,
-                ///  divider = reg_ck8m_div_sel + 1
-                CK8M_DIV_SEL: u3,
-                ///  XTAL force no gating during sleep
-                XTAL_FORCE_NOGATING: u1,
-                ///  CK8M force no gating during sleep
-                CK8M_FORCE_NOGATING: u1,
-                ///  CK8M_DFREQ
-                CK8M_DFREQ: u8,
-                ///  CK8M force power down
-                CK8M_FORCE_PD: u1,
-                ///  CK8M force power up
-                CK8M_FORCE_PU: u1,
-                ///  force enable xtal clk gating
-                XTAL_GLOBAL_FORCE_GATING: u1,
-                ///  force bypass xtal clk gating
-                XTAL_GLOBAL_FORCE_NOGATING: u1,
-                ///  fast_clk_rtc sel. 0: XTAL div 4
-                FAST_CLK_RTC_SEL: u1,
-                ///  slelect rtc slow clk
-                ANA_CLK_RTC_SEL: u2,
-            }),
-            ///  rtc configure register
-            SLOW_CLK_CONF: mmio.Mmio(packed struct(u32) {
-                reserved22: u22,
-                ///  used to sync div bus. clear vld before set reg_rtc_ana_clk_div
-                RTC_ANA_CLK_DIV_VLD: u1,
-                ///  the clk divider num of RTC_CLK
-                RTC_ANA_CLK_DIV: u8,
-                ///  flag rtc_slow_clk_next_edge
-                RTC_SLOW_CLK_NEXT_EDGE: u1,
-            }),
-            ///  rtc configure register
-            SDIO_CONF: mmio.Mmio(packed struct(u32) {
-                ///  timer count to apply reg_sdio_dcap after sdio power on
-                SDIO_TIMER_TARGET: u8,
-                reserved9: u1,
-                ///  Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
-                SDIO_DTHDRV: u2,
-                ///  ability to prevent LDO from overshoot
-                SDIO_DCAP: u2,
-                ///  add resistor from ldo output to ground. 0: no res
-                SDIO_INITI: u2,
-                ///  0 to set init[1:0]=0
-                SDIO_EN_INITI: u1,
-                ///  tune current limit threshold when tieh = 0. About 800mA/(8+d)
-                SDIO_DCURLIM: u3,
-                ///  select current limit mode
-                SDIO_MODECURLIM: u1,
-                ///  enable current limit
-                SDIO_ENCURLIM: u1,
-                ///  power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
-                SDIO_REG_PD_EN: u1,
-                ///  1: use SW option to control SDIO_REG
-                SDIO_FORCE: u1,
-                ///  SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
-                SDIO_TIEH: u1,
-                ///  read only register for REG1P8_READY
-                _1P8_READY: u1,
-                ///  SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
-                DREFL_SDIO: u2,
-                ///  SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
-                DREFM_SDIO: u2,
-                ///  SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
-                DREFH_SDIO: u2,
-                XPD_SDIO: u1,
-            }),
-            ///  rtc configure register
-            BIAS_CONF: mmio.Mmio(packed struct(u32) {
-                DG_VDD_DRV_B_SLP: u8,
-                DG_VDD_DRV_B_SLP_EN: u1,
-                reserved10: u1,
-                ///  bias buf when rtc in normal work state
-                BIAS_BUF_IDLE: u1,
-                ///  bias buf when rtc in wakeup state
-                BIAS_BUF_WAKE: u1,
-                ///  bias buf when rtc in sleep state
-                BIAS_BUF_DEEP_SLP: u1,
-                ///  bias buf when rtc in monitor state
-                BIAS_BUF_MONITOR: u1,
-                ///  xpd cur when rtc in sleep_state
-                PD_CUR_DEEP_SLP: u1,
-                ///  xpd cur when rtc in monitor state
-                PD_CUR_MONITOR: u1,
-                ///  bias_sleep when rtc in sleep_state
-                BIAS_SLEEP_DEEP_SLP: u1,
-                ///  bias_sleep when rtc in monitor state
-                BIAS_SLEEP_MONITOR: u1,
-                ///  DBG_ATTEN when rtc in sleep state
-                DBG_ATTEN_DEEP_SLP: u4,
-                ///  DBG_ATTEN when rtc in monitor state
-                DBG_ATTEN_MONITOR: u4,
-                padding: u6,
-            }),
-            ///  rtc configure register
-            RTC_CNTL: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  software enable digital regulator cali
-                DIG_REG_CAL_EN: u1,
-                reserved14: u6,
-                ///  SCK_DCAP
-                SCK_DCAP: u8,
-                reserved28: u6,
-                ///  RTC_DBOOST force power down
-                DBOOST_FORCE_PD: u1,
-                ///  RTC_DBOOST force power up
-                DBOOST_FORCE_PU: u1,
-                ///  RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
-                REGULATOR_FORCE_PD: u1,
-                ///  RTC_REG force power up
-                REGULATOR_FORCE_PU: u1,
-            }),
-            ///  rtc configure register
-            PWC: mmio.Mmio(packed struct(u32) {
-                reserved21: u21,
-                ///  rtc pad force hold
-                RTC_PAD_FORCE_HOLD: u1,
-                padding: u10,
-            }),
-            ///  rtc configure register
-            DIG_PWC: mmio.Mmio(packed struct(u32) {
-                ///  vdd_spi drv's software value
-                VDD_SPI_PWR_DRV: u2,
-                ///  vdd_spi drv use software value
-                VDD_SPI_PWR_FORCE: u1,
-                ///  memories in digital core force PD in sleep
-                LSLP_MEM_FORCE_PD: u1,
-                ///  memories in digital core force PU in sleep
-                LSLP_MEM_FORCE_PU: u1,
-                reserved11: u6,
-                ///  bt force power down
-                BT_FORCE_PD: u1,
-                ///  bt force power up
-                BT_FORCE_PU: u1,
-                ///  digital peri force power down
-                DG_PERI_FORCE_PD: u1,
-                ///  digital peri force power up
-                DG_PERI_FORCE_PU: u1,
-                ///  fastmemory retention mode in sleep
-                RTC_FASTMEM_FORCE_LPD: u1,
-                ///  fastmemory donlt entry retention mode in sleep
-                RTC_FASTMEM_FORCE_LPU: u1,
-                ///  wifi force power down
-                WIFI_FORCE_PD: u1,
-                ///  wifi force power up
-                WIFI_FORCE_PU: u1,
-                ///  digital core force power down
-                DG_WRAP_FORCE_PD: u1,
-                ///  digital core force power up
-                DG_WRAP_FORCE_PU: u1,
-                ///  cpu core force power down
-                CPU_TOP_FORCE_PD: u1,
-                ///  cpu force power up
-                CPU_TOP_FORCE_PU: u1,
-                reserved27: u4,
-                ///  enable power down bt in sleep
-                BT_PD_EN: u1,
-                ///  enable power down digital peri in sleep
-                DG_PERI_PD_EN: u1,
-                ///  enable power down cpu in sleep
-                CPU_TOP_PD_EN: u1,
-                ///  enable power down wifi in sleep
-                WIFI_PD_EN: u1,
-                ///  enable power down digital wrap in sleep
-                DG_WRAP_PD_EN: u1,
-            }),
-            ///  rtc configure register
-            DIG_ISO: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  DIG_ISO force off
-                FORCE_OFF: u1,
-                ///  DIG_ISO force on
-                FORCE_ON: u1,
-                ///  read only register to indicate digital pad auto-hold status
-                DG_PAD_AUTOHOLD: u1,
-                ///  wtite only register to clear digital pad auto-hold
-                CLR_DG_PAD_AUTOHOLD: u1,
-                ///  digital pad enable auto-hold
-                DG_PAD_AUTOHOLD_EN: u1,
-                ///  digital pad force no ISO
-                DG_PAD_FORCE_NOISO: u1,
-                ///  digital pad force ISO
-                DG_PAD_FORCE_ISO: u1,
-                ///  digital pad force un-hold
-                DG_PAD_FORCE_UNHOLD: u1,
-                ///  digital pad force hold
-                DG_PAD_FORCE_HOLD: u1,
-                reserved22: u6,
-                ///  bt force ISO
-                BT_FORCE_ISO: u1,
-                ///  bt force no ISO
-                BT_FORCE_NOISO: u1,
-                ///  Digital peri force ISO
-                DG_PERI_FORCE_ISO: u1,
-                ///  digital peri force no ISO
-                DG_PERI_FORCE_NOISO: u1,
-                ///  cpu force ISO
-                CPU_TOP_FORCE_ISO: u1,
-                ///  cpu force no ISO
-                CPU_TOP_FORCE_NOISO: u1,
-                ///  wifi force ISO
-                WIFI_FORCE_ISO: u1,
-                ///  wifi force no ISO
-                WIFI_FORCE_NOISO: u1,
-                ///  digital core force ISO
-                DG_WRAP_FORCE_ISO: u1,
-                ///  digital core force no ISO
-                DG_WRAP_FORCE_NOISO: u1,
-            }),
-            ///  rtc configure register
-            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
-                ///  chip reset siginal pulse width
-                WDT_CHIP_RESET_WIDTH: u8,
-                ///  wdt reset whole chip enable
-                WDT_CHIP_RESET_EN: u1,
-                ///  pause WDT in sleep
-                WDT_PAUSE_IN_SLP: u1,
-                ///  enable WDT reset APP CPU
-                WDT_APPCPU_RESET_EN: u1,
-                ///  enable WDT reset PRO CPU
-                WDT_PROCPU_RESET_EN: u1,
-                ///  enable WDT in flash boot
-                WDT_FLASHBOOT_MOD_EN: u1,
-                ///  system reset counter length
-                WDT_SYS_RESET_LENGTH: u3,
-                ///  CPU reset counter length
-                WDT_CPU_RESET_LENGTH: u3,
-                ///  1: interrupt stage en
-                WDT_STG3: u3,
-                ///  1: interrupt stage en
-                WDT_STG2: u3,
-                ///  1: interrupt stage en
-                WDT_STG1: u3,
-                ///  1: interrupt stage en
-                WDT_STG0: u3,
-                ///  enable rtc wdt
-                WDT_EN: u1,
-            }),
-            ///  rtc configure register
-            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage0
-                WDT_STG0_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage1
-                WDT_STG1_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage2
-                WDT_STG2_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage3
-                WDT_STG3_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTFEED: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  sw feed rtc wdt
-                RTC_WDT_FEED: u1,
-            }),
-            ///  rtc configure register
-            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  the key of rtc wdt
-                WDT_WKEY: u32,
-            }),
-            ///  rtc configure register
-            SWD_CONF: mmio.Mmio(packed struct(u32) {
-                ///  swd reset flag
-                SWD_RESET_FLAG: u1,
-                ///  swd interrupt for feeding
-                SWD_FEED_INT: u1,
-                reserved17: u15,
-                ///  Bypass swd rst
-                SWD_BYPASS_RST: u1,
-                ///  adjust signal width send to swd
-                SWD_SIGNAL_WIDTH: u10,
-                ///  reset swd reset flag
-                SWD_RST_FLAG_CLR: u1,
-                ///  Sw feed swd
-                SWD_FEED: u1,
-                ///  disabel SWD
-                SWD_DISABLE: u1,
-                ///  automatically feed swd when int comes
-                SWD_AUTO_FEED_EN: u1,
-            }),
-            ///  rtc configure register
-            SWD_WPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  the key of super wdt
-                SWD_WKEY: u32,
-            }),
-            ///  rtc configure register
-            SW_CPU_STALL: mmio.Mmio(packed struct(u32) {
-                reserved20: u20,
-                ///  {reg_sw_stall_appcpu_c1[5:0]
-                SW_STALL_APPCPU_C1: u6,
-                ///  stall cpu by software
-                SW_STALL_PROCPU_C1: u6,
-            }),
-            ///  rtc configure register
-            STORE4: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH4: u32,
-            }),
-            ///  rtc configure register
-            STORE5: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH5: u32,
-            }),
-            ///  rtc configure register
-            STORE6: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH6: u32,
-            }),
-            ///  rtc configure register
-            STORE7: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH7: u32,
-            }),
-            ///  rtc configure register
-            LOW_POWER_ST: mmio.Mmio(packed struct(u32) {
-                ///  rom0 power down
-                XPD_ROM0: u1,
-                reserved2: u1,
-                ///  External DCDC power down
-                XPD_DIG_DCDC: u1,
-                ///  rtc peripheral iso
-                RTC_PERI_ISO: u1,
-                ///  rtc peripheral power down
-                XPD_RTC_PERI: u1,
-                ///  wifi iso
-                WIFI_ISO: u1,
-                ///  wifi wrap power down
-                XPD_WIFI: u1,
-                ///  digital wrap iso
-                DIG_ISO: u1,
-                ///  digital wrap power down
-                XPD_DIG: u1,
-                ///  touch should start to work
-                RTC_TOUCH_STATE_START: u1,
-                ///  touch is about to working. Switch rtc main state
-                RTC_TOUCH_STATE_SWITCH: u1,
-                ///  touch is in sleep state
-                RTC_TOUCH_STATE_SLP: u1,
-                ///  touch is done
-                RTC_TOUCH_STATE_DONE: u1,
-                ///  ulp/cocpu should start to work
-                RTC_COCPU_STATE_START: u1,
-                ///  ulp/cocpu is about to working. Switch rtc main state
-                RTC_COCPU_STATE_SWITCH: u1,
-                ///  ulp/cocpu is in sleep state
-                RTC_COCPU_STATE_SLP: u1,
-                ///  ulp/cocpu is done
-                RTC_COCPU_STATE_DONE: u1,
-                ///  no use any more
-                RTC_MAIN_STATE_XTAL_ISO: u1,
-                ///  rtc main state machine is in states that pll should be running
-                RTC_MAIN_STATE_PLL_ON: u1,
-                ///  rtc is ready to receive wake up trigger from wake up source
-                RTC_RDY_FOR_WAKEUP: u1,
-                ///  rtc main state machine has been waited for some cycles
-                RTC_MAIN_STATE_WAIT_END: u1,
-                ///  rtc main state machine is in the states of wakeup process
-                RTC_IN_WAKEUP_STATE: u1,
-                ///  rtc main state machine is in the states of low power
-                RTC_IN_LOW_POWER_STATE: u1,
-                ///  rtc main state machine is in wait 8m state
-                RTC_MAIN_STATE_IN_WAIT_8M: u1,
-                ///  rtc main state machine is in wait pll state
-                RTC_MAIN_STATE_IN_WAIT_PLL: u1,
-                ///  rtc main state machine is in wait xtal state
-                RTC_MAIN_STATE_IN_WAIT_XTL: u1,
-                ///  rtc main state machine is in sleep state
-                RTC_MAIN_STATE_IN_SLP: u1,
-                ///  rtc main state machine is in idle state
-                RTC_MAIN_STATE_IN_IDLE: u1,
-                ///  rtc main state machine status
-                RTC_MAIN_STATE: u4,
-            }),
-            ///  rtc configure register
-            DIAG0: mmio.Mmio(packed struct(u32) {
-                RTC_LOW_POWER_DIAG1: u32,
-            }),
-            ///  rtc configure register
-            PAD_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  the hold configure of rtc gpio0
-                RTC_GPIO_PIN0_HOLD: u1,
-                ///  the hold configure of rtc gpio1
-                RTC_GPIO_PIN1_HOLD: u1,
-                ///  the hold configure of rtc gpio2
-                RTC_GPIO_PIN2_HOLD: u1,
-                ///  the hold configure of rtc gpio3
-                RTC_GPIO_PIN3_HOLD: u1,
-                ///  the hold configure of rtc gpio4
-                RTC_GPIO_PIN4_HOLD: u1,
-                ///  the hold configure of rtc gpio5
-                RTC_GPIO_PIN5_HOLD: u1,
-                padding: u26,
-            }),
-            ///  rtc configure register
-            DIG_PAD_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  the configure of digital pad
-                DIG_PAD_HOLD: u32,
-            }),
-            ///  rtc configure register
-            BROWN_OUT: mmio.Mmio(packed struct(u32) {
-                reserved4: u4,
-                ///  brown out interrupt wait cycles
-                INT_WAIT: u10,
-                ///  enable close flash when brown out happens
-                CLOSE_FLASH_ENA: u1,
-                ///  enable power down RF when brown out happens
-                PD_RF_ENA: u1,
-                ///  brown out reset wait cycles
-                RST_WAIT: u10,
-                ///  enable brown out reset
-                RST_ENA: u1,
-                ///  1: 4-pos reset
-                RST_SEL: u1,
-                ///  brown_out origin reset enable
-                ANA_RST_EN: u1,
-                ///  clear brown out counter
-                CNT_CLR: u1,
-                ///  enable brown out
-                ENA: u1,
-                ///  the flag of brown det from analog
-                DET: u1,
-            }),
-            ///  rtc configure register
-            TIME_LOW1: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer low 32 bits
-                RTC_TIMER_VALUE1_LOW: u32,
-            }),
-            ///  rtc configure register
-            TIME_HIGH1: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer high 16 bits
-                RTC_TIMER_VALUE1_HIGH: u16,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            XTAL32K_CLK_FACTOR: mmio.Mmio(packed struct(u32) {
-                ///  xtal 32k watch dog backup clock factor
-                XTAL32K_CLK_FACTOR: u32,
-            }),
-            ///  rtc configure register
-            XTAL32K_CONF: mmio.Mmio(packed struct(u32) {
-                ///  cycles to wait to return noral xtal 32k
-                XTAL32K_RETURN_WAIT: u4,
-                ///  cycles to wait to repower on xtal 32k
-                XTAL32K_RESTART_WAIT: u16,
-                ///  If no clock detected for this amount of time
-                XTAL32K_WDT_TIMEOUT: u8,
-                ///  if restarted xtal32k period is smaller than this
-                XTAL32K_STABLE_THRES: u4,
-            }),
-            ///  rtc configure register
-            USB_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  disable io_mux reset
-                IO_MUX_RESET_DISABLE: u1,
-                padding: u13,
-            }),
-            ///  RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
-            SLP_REJECT_CAUSE: mmio.Mmio(packed struct(u32) {
-                ///  sleep reject cause
-                REJECT_CAUSE: u18,
-                padding: u14,
-            }),
-            ///  rtc configure register
-            OPTION1: mmio.Mmio(packed struct(u32) {
-                ///  force chip entry download mode
-                FORCE_DOWNLOAD_BOOT: u1,
-                padding: u31,
-            }),
-            ///  RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
-            SLP_WAKEUP_CAUSE: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup cause
-                WAKEUP_CAUSE: u17,
-                padding: u15,
-            }),
-            ///  rtc configure register
-            ULP_CP_TIMER_1: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  sleep cycles for ULP-coprocessor timer
-                ULP_CP_TIMER_SLP_CYCLE: u24,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  enable sleep wakeup interrupt
-                SLP_WAKEUP_INT_ENA_W1TS: u1,
-                ///  enable sleep reject interrupt
-                SLP_REJECT_INT_ENA_W1TS: u1,
-                reserved3: u1,
-                ///  enable RTC WDT interrupt
-                RTC_WDT_INT_ENA_W1TS: u1,
-                reserved9: u5,
-                ///  enable brown out interrupt
-                RTC_BROWN_OUT_INT_ENA_W1TS: u1,
-                ///  enable RTC main timer interrupt
-                RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
-                reserved15: u4,
-                ///  enable super watch dog interrupt
-                RTC_SWD_INT_ENA_W1TS: u1,
-                ///  enable xtal32k_dead interrupt
-                RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
-                reserved19: u2,
-                ///  enbale gitch det interrupt
-                RTC_GLITCH_DET_INT_ENA_W1TS: u1,
-                ///  enbale bbpll cal interrupt
-                RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  clear sleep wakeup interrupt enable
-                SLP_WAKEUP_INT_ENA_W1TC: u1,
-                ///  clear sleep reject interrupt enable
-                SLP_REJECT_INT_ENA_W1TC: u1,
-                reserved3: u1,
-                ///  clear RTC WDT interrupt enable
-                RTC_WDT_INT_ENA_W1TC: u1,
-                reserved9: u5,
-                ///  clear brown out interrupt enable
-                RTC_BROWN_OUT_INT_ENA_W1TC: u1,
-                ///  Clear RTC main timer interrupt enable
-                RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
-                reserved15: u4,
-                ///  clear super watch dog interrupt enable
-                RTC_SWD_INT_ENA_W1TC: u1,
-                ///  clear xtal32k_dead interrupt enable
-                RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
-                reserved19: u2,
-                ///  clear gitch det interrupt enable
-                RTC_GLITCH_DET_INT_ENA_W1TC: u1,
-                ///  clear bbpll cal interrupt enable
-                RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  Retention clk sel
-                RETENTION_CLK_SEL: u1,
-                ///  Retention done wait time
-                RETENTION_DONE_WAIT: u3,
-                ///  Retention clkoff wait time
-                RETENTION_CLKOFF_WAIT: u4,
-                ///  enable cpu retention when light sleep
-                RETENTION_EN: u1,
-                ///  wait cycles for rention operation
-                RETENTION_WAIT: u5,
-            }),
-            ///  rtc configure register
-            FIB_SEL: mmio.Mmio(packed struct(u32) {
-                ///  select use analog fib signal
-                RTC_FIB_SEL: u3,
-                padding: u29,
-            }),
-            ///  rtc configure register
-            GPIO_WAKEUP: mmio.Mmio(packed struct(u32) {
-                ///  rtc gpio wakeup flag
-                RTC_GPIO_WAKEUP_STATUS: u6,
-                ///  clear rtc gpio wakeup flag
-                RTC_GPIO_WAKEUP_STATUS_CLR: u1,
-                ///  enable rtc io clk gate
-                RTC_GPIO_PIN_CLK_GATE: u1,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN5_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN4_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN3_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN2_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN1_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN0_INT_TYPE: u3,
-                ///  enable wakeup from rtc gpio5
-                RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio4
-                RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio3
-                RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio2
-                RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio1
-                RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio0
-                RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
-            }),
-            ///  rtc configure register
-            DBG_SEL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  use for debug
-                RTC_DEBUG_12M_NO_GATING: u1,
-                ///  use for debug
-                RTC_DEBUG_BIT_SEL: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL0: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL1: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL2: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL3: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL4: u5,
-            }),
-            ///  rtc configure register
-            DBG_MAP: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  use for debug
-                RTC_GPIO_PIN5_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN4_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN3_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN2_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN1_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN0_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN5_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN4_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN3_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN2_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN1_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN0_FUN_SEL: u4,
-            }),
-            ///  rtc configure register
-            SENSOR_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  reg_sar2_pwdet_cct
-                SAR2_PWDET_CCT: u3,
-                ///  force power up SAR
-                FORCE_XPD_SAR: u2,
-            }),
-            ///  rtc configure register
-            DBG_SAR_SEL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  use for debug
-                SAR_DEBUG_SEL: u5,
-            }),
-            ///  rtc configure register
-            PG_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  power glitch desense
-                POWER_GLITCH_DSENSE: u2,
-                ///  force disable power glitch
-                POWER_GLITCH_FORCE_PD: u1,
-                ///  force enable power glitch
-                POWER_GLITCH_FORCE_PU: u1,
-                ///  use efuse value control power glitch enable
-                POWER_GLITCH_EFUSE_SEL: u1,
-                ///  enable power glitch
-                POWER_GLITCH_EN: u1,
-            }),
-            reserved508: [212]u8,
-            ///  rtc configure register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  verision
-                RTC_CNTL_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Sensitive
-        pub const SENSITIVE = extern struct {
-            ///  SENSITIVE_ROM_TABLE_LOCK_REG
-            ROM_TABLE_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  rom_table_lock
-                ROM_TABLE_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_ROM_TABLE_REG
-            ROM_TABLE: mmio.Mmio(packed struct(u32) {
-                ///  rom_table
-                ROM_TABLE: u32,
-            }),
-            ///  SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
-            PRIVILEGE_MODE_SEL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  privilege_mode_sel_lock
-                PRIVILEGE_MODE_SEL_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_PRIVILEGE_MODE_SEL_REG
-            PRIVILEGE_MODE_SEL: mmio.Mmio(packed struct(u32) {
-                ///  privilege_mode_sel
-                PRIVILEGE_MODE_SEL: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
-            APB_PERIPHERAL_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  apb_peripheral_access_lock
-                APB_PERIPHERAL_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
-            APB_PERIPHERAL_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  apb_peripheral_access_split_burst
-                APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
-            INTERNAL_SRAM_USAGE_0: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_lock
-                INTERNAL_SRAM_USAGE_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
-            INTERNAL_SRAM_USAGE_1: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_cpu_cache
-                INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
-                ///  internal_sram_usage_cpu_sram
-                INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
-                padding: u28,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
-            INTERNAL_SRAM_USAGE_3: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_mac_dump_sram
-                INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
-                ///  internal_sram_alloc_mac_dump
-                INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
-                padding: u28,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
-            INTERNAL_SRAM_USAGE_4: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_log_sram
-                INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_TAG_ACCESS_0_REG
-            CACHE_TAG_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  cache_tag_access_lock
-                CACHE_TAG_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_TAG_ACCESS_1_REG
-            CACHE_TAG_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  pro_i_tag_rd_acs
-                PRO_I_TAG_RD_ACS: u1,
-                ///  pro_i_tag_wr_acs
-                PRO_I_TAG_WR_ACS: u1,
-                ///  pro_d_tag_rd_acs
-                PRO_D_TAG_RD_ACS: u1,
-                ///  pro_d_tag_wr_acs
-                PRO_D_TAG_WR_ACS: u1,
-                padding: u28,
-            }),
-            ///  SENSITIVE_CACHE_MMU_ACCESS_0_REG
-            CACHE_MMU_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  cache_mmu_access_lock
-                CACHE_MMU_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_MMU_ACCESS_1_REG
-            CACHE_MMU_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  pro_mmu_rd_acs
-                PRO_MMU_RD_ACS: u1,
-                ///  pro_mmu_wr_acs
-                PRO_MMU_WR_ACS: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_spi2_pms_constrain_lock
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_uchi0_pms_constrain_lock
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_i2s0_pms_constrain_lock
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_mac_pms_constrain_lock
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_backup_pms_constrain_lock
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_LC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_lc_pms_constrain_lock
-                DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_LC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_AES_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_aes_pms_constrain_lock
-                DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_AES_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_sha_pms_constrain_lock
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_adc_dac_pms_constrain_lock
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
-            DMA_APBPERI_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_lock
-                DMA_APBPERI_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
-            DMA_APBPERI_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_clr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  dma_apbperi_pms_monitor_violate_en
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
-            DMA_APBPERI_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_intr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  dma_apbperi_pms_monitor_violate_status_world
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  dma_apbperi_pms_monitor_violate_status_addr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u5,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
-            DMA_APBPERI_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_status_wr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  dma_apbperi_pms_monitor_violate_status_byteen
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_dram0_dma_split_line_constrain_lock
-                CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_dram0_dma_sram_category_0
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
-                ///  core_x_iram0_dram0_dma_sram_category_1
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
-                ///  core_x_iram0_dram0_dma_sram_category_2
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_dram0_dma_sram_splitaddr
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_sram_line_0_category_0
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
-                ///  core_x_iram0_sram_line_0_category_1
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
-                ///  core_x_iram0_sram_line_0_category_2
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_sram_line_0_splitaddr
-                CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_sram_line_1_category_0
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
-                ///  core_x_iram0_sram_line_1_category_1
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
-                ///  core_x_iram0_sram_line_1_category_2
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_sram_line_1_splitaddr
-                CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_dma_sram_line_0_category_0
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
-                ///  core_x_dram0_dma_sram_line_0_category_1
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
-                ///  core_x_dram0_dma_sram_line_0_category_2
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_dram0_dma_sram_line_0_splitaddr
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_dma_sram_line_1_category_0
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
-                ///  core_x_dram0_dma_sram_line_1_category_1
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
-                ///  core_x_dram0_dma_sram_line_1_category_2
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_dram0_dma_sram_line_1_splitaddr
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_lock
-                CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_1
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_2
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_3
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
-                reserved18: u3,
-                ///  core_x_iram0_pms_constrain_rom_world_1_pms
-                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
-                padding: u11,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_1
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_2
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_3
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
-                reserved18: u3,
-                ///  core_x_iram0_pms_constrain_rom_world_0_pms
-                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
-                padding: u11,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
-            CORE_0_IRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_lock
-                CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
-            CORE_0_IRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_violate_clr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_iram0_pms_monitor_violate_en
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
-            CORE_0_IRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_violate_intr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_wr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_loadstore
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_world
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  core_0_iram0_pms_monitor_violate_status_addr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u3,
-            }),
-            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
-            CORE_X_DRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_pms_constrain_lock
-                CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
-            CORE_X_DRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_0
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_1
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_2
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_3
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_0
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_1
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_2
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_3
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                reserved24: u4,
-                ///  core_x_dram0_pms_constrain_rom_world_0_pms
-                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
-                ///  core_x_dram0_pms_constrain_rom_world_1_pms
-                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
-                padding: u4,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
-            CORE_0_DRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_lock
-                CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
-            CORE_0_DRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_clr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_dram0_pms_monitor_violate_en
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
-            CORE_0_DRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_intr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_lock
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_world
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  core_0_dram0_pms_monitor_violate_status_addr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u4,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
-            CORE_0_DRAM0_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_status_wr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_byteen
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
-            CORE_0_PIF_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_lock
-                CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
-            CORE_0_PIF_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_uart
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
-                ///  core_0_pif_pms_constrain_world_0_g0spi_1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
-                ///  core_0_pif_pms_constrain_world_0_g0spi_0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
-                ///  core_0_pif_pms_constrain_world_0_gpio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
-                ///  core_0_pif_pms_constrain_world_0_fe2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
-                ///  core_0_pif_pms_constrain_world_0_fe
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
-                ///  core_0_pif_pms_constrain_world_0_timer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
-                ///  core_0_pif_pms_constrain_world_0_rtc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
-                ///  core_0_pif_pms_constrain_world_0_io_mux
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
-                ///  core_0_pif_pms_constrain_world_0_wdg
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
-                reserved24: u4,
-                ///  core_0_pif_pms_constrain_world_0_misc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2c
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
-                reserved30: u2,
-                ///  core_0_pif_pms_constrain_world_0_uart1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
-            CORE_0_PIF_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_bt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2c_ext0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
-                ///  core_0_pif_pms_constrain_world_0_uhci0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
-                reserved10: u2,
-                ///  core_0_pif_pms_constrain_world_0_rmt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
-                reserved16: u4,
-                ///  core_0_pif_pms_constrain_world_0_ledc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
-                reserved22: u4,
-                ///  core_0_pif_pms_constrain_world_0_bb
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_0_timergroup
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
-                ///  core_0_pif_pms_constrain_world_0_timergroup1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
-                ///  core_0_pif_pms_constrain_world_0_systimer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
-            CORE_0_PIF_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_spi_2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_0_apb_ctrl
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
-                reserved10: u4,
-                ///  core_0_pif_pms_constrain_world_0_can
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
-                reserved14: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2s1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
-                reserved22: u6,
-                ///  core_0_pif_pms_constrain_world_0_rwbt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_0_wifimac
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
-                ///  core_0_pif_pms_constrain_world_0_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
-            CORE_0_PIF_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  core_0_pif_pms_constrain_world_0_usb_wrap
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
-                ///  core_0_pif_pms_constrain_world_0_crypto_peri
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
-                ///  core_0_pif_pms_constrain_world_0_crypto_dma
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
-                ///  core_0_pif_pms_constrain_world_0_apb_adc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
-                reserved12: u2,
-                ///  core_0_pif_pms_constrain_world_0_bt_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
-                ///  core_0_pif_pms_constrain_world_0_usb_device
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
-                ///  core_0_pif_pms_constrain_world_0_system
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
-                ///  core_0_pif_pms_constrain_world_0_sensitive
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
-                ///  core_0_pif_pms_constrain_world_0_interrupt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
-                ///  core_0_pif_pms_constrain_world_0_dma_copy
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
-                ///  core_0_pif_pms_constrain_world_0_cache_config
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
-                ///  core_0_pif_pms_constrain_world_0_ad
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
-                ///  core_0_pif_pms_constrain_world_0_dio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
-                ///  core_0_pif_pms_constrain_world_0_world_controller
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
-            CORE_0_PIF_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_uart
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
-                ///  core_0_pif_pms_constrain_world_1_g0spi_1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
-                ///  core_0_pif_pms_constrain_world_1_g0spi_0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
-                ///  core_0_pif_pms_constrain_world_1_gpio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
-                ///  core_0_pif_pms_constrain_world_1_fe2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
-                ///  core_0_pif_pms_constrain_world_1_fe
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
-                ///  core_0_pif_pms_constrain_world_1_timer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
-                ///  core_0_pif_pms_constrain_world_1_rtc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
-                ///  core_0_pif_pms_constrain_world_1_io_mux
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
-                ///  core_0_pif_pms_constrain_world_1_wdg
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
-                reserved24: u4,
-                ///  core_0_pif_pms_constrain_world_1_misc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2c
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
-                reserved30: u2,
-                ///  core_0_pif_pms_constrain_world_1_uart1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
-            CORE_0_PIF_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_bt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2c_ext0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
-                ///  core_0_pif_pms_constrain_world_1_uhci0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
-                reserved10: u2,
-                ///  core_0_pif_pms_constrain_world_1_rmt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
-                reserved16: u4,
-                ///  core_0_pif_pms_constrain_world_1_ledc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
-                reserved22: u4,
-                ///  core_0_pif_pms_constrain_world_1_bb
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_1_timergroup
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
-                ///  core_0_pif_pms_constrain_world_1_timergroup1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
-                ///  core_0_pif_pms_constrain_world_1_systimer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
-            CORE_0_PIF_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_spi_2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_1_apb_ctrl
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
-                reserved10: u4,
-                ///  core_0_pif_pms_constrain_world_1_can
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
-                reserved14: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2s1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
-                reserved22: u6,
-                ///  core_0_pif_pms_constrain_world_1_rwbt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_1_wifimac
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
-                ///  core_0_pif_pms_constrain_world_1_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
-            CORE_0_PIF_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  core_0_pif_pms_constrain_world_1_usb_wrap
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
-                ///  core_0_pif_pms_constrain_world_1_crypto_peri
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
-                ///  core_0_pif_pms_constrain_world_1_crypto_dma
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
-                ///  core_0_pif_pms_constrain_world_1_apb_adc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
-                reserved12: u2,
-                ///  core_0_pif_pms_constrain_world_1_bt_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
-                ///  core_0_pif_pms_constrain_world_1_usb_device
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
-                ///  core_0_pif_pms_constrain_world_1_system
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
-                ///  core_0_pif_pms_constrain_world_1_sensitive
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
-                ///  core_0_pif_pms_constrain_world_1_interrupt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
-                ///  core_0_pif_pms_constrain_world_1_dma_copy
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
-                ///  core_0_pif_pms_constrain_world_1_cache_config
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
-                ///  core_0_pif_pms_constrain_world_1_ad
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
-                ///  core_0_pif_pms_constrain_world_1_dio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
-                ///  core_0_pif_pms_constrain_world_1_world_controller
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
-            CORE_0_PIF_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
-                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
-            CORE_0_PIF_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_rtcfast_world_0_l
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_0_h
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_1_l
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_1_h
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
-                padding: u20,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
-            REGION_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_lock
-                REGION_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
-            REGION_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_world_0_area_0
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
-                ///  region_pms_constrain_world_0_area_1
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
-                ///  region_pms_constrain_world_0_area_2
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
-                ///  region_pms_constrain_world_0_area_3
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
-                ///  region_pms_constrain_world_0_area_4
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
-                ///  region_pms_constrain_world_0_area_5
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
-                ///  region_pms_constrain_world_0_area_6
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
-                padding: u18,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
-            REGION_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_world_1_area_0
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
-                ///  region_pms_constrain_world_1_area_1
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
-                ///  region_pms_constrain_world_1_area_2
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
-                ///  region_pms_constrain_world_1_area_3
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
-                ///  region_pms_constrain_world_1_area_4
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
-                ///  region_pms_constrain_world_1_area_5
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
-                ///  region_pms_constrain_world_1_area_6
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
-                padding: u18,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
-            REGION_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_0
-                REGION_PMS_CONSTRAIN_ADDR_0: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
-            REGION_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_1
-                REGION_PMS_CONSTRAIN_ADDR_1: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
-            REGION_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_2
-                REGION_PMS_CONSTRAIN_ADDR_2: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
-            REGION_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_3
-                REGION_PMS_CONSTRAIN_ADDR_3: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
-            REGION_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_4
-                REGION_PMS_CONSTRAIN_ADDR_4: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
-            REGION_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_5
-                REGION_PMS_CONSTRAIN_ADDR_5: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
-            REGION_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_6
-                REGION_PMS_CONSTRAIN_ADDR_6: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
-            REGION_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_7
-                REGION_PMS_CONSTRAIN_ADDR_7: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
-            CORE_0_PIF_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_lock
-                CORE_0_PIF_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
-            CORE_0_PIF_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_clr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_pif_pms_monitor_violate_en
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
-            CORE_0_PIF_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_intr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hport_0
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hsize
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-                ///  core_0_pif_pms_monitor_violate_status_hwrite
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hworld
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
-                padding: u24,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
-            CORE_0_PIF_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_status_haddr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
-            CORE_0_PIF_PMS_MONITOR_4: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_clr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
-                ///  core_0_pif_pms_monitor_nonword_violate_en
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
-            CORE_0_PIF_PMS_MONITOR_5: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_intr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
-                ///  core_0_pif_pms_monitor_nonword_violate_status_hsize
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
-                ///  core_0_pif_pms_monitor_nonword_violate_status_hworld
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
-            CORE_0_PIF_PMS_MONITOR_6: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_status_haddr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
-            BACKUP_BUS_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_lock
-                BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
-            BACKUP_BUS_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_uart
-                BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
-                ///  backup_bus_pms_constrain_g0spi_1
-                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
-                ///  backup_bus_pms_constrain_g0spi_0
-                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
-                ///  backup_bus_pms_constrain_gpio
-                BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
-                ///  backup_bus_pms_constrain_fe2
-                BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
-                ///  backup_bus_pms_constrain_fe
-                BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
-                ///  backup_bus_pms_constrain_timer
-                BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
-                ///  backup_bus_pms_constrain_rtc
-                BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
-                ///  backup_bus_pms_constrain_io_mux
-                BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
-                ///  backup_bus_pms_constrain_wdg
-                BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
-                reserved24: u4,
-                ///  backup_bus_pms_constrain_misc
-                BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
-                ///  backup_bus_pms_constrain_i2c
-                BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
-                reserved30: u2,
-                ///  backup_bus_pms_constrain_uart1
-                BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
-            BACKUP_BUS_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_bt
-                BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
-                reserved4: u2,
-                ///  backup_bus_pms_constrain_i2c_ext0
-                BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
-                ///  backup_bus_pms_constrain_uhci0
-                BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
-                reserved10: u2,
-                ///  backup_bus_pms_constrain_rmt
-                BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
-                reserved16: u4,
-                ///  backup_bus_pms_constrain_ledc
-                BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
-                reserved22: u4,
-                ///  backup_bus_pms_constrain_bb
-                BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
-                reserved26: u2,
-                ///  backup_bus_pms_constrain_timergroup
-                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
-                ///  backup_bus_pms_constrain_timergroup1
-                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
-                ///  backup_bus_pms_constrain_systimer
-                BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
-            BACKUP_BUS_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_spi_2
-                BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
-                reserved4: u2,
-                ///  backup_bus_pms_constrain_apb_ctrl
-                BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
-                reserved10: u4,
-                ///  backup_bus_pms_constrain_can
-                BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
-                reserved14: u2,
-                ///  backup_bus_pms_constrain_i2s1
-                BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
-                reserved22: u6,
-                ///  backup_bus_pms_constrain_rwbt
-                BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
-                reserved26: u2,
-                ///  backup_bus_pms_constrain_wifimac
-                BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
-                ///  backup_bus_pms_constrain_pwr
-                BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
-            BACKUP_BUS_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  backup_bus_pms_constrain_usb_wrap
-                BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
-                ///  backup_bus_pms_constrain_crypto_peri
-                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
-                ///  backup_bus_pms_constrain_crypto_dma
-                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
-                ///  backup_bus_pms_constrain_apb_adc
-                BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
-                reserved12: u2,
-                ///  backup_bus_pms_constrain_bt_pwr
-                BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
-                ///  backup_bus_pms_constrain_usb_device
-                BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
-                padding: u16,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
-            BACKUP_BUS_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_lock
-                BACKUP_BUS_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
-            BACKUP_BUS_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_clr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  backup_bus_pms_monitor_violate_en
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
-            BACKUP_BUS_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_intr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  backup_bus_pms_monitor_violate_status_htrans
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
-                ///  backup_bus_pms_monitor_violate_status_hsize
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-                ///  backup_bus_pms_monitor_violate_status_hwrite
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-                padding: u25,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
-            BACKUP_BUS_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_haddr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
-            }),
-            ///  SENSITIVE_CLOCK_GATE_REG
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  clk_en
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved4092: [3720]u8,
-            ///  SENSITIVE_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SHA (Secure Hash Algorithm) Accelerator
-        pub const SHA = extern struct {
-            ///  Initial configuration register.
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Sha mode.
-                MODE: u3,
-                padding: u29,
-            }),
-            ///  SHA 512/t configuration register 0.
-            T_STRING: mmio.Mmio(packed struct(u32) {
-                ///  Sha t_string (used if and only if mode == SHA_512/t).
-                T_STRING: u32,
-            }),
-            ///  SHA 512/t configuration register 1.
-            T_LENGTH: mmio.Mmio(packed struct(u32) {
-                ///  Sha t_length (used if and only if mode == SHA_512/t).
-                T_LENGTH: u6,
-                padding: u26,
-            }),
-            ///  DMA configuration register 0.
-            DMA_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Dma-sha block number.
-                DMA_BLOCK_NUM: u6,
-                padding: u26,
-            }),
-            ///  Typical SHA configuration register 0.
-            START: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Reserved.
-                START: u31,
-            }),
-            ///  Typical SHA configuration register 1.
-            CONTINUE: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Reserved.
-                CONTINUE: u31,
-            }),
-            ///  Busy register.
-            BUSY: mmio.Mmio(packed struct(u32) {
-                ///  Sha busy state. 1'b0: idle. 1'b1: busy.
-                STATE: u1,
-                padding: u31,
-            }),
-            ///  DMA configuration register 1.
-            DMA_START: mmio.Mmio(packed struct(u32) {
-                ///  Start dma-sha.
-                DMA_START: u1,
-                padding: u31,
-            }),
-            ///  DMA configuration register 2.
-            DMA_CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  Continue dma-sha.
-                DMA_CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  Interrupt clear register.
-            CLEAR_IRQ: mmio.Mmio(packed struct(u32) {
-                ///  Clear sha interrupt.
-                CLEAR_INTERRUPT: u1,
-                padding: u31,
-            }),
-            ///  Interrupt enable register.
-            IRQ_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
-                INTERRUPT_ENA: u1,
-                padding: u31,
-            }),
-            ///  Date register.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Sha date information/ sha version information.
-                DATE: u30,
-                padding: u2,
-            }),
-            reserved64: [16]u8,
-            ///  Sha H memory which contains intermediate hash or finial hash.
-            H_MEM: [64]u8,
-            ///  Sha M memory which contains message.
-            M_MEM: [64]u8,
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI0 = extern struct {
-            reserved8: [8]u8,
-            ///  SPI0 control register.
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller.
-                FDUMMY_OUT: u1,
-                reserved7: u3,
-                ///  Apply 2 signals during command phase 1:enable 0: disable
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable
-                FCMD_QUAD: u1,
-                reserved13: u4,
-                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-                FASTRD_MODE: u1,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DUAL: u1,
-                reserved18: u3,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low
-                D_POL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QUAD: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
-                WP: u1,
-                reserved23: u1,
-                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DIO: u1,
-                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QIO: u1,
-                padding: u7,
-            }),
-            ///  SPI0 control1 register.
-            CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
-                CLK_MODE: u2,
-                reserved30: u28,
-                ///  SPI0 RX FIFO reset signal.
-                RXFIFO_RST: u1,
-                padding: u1,
-            }),
-            ///  SPI0 control2 register.
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
-                CS_SETUP_TIME: u5,
-                ///  Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
-                CS_HOLD_TIME: u5,
-                reserved25: u15,
-                ///  These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
-                CS_HOLD_DELAY: u6,
-                ///  The FSM will be reset.
-                SYNC_RESET: u1,
-            }),
-            ///  SPI clock division control register.
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
-                CLKCNT_L: u8,
-                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-                CLKCNT_H: u8,
-                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
-                CLKCNT_N: u8,
-                reserved31: u7,
-                ///  Set this bit in 1-division mode.
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI0 user register.
-            USER: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable.
-                CS_HOLD: u1,
-                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
-                CS_SETUP: u1,
-                reserved9: u1,
-                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
-                CK_OUT_EDGE: u1,
-                reserved26: u16,
-                ///  spi clock is disable in dummy phase when the bit is enable.
-                USR_DUMMY_IDLE: u1,
-                reserved29: u2,
-                ///  This bit enable the dummy phase of an operation.
-                USR_DUMMY: u1,
-                padding: u2,
-            }),
-            ///  SPI0 user1 register.
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
-                USR_DUMMY_CYCLELEN: u6,
-                reserved26: u20,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1).
-                USR_ADDR_BITLEN: u6,
-            }),
-            ///  SPI0 user2 register.
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command.
-                USR_COMMAND_VALUE: u16,
-                reserved28: u12,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1)
-                USR_COMMAND_BITLEN: u4,
-            }),
-            reserved44: [8]u8,
-            ///  SPI0 read control register.
-            RD_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
-                WB_MODE: u8,
-                padding: u8,
-            }),
-            reserved52: [4]u8,
-            ///  SPI0 misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  The bit is used to indicate the spi0_mst_st controlled transmitting is done.
-                TRANS_END: u1,
-                ///  The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
-                TRANS_END_INT_ENA: u1,
-                ///  The bit is used to indicate the spi0_slv_st controlled transmitting is done.
-                CSPI_ST_TRANS_END: u1,
-                ///  The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
-                CSPI_ST_TRANS_END_INT_ENA: u1,
-                reserved9: u2,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set.
-                CS_KEEP_ACTIVE: u1,
-                padding: u21,
-            }),
-            reserved60: [4]u8,
-            ///  SPI0 bit mode control register.
-            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
-                ///  For SPI0, Cache access enable, 1: enable, 0:disable.
-                CACHE_REQ_EN: u1,
-                ///  For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
-                CACHE_USR_ADDR_4BYTE: u1,
-                ///  For SPI0, cache read flash for user define command, 1: enable, 0:disable.
-                CACHE_FLASH_USR_CMD: u1,
-                ///  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDIN_DUAL: u1,
-                ///  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDOUT_DUAL: u1,
-                ///  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FADDR_DUAL: u1,
-                ///  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDIN_QUAD: u1,
-                ///  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDOUT_QUAD: u1,
-                ///  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FADDR_QUAD: u1,
-                padding: u23,
-            }),
-            reserved84: [20]u8,
-            ///  SPI0 FSM status register
-            FSM: mmio.Mmio(packed struct(u32) {
-                ///  The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
-                CSPI_ST: u4,
-                ///  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
-                EM_ST: u3,
-                ///  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
-                CSPI_LOCK_DELAY_TIME: u5,
-                padding: u20,
-            }),
-            reserved168: [80]u8,
-            ///  SPI0 timing calibration register
-            TIMING_CALI: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable timing adjust clock for all reading operations.
-                TIMING_CLK_ENA: u1,
-                ///  The bit is used to enable timing auto-calibration for all reading operations.
-                TIMING_CALI: u1,
-                ///  add extra dummy spi clock cycle length for spi clock calibration.
-                EXTRA_DUMMY_CYCLELEN: u3,
-                padding: u27,
-            }),
-            ///  SPI0 input delay mode control register
-            DIN_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN0_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN1_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN2_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN3_MODE: u2,
-                padding: u24,
-            }),
-            ///  SPI0 input delay number control register
-            DIN_NUM: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN0_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN1_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN2_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN3_NUM: u2,
-                padding: u24,
-            }),
-            ///  SPI0 output delay mode control register
-            DOUT_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT0_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT1_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT2_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT3_MODE: u1,
-                padding: u28,
-            }),
-            reserved220: [36]u8,
-            ///  SPI0 clk_gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  SPI0 module clock select register
-            CORE_CLK_SEL: mmio.Mmio(packed struct(u32) {
-                ///  When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
-                SPI01_CLK_SEL: u2,
-                padding: u30,
-            }),
-            reserved1020: [792]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  SPI register version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI1 = extern struct {
-            ///  SPI1 memory command register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  The current status of SPI1 master FSM.
-                SPI1_MST_ST: u4,
-                ///  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
-                MSPI_ST: u4,
-                reserved17: u9,
-                ///  In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PE: u1,
-                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                USR: u1,
-                ///  Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_HPM: u1,
-                ///  This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_RES: u1,
-                ///  Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_DP: u1,
-                ///  Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_CE: u1,
-                ///  Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_BE: u1,
-                ///  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_SE: u1,
-                ///  Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
-                FLASH_PP: u1,
-                ///  Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_WRSR: u1,
-                ///  Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_RDSR: u1,
-                ///  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_RDID: u1,
-                ///  Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_WRDI: u1,
-                ///  Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_WREN: u1,
-                ///  Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_READ: u1,
-            }),
-            ///  SPI1 address register
-            ADDR: mmio.Mmio(packed struct(u32) {
-                ///  In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
-                USR_ADDR_VALUE: u32,
-            }),
-            ///  SPI1 control register.
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller.
-                FDUMMY_OUT: u1,
-                reserved7: u3,
-                ///  Apply 2 signals during command phase 1:enable 0: disable
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable
-                FCMD_QUAD: u1,
-                reserved10: u1,
-                ///  For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
-                FCS_CRC_EN: u1,
-                ///  For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
-                TX_CRC_EN: u1,
-                reserved13: u1,
-                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-                FASTRD_MODE: u1,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DUAL: u1,
-                ///  The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
-                RESANDRES: u1,
-                reserved18: u2,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low
-                D_POL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QUAD: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
-                WP: u1,
-                ///  two bytes data will be written to status register when it is set. 1: enable 0: disable.
-                WRSR_2B: u1,
-                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DIO: u1,
-                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QIO: u1,
-                padding: u7,
-            }),
-            ///  SPI1 control1 register.
-            CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
-                CLK_MODE: u2,
-                ///  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
-                CS_HOLD_DLY_RES: u10,
-                padding: u20,
-            }),
-            ///  SPI1 control2 register.
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  The FSM will be reset.
-                SYNC_RESET: u1,
-            }),
-            ///  SPI1 clock division control register.
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
-                CLKCNT_L: u8,
-                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-                CLKCNT_H: u8,
-                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
-                CLKCNT_N: u8,
-                reserved31: u7,
-                ///  reserved
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI1 user register.
-            USER: mmio.Mmio(packed struct(u32) {
-                reserved9: u9,
-                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
-                CK_OUT_EDGE: u1,
-                reserved12: u2,
-                ///  In the write operations read-data phase apply 2 signals
-                FWRITE_DUAL: u1,
-                ///  In the write operations read-data phase apply 4 signals
-                FWRITE_QUAD: u1,
-                ///  In the write operations address phase and read-data phase apply 2 signals.
-                FWRITE_DIO: u1,
-                ///  In the write operations address phase and read-data phase apply 4 signals.
-                FWRITE_QIO: u1,
-                reserved24: u8,
-                ///  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
-                USR_MISO_HIGHPART: u1,
-                ///  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
-                USR_MOSI_HIGHPART: u1,
-                ///  SPI clock is disable in dummy phase when the bit is enable.
-                USR_DUMMY_IDLE: u1,
-                ///  This bit enable the write-data phase of an operation.
-                USR_MOSI: u1,
-                ///  This bit enable the read-data phase of an operation.
-                USR_MISO: u1,
-                ///  This bit enable the dummy phase of an operation.
-                USR_DUMMY: u1,
-                ///  This bit enable the address phase of an operation.
-                USR_ADDR: u1,
-                ///  This bit enable the command phase of an operation.
-                USR_COMMAND: u1,
-            }),
-            ///  SPI1 user1 register.
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
-                USR_DUMMY_CYCLELEN: u6,
-                reserved26: u20,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1).
-                USR_ADDR_BITLEN: u6,
-            }),
-            ///  SPI1 user2 register.
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command.
-                USR_COMMAND_VALUE: u16,
-                reserved28: u12,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1)
-                USR_COMMAND_BITLEN: u4,
-            }),
-            ///  SPI1 send data bit length control register.
-            MOSI_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The length in bits of write-data. The register value shall be (bit_num-1).
-                USR_MOSI_DBITLEN: u10,
-                padding: u22,
-            }),
-            ///  SPI1 receive data bit length control register.
-            MISO_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The length in bits of read-data. The register value shall be (bit_num-1).
-                USR_MISO_DBITLEN: u10,
-                padding: u22,
-            }),
-            ///  SPI1 status register.
-            RD_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
-                STATUS: u16,
-                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
-                WB_MODE: u8,
-                padding: u8,
-            }),
-            reserved52: [4]u8,
-            ///  SPI1 misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                ///  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
-                CS0_DIS: u1,
-                ///  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
-                CS1_DIS: u1,
-                reserved9: u7,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set.
-                CS_KEEP_ACTIVE: u1,
-                padding: u21,
-            }),
-            ///  SPI1 TX CRC data register.
-            TX_CRC: mmio.Mmio(packed struct(u32) {
-                ///  For SPI1, the value of crc32.
-                DATA: u32,
-            }),
-            ///  SPI1 bit mode control register.
-            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
-                CACHE_USR_ADDR_4BYTE: u1,
-                reserved3: u1,
-                ///  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDIN_DUAL: u1,
-                ///  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDOUT_DUAL: u1,
-                ///  For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FADDR_DUAL: u1,
-                ///  For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDIN_QUAD: u1,
-                ///  For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDOUT_QUAD: u1,
-                ///  For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FADDR_QUAD: u1,
-                padding: u23,
-            }),
-            reserved88: [24]u8,
-            ///  SPI1 memory data buffer0
-            W0: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF0: u32,
-            }),
-            ///  SPI1 memory data buffer1
-            W1: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF1: u32,
-            }),
-            ///  SPI1 memory data buffer2
-            W2: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF2: u32,
-            }),
-            ///  SPI1 memory data buffer3
-            W3: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF3: u32,
-            }),
-            ///  SPI1 memory data buffer4
-            W4: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF4: u32,
-            }),
-            ///  SPI1 memory data buffer5
-            W5: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF5: u32,
-            }),
-            ///  SPI1 memory data buffer6
-            W6: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF6: u32,
-            }),
-            ///  SPI1 memory data buffer7
-            W7: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF7: u32,
-            }),
-            ///  SPI1 memory data buffer8
-            W8: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF8: u32,
-            }),
-            ///  SPI1 memory data buffer9
-            W9: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF9: u32,
-            }),
-            ///  SPI1 memory data buffer10
-            W10: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF10: u32,
-            }),
-            ///  SPI1 memory data buffer11
-            W11: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF11: u32,
-            }),
-            ///  SPI1 memory data buffer12
-            W12: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF12: u32,
-            }),
-            ///  SPI1 memory data buffer13
-            W13: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF13: u32,
-            }),
-            ///  SPI1 memory data buffer14
-            W14: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF14: u32,
-            }),
-            ///  SPI1 memory data buffer15
-            W15: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF15: u32,
-            }),
-            ///  SPI1 wait idle control register
-            FLASH_WAITI_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  The dummy phase enable when wait flash idle (RDSR)
-                WAITI_DUMMY: u1,
-                ///  The command to wait flash idle(RDSR).
-                WAITI_CMD: u8,
-                ///  The dummy cycle length when wait flash idle(RDSR).
-                WAITI_DUMMY_CYCLELEN: u6,
-                padding: u16,
-            }),
-            ///  SPI1 flash suspend control register
-            FLASH_SUS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PER: u1,
-                ///  program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PES: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
-                FLASH_PER_WAIT_EN: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
-                FLASH_PES_WAIT_EN: u1,
-                ///  Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
-                PES_PER_EN: u1,
-                ///  Set this bit to enable Auto-suspending function.
-                FLASH_PES_EN: u1,
-                ///  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
-                PESR_END_MSK: u16,
-                ///  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit
-                RD_SUS_2B: u1,
-                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
-                PER_END_EN: u1,
-                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
-                PES_END_EN: u1,
-                ///  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
-                SUS_TIMEOUT_CNT: u7,
-            }),
-            ///  SPI1 flash suspend command register
-            FLASH_SUS_CMD: mmio.Mmio(packed struct(u32) {
-                ///  Program/Erase resume command.
-                FLASH_PER_COMMAND: u8,
-                ///  Program/Erase suspend command.
-                FLASH_PES_COMMAND: u8,
-                ///  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
-                WAIT_PESR_COMMAND: u16,
-            }),
-            ///  SPI1 flash suspend status register
-            SUS_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The status of flash suspend, only used in SPI1.
-                FLASH_SUS: u1,
-                ///  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
-                WAIT_PESR_CMD_2B: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
-                FLASH_HPM_DLY_128: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
-                FLASH_RES_DLY_128: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
-                FLASH_DP_DLY_128: u1,
-                ///  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
-                FLASH_PER_DLY_128: u1,
-                ///  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
-                FLASH_PES_DLY_128: u1,
-                ///  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
-                SPI0_LOCK_EN: u1,
-                padding: u24,
-            }),
-            ///  SPI1 timing control register
-            TIMING_CALI: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  The bit is used to enable timing auto-calibration for all reading operations.
-                TIMING_CALI: u1,
-                ///  add extra dummy spi clock cycle length for spi clock calibration.
-                EXTRA_DUMMY_CYCLELEN: u3,
-                padding: u27,
-            }),
-            reserved192: [20]u8,
-            ///  SPI1 interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_ENA: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt clear register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_CLR: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt raw register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
-                PER_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
-                PES_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
-                WPE_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
-                SLV_ST_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
-                MST_ST_END_INT_RAW: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt status register
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_ST: u1,
-                padding: u27,
-            }),
-            reserved220: [12]u8,
-            ///  SPI1 clk_gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1020: [796]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Version control register
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI2 = extern struct {
-            ///  Command control register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
-                CONF_BITLEN: u18,
-                reserved23: u5,
-                ///  Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
-                UPDATE: u1,
-                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
-                USR: u1,
-                padding: u7,
-            }),
-            ///  Address value register
-            ADDR: mmio.Mmio(packed struct(u32) {
-                ///  Address to slave. Can be configured in CONF state.
-                USR_ADDR_VALUE: u32,
-            }),
-            ///  SPI control register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
-                DUMMY_OUT: u1,
-                reserved5: u1,
-                ///  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
-                FADDR_DUAL: u1,
-                ///  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
-                FADDR_QUAD: u1,
-                reserved8: u1,
-                ///  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
-                FCMD_QUAD: u1,
-                reserved14: u4,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
-                FREAD_DUAL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
-                FREAD_QUAD: u1,
-                reserved18: u2,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
-                D_POL: u1,
-                ///  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
-                HOLD_POL: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
-                WP_POL: u1,
-                reserved25: u3,
-                ///  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
-                RD_BIT_ORDER: u1,
-                ///  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
-                WR_BIT_ORDER: u1,
-                padding: u5,
-            }),
-            ///  SPI clock control register
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
-                CLKCNT_L: u6,
-                ///  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
-                CLKCNT_H: u6,
-                ///  In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-                CLKCNT_N: u6,
-                ///  In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
-                CLKDIV_PRE: u4,
-                reserved31: u9,
-                ///  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI USER control register
-            USER: mmio.Mmio(packed struct(u32) {
-                ///  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
-                DOUTDIN: u1,
-                reserved3: u2,
-                ///  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
-                QPI_MODE: u1,
-                reserved5: u1,
-                ///  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
-                TSCK_I_EDGE: u1,
-                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
-                CS_HOLD: u1,
-                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
-                CS_SETUP: u1,
-                ///  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
-                RSCK_I_EDGE: u1,
-                ///  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
-                CK_OUT_EDGE: u1,
-                reserved12: u2,
-                ///  In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
-                FWRITE_DUAL: u1,
-                ///  In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
-                FWRITE_QUAD: u1,
-                reserved15: u1,
-                ///  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
-                USR_CONF_NXT: u1,
-                reserved17: u1,
-                ///  Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
-                SIO: u1,
-                reserved24: u6,
-                ///  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
-                USR_MISO_HIGHPART: u1,
-                ///  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
-                USR_MOSI_HIGHPART: u1,
-                ///  spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
-                USR_DUMMY_IDLE: u1,
-                ///  This bit enable the write-data phase of an operation. Can be configured in CONF state.
-                USR_MOSI: u1,
-                ///  This bit enable the read-data phase of an operation. Can be configured in CONF state.
-                USR_MISO: u1,
-                ///  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-                USR_DUMMY: u1,
-                ///  This bit enable the address phase of an operation. Can be configured in CONF state.
-                USR_ADDR: u1,
-                ///  This bit enable the command phase of an operation. Can be configured in CONF state.
-                USR_COMMAND: u1,
-            }),
-            ///  SPI USER control register 1
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
-                USR_DUMMY_CYCLELEN: u8,
-                reserved16: u8,
-                ///  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
-                MST_WFULL_ERR_END_EN: u1,
-                ///  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
-                CS_SETUP_TIME: u5,
-                ///  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
-                CS_HOLD_TIME: u5,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
-                USR_ADDR_BITLEN: u5,
-            }),
-            ///  SPI USER control register 2
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command. Can be configured in CONF state.
-                USR_COMMAND_VALUE: u16,
-                reserved27: u11,
-                ///  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
-                MST_REMPTY_ERR_END_EN: u1,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
-                USR_COMMAND_BITLEN: u4,
-            }),
-            ///  SPI data bit length control register
-            MS_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
-                MS_DATA_BITLEN: u18,
-                padding: u14,
-            }),
-            ///  SPI misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                ///  SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
-                CS0_DIS: u1,
-                ///  SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
-                CS1_DIS: u1,
-                ///  SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
-                CS2_DIS: u1,
-                ///  SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
-                CS3_DIS: u1,
-                ///  SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
-                CS4_DIS: u1,
-                ///  SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
-                CS5_DIS: u1,
-                ///  1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
-                CK_DIS: u1,
-                ///  In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-                MASTER_CS_POL: u6,
-                reserved23: u10,
-                ///  spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.
-                SLAVE_CS_POL: u1,
-                reserved29: u5,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set. Can be configured in CONF state.
-                CS_KEEP_ACTIVE: u1,
-                ///  1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.
-                QUAD_DIN_PIN_SWAP: u1,
-            }),
-            ///  SPI input delay mode configuration
-            DIN_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN0_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN1_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN2_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN3_MODE: u2,
-                reserved16: u8,
-                ///  1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
-                TIMING_HCLK_ACTIVE: u1,
-                padding: u15,
-            }),
-            ///  SPI input delay number configuration
-            DIN_NUM: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN0_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN1_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN2_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN3_NUM: u2,
-                padding: u24,
-            }),
-            ///  SPI output delay mode configuration
-            DOUT_MODE: mmio.Mmio(packed struct(u32) {
-                ///  The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT0_MODE: u1,
-                ///  The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT1_MODE: u1,
-                ///  The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT2_MODE: u1,
-                ///  The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT3_MODE: u1,
-                padding: u28,
-            }),
-            ///  SPI DMA control register
-            DMA_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-                DMA_SLV_SEG_TRANS_EN: u1,
-                ///  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
-                SLV_RX_SEG_TRANS_CLR_EN: u1,
-                ///  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-                SLV_TX_SEG_TRANS_CLR_EN: u1,
-                ///  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
-                RX_EOF_EN: u1,
-                reserved27: u5,
-                ///  Set this bit to enable SPI DMA controlled receive data mode.
-                DMA_RX_ENA: u1,
-                ///  Set this bit to enable SPI DMA controlled send data mode.
-                DMA_TX_ENA: u1,
-                ///  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
-                RX_AFIFO_RST: u1,
-                ///  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
-                BUF_AFIFO_RST: u1,
-                ///  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
-                DMA_AFIFO_RST: u1,
-            }),
-            ///  SPI DMA interrupt enable register
-            DMA_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_ENA: u1,
-                ///  The enable bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_APP2_INT interrupt.
-                APP2_INT_ENA: u1,
-                ///  The enable bit for SPI_APP1_INT interrupt.
-                APP1_INT_ENA: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt clear register
-            DMA_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_CLR: u1,
-                ///  The clear bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_APP2_INT interrupt.
-                APP2_INT_CLR: u1,
-                ///  The clear bit for SPI_APP1_INT interrupt.
-                APP1_INT_CLR: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt raw register
-            DMA_INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.
-                DMA_INFIFO_FULL_ERR_INT_RAW: u1,
-                ///  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.
-                DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
-                SLV_EX_QPI_INT_RAW: u1,
-                ///  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
-                SLV_EN_QPI_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
-                SLV_CMD7_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
-                SLV_CMD8_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
-                SLV_CMD9_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
-                SLV_CMDA_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
-                SLV_RD_DMA_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
-                SLV_WR_DMA_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
-                SLV_RD_BUF_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
-                SLV_WR_BUF_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
-                TRANS_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.
-                DMA_SEG_TRANS_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
-                SEG_MAGIC_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
-                SLV_BUF_ADDR_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
-                SLV_CMD_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
-                MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-                MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
-                APP2_INT_RAW: u1,
-                ///  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
-                APP1_INT_RAW: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt status register
-            DMA_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_ST: u1,
-                ///  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
-                ///  The status bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_ST: u1,
-                ///  The status bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_ST: u1,
-                ///  The status bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_ST: u1,
-                ///  The status bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_ST: u1,
-                ///  The status bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_ST: u1,
-                ///  The status bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_ST: u1,
-                ///  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_ST: u1,
-                ///  The status bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_ST: u1,
-                ///  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_ST: u1,
-                ///  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_ST: u1,
-                ///  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_ST: u1,
-                ///  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
-                ///  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
-                ///  The status bit for SPI_APP2_INT interrupt.
-                APP2_INT_ST: u1,
-                ///  The status bit for SPI_APP1_INT interrupt.
-                APP1_INT_ST: u1,
-                padding: u11,
-            }),
-            reserved152: [84]u8,
-            ///  SPI CPU-controlled buffer0
-            W0: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF0: u32,
-            }),
-            ///  SPI CPU-controlled buffer1
-            W1: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF1: u32,
-            }),
-            ///  SPI CPU-controlled buffer2
-            W2: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF2: u32,
-            }),
-            ///  SPI CPU-controlled buffer3
-            W3: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF3: u32,
-            }),
-            ///  SPI CPU-controlled buffer4
-            W4: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF4: u32,
-            }),
-            ///  SPI CPU-controlled buffer5
-            W5: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF5: u32,
-            }),
-            ///  SPI CPU-controlled buffer6
-            W6: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF6: u32,
-            }),
-            ///  SPI CPU-controlled buffer7
-            W7: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF7: u32,
-            }),
-            ///  SPI CPU-controlled buffer8
-            W8: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF8: u32,
-            }),
-            ///  SPI CPU-controlled buffer9
-            W9: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF9: u32,
-            }),
-            ///  SPI CPU-controlled buffer10
-            W10: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF10: u32,
-            }),
-            ///  SPI CPU-controlled buffer11
-            W11: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF11: u32,
-            }),
-            ///  SPI CPU-controlled buffer12
-            W12: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF12: u32,
-            }),
-            ///  SPI CPU-controlled buffer13
-            W13: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF13: u32,
-            }),
-            ///  SPI CPU-controlled buffer14
-            W14: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF14: u32,
-            }),
-            ///  SPI CPU-controlled buffer15
-            W15: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF15: u32,
-            }),
-            reserved224: [8]u8,
-            ///  SPI slave control register
-            SLAVE: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
-                CLK_MODE: u2,
-                ///  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-                CLK_MODE_13: u1,
-                ///  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge
-                RSCK_DATA_OUT: u1,
-                reserved8: u4,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
-                SLV_RDDMA_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
-                SLV_WRDMA_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
-                SLV_RDBUF_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
-                SLV_WRBUF_BITLEN_EN: u1,
-                reserved22: u10,
-                ///  The magic value of BM table in master DMA seg-trans.
-                DMA_SEG_MAGIC_VALUE: u4,
-                ///  Set SPI work mode. 1: slave mode 0: master mode.
-                MODE: u1,
-                ///  Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
-                SOFT_RESET: u1,
-                ///  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
-                USR_CONF: u1,
-                padding: u3,
-            }),
-            ///  SPI slave control register 1
-            SLAVE1: mmio.Mmio(packed struct(u32) {
-                ///  The transferred data bit length in SPI slave FD and HD mode.
-                SLV_DATA_BITLEN: u18,
-                ///  In the slave mode it is the value of command.
-                SLV_LAST_COMMAND: u8,
-                ///  In the slave mode it is the value of address.
-                SLV_LAST_ADDR: u6,
-            }),
-            ///  SPI module clock and register clock control
-            CLK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable clk gate
-                CLK_EN: u1,
-                ///  Set this bit to power on the SPI module clock.
-                MST_CLK_ACTIVE: u1,
-                ///  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
-                MST_CLK_SEL: u1,
-                padding: u29,
-            }),
-            reserved240: [4]u8,
-            ///  Version control
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  SPI register version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  System
-        pub const SYSTEM = extern struct {
-            ///  cpu_peripheral clock gating register
-            CPU_PERI_CLK_EN: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  reg_clk_en_assist_debug
-                CLK_EN_ASSIST_DEBUG: u1,
-                ///  reg_clk_en_dedicated_gpio
-                CLK_EN_DEDICATED_GPIO: u1,
-                padding: u24,
-            }),
-            ///  cpu_peripheral reset register
-            CPU_PERI_RST_EN: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  reg_rst_en_assist_debug
-                RST_EN_ASSIST_DEBUG: u1,
-                ///  reg_rst_en_dedicated_gpio
-                RST_EN_DEDICATED_GPIO: u1,
-                padding: u24,
-            }),
-            ///  cpu clock config register
-            CPU_PER_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpuperiod_sel
-                CPUPERIOD_SEL: u2,
-                ///  reg_pll_freq_sel
-                PLL_FREQ_SEL: u1,
-                ///  reg_cpu_wait_mode_force_on
-                CPU_WAIT_MODE_FORCE_ON: u1,
-                ///  reg_cpu_waiti_delay_num
-                CPU_WAITI_DELAY_NUM: u4,
-                padding: u24,
-            }),
-            ///  memory power down mask register
-            MEM_PD_MASK: mmio.Mmio(packed struct(u32) {
-                ///  reg_lslp_mem_pd_mask
-                LSLP_MEM_PD_MASK: u1,
-                padding: u31,
-            }),
-            ///  peripheral clock gating register
-            PERIP_CLK_EN0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timers_clk_en
-                TIMERS_CLK_EN: u1,
-                ///  reg_spi01_clk_en
-                SPI01_CLK_EN: u1,
-                ///  reg_uart_clk_en
-                UART_CLK_EN: u1,
-                ///  reg_wdg_clk_en
-                WDG_CLK_EN: u1,
-                ///  reg_i2s0_clk_en
-                I2S0_CLK_EN: u1,
-                ///  reg_uart1_clk_en
-                UART1_CLK_EN: u1,
-                ///  reg_spi2_clk_en
-                SPI2_CLK_EN: u1,
-                ///  reg_ext0_clk_en
-                I2C_EXT0_CLK_EN: u1,
-                ///  reg_uhci0_clk_en
-                UHCI0_CLK_EN: u1,
-                ///  reg_rmt_clk_en
-                RMT_CLK_EN: u1,
-                ///  reg_pcnt_clk_en
-                PCNT_CLK_EN: u1,
-                ///  reg_ledc_clk_en
-                LEDC_CLK_EN: u1,
-                ///  reg_uhci1_clk_en
-                UHCI1_CLK_EN: u1,
-                ///  reg_timergroup_clk_en
-                TIMERGROUP_CLK_EN: u1,
-                ///  reg_efuse_clk_en
-                EFUSE_CLK_EN: u1,
-                ///  reg_timergroup1_clk_en
-                TIMERGROUP1_CLK_EN: u1,
-                ///  reg_spi3_clk_en
-                SPI3_CLK_EN: u1,
-                ///  reg_pwm0_clk_en
-                PWM0_CLK_EN: u1,
-                ///  reg_ext1_clk_en
-                EXT1_CLK_EN: u1,
-                ///  reg_can_clk_en
-                CAN_CLK_EN: u1,
-                ///  reg_pwm1_clk_en
-                PWM1_CLK_EN: u1,
-                ///  reg_i2s1_clk_en
-                I2S1_CLK_EN: u1,
-                ///  reg_spi2_dma_clk_en
-                SPI2_DMA_CLK_EN: u1,
-                ///  reg_usb_device_clk_en
-                USB_DEVICE_CLK_EN: u1,
-                ///  reg_uart_mem_clk_en
-                UART_MEM_CLK_EN: u1,
-                ///  reg_pwm2_clk_en
-                PWM2_CLK_EN: u1,
-                ///  reg_pwm3_clk_en
-                PWM3_CLK_EN: u1,
-                ///  reg_spi3_dma_clk_en
-                SPI3_DMA_CLK_EN: u1,
-                ///  reg_apb_saradc_clk_en
-                APB_SARADC_CLK_EN: u1,
-                ///  reg_systimer_clk_en
-                SYSTIMER_CLK_EN: u1,
-                ///  reg_adc2_arb_clk_en
-                ADC2_ARB_CLK_EN: u1,
-                ///  reg_spi4_clk_en
-                SPI4_CLK_EN: u1,
-            }),
-            ///  peripheral clock gating register
-            PERIP_CLK_EN1: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_crypto_aes_clk_en
-                CRYPTO_AES_CLK_EN: u1,
-                ///  reg_crypto_sha_clk_en
-                CRYPTO_SHA_CLK_EN: u1,
-                ///  reg_crypto_rsa_clk_en
-                CRYPTO_RSA_CLK_EN: u1,
-                ///  reg_crypto_ds_clk_en
-                CRYPTO_DS_CLK_EN: u1,
-                ///  reg_crypto_hmac_clk_en
-                CRYPTO_HMAC_CLK_EN: u1,
-                ///  reg_dma_clk_en
-                DMA_CLK_EN: u1,
-                ///  reg_sdio_host_clk_en
-                SDIO_HOST_CLK_EN: u1,
-                ///  reg_lcd_cam_clk_en
-                LCD_CAM_CLK_EN: u1,
-                ///  reg_uart2_clk_en
-                UART2_CLK_EN: u1,
-                ///  reg_tsens_clk_en
-                TSENS_CLK_EN: u1,
-                padding: u21,
-            }),
-            ///  reserved
-            PERIP_RST_EN0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timers_rst
-                TIMERS_RST: u1,
-                ///  reg_spi01_rst
-                SPI01_RST: u1,
-                ///  reg_uart_rst
-                UART_RST: u1,
-                ///  reg_wdg_rst
-                WDG_RST: u1,
-                ///  reg_i2s0_rst
-                I2S0_RST: u1,
-                ///  reg_uart1_rst
-                UART1_RST: u1,
-                ///  reg_spi2_rst
-                SPI2_RST: u1,
-                ///  reg_ext0_rst
-                I2C_EXT0_RST: u1,
-                ///  reg_uhci0_rst
-                UHCI0_RST: u1,
-                ///  reg_rmt_rst
-                RMT_RST: u1,
-                ///  reg_pcnt_rst
-                PCNT_RST: u1,
-                ///  reg_ledc_rst
-                LEDC_RST: u1,
-                ///  reg_uhci1_rst
-                UHCI1_RST: u1,
-                ///  reg_timergroup_rst
-                TIMERGROUP_RST: u1,
-                ///  reg_efuse_rst
-                EFUSE_RST: u1,
-                ///  reg_timergroup1_rst
-                TIMERGROUP1_RST: u1,
-                ///  reg_spi3_rst
-                SPI3_RST: u1,
-                ///  reg_pwm0_rst
-                PWM0_RST: u1,
-                ///  reg_ext1_rst
-                EXT1_RST: u1,
-                ///  reg_can_rst
-                CAN_RST: u1,
-                ///  reg_pwm1_rst
-                PWM1_RST: u1,
-                ///  reg_i2s1_rst
-                I2S1_RST: u1,
-                ///  reg_spi2_dma_rst
-                SPI2_DMA_RST: u1,
-                ///  reg_usb_device_rst
-                USB_DEVICE_RST: u1,
-                ///  reg_uart_mem_rst
-                UART_MEM_RST: u1,
-                ///  reg_pwm2_rst
-                PWM2_RST: u1,
-                ///  reg_pwm3_rst
-                PWM3_RST: u1,
-                ///  reg_spi3_dma_rst
-                SPI3_DMA_RST: u1,
-                ///  reg_apb_saradc_rst
-                APB_SARADC_RST: u1,
-                ///  reg_systimer_rst
-                SYSTIMER_RST: u1,
-                ///  reg_adc2_arb_rst
-                ADC2_ARB_RST: u1,
-                ///  reg_spi4_rst
-                SPI4_RST: u1,
-            }),
-            ///  peripheral reset register
-            PERIP_RST_EN1: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_crypto_aes_rst
-                CRYPTO_AES_RST: u1,
-                ///  reg_crypto_sha_rst
-                CRYPTO_SHA_RST: u1,
-                ///  reg_crypto_rsa_rst
-                CRYPTO_RSA_RST: u1,
-                ///  reg_crypto_ds_rst
-                CRYPTO_DS_RST: u1,
-                ///  reg_crypto_hmac_rst
-                CRYPTO_HMAC_RST: u1,
-                ///  reg_dma_rst
-                DMA_RST: u1,
-                ///  reg_sdio_host_rst
-                SDIO_HOST_RST: u1,
-                ///  reg_lcd_cam_rst
-                LCD_CAM_RST: u1,
-                ///  reg_uart2_rst
-                UART2_RST: u1,
-                ///  reg_tsens_rst
-                TSENS_RST: u1,
-                padding: u21,
-            }),
-            ///  clock config register
-            BT_LPCK_DIV_INT: mmio.Mmio(packed struct(u32) {
-                ///  reg_bt_lpck_div_num
-                BT_LPCK_DIV_NUM: u12,
-                padding: u20,
-            }),
-            ///  clock config register
-            BT_LPCK_DIV_FRAC: mmio.Mmio(packed struct(u32) {
-                ///  reg_bt_lpck_div_b
-                BT_LPCK_DIV_B: u12,
-                ///  reg_bt_lpck_div_a
-                BT_LPCK_DIV_A: u12,
-                ///  reg_lpclk_sel_rtc_slow
-                LPCLK_SEL_RTC_SLOW: u1,
-                ///  reg_lpclk_sel_8m
-                LPCLK_SEL_8M: u1,
-                ///  reg_lpclk_sel_xtal
-                LPCLK_SEL_XTAL: u1,
-                ///  reg_lpclk_sel_xtal32k
-                LPCLK_SEL_XTAL32K: u1,
-                ///  reg_lpclk_rtc_en
-                LPCLK_RTC_EN: u1,
-                padding: u3,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_0
-                CPU_INTR_FROM_CPU_0: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_1
-                CPU_INTR_FROM_CPU_1: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_2
-                CPU_INTR_FROM_CPU_2: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_3
-                CPU_INTR_FROM_CPU_3: u1,
-                padding: u31,
-            }),
-            ///  rsa memory power control register
-            RSA_PD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_rsa_mem_pd
-                RSA_MEM_PD: u1,
-                ///  reg_rsa_mem_force_pu
-                RSA_MEM_FORCE_PU: u1,
-                ///  reg_rsa_mem_force_pd
-                RSA_MEM_FORCE_PD: u1,
-                padding: u29,
-            }),
-            ///  edma clcok and reset register
-            EDMA_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_edma_clk_on
-                EDMA_CLK_ON: u1,
-                ///  reg_edma_reset
-                EDMA_RESET: u1,
-                padding: u30,
-            }),
-            ///  cache control register
-            CACHE_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  reg_icache_clk_on
-                ICACHE_CLK_ON: u1,
-                ///  reg_icache_reset
-                ICACHE_RESET: u1,
-                ///  reg_dcache_clk_on
-                DCACHE_CLK_ON: u1,
-                ///  reg_dcache_reset
-                DCACHE_RESET: u1,
-                padding: u28,
-            }),
-            ///  SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
-            EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  reg_enable_spi_manual_encrypt
-                ENABLE_SPI_MANUAL_ENCRYPT: u1,
-                ///  reg_enable_download_db_encrypt
-                ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
-                ///  reg_enable_download_g0cb_decrypt
-                ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
-                ///  reg_enable_download_manual_encrypt
-                ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
-                padding: u28,
-            }),
-            ///  fast memory config register
-            RTC_FASTMEM_CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  reg_rtc_mem_crc_start
-                RTC_MEM_CRC_START: u1,
-                ///  reg_rtc_mem_crc_addr
-                RTC_MEM_CRC_ADDR: u11,
-                ///  reg_rtc_mem_crc_len
-                RTC_MEM_CRC_LEN: u11,
-                ///  reg_rtc_mem_crc_finish
-                RTC_MEM_CRC_FINISH: u1,
-            }),
-            ///  reserved
-            RTC_FASTMEM_CRC: mmio.Mmio(packed struct(u32) {
-                ///  reg_rtc_mem_crc_res
-                RTC_MEM_CRC_RES: u32,
-            }),
-            ///  eco register
-            REDUNDANT_ECO_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_redundant_eco_drive
-                REDUNDANT_ECO_DRIVE: u1,
-                ///  reg_redundant_eco_result
-                REDUNDANT_ECO_RESULT: u1,
-                padding: u30,
-            }),
-            ///  clock gating register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_clk_en
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  system clock config register
-            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_pre_div_cnt
-                PRE_DIV_CNT: u10,
-                ///  reg_soc_clk_sel
-                SOC_CLK_SEL: u2,
-                ///  reg_clk_xtal_freq
-                CLK_XTAL_FREQ: u7,
-                ///  reg_clk_div_en
-                CLK_DIV_EN: u1,
-                padding: u12,
-            }),
-            ///  mem pvt register
-            MEM_PVT: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_path_len
-                MEM_PATH_LEN: u4,
-                ///  reg_mem_err_cnt_clr
-                MEM_ERR_CNT_CLR: u1,
-                ///  reg_mem_pvt_monitor_en
-                MONITOR_EN: u1,
-                ///  reg_mem_timing_err_cnt
-                MEM_TIMING_ERR_CNT: u16,
-                ///  reg_mem_vt_sel
-                MEM_VT_SEL: u2,
-                padding: u8,
-            }),
-            ///  mem pvt register
-            COMB_PVT_LVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_lvt
-                COMB_PATH_LEN_LVT: u5,
-                ///  reg_comb_err_cnt_clr_lvt
-                COMB_ERR_CNT_CLR_LVT: u1,
-                ///  reg_comb_pvt_monitor_en_lvt
-                COMB_PVT_MONITOR_EN_LVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_NVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_nvt
-                COMB_PATH_LEN_NVT: u5,
-                ///  reg_comb_err_cnt_clr_nvt
-                COMB_ERR_CNT_CLR_NVT: u1,
-                ///  reg_comb_pvt_monitor_en_nvt
-                COMB_PVT_MONITOR_EN_NVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_HVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_hvt
-                COMB_PATH_LEN_HVT: u5,
-                ///  reg_comb_err_cnt_clr_hvt
-                COMB_ERR_CNT_CLR_HVT: u1,
-                ///  reg_comb_pvt_monitor_en_hvt
-                COMB_PVT_MONITOR_EN_HVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site0
-                COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site0
-                COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site0
-                COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site1
-                COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site1
-                COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site1
-                COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site2
-                COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site2
-                COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site2
-                COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site3
-                COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site3
-                COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site3
-                COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
-                padding: u16,
-            }),
-            reserved4092: [3936]u8,
-            ///  Version register
-            SYSTEM_REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_system_reg_date
-                SYSTEM_REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  System Timer
-        pub const SYSTIMER = extern struct {
-            ///  SYSTIMER_CONF.
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  systimer clock force on
-                SYSTIMER_CLK_FO: u1,
-                reserved22: u21,
-                ///  target2 work enable
-                TARGET2_WORK_EN: u1,
-                ///  target1 work enable
-                TARGET1_WORK_EN: u1,
-                ///  target0 work enable
-                TARGET0_WORK_EN: u1,
-                ///  If timer unit1 is stalled when core1 stalled
-                TIMER_UNIT1_CORE1_STALL_EN: u1,
-                ///  If timer unit1 is stalled when core0 stalled
-                TIMER_UNIT1_CORE0_STALL_EN: u1,
-                ///  If timer unit0 is stalled when core1 stalled
-                TIMER_UNIT0_CORE1_STALL_EN: u1,
-                ///  If timer unit0 is stalled when core0 stalled
-                TIMER_UNIT0_CORE0_STALL_EN: u1,
-                ///  timer unit1 work enable
-                TIMER_UNIT1_WORK_EN: u1,
-                ///  timer unit0 work enable
-                TIMER_UNIT0_WORK_EN: u1,
-                ///  register file clk gating
-                CLK_EN: u1,
-            }),
-            ///  SYSTIMER_UNIT0_OP.
-            UNIT0_OP: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  reg_timer_unit0_value_valid
-                TIMER_UNIT0_VALUE_VALID: u1,
-                ///  update timer_unit0
-                TIMER_UNIT0_UPDATE: u1,
-                padding: u1,
-            }),
-            ///  SYSTIMER_UNIT1_OP.
-            UNIT1_OP: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  timer value is sync and valid
-                TIMER_UNIT1_VALUE_VALID: u1,
-                ///  update timer unit1
-                TIMER_UNIT1_UPDATE: u1,
-                padding: u1,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD_HI.
-            UNIT0_LOAD_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load high 32 bit
-                TIMER_UNIT0_LOAD_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD_LO.
-            UNIT0_LOAD_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load low 32 bit
-                TIMER_UNIT0_LOAD_LO: u32,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD_HI.
-            UNIT1_LOAD_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load high 32 bit
-                TIMER_UNIT1_LOAD_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD_LO.
-            UNIT1_LOAD_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load low 32 bit
-                TIMER_UNIT1_LOAD_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET0_HI.
-            TARGET0_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget0 high 32 bit
-                TIMER_TARGET0_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET0_LO.
-            TARGET0_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget0 low 32 bit
-                TIMER_TARGET0_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET1_HI.
-            TARGET1_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget1 high 32 bit
-                TIMER_TARGET1_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET1_LO.
-            TARGET1_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget1 low 32 bit
-                TIMER_TARGET1_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET2_HI.
-            TARGET2_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget2 high 32 bit
-                TIMER_TARGET2_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET2_LO.
-            TARGET2_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget2 low 32 bit
-                TIMER_TARGET2_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET0_CONF.
-            TARGET0_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target0 period
-                TARGET0_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target0 to period mode
-                TARGET0_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET0_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_TARGET1_CONF.
-            TARGET1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target1 period
-                TARGET1_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target1 to period mode
-                TARGET1_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET1_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_TARGET2_CONF.
-            TARGET2_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target2 period
-                TARGET2_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target2 to period mode
-                TARGET2_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET2_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_UNIT0_VALUE_HI.
-            UNIT0_VALUE_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer read value high 32bit
-                TIMER_UNIT0_VALUE_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT0_VALUE_LO.
-            UNIT0_VALUE_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer read value low 32bit
-                TIMER_UNIT0_VALUE_LO: u32,
-            }),
-            ///  SYSTIMER_UNIT1_VALUE_HI.
-            UNIT1_VALUE_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer read value high 32bit
-                TIMER_UNIT1_VALUE_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT1_VALUE_LO.
-            UNIT1_VALUE_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer read value low 32bit
-                TIMER_UNIT1_VALUE_LO: u32,
-            }),
-            ///  SYSTIMER_COMP0_LOAD.
-            COMP0_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp0 load value
-                TIMER_COMP0_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_COMP1_LOAD.
-            COMP1_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp1 load value
-                TIMER_COMP1_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_COMP2_LOAD.
-            COMP2_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp2 load value
-                TIMER_COMP2_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD.
-            UNIT0_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load value
-                TIMER_UNIT0_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD.
-            UNIT1_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load value
-                TIMER_UNIT1_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_INT_ENA.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 enable
-                TARGET0_INT_ENA: u1,
-                ///  interupt1 enable
-                TARGET1_INT_ENA: u1,
-                ///  interupt2 enable
-                TARGET2_INT_ENA: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_RAW.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 raw
-                TARGET0_INT_RAW: u1,
-                ///  interupt1 raw
-                TARGET1_INT_RAW: u1,
-                ///  interupt2 raw
-                TARGET2_INT_RAW: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_CLR.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 clear
-                TARGET0_INT_CLR: u1,
-                ///  interupt1 clear
-                TARGET1_INT_CLR: u1,
-                ///  interupt2 clear
-                TARGET2_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_ST.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_target0_int_st
-                TARGET0_INT_ST: u1,
-                ///  reg_target1_int_st
-                TARGET1_INT_ST: u1,
-                ///  reg_target2_int_st
-                TARGET2_INT_ST: u1,
-                padding: u29,
-            }),
-            reserved252: [136]u8,
-            ///  SYSTIMER_DATE.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u32,
-            }),
-        };
-
-        ///  Timer Group
-        pub const TIMG0 = extern struct {
-            ///  TIMG_T0CONFIG_REG.
-            T0CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved9: u9,
-                ///  reg_t0_use_xtal.
-                T0_USE_XTAL: u1,
-                ///  reg_t0_alarm_en.
-                T0_ALARM_EN: u1,
-                reserved12: u1,
-                ///  reg_t0_divcnt_rst.
-                T0_DIVCNT_RST: u1,
-                ///  reg_t0_divider.
-                T0_DIVIDER: u16,
-                ///  reg_t0_autoreload.
-                T0_AUTORELOAD: u1,
-                ///  reg_t0_increase.
-                T0_INCREASE: u1,
-                ///  reg_t0_en.
-                T0_EN: u1,
-            }),
-            ///  TIMG_T0LO_REG.
-            T0LO: mmio.Mmio(packed struct(u32) {
-                ///  t0_lo
-                T0_LO: u32,
-            }),
-            ///  TIMG_T0HI_REG.
-            T0HI: mmio.Mmio(packed struct(u32) {
-                ///  t0_hi
-                T0_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0UPDATE_REG.
-            T0UPDATE: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  t0_update
-                T0_UPDATE: u1,
-            }),
-            ///  TIMG_T0ALARMLO_REG.
-            T0ALARMLO: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_alarm_lo.
-                T0_ALARM_LO: u32,
-            }),
-            ///  TIMG_T0ALARMHI_REG.
-            T0ALARMHI: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_alarm_hi.
-                T0_ALARM_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0LOADLO_REG.
-            T0LOADLO: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_load_lo.
-                T0_LOAD_LO: u32,
-            }),
-            ///  TIMG_T0LOADHI_REG.
-            T0LOADHI: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_load_hi.
-                T0_LOAD_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0LOAD_REG.
-            T0LOAD: mmio.Mmio(packed struct(u32) {
-                ///  t0_load
-                T0_LOAD: u32,
-            }),
-            reserved72: [36]u8,
-            ///  TIMG_WDTCONFIG0_REG.
-            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  reg_wdt_appcpu_reset_en.
-                WDT_APPCPU_RESET_EN: u1,
-                ///  reg_wdt_procpu_reset_en.
-                WDT_PROCPU_RESET_EN: u1,
-                ///  reg_wdt_flashboot_mod_en.
-                WDT_FLASHBOOT_MOD_EN: u1,
-                ///  reg_wdt_sys_reset_length.
-                WDT_SYS_RESET_LENGTH: u3,
-                ///  reg_wdt_cpu_reset_length.
-                WDT_CPU_RESET_LENGTH: u3,
-                ///  reg_wdt_use_xtal.
-                WDT_USE_XTAL: u1,
-                ///  reg_wdt_conf_update_en.
-                WDT_CONF_UPDATE_EN: u1,
-                ///  reg_wdt_stg3.
-                WDT_STG3: u2,
-                ///  reg_wdt_stg2.
-                WDT_STG2: u2,
-                ///  reg_wdt_stg1.
-                WDT_STG1: u2,
-                ///  reg_wdt_stg0.
-                WDT_STG0: u2,
-                ///  reg_wdt_en.
-                WDT_EN: u1,
-            }),
-            ///  TIMG_WDTCONFIG1_REG.
-            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_divcnt_rst.
-                WDT_DIVCNT_RST: u1,
-                reserved16: u15,
-                ///  reg_wdt_clk_prescale.
-                WDT_CLK_PRESCALE: u16,
-            }),
-            ///  TIMG_WDTCONFIG2_REG.
-            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg0_hold.
-                WDT_STG0_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG3_REG.
-            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg1_hold.
-                WDT_STG1_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG4_REG.
-            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg2_hold.
-                WDT_STG2_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG5_REG.
-            WDTCONFIG5: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg3_hold.
-                WDT_STG3_HOLD: u32,
-            }),
-            ///  TIMG_WDTFEED_REG.
-            WDTFEED: mmio.Mmio(packed struct(u32) {
-                ///  wdt_feed
-                WDT_FEED: u32,
-            }),
-            ///  TIMG_WDTWPROTECT_REG.
-            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_wkey.
-                WDT_WKEY: u32,
-            }),
-            ///  TIMG_RTCCALICFG_REG.
-            RTCCALICFG: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  reg_rtc_cali_start_cycling.
-                RTC_CALI_START_CYCLING: u1,
-                ///  reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-                RTC_CALI_CLK_SEL: u2,
-                ///  rtc_cali_rdy
-                RTC_CALI_RDY: u1,
-                ///  reg_rtc_cali_max.
-                RTC_CALI_MAX: u15,
-                ///  reg_rtc_cali_start.
-                RTC_CALI_START: u1,
-            }),
-            ///  TIMG_RTCCALICFG1_REG.
-            RTCCALICFG1: mmio.Mmio(packed struct(u32) {
-                ///  rtc_cali_cycling_data_vld
-                RTC_CALI_CYCLING_DATA_VLD: u1,
-                reserved7: u6,
-                ///  rtc_cali_value
-                RTC_CALI_VALUE: u25,
-            }),
-            ///  INT_ENA_TIMG_REG
-            INT_ENA_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_ena
-                T0_INT_ENA: u1,
-                ///  wdt_int_ena
-                WDT_INT_ENA: u1,
-                padding: u30,
-            }),
-            ///  INT_RAW_TIMG_REG
-            INT_RAW_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_raw
-                T0_INT_RAW: u1,
-                ///  wdt_int_raw
-                WDT_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  INT_ST_TIMG_REG
-            INT_ST_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_st
-                T0_INT_ST: u1,
-                ///  wdt_int_st
-                WDT_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  INT_CLR_TIMG_REG
-            INT_CLR_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_clr
-                T0_INT_CLR: u1,
-                ///  wdt_int_clr
-                WDT_INT_CLR: u1,
-                padding: u30,
-            }),
-            ///  TIMG_RTCCALICFG2_REG.
-            RTCCALICFG2: mmio.Mmio(packed struct(u32) {
-                ///  timeoutindicator
-                RTC_CALI_TIMEOUT: u1,
-                reserved3: u2,
-                ///  reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-                RTC_CALI_TIMEOUT_RST_CNT: u4,
-                ///  reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-                RTC_CALI_TIMEOUT_THRES: u25,
-            }),
-            reserved248: [116]u8,
-            ///  TIMG_NTIMG_DATE_REG.
-            NTIMG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_ntimers_date.
-                NTIMGS_DATE: u28,
-                padding: u4,
-            }),
-            ///  TIMG_REGCLK_REG.
-            REGCLK: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  reg_wdt_clk_is_active.
-                WDT_CLK_IS_ACTIVE: u1,
-                ///  reg_timer_clk_is_active.
-                TIMER_CLK_IS_ACTIVE: u1,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-        };
-
-        ///  XTS-AES-128 Flash Encryption
-        pub const XTS_AES = extern struct {
-            ///  The memory that stores plaintext
-            PLAIN_MEM: [16]u8,
-            reserved64: [48]u8,
-            ///  XTS-AES line-size register
-            LINESIZE: mmio.Mmio(packed struct(u32) {
-                ///  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
-                LINESIZE: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES destination register
-            DESTINATION: mmio.Mmio(packed struct(u32) {
-                ///  This bit stores the destination. 0: flash(default). 1: reserved.
-                DESTINATION: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES physical address register
-            PHYSICAL_ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
-                PHYSICAL_ADDRESS: u30,
-                padding: u2,
-            }),
-            ///  XTS-AES trigger register
-            TRIGGER: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to start manual encryption calculation
-                TRIGGER: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES release register
-            RELEASE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to release the manual encrypted result, after that the result will be visible to spi
-                RELEASE: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES destroy register
-            DESTROY: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to destroy XTS-AES result.
-                DESTROY: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES status register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
-                STATE: u2,
-                padding: u30,
-            }),
-            ///  XTS-AES version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the version information of XTS-AES.
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  Two-Wire Automotive Interface
-        pub const TWAI = extern struct {
-            ///  Mode Register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
-                RESET_MODE: u1,
-                ///  1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
-                LISTEN_ONLY_MODE: u1,
-                ///  1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
-                SELF_TEST_MODE: u1,
-                ///  This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
-                RX_FILTER_MODE: u1,
-                padding: u28,
-            }),
-            ///  Command Register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Set the bit to 1 to allow the driving nodes start transmission.
-                TX_REQ: u1,
-                ///  Set the bit to 1 to cancel a pending transmission request.
-                ABORT_TX: u1,
-                ///  Set the bit to 1 to release the RX buffer.
-                RELEASE_BUF: u1,
-                ///  Set the bit to 1 to clear the data overrun status bit.
-                CLR_OVERRUN: u1,
-                ///  Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
-                SELF_RX_REQ: u1,
-                padding: u27,
-            }),
-            ///  Status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  1: The data in the RX buffer is not empty, with at least one received data packet.
-                RX_BUF_ST: u1,
-                ///  1: The RX FIFO is full and data overrun has occurred.
-                OVERRUN_ST: u1,
-                ///  1: The TX buffer is empty, the CPU may write a message into it.
-                TX_BUF_ST: u1,
-                ///  1: The TWAI controller has successfully received a packet from the bus.
-                TX_COMPLETE: u1,
-                ///  1: The TWAI Controller is receiving a message from the bus.
-                RX_ST: u1,
-                ///  1: The TWAI Controller is transmitting a message to the bus.
-                TX_ST: u1,
-                ///  1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
-                ERR_ST: u1,
-                ///  1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
-                BUS_OFF_ST: u1,
-                ///  This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
-                MISS_ST: u1,
-                padding: u23,
-            }),
-            ///  Interrupt Register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
-                RX_INT_ST: u1,
-                ///  Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
-                TX_INT_ST: u1,
-                ///  Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
-                ERR_WARN_INT_ST: u1,
-                ///  Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
-                OVERRUN_INT_ST: u1,
-                reserved5: u1,
-                ///  Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
-                ERR_PASSIVE_INT_ST: u1,
-                ///  Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
-                ARB_LOST_INT_ST: u1,
-                ///  Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
-                BUS_ERR_INT_ST: u1,
-                padding: u24,
-            }),
-            ///  Interrupt Enable Register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to 1 to enable receive interrupt.
-                RX_INT_ENA: u1,
-                ///  Set this bit to 1 to enable transmit interrupt.
-                TX_INT_ENA: u1,
-                ///  Set this bit to 1 to enable error warning interrupt.
-                ERR_WARN_INT_ENA: u1,
-                ///  Set this bit to 1 to enable data overrun interrupt.
-                OVERRUN_INT_ENA: u1,
-                reserved5: u1,
-                ///  Set this bit to 1 to enable error passive interrupt.
-                ERR_PASSIVE_INT_ENA: u1,
-                ///  Set this bit to 1 to enable arbitration lost interrupt.
-                ARB_LOST_INT_ENA: u1,
-                ///  Set this bit to 1 to enable error interrupt.
-                BUS_ERR_INT_ENA: u1,
-                padding: u24,
-            }),
-            reserved24: [4]u8,
-            ///  Bus Timing Register 0
-            BUS_TIMING_0: mmio.Mmio(packed struct(u32) {
-                ///  Baud Rate Prescaler, determines the frequency dividing ratio.
-                BAUD_PRESC: u13,
-                reserved14: u1,
-                ///  Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
-                SYNC_JUMP_WIDTH: u2,
-                padding: u16,
-            }),
-            ///  Bus Timing Register 1
-            BUS_TIMING_1: mmio.Mmio(packed struct(u32) {
-                ///  The width of PBS1.
-                TIME_SEG1: u4,
-                ///  The width of PBS2.
-                TIME_SEG2: u3,
-                ///  The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
-                TIME_SAMP: u1,
-                padding: u24,
-            }),
-            reserved44: [12]u8,
-            ///  Arbitration Lost Capture Register
-            ARB_LOST_CAP: mmio.Mmio(packed struct(u32) {
-                ///  This register contains information about the bit position of lost arbitration.
-                ARB_LOST_CAP: u5,
-                padding: u27,
-            }),
-            ///  Error Code Capture Register
-            ERR_CODE_CAP: mmio.Mmio(packed struct(u32) {
-                ///  This register contains information about the location of errors, see Table 181 for details.
-                ECC_SEGMENT: u5,
-                ///  This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
-                ECC_DIRECTION: u1,
-                ///  This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
-                ECC_TYPE: u2,
-                padding: u24,
-            }),
-            ///  Error Warning Limit Register
-            ERR_WARNING_LIMIT: mmio.Mmio(packed struct(u32) {
-                ///  Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
-                ERR_WARNING_LIMIT: u8,
-                padding: u24,
-            }),
-            ///  Receive Error Counter Register
-            RX_ERR_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The RX error counter register, reflects value changes under reception status.
-                RX_ERR_CNT: u8,
-                padding: u24,
-            }),
-            ///  Transmit Error Counter Register
-            TX_ERR_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The TX error counter register, reflects value changes under transmission status.
-                TX_ERR_CNT: u8,
-                padding: u24,
-            }),
-            ///  Data register 0
-            DATA_0: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_0: u8,
-                padding: u24,
-            }),
-            ///  Data register 1
-            DATA_1: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
-                TX_BYTE_1: u8,
-                padding: u24,
-            }),
-            ///  Data register 2
-            DATA_2: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
-                TX_BYTE_2: u8,
-                padding: u24,
-            }),
-            ///  Data register 3
-            DATA_3: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
-                TX_BYTE_3: u8,
-                padding: u24,
-            }),
-            ///  Data register 4
-            DATA_4: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_4: u8,
-                padding: u24,
-            }),
-            ///  Data register 5
-            DATA_5: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_5: u8,
-                padding: u24,
-            }),
-            ///  Data register 6
-            DATA_6: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_6: u8,
-                padding: u24,
-            }),
-            ///  Data register 7
-            DATA_7: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_7: u8,
-                padding: u24,
-            }),
-            ///  Data register 8
-            DATA_8: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 8th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_8: u8,
-                padding: u24,
-            }),
-            ///  Data register 9
-            DATA_9: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 9th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_9: u8,
-                padding: u24,
-            }),
-            ///  Data register 10
-            DATA_10: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 10th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_10: u8,
-                padding: u24,
-            }),
-            ///  Data register 11
-            DATA_11: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 11th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_11: u8,
-                padding: u24,
-            }),
-            ///  Data register 12
-            DATA_12: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 12th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_12: u8,
-                padding: u24,
-            }),
-            ///  Receive Message Counter Register
-            RX_MESSAGE_CNT: mmio.Mmio(packed struct(u32) {
-                ///  This register reflects the number of messages available within the RX FIFO.
-                RX_MESSAGE_COUNTER: u7,
-                padding: u25,
-            }),
-            reserved124: [4]u8,
-            ///  Clock Divider register
-            CLOCK_DIVIDER: mmio.Mmio(packed struct(u32) {
-                ///  These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
-                CD: u8,
-                ///  This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
-                CLOCK_OFF: u1,
-                padding: u23,
-            }),
-        };
-
-        ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-        pub const UART0 = extern struct {
-            ///  FIFO data register
-            FIFO: mmio.Mmio(packed struct(u32) {
-                ///  UART 0 accesses FIFO via this register.
-                RXFIFO_RD_BYTE: u8,
-                padding: u24,
-            }),
-            ///  Raw interrupt status
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
-                RXFIFO_FULL_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
-                TXFIFO_EMPTY_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a parity error in the data.
-                PARITY_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a data frame error .
-                FRM_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
-                RXFIFO_OVF_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
-                DSR_CHG_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
-                CTS_CHG_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
-                BRK_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
-                RXFIFO_TOUT_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
-                SW_XON_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
-                SW_XOFF_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
-                GLITCH_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.
-                TX_BRK_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.
-                TX_BRK_IDLE_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
-                TX_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
-                RS485_PARITY_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
-                RS485_FRM_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
-                RS485_CLASH_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
-                AT_CMD_CHAR_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
-                WAKEUP_INT_RAW: u1,
-                padding: u12,
-            }),
-            ///  Masked interrupt status
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-                RXFIFO_FULL_INT_ST: u1,
-                ///  This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.
-                TXFIFO_EMPTY_INT_ST: u1,
-                ///  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-                PARITY_ERR_INT_ST: u1,
-                ///  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-                FRM_ERR_INT_ST: u1,
-                ///  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-                RXFIFO_OVF_INT_ST: u1,
-                ///  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-                DSR_CHG_INT_ST: u1,
-                ///  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-                CTS_CHG_INT_ST: u1,
-                ///  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-                BRK_DET_INT_ST: u1,
-                ///  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-                RXFIFO_TOUT_INT_ST: u1,
-                ///  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-                SW_XON_INT_ST: u1,
-                ///  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-                SW_XOFF_INT_ST: u1,
-                ///  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-                GLITCH_DET_INT_ST: u1,
-                ///  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-                TX_BRK_DONE_INT_ST: u1,
-                ///  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
-                TX_BRK_IDLE_DONE_INT_ST: u1,
-                ///  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-                TX_DONE_INT_ST: u1,
-                ///  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
-                RS485_PARITY_ERR_INT_ST: u1,
-                ///  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
-                RS485_FRM_ERR_INT_ST: u1,
-                ///  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-                RS485_CLASH_INT_ST: u1,
-                ///  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
-                AT_CMD_CHAR_DET_INT_ST: u1,
-                ///  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-                WAKEUP_INT_ST: u1,
-                padding: u12,
-            }),
-            ///  Interrupt enable bits
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  This is the enable bit for rxfifo_full_int_st register.
-                RXFIFO_FULL_INT_ENA: u1,
-                ///  This is the enable bit for txfifo_empty_int_st register.
-                TXFIFO_EMPTY_INT_ENA: u1,
-                ///  This is the enable bit for parity_err_int_st register.
-                PARITY_ERR_INT_ENA: u1,
-                ///  This is the enable bit for frm_err_int_st register.
-                FRM_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rxfifo_ovf_int_st register.
-                RXFIFO_OVF_INT_ENA: u1,
-                ///  This is the enable bit for dsr_chg_int_st register.
-                DSR_CHG_INT_ENA: u1,
-                ///  This is the enable bit for cts_chg_int_st register.
-                CTS_CHG_INT_ENA: u1,
-                ///  This is the enable bit for brk_det_int_st register.
-                BRK_DET_INT_ENA: u1,
-                ///  This is the enable bit for rxfifo_tout_int_st register.
-                RXFIFO_TOUT_INT_ENA: u1,
-                ///  This is the enable bit for sw_xon_int_st register.
-                SW_XON_INT_ENA: u1,
-                ///  This is the enable bit for sw_xoff_int_st register.
-                SW_XOFF_INT_ENA: u1,
-                ///  This is the enable bit for glitch_det_int_st register.
-                GLITCH_DET_INT_ENA: u1,
-                ///  This is the enable bit for tx_brk_done_int_st register.
-                TX_BRK_DONE_INT_ENA: u1,
-                ///  This is the enable bit for tx_brk_idle_done_int_st register.
-                TX_BRK_IDLE_DONE_INT_ENA: u1,
-                ///  This is the enable bit for tx_done_int_st register.
-                TX_DONE_INT_ENA: u1,
-                ///  This is the enable bit for rs485_parity_err_int_st register.
-                RS485_PARITY_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rs485_parity_err_int_st register.
-                RS485_FRM_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rs485_clash_int_st register.
-                RS485_CLASH_INT_ENA: u1,
-                ///  This is the enable bit for at_cmd_char_det_int_st register.
-                AT_CMD_CHAR_DET_INT_ENA: u1,
-                ///  This is the enable bit for uart_wakeup_int_st register.
-                WAKEUP_INT_ENA: u1,
-                padding: u12,
-            }),
-            ///  Interrupt clear bits
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the rxfifo_full_int_raw interrupt.
-                RXFIFO_FULL_INT_CLR: u1,
-                ///  Set this bit to clear txfifo_empty_int_raw interrupt.
-                TXFIFO_EMPTY_INT_CLR: u1,
-                ///  Set this bit to clear parity_err_int_raw interrupt.
-                PARITY_ERR_INT_CLR: u1,
-                ///  Set this bit to clear frm_err_int_raw interrupt.
-                FRM_ERR_INT_CLR: u1,
-                ///  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-                RXFIFO_OVF_INT_CLR: u1,
-                ///  Set this bit to clear the dsr_chg_int_raw interrupt.
-                DSR_CHG_INT_CLR: u1,
-                ///  Set this bit to clear the cts_chg_int_raw interrupt.
-                CTS_CHG_INT_CLR: u1,
-                ///  Set this bit to clear the brk_det_int_raw interrupt.
-                BRK_DET_INT_CLR: u1,
-                ///  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-                RXFIFO_TOUT_INT_CLR: u1,
-                ///  Set this bit to clear the sw_xon_int_raw interrupt.
-                SW_XON_INT_CLR: u1,
-                ///  Set this bit to clear the sw_xoff_int_raw interrupt.
-                SW_XOFF_INT_CLR: u1,
-                ///  Set this bit to clear the glitch_det_int_raw interrupt.
-                GLITCH_DET_INT_CLR: u1,
-                ///  Set this bit to clear the tx_brk_done_int_raw interrupt..
-                TX_BRK_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-                TX_BRK_IDLE_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the tx_done_int_raw interrupt.
-                TX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-                RS485_PARITY_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-                RS485_FRM_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_clash_int_raw interrupt.
-                RS485_CLASH_INT_CLR: u1,
-                ///  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-                AT_CMD_CHAR_DET_INT_CLR: u1,
-                ///  Set this bit to clear the uart_wakeup_int_raw interrupt.
-                WAKEUP_INT_CLR: u1,
-                padding: u12,
-            }),
-            ///  Clock divider configuration
-            CLKDIV: mmio.Mmio(packed struct(u32) {
-                ///  The integral part of the frequency divider factor.
-                CLKDIV: u12,
-                reserved20: u8,
-                ///  The decimal part of the frequency divider factor.
-                FRAG: u4,
-                padding: u8,
-            }),
-            ///  Rx Filter configuration
-            RX_FILT: mmio.Mmio(packed struct(u32) {
-                ///  when input pulse width is lower than this value, the pulse is ignored.
-                GLITCH_FILT: u8,
-                ///  Set this bit to enable Rx signal filter.
-                GLITCH_FILT_EN: u1,
-                padding: u23,
-            }),
-            ///  UART status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Stores the byte number of valid data in Rx-FIFO.
-                RXFIFO_CNT: u10,
-                reserved13: u3,
-                ///  The register represent the level value of the internal uart dsr signal.
-                DSRN: u1,
-                ///  This register represent the level value of the internal uart cts signal.
-                CTSN: u1,
-                ///  This register represent the level value of the internal uart rxd signal.
-                RXD: u1,
-                ///  Stores the byte number of data in Tx-FIFO.
-                TXFIFO_CNT: u10,
-                reserved29: u3,
-                ///  This bit represents the level of the internal uart dtr signal.
-                DTRN: u1,
-                ///  This bit represents the level of the internal uart rts signal.
-                RTSN: u1,
-                ///  This bit represents the level of the internal uart txd signal.
-                TXD: u1,
-            }),
-            ///  a
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the parity check mode.
-                PARITY: u1,
-                ///  Set this bit to enable uart parity check.
-                PARITY_EN: u1,
-                ///  This register is used to set the length of data.
-                BIT_NUM: u2,
-                ///  This register is used to set the length of stop bit.
-                STOP_BIT_NUM: u2,
-                ///  This register is used to configure the software rts signal which is used in software flow control.
-                SW_RTS: u1,
-                ///  This register is used to configure the software dtr signal which is used in software flow control.
-                SW_DTR: u1,
-                ///  Set this bit to enbale transmitter to send NULL when the process of sending data is done.
-                TXD_BRK: u1,
-                ///  Set this bit to enable IrDA loopback mode.
-                IRDA_DPLX: u1,
-                ///  This is the start enable bit for IrDA transmitter.
-                IRDA_TX_EN: u1,
-                ///  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
-                IRDA_WCTL: u1,
-                ///  Set this bit to invert the level of IrDA transmitter.
-                IRDA_TX_INV: u1,
-                ///  Set this bit to invert the level of IrDA receiver.
-                IRDA_RX_INV: u1,
-                ///  Set this bit to enable uart loopback test mode.
-                LOOPBACK: u1,
-                ///  Set this bit to enable flow control function for transmitter.
-                TX_FLOW_EN: u1,
-                ///  Set this bit to enable IrDA protocol.
-                IRDA_EN: u1,
-                ///  Set this bit to reset the uart receive-FIFO.
-                RXFIFO_RST: u1,
-                ///  Set this bit to reset the uart transmit-FIFO.
-                TXFIFO_RST: u1,
-                ///  Set this bit to inverse the level value of uart rxd signal.
-                RXD_INV: u1,
-                ///  Set this bit to inverse the level value of uart cts signal.
-                CTS_INV: u1,
-                ///  Set this bit to inverse the level value of uart dsr signal.
-                DSR_INV: u1,
-                ///  Set this bit to inverse the level value of uart txd signal.
-                TXD_INV: u1,
-                ///  Set this bit to inverse the level value of uart rts signal.
-                RTS_INV: u1,
-                ///  Set this bit to inverse the level value of uart dtr signal.
-                DTR_INV: u1,
-                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                ///  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.
-                ERR_WR_MASK: u1,
-                ///  This is the enable bit for detecting baudrate.
-                AUTOBAUD_EN: u1,
-                ///  UART memory clock gate enable signal.
-                MEM_CLK_EN: u1,
-                padding: u3,
-            }),
-            ///  Configuration register 1
-            CONF1: mmio.Mmio(packed struct(u32) {
-                ///  It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
-                RXFIFO_FULL_THRHD: u9,
-                ///  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
-                TXFIFO_EMPTY_THRHD: u9,
-                ///  Disable UART Rx data overflow detect.
-                DIS_RX_DAT_OVF: u1,
-                ///  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-                RX_TOUT_FLOW_DIS: u1,
-                ///  This is the flow enable bit for UART receiver.
-                RX_FLOW_EN: u1,
-                ///  This is the enble bit for uart receiver's timeout function.
-                RX_TOUT_EN: u1,
-                padding: u10,
-            }),
-            ///  Autobaud minimum low pulse duration register
-            LOWPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
-                MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud minimum high pulse duration register
-            HIGHPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
-                MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud edge change count register
-            RXD_CNT: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the count of rxd edge change. It is used in baud rate-detect process.
-                RXD_EDGE_CNT: u10,
-                padding: u22,
-            }),
-            ///  Software flow-control configuration
-            FLOW_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
-                SW_FLOW_CON_EN: u1,
-                ///  Set this bit to remove flow control char from the received data.
-                XONOFF_DEL: u1,
-                ///  Set this bit to enable the transmitter to go on sending data.
-                FORCE_XON: u1,
-                ///  Set this bit to stop the transmitter from sending data.
-                FORCE_XOFF: u1,
-                ///  Set this bit to send Xon char. It is cleared by hardware automatically.
-                SEND_XON: u1,
-                ///  Set this bit to send Xoff char. It is cleared by hardware automatically.
-                SEND_XOFF: u1,
-                padding: u26,
-            }),
-            ///  Sleep-mode configuration
-            SLEEP_CONF: mmio.Mmio(packed struct(u32) {
-                ///  The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
-                ACTIVE_THRESHOLD: u10,
-                padding: u22,
-            }),
-            ///  Software flow-control character configuration
-            SWFC_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
-                XOFF_THRESHOLD: u9,
-                ///  This register stores the Xoff flow control char.
-                XOFF_CHAR: u8,
-                padding: u15,
-            }),
-            ///  Software flow-control character configuration
-            SWFC_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
-                XON_THRESHOLD: u9,
-                ///  This register stores the Xon flow control char.
-                XON_CHAR: u8,
-                padding: u15,
-            }),
-            ///  Tx Break character configuration
-            TXBRK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
-                TX_BRK_NUM: u8,
-                padding: u24,
-            }),
-            ///  Frame-end idle configuration
-            IDLE_CONF: mmio.Mmio(packed struct(u32) {
-                ///  It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
-                RX_IDLE_THRHD: u10,
-                ///  This register is used to configure the duration time between transfers.
-                TX_IDLE_NUM: u10,
-                padding: u12,
-            }),
-            ///  RS485 mode configuration
-            RS485_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to choose the rs485 mode.
-                RS485_EN: u1,
-                ///  Set this bit to delay the stop bit by 1 bit.
-                DL0_EN: u1,
-                ///  Set this bit to delay the stop bit by 1 bit.
-                DL1_EN: u1,
-                ///  Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
-                RS485TX_RX_EN: u1,
-                ///  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-                RS485RXBY_TX_EN: u1,
-                ///  This register is used to delay the receiver's internal data signal.
-                RS485_RX_DLY_NUM: u1,
-                ///  This register is used to delay the transmitter's internal data signal.
-                RS485_TX_DLY_NUM: u4,
-                padding: u22,
-            }),
-            ///  Pre-sequence timing configuration
-            AT_CMD_PRECNT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the idle duration time before the first at_cmd is received by receiver.
-                PRE_IDLE_NUM: u16,
-                padding: u16,
-            }),
-            ///  Post-sequence timing configuration
-            AT_CMD_POSTCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the duration time between the last at_cmd and the next data.
-                POST_IDLE_NUM: u16,
-                padding: u16,
-            }),
-            ///  Timeout configuration
-            AT_CMD_GAPTOUT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the duration time between the at_cmd chars.
-                RX_GAP_TOUT: u16,
-                padding: u16,
-            }),
-            ///  AT escape sequence detection configuration
-            AT_CMD_CHAR: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the content of at_cmd char.
-                AT_CMD_CHAR: u8,
-                ///  This register is used to configure the num of continuous at_cmd chars received by receiver.
-                CHAR_NUM: u8,
-                padding: u16,
-            }),
-            ///  UART threshold and allocation configuration
-            MEM_CONF: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
-                RX_SIZE: u3,
-                ///  This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
-                TX_SIZE: u3,
-                ///  This register is used to configure the maximum amount of data that can be received when hardware flow control works.
-                RX_FLOW_THRHD: u9,
-                ///  This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
-                RX_TOUT_THRHD: u10,
-                ///  Set this bit to force power down UART memory.
-                MEM_FORCE_PD: u1,
-                ///  Set this bit to force power up UART memory.
-                MEM_FORCE_PU: u1,
-                padding: u4,
-            }),
-            ///  Tx-FIFO write and read offset address.
-            MEM_TX_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
-                APB_TX_WADDR: u10,
-                reserved11: u1,
-                ///  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
-                TX_RADDR: u10,
-                padding: u11,
-            }),
-            ///  Rx-FIFO write and read offset address.
-            MEM_RX_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-                APB_RX_RADDR: u10,
-                reserved11: u1,
-                ///  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-                RX_WADDR: u10,
-                padding: u11,
-            }),
-            ///  UART transmit and receive status.
-            FSM_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This is the status register of receiver.
-                ST_URX_OUT: u4,
-                ///  This is the status register of transmitter.
-                ST_UTX_OUT: u4,
-                padding: u24,
-            }),
-            ///  Autobaud high pulse register
-            POSPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
-                POSEDGE_MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud low pulse register
-            NEGPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
-                NEGEDGE_MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  UART core clock configuration
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  The denominator of the frequency divider factor.
-                SCLK_DIV_B: u6,
-                ///  The numerator of the frequency divider factor.
-                SCLK_DIV_A: u6,
-                ///  The integral part of the frequency divider factor.
-                SCLK_DIV_NUM: u8,
-                ///  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-                SCLK_SEL: u2,
-                ///  Set this bit to enable UART Tx/Rx clock.
-                SCLK_EN: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Tx/Rx.
-                RST_CORE: u1,
-                ///  Set this bit to enable UART Tx clock.
-                TX_SCLK_EN: u1,
-                ///  Set this bit to enable UART Rx clock.
-                RX_SCLK_EN: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Tx.
-                TX_RST_CORE: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Rx.
-                RX_RST_CORE: u1,
-                padding: u4,
-            }),
-            ///  UART Version register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  This is the version register.
-                DATE: u32,
-            }),
-            ///  UART ID register
-            ID: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the uart_id.
-                ID: u30,
-                ///  This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
-                HIGH_SPEED: u1,
-                ///  Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
-                REG_UPDATE: u1,
-            }),
-        };
-
-        ///  Full-speed USB Serial/JTAG Controller
-        pub const USB_DEVICE = extern struct {
-            ///  USB_DEVICE_EP1_REG.
-            EP1: mmio.Mmio(packed struct(u32) {
-                ///  Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
-                RDWR_BYTE: u8,
-                padding: u24,
-            }),
-            ///  USB_DEVICE_EP1_CONF_REG.
-            EP1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to indicate writing byte data to UART Tx FIFO is done.
-                WR_DONE: u1,
-                ///  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
-                SERIAL_IN_EP_DATA_FREE: u1,
-                ///  1'b1: Indicate there is data in UART Rx FIFO.
-                SERIAL_OUT_EP_DATA_AVAIL: u1,
-                padding: u29,
-            }),
-            ///  USB_DEVICE_INT_RAW_REG.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
-                JTAG_IN_FLUSH_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when SOF frame is received.
-                SOF_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
-                SERIAL_OUT_RECV_PKT_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-                SERIAL_IN_EMPTY_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when pid error is detected.
-                PID_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when CRC5 error is detected.
-                CRC5_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when CRC16 error is detected.
-                CRC16_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when stuff error is detected.
-                STUFF_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
-                IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when usb bus reset is detected.
-                USB_BUS_RESET_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
-                OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
-                OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_ST_REG.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
-                SOF_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_ENA_REG.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
-                SOF_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_CLR_REG.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
-                SOF_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_CONF0_REG.
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  Select internal/external PHY
-                PHY_SEL: u1,
-                ///  Enable software control USB D+ D- exchange
-                EXCHG_PINS_OVERRIDE: u1,
-                ///  USB D+ D- exchange
-                EXCHG_PINS: u1,
-                ///  Control single-end input high threshold,1.76V to 2V, step 80mV
-                VREFH: u2,
-                ///  Control single-end input low threshold,0.8V to 1.04V, step 80mV
-                VREFL: u2,
-                ///  Enable software control input threshold
-                VREF_OVERRIDE: u1,
-                ///  Enable software control USB D+ D- pullup pulldown
-                PAD_PULL_OVERRIDE: u1,
-                ///  Control USB D+ pull up.
-                DP_PULLUP: u1,
-                ///  Control USB D+ pull down.
-                DP_PULLDOWN: u1,
-                ///  Control USB D- pull up.
-                DM_PULLUP: u1,
-                ///  Control USB D- pull down.
-                DM_PULLDOWN: u1,
-                ///  Control pull up value.
-                PULLUP_VALUE: u1,
-                ///  Enable USB pad function.
-                USB_PAD_ENABLE: u1,
-                padding: u17,
-            }),
-            ///  USB_DEVICE_TEST_REG.
-            TEST: mmio.Mmio(packed struct(u32) {
-                ///  Enable test of the USB pad
-                ENABLE: u1,
-                ///  USB pad oen in test
-                USB_OE: u1,
-                ///  USB D+ tx value in test
-                TX_DP: u1,
-                ///  USB D- tx value in test
-                TX_DM: u1,
-                padding: u28,
-            }),
-            ///  USB_DEVICE_JFIFO_ST_REG.
-            JFIFO_ST: mmio.Mmio(packed struct(u32) {
-                ///  JTAT in fifo counter.
-                IN_FIFO_CNT: u2,
-                ///  1: JTAG in fifo is empty.
-                IN_FIFO_EMPTY: u1,
-                ///  1: JTAG in fifo is full.
-                IN_FIFO_FULL: u1,
-                ///  JTAT out fifo counter.
-                OUT_FIFO_CNT: u2,
-                ///  1: JTAG out fifo is empty.
-                OUT_FIFO_EMPTY: u1,
-                ///  1: JTAG out fifo is full.
-                OUT_FIFO_FULL: u1,
-                ///  Write 1 to reset JTAG in fifo.
-                IN_FIFO_RESET: u1,
-                ///  Write 1 to reset JTAG out fifo.
-                OUT_FIFO_RESET: u1,
-                padding: u22,
-            }),
-            ///  USB_DEVICE_FRAM_NUM_REG.
-            FRAM_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Frame index of received SOF frame.
-                SOF_FRAME_INDEX: u11,
-                padding: u21,
-            }),
-            ///  USB_DEVICE_IN_EP0_ST_REG.
-            IN_EP0_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 0.
-                IN_EP0_STATE: u2,
-                ///  Write data address of IN endpoint 0.
-                IN_EP0_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 0.
-                IN_EP0_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP1_ST_REG.
-            IN_EP1_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 1.
-                IN_EP1_STATE: u2,
-                ///  Write data address of IN endpoint 1.
-                IN_EP1_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 1.
-                IN_EP1_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP2_ST_REG.
-            IN_EP2_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 2.
-                IN_EP2_STATE: u2,
-                ///  Write data address of IN endpoint 2.
-                IN_EP2_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 2.
-                IN_EP2_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP3_ST_REG.
-            IN_EP3_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 3.
-                IN_EP3_STATE: u2,
-                ///  Write data address of IN endpoint 3.
-                IN_EP3_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 3.
-                IN_EP3_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_OUT_EP0_ST_REG.
-            OUT_EP0_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 0.
-                OUT_EP0_STATE: u2,
-                ///  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-                OUT_EP0_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 0.
-                OUT_EP0_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_OUT_EP1_ST_REG.
-            OUT_EP1_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 1.
-                OUT_EP1_STATE: u2,
-                ///  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-                OUT_EP1_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 1.
-                OUT_EP1_RD_ADDR: u7,
-                ///  Data count in OUT endpoint 1 when one packet is received.
-                OUT_EP1_REC_DATA_CNT: u7,
-                padding: u9,
-            }),
-            ///  USB_DEVICE_OUT_EP2_ST_REG.
-            OUT_EP2_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 2.
-                OUT_EP2_STATE: u2,
-                ///  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-                OUT_EP2_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 2.
-                OUT_EP2_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_MISC_CONF_REG.
-            MISC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  USB_DEVICE_MEM_CONF_REG.
-            MEM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  1: power down usb memory.
-                USB_MEM_PD: u1,
-                ///  1: Force clock on for usb memory.
-                USB_MEM_CLK_EN: u1,
-                padding: u30,
-            }),
-            reserved128: [52]u8,
-            ///  USB_DEVICE_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  register version.
-                DATE: u32,
-            }),
-        };
-
-        ///  Universal Host Controller Interface
-        pub const UHCI0 = extern struct {
-            ///  a
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  Write 1, then write 0 to this bit to reset decode state machine.
-                TX_RST: u1,
-                ///  Write 1, then write 0 to this bit to reset encode state machine.
-                RX_RST: u1,
-                ///  Set this bit to link up HCI and UART0.
-                UART0_CE: u1,
-                ///  Set this bit to link up HCI and UART1.
-                UART1_CE: u1,
-                reserved5: u1,
-                ///  Set this bit to separate the data frame using a special char.
-                SEPER_EN: u1,
-                ///  Set this bit to encode the data packet with a formatting header.
-                HEAD_EN: u1,
-                ///  Set this bit to enable UHCI to receive the 16 bit CRC.
-                CRC_REC_EN: u1,
-                ///  If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
-                UART_IDLE_EOF_EN: u1,
-                ///  If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
-                LEN_EOF_EN: u1,
-                ///  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
-                ENCODE_CRC_EN: u1,
-                ///  1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                ///  If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
-                UART_RX_BRK_EOF_EN: u1,
-                padding: u19,
-            }),
-            ///  a
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_RAW: u1,
-                ///  a
-                TX_START_INT_RAW: u1,
-                ///  a
-                RX_HUNG_INT_RAW: u1,
-                ///  a
-                TX_HUNG_INT_RAW: u1,
-                ///  a
-                SEND_S_REG_Q_INT_RAW: u1,
-                ///  a
-                SEND_A_REG_Q_INT_RAW: u1,
-                ///  This is the interrupt raw bit. Triggered when there are some errors in EOF in the
-                OUT_EOF_INT_RAW: u1,
-                ///  Soft control int raw bit.
-                APP_CTRL0_INT_RAW: u1,
-                ///  Soft control int raw bit.
-                APP_CTRL1_INT_RAW: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_ST: u1,
-                ///  a
-                TX_START_INT_ST: u1,
-                ///  a
-                RX_HUNG_INT_ST: u1,
-                ///  a
-                TX_HUNG_INT_ST: u1,
-                ///  a
-                SEND_S_REG_Q_INT_ST: u1,
-                ///  a
-                SEND_A_REG_Q_INT_ST: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_ST: u1,
-                ///  a
-                APP_CTRL0_INT_ST: u1,
-                ///  a
-                APP_CTRL1_INT_ST: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_ENA: u1,
-                ///  a
-                TX_START_INT_ENA: u1,
-                ///  a
-                RX_HUNG_INT_ENA: u1,
-                ///  a
-                TX_HUNG_INT_ENA: u1,
-                ///  a
-                SEND_S_REG_Q_INT_ENA: u1,
-                ///  a
-                SEND_A_REG_Q_INT_ENA: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_ENA: u1,
-                ///  a
-                APP_CTRL0_INT_ENA: u1,
-                ///  a
-                APP_CTRL1_INT_ENA: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_CLR: u1,
-                ///  a
-                TX_START_INT_CLR: u1,
-                ///  a
-                RX_HUNG_INT_CLR: u1,
-                ///  a
-                TX_HUNG_INT_CLR: u1,
-                ///  a
-                SEND_S_REG_Q_INT_CLR: u1,
-                ///  a
-                SEND_A_REG_Q_INT_CLR: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_CLR: u1,
-                ///  a
-                APP_CTRL0_INT_CLR: u1,
-                ///  a
-                APP_CTRL1_INT_CLR: u1,
-                padding: u23,
-            }),
-            ///  a
-            CONF1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                CHECK_SUM_EN: u1,
-                ///  a
-                CHECK_SEQ_EN: u1,
-                ///  a
-                CRC_DISABLE: u1,
-                ///  a
-                SAVE_HEAD: u1,
-                ///  a
-                TX_CHECK_SUM_RE: u1,
-                ///  a
-                TX_ACK_NUM_RE: u1,
-                reserved7: u1,
-                ///  a
-                WAIT_SW_START: u1,
-                ///  a
-                SW_START: u1,
-                padding: u23,
-            }),
-            ///  a
-            STATE0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_ERR_CAUSE: u3,
-                ///  a
-                DECODE_STATE: u3,
-                padding: u26,
-            }),
-            ///  a
-            STATE1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ENCODE_STATE: u3,
-                padding: u29,
-            }),
-            ///  a
-            ESCAPE_CONF: mmio.Mmio(packed struct(u32) {
-                ///  a
-                TX_C0_ESC_EN: u1,
-                ///  a
-                TX_DB_ESC_EN: u1,
-                ///  a
-                TX_11_ESC_EN: u1,
-                ///  a
-                TX_13_ESC_EN: u1,
-                ///  a
-                RX_C0_ESC_EN: u1,
-                ///  a
-                RX_DB_ESC_EN: u1,
-                ///  a
-                RX_11_ESC_EN: u1,
-                ///  a
-                RX_13_ESC_EN: u1,
-                padding: u24,
-            }),
-            ///  a
-            HUNG_CONF: mmio.Mmio(packed struct(u32) {
-                ///  a
-                TXFIFO_TIMEOUT: u8,
-                ///  a
-                TXFIFO_TIMEOUT_SHIFT: u3,
-                ///  a
-                TXFIFO_TIMEOUT_ENA: u1,
-                ///  a
-                RXFIFO_TIMEOUT: u8,
-                ///  a
-                RXFIFO_TIMEOUT_SHIFT: u3,
-                ///  a
-                RXFIFO_TIMEOUT_ENA: u1,
-                padding: u8,
-            }),
-            ///  a
-            ACK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ACK_NUM: u3,
-                ///  a
-                LOAD: u1,
-                padding: u28,
-            }),
-            ///  a
-            RX_HEAD: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_HEAD: u32,
-            }),
-            ///  a
-            QUICK_SENT: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SINGLE_SEND_NUM: u3,
-                ///  a
-                SINGLE_SEND_EN: u1,
-                ///  a
-                ALWAYS_SEND_NUM: u3,
-                ///  a
-                ALWAYS_SEND_EN: u1,
-                padding: u24,
-            }),
-            ///  a
-            REG_Q0_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q0_WORD0: u32,
-            }),
-            ///  a
-            REG_Q0_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q0_WORD1: u32,
-            }),
-            ///  a
-            REG_Q1_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q1_WORD0: u32,
-            }),
-            ///  a
-            REG_Q1_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q1_WORD1: u32,
-            }),
-            ///  a
-            REG_Q2_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q2_WORD0: u32,
-            }),
-            ///  a
-            REG_Q2_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q2_WORD1: u32,
-            }),
-            ///  a
-            REG_Q3_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q3_WORD0: u32,
-            }),
-            ///  a
-            REG_Q3_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q3_WORD1: u32,
-            }),
-            ///  a
-            REG_Q4_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q4_WORD0: u32,
-            }),
-            ///  a
-            REG_Q4_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q4_WORD1: u32,
-            }),
-            ///  a
-            REG_Q5_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q5_WORD0: u32,
-            }),
-            ///  a
-            REG_Q5_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q5_WORD1: u32,
-            }),
-            ///  a
-            REG_Q6_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q6_WORD0: u32,
-            }),
-            ///  a
-            REG_Q6_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q6_WORD1: u32,
-            }),
-            ///  a
-            ESC_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEPER_CHAR: u8,
-                ///  a
-                SEPER_ESC_CHAR0: u8,
-                ///  a
-                SEPER_ESC_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ0: u8,
-                ///  a
-                ESC_SEQ0_CHAR0: u8,
-                ///  a
-                ESC_SEQ0_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF2: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ1: u8,
-                ///  a
-                ESC_SEQ1_CHAR0: u8,
-                ///  a
-                ESC_SEQ1_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF3: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ2: u8,
-                ///  a
-                ESC_SEQ2_CHAR0: u8,
-                ///  a
-                ESC_SEQ2_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            PKT_THRES: mmio.Mmio(packed struct(u32) {
-                ///  a
-                PKT_THRS: u13,
-                padding: u19,
-            }),
-            ///  a
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  a
-                DATE: u32,
-            }),
-        };
-    };
-};
diff --git a/src/cpus.zig b/src/cpus.zig
deleted file mode 100644
index c8bda91..0000000
--- a/src/cpus.zig
+++ /dev/null
@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Cpu{
-    .name = "Espressif RISC-V",
-    .source = .{
-        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .riscv32,
-        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-        .cpu_features_add = std.Target.riscv.featureSet(&.{
-            std.Target.riscv.Feature.c,
-            std.Target.riscv.Feature.m,
-        }),
-        .os_tag = .freestanding,
-        .abi = .eabi,
-    },
-};

From 2fb0b5eeca59b381bfea1c536a1564b1a3d7fa0b Mon Sep 17 00:00:00 2001
From: Yerlan 
Date: Sat, 23 Sep 2023 13:55:50 +0200
Subject: [PATCH 29/29] Update README.adoc for Zig 0.11 release (#29)

Zig 0.11 was released.
I guess it makes sense to update the readme.
Looking at microzig, it looks like 0.11 is the supported version.
---
 README.adoc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 4123f3c..d1a8bf8 100644
--- a/README.adoc
+++ b/README.adoc
@@ -6,4 +6,4 @@ SVD is copied from https://github.com/esp-rs/esp-pacs
 
 == What version of Zig to use
 
-Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+0.11.0