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87 lines
2.7 KiB
Markdown
87 lines
2.7 KiB
Markdown
3 years ago
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# regz
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regz is a Zig code generator for microcontrollers. Vendors often publish files
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that have the details of special function registers, for ARM this is called a
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"System View Description" (SVD), and this tool outputs a single file for you to
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start interacting with the hardware:
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```zig
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const regs = @import("nrf52.zig").registers;
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pub fn main() void {
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regs.P0.PIN_CNF[17].modify(.{
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.DIR = 1,
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.INPUT = 1,
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.PULL = 0,
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.DRIVE = 0,
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.SENSE = 0,
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});
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regs.P0.OUT.modify(.{ .PIN17 = 1 });
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}
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```
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NOTE: just including that file is not enough to run code on a microcontroller,
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this is a fairly low-level tool and it is intended that the generated code be
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used with [microzig](https://github.com/ZigEmbeddedGroup/microzig)
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One can get the required SVD file from your vendor, or another good place is
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[posborne/cmsis-svd](https://github.com/posborne/cmsis-svd/tree/master/data),
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it's a python based SVD parser and they have a large number of files available.
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## Building
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regz targets zig master.
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```
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git clone --recursive https://github.com/ZigEmbeddedGroup/regz.git
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zig build
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```
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## Using regz to generate code
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Provide path on command line:
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```
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regz <path-to-svd> > my-chip.zig
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```
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Provide schema via stdin, must specify the schema type:
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```
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cat my-file.svd | regz --schema svd > my-chip.zig
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```
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### Does this work for RISC-V?
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It seems that manufacturers are using SVD to represent registers on their
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RISC-V based products despite it being an ARM standard. At best regz will
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generate the register definitions without an interrupt table (for now), if you
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run into problems issues will be warmly welcomed!
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### How about AVR?
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Atmel/Microchip publishes their register definitions for AVRs in ATDF, it is
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not implemented, but we do plan on supporting it. There are tools like
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[Rahix/atdf2svd](https://github.com/Rahix/atdf2svd) if you really can't wait to
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get your hands dirty.
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### What about MSP430?
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TI does have another type of XML-based register schema, it is also
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unimplemented but planned for support.
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### Okay but I want [some other architecture/format]
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The main idea is to target what LLVM can target, however Zig's C backend in
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underway so it's likely more exotic architectures could be reached in the
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future. If you know of any others we should look into, please make an issue!
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## Roadmap
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- SVD: mostly implemented and usable for mosts MCUs, but a few finishing touches in order to suss out any bugs:
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- [ ] nested clusters
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- [ ] order generated exactly as defined in schema
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- [ ] finalize derivation of different components
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- [ ] comprehensive suite of tests
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- [ ] RISC-V interrupt table generation
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- [ ] ATDF: Atmel's register schema format
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- [ ] insert name of Texus Insturment's register schema format for MSP430
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