From d7b3cda3f7702f2c9e187beeba202c7343858d18 Mon Sep 17 00:00:00 2001
From: ElicMagus <nikmaos@nikmaos.ru>
Date: Wed, 8 Feb 2023 22:17:56 +0300
Subject: [PATCH] DRAM Init

---
 Cargo.toml      |  2 +-
 src/dram/mod.rs | 16 ++++++++--------
 src/io/mod.rs   |  4 ++--
 src/main.rs     |  2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Cargo.toml b/Cargo.toml
index a1b766c..0d1977f 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -16,5 +16,5 @@ opt-level = 0
 
 [profile.release]
 panic = "abort"
-opt-level = "s"
+opt-level = "z"
 lto = true
\ No newline at end of file
diff --git a/src/dram/mod.rs b/src/dram/mod.rs
index 05beb2e..d8146c5 100644
--- a/src/dram/mod.rs
+++ b/src/dram/mod.rs
@@ -91,17 +91,17 @@ impl DramPara_t
         }
 
         // Init core, final run
-        // if self.mctl_core_init() == 0 {
+        if self.mctl_core_init() == 0 {
             print!("DRAM initialisation error : 1 !\r\n");
             return 0;
-        // }
+        }
 
         // Get sdram size
         rc = self.dram_para2;
         if rc < 0 {
             rc = (rc & 0x7fff0000u32) >> 16;
         } else {
-            // rc = self.get_size();
+            rc = self.get_size();
             print!("DRAM SIZE = {:?}M\r\n", rc);
             self.dram_para2 = (self.dram_para2 & 0xffffu32) | rc << 16;
         }
@@ -154,12 +154,12 @@ impl DramPara_t
             write32(0x310307c, rc);
         }
 
-        // self.enable_all_master();
+        self.enable_all_master();
         if (self.dram_tpr13 & (1 << 28)) != 0 {
             rc = read32(0x70005d4);
-            // if ((rc & (1 << 16))!=0 || dramc_simple_wr_test(mem_size, 4096))!=0 {
-            //     return 0;
-            // }
+            if ((rc & (1 << 16))!=0 || self.simple_wr_test(mem_size, 4096)!=0) {
+                return 0;
+            }
         }
         mem_size
     }
@@ -1544,7 +1544,7 @@ impl DramPara_t
         sdelay(10);
     }
 
-    fn dramc_simple_wr_test(mem_size: u32, test: u32) -> u32 {
+    fn simple_wr_test(mut self,mem_size: u32, test: u32) -> u32 {
         0u32
     }
  
diff --git a/src/io/mod.rs b/src/io/mod.rs
index 8c15a9e..25b6052 100644
--- a/src/io/mod.rs
+++ b/src/io/mod.rs
@@ -1,4 +1,4 @@
-// #[inline(always)]
+#[inline(always)]
 pub fn write32(addr:u32, value:u32)
 {
     unsafe {        
@@ -6,7 +6,7 @@ pub fn write32(addr:u32, value:u32)
     }
 }
 
-// #[inline(always)]
+#[inline(always)]
 pub fn read32(addr:u32)->u32
 {
     let value:u32;
diff --git a/src/main.rs b/src/main.rs
index af873b2..1cbc724 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -49,7 +49,7 @@ fn main() -> ! {
 	let val  = (1 << 16) | (1 << 0);
 	write32(addr, val);
 	delay();
-    let mut dram=dram::DramPara_t::default();
+    let dram=dram::DramPara_t::default();
     dram.init();
     //мигаем
     loop {