start

.cargo/config

@@ -0,0 +1,9 @@
+# [target.thumbv7em-none-eabihf]
+# [target.armv7r-none-eabihf]
+[target.armv7a-none-eabi]
+rustflags = ["-C", "link-arg=-Tlink.x"]
+
+[build]
+# target = "thumbv7em-none-eabihf"
+target = "armv7a-none-eabi"
+# target = "armv7r-none-eabihf"

.gitignore

@@ -0,0 +1 @@
+/target

123.txt

@@ -0,0 +1 @@
+<EFBFBD>ٌَ<EFBFBD>ٍوي

Cargo.lock

@@ -0,0 +1,23 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "app"
+version = "0.1.0"
+dependencies = [
+ "rt",
+]
+
+[[package]]
+name = "cc"
+version = "1.0.73"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "2fff2a6927b3bb87f9595d67196a70493f627687a71d87a0d692242c33f58c11"
+
+[[package]]
+name = "rt"
+version = "0.1.0"
+dependencies = [
+ "cc",
+]

Cargo.toml

@@ -0,0 +1,20 @@
+[package]
+name = "app"
+version = "0.1.0"
+edition = "2021"
+
+# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
+
+[dependencies]
+rt = { path = "../rt" }
+# volatile-register = "*"
+
+
+[profile.dev]
+panic = "abort"
+opt-level = 0
+
+[profile.release]
+panic = "abort"
+opt-level = "z"
+lto = true

app.asm

@@ -0,0 +1,119 @@
+0x00000000 mrsmi        r0, (UNDEF: 0)
+0x00000004 andmi        r0, r0, ip
+0x00000008 b    0x00000008
+0x0000000c movw r1, #476        ; 0x1dc
+0x00000010 movw r0, #476        ; 0x1dc
+0x00000014 movt r1, #16384      ; 0x4000
+0x00000018 movt r0, #16384      ; 0x4000
+0x0000001c sub  r1, r1, r0
+0x00000020 bl   0x00000050
+0x00000024 movw r1, #476        ; 0x1dc
+0x00000028 movw r0, #476        ; 0x1dc
+0x0000002c movt r1, #16384      ; 0x4000
+0x00000030 movt r0, #16384      ; 0x4000
+0x00000034 sub  r2, r1, r0
+0x00000038 movw r1, #480        ; 0x1e0
+0x0000003c movt r1, #16384      ; 0x4000
+0x00000040 bl   0x0000004c
+0x00000044 bl   0x00000008
+0x00000048 udf  #65006  ; 0xfdee
+0x0000004c b    0x00000054
+0x00000050 b    0x00000068
+0x00000054 b    0x00000070
+0x00000058 mov  r3, r1
+0x0000005c mov  r1, r2
+0x00000060 mov  r2, r3
+0x00000064 b    0x00000158
+0x00000068 mov  r2, #0
+0x0000006c b    0x00000058
+0x00000070 push {r4, r5, r6, r7, r8, r9, sl, lr}
+0x00000074 cmp  r2, #15
+0x00000078 bls  0x00000104
+0x0000007c rsb  r3, r0, #0
+0x00000080 ands r3, r3, #3
+0x00000084 add  ip, r0, r3
+0x00000088 beq  0x000000a4
+0x0000008c mov  r7, r0
+0x00000090 mov  r6, r1
+0x00000094 ldrb r5, [r6], #1
+0x00000098 strb r5, [r7], #1
+0x0000009c cmp  r7, ip
+0x000000a0 bcc  0x00000094
+0x000000a4 sub  lr, r2, r3
+0x000000a8 add  sl, r1, r3
+0x000000ac bic  r9, lr, #3
+0x000000b0 tst  sl, #3
+0x000000b4 add  r3, ip, r9
+0x000000b8 beq  0x00000114
+0x000000bc cmp  r9, #1
+0x000000c0 blt  0x00000130
+0x000000c4 bic  r6, sl, #3
+0x000000c8 mov  r4, #24
+0x000000cc lsl  r8, sl, #3
+0x000000d0 add  r5, r6, #4
+0x000000d4 ldr  r7, [r6]
+0x000000d8 rsb  r6, r8, #0
+0x000000dc and  r4, r4, sl, lsl #3
+0x000000e0 and  r6, r6, #24
+0x000000e4 ldr  r2, [r5], #4
+0x000000e8 lsl  r1, r2, r6
+0x000000ec orr  r1, r1, r7, lsr r4
+0x000000f0 str  r1, [ip], #4
+0x000000f4 cmp  ip, r3
+0x000000f8 mov  r7, r2
+0x000000fc bcc  0x000000e4
+0x00000100 b    0x00000130
+0x00000104 mov  r3, r0
+0x00000108 cmp  r2, #0
+0x0000010c bne  0x00000140
+0x00000110 b    0x00000154
+0x00000114 cmp  r9, #1
+0x00000118 blt  0x00000130
+0x0000011c mov  r4, sl
+0x00000120 ldr  r1, [r4], #4
+0x00000124 str  r1, [ip], #4
+0x00000128 cmp  ip, r3
+0x0000012c bcc  0x00000120
+0x00000130 add  r1, sl, r9
+0x00000134 and  r2, lr, #3
+0x00000138 cmp  r2, #0
+0x0000013c beq  0x00000154
+0x00000140 add  r2, r3, r2
+0x00000144 ldrb r7, [r1], #1
+0x00000148 strb r7, [r3], #1
+0x0000014c cmp  r3, r2
+0x00000150 bcc  0x00000144
+0x00000154 pop  {r4, r5, r6, r7, r8, r9, sl, pc}
+0x00000158 push {r4, lr}
+0x0000015c cmp  r2, #15
+0x00000160 bls  0x000001bc
+0x00000164 rsb  r3, r0, #0
+0x00000168 ands lr, r3, #3
+0x0000016c add  ip, r0, lr
+0x00000170 beq  0x00000184
+0x00000174 mov  r3, r0
+0x00000178 strb r1, [r3], #1
+0x0000017c cmp  r3, ip
+0x00000180 bcc  0x00000178
+0x00000184 sub  lr, r2, lr
+0x00000188 bic  r2, lr, #3
+0x0000018c add  r3, ip, r2
+0x00000190 cmp  r2, #1
+0x00000194 blt  0x000001b4
+0x00000198 movw r4, #257        ; 0x101
+0x0000019c uxtb r2, r1
+0x000001a0 movt r4, #257        ; 0x101
+0x000001a4 mul  r2, r2, r4
+0x000001a8 str  r2, [ip], #4
+0x000001ac cmp  ip, r3
+0x000001b0 bcc  0x000001a8
+0x000001b4 and  r2, lr, #3
+0x000001b8 b    0x000001c0
+0x000001bc mov  r3, r0
+0x000001c0 cmp  r2, #0
+0x000001c4 popeq        {r4, pc}
+0x000001c8 add  r2, r3, r2
+0x000001cc strb r1, [r3], #1
+0x000001d0 cmp  r3, r2
+0x000001d4 bcc  0x000001cc
+0x000001d8 pop  {r4, pc}

build.bat

@@ -0,0 +1,8 @@
+cd ../rt
+cargo clean
+cd ../app
+cargo clean
+@REM cargo build --release
+cargo objcopy --bin app --target armv7a-none-eabi --release -- -O binary app.bin
+@REM cargo objcopy --bin app --target thumbv7em-none-eabihf --release -- -O binary app.bin
+@REM arm-none-eabi-objdump b:\RUST\AWDev\embed\app\target\armv7a-none-eabi\release\app binary -d

sdclr.bat

@@ -0,0 +1,2 @@
+dd if=/dev/zero of=\\?\Device\Harddisk1\Partition0 bs=1M --progress
+pause

sdwrite.bat

@@ -0,0 +1,4 @@
+FSUTIL file seteof app.bin 32768
+checksum app.bin app.bin
+dd if=app.bin of=\\?\Device\Harddisk3\Partition0 bs=1024 seek=8
+pause

src/clk/mod.rs

@@ -0,0 +1,72 @@
+use crate::{
+    ccu,
+    io::{read32, write32},
+    print,
+};
+
+pub fn set_pll_cpux_axi() {
+    let mut val;
+
+    /* Select cpux clock src to osc24m, axi divide ratio is 3, system apb clk ratio is 4 */
+    write32(
+        ccu::BASE + ccu::CPU_AXI_CFG_REG,
+        (0 << 24) | (3 << 8) | (1 << 0),
+    );
+    // sdelay(1);
+
+    /* Disable pll gating */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val &= !(1 << 27);
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+
+    /* Enable pll ldo */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val |= (1 << 30);
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+    // sdelay(5);
+
+    /* Set default clk to 1008mhz */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val &= !((0x3 << 16) | (0xff << 8) | (0x3 << 0));
+    val |= (41 << 8);
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+
+    /* Lock enable */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val |= 1 << 29;
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+
+    /* Enable pll */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val |= 1 << 31;
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+
+    /* Wait pll stable */
+    //while(!(read32(T113_ccu::BASE + ccu::PLL_CPU_CTRL_REG) & (0x1 << 28))); //Си
+    loop {
+        let v = !(read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG) & (0x1 << 28));
+        if v == 0 {
+            print!("Pll is Stable\n");
+            break;
+        }
+    }
+    // sdelay(20);
+
+    /* Enable pll gating */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val |= (1 << 27);
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+
+    /* Lock disable */
+    val = read32(ccu::BASE + ccu::PLL_CPU_CTRL_REG);
+    val &= !(1 << 29);
+    write32(ccu::BASE + ccu::PLL_CPU_CTRL_REG, val);
+    // sdelay(1);
+
+    /* set and change cpu clk src to PLL_CPUX, PLL_CPUX:AXI0 = 1008M:504M */
+    val = read32(ccu::BASE + ccu::CPU_AXI_CFG_REG);
+    val &= !(0x07 << 24 | 0x3 << 16 | 0x3 << 8 | 0xf << 0);
+    val |= (0x03 << 24 | 0x0 << 16 | 0x0 << 8 | 0x1 << 0);
+    write32(ccu::BASE + ccu::CPU_AXI_CFG_REG, val);
+    // sdelay(1);
+}

src/gpio/mod.rs

@@ -0,0 +1,73 @@
+
+
+pub const GPIO_BASE: u32 = 0x0200_0000;
+const MP: u32 = 0x30;
+pub const GPIO_B: u32 = GPIO_BASE + MP * 1;
+pub const GPIO_C: u32 = GPIO_BASE + MP * 2;
+pub const GPIO_D: u32 = GPIO_BASE + MP * 3;
+pub const GPIO_E: u32 = GPIO_BASE + MP * 4;
+pub const GPIO_F: u32 = GPIO_BASE + MP * 5;
+pub const GPIO_G: u32 = GPIO_BASE + MP * 6;
+
+#[derive(Default,Debug)]
+#[repr(C)]
+pub struct GpioRegT {
+    pub cfg: u128,    
+    pub dat: u32, //0-31 pin state; 1 bit per pipn
+    pub drv: u128,    
+    pub pull: u64,    
+}
+
+// #[inline(always)]
+pub fn init(gpio: *mut GpioRegT, pin: u32, cfg: u8) {
+    unsafe {
+        // let mut tmp = core::ptr::read_volatile(&(*gpio).cfg as *const u128);
+        // tmp &=!(0b1111 << (pin * 4));
+        // core::ptr::write_volatile((&(*gpio).cfg as *const _) as *mut _, tmp);
+
+        // let mut tmp = core::ptr::read_volatile(&(*gpio).cfg as *const u128);
+        // tmp |=(cfg as u128) << (pin * 4) ;
+        // core::ptr::write_volatile((&(*gpio).cfg as *const _) as *mut _, tmp);
+
+        (*gpio).cfg &= !(0b1111 << (pin * 4));
+        (*gpio).cfg |= (cfg as u128) << (pin * 4);
+    }
+}
+
+
+pub enum PD22_Select {
+    Input = 0b0000,
+    Output,
+    OwaOut,
+    IrRx,
+    Uart1Rx,
+    Pwm7,
+    PdEint22 = 10,
+    Disable = 0b1111,
+}
+
+pub enum PE3_Select {
+    Input = 0b0000,
+    Output = 0b0001,
+    NCSI0_MCLK = 0b0010,
+    Uart2Rx = 0b0011,
+    TWI0_SDA = 0b0100,
+    ClkFanout1 = 0b0101,
+    Uart0Rx = 0b0110,
+    RMII_TXCK = 0b1000,
+    PE_EINT3 = 0b1110,
+    Disable = 0b1111,
+}
+
+pub enum PE2_Select {
+    Input = 0b0000,
+    Output = 0b0001,
+    NCSI0_PCLK = 0b0010,
+    Uart2Tx = 0b0011,
+    TWI0_SCK = 0b0100,
+    ClkFanout0 = 0b0101,
+    Uart0Tx = 0b0110,
+    RMII_RXD1 = 0b1000,
+    PE_EINT2 = 0b1110,
+    Disable = 0b1111,
+}

src/io/mod.rs

@@ -0,0 +1,17 @@
+#[inline(always)]
+pub fn write32(addr:u32, value:u32)
+{
+    unsafe {        
+        core::ptr::write_volatile(addr as *mut u32, value as u32);
+    }
+}
+
+#[inline(always)]
+pub fn read32(addr:u32)->u32
+{
+    let value:u32;
+    unsafe {        
+        value = core::ptr::read_volatile(addr as *const u32);                
+    }
+    value
+}

src/main.rs

@@ -0,0 +1,70 @@
+#![no_std]
+#![no_main]
+
+use core::panic::PanicInfo;
+extern crate rt;
+
+use rt::entry;
+entry!(main);
+
+use rt::cpu;
+pub mod ccu;
+pub mod clk;
+pub mod gpio;
+pub mod io;
+pub mod print;
+pub mod sdhci;
+pub mod uart;
+
+fn main() -> ! {
+    uart::init();
+    print!("Uart inited\n");
+    // set_sp_base();
+    let gpio_d = gpio::GPIO_D as *mut gpio::GpioRegT;
+    let pin22: u32 = 1 << 22;
+    //инициализация порта D ноги 22
+    gpio::init(gpio_d, 22, gpio::PD22_Select::Output as u8);
+    print!("PD22 inited\n");
+    //мигаем
+    loop {
+        unsafe {
+            (*gpio_d).dat ^= pin22;
+            delay();
+        }
+    }
+}
+
+#[inline(always)]
+fn delay() {
+    let mut rnd_addr = 0u32;
+    let addr = &mut rnd_addr as *mut u32;
+    let mut z: u32 = 10000000;
+    unsafe {
+        // asm!(
+        // "1:",
+        // "subs {0}, {0}, #1",
+        // "bne 1b",
+        // in(reg) i
+        // );
+        while z > 0 {
+            core::ptr::write_volatile(addr, z);
+            z -= 1;
+        }
+    }
+}
+
+#[panic_handler]
+fn panic(info: &PanicInfo<'_>) -> ! {
+    let (location, line, column) = match info.location() {
+        Some(loc) => (loc.file(), loc.line(), loc.column()),
+        _ => ("???", 0, 0),
+    };
+    print!(
+        "Kernel panic!\n\n\
+        Panic location:\n      File '{}', line {}, column {}\n\n\
+    ",
+        location, line, column,
+    );
+    cpu::wfe();
+    loop {}
+}

src/mod.rs

@@ -0,0 +1,6 @@
+pub mod ccu;
+pub mod gpio;
+pub mod uart;
+pub mod print;
+pub mod sdhci;
+pub mod io;

src/print.rs

@@ -0,0 +1,26 @@
+use core::fmt;
+use crate::uart;
+
+pub fn _print(args: fmt::Arguments) {
+    pub use core::fmt::Write;    
+    uart::console().write_fmt(args).unwrap();
+}
+
+/// Prints without a newline.
+///
+/// Carbon copy from <https://doc.rust-lang.org/src/std/macros.rs.html>
+#[macro_export]
+macro_rules! print {
+    ($($arg:tt)*) => ($crate::print::_print(format_args!($($arg)*)));
+}
+
+/// Prints with a newline.
+///
+/// Carbon copy from <https://doc.rust-lang.org/src/std/macros.rs.html>
+#[macro_export]
+macro_rules! println {
+    () => ($crate::print!("\n"));
+    ($($arg:tt)*) => ({
+        $crate::print::_print(format_args_nl!($($arg)*));
+    })
+}

src/sdhci.rs

@@ -0,0 +1,37 @@
+use crate::gpio::{self, GpioRegT};
+
+struct sdhci_cmd_t {
+	cmdidx:u32,
+	cmdarg:u32,
+	resptype:u32,
+	response:[u32;4],
+}
+
+struct sdhci_data_t {
+	buf:*mut u8, //указатель на буфер
+	flag:u32,
+	blksz:u32,
+	blkcnt:u32,
+}
+
+struct sdhci_t
+{
+	name:char, //указатель
+	addr:u32,
+	pclk:u32,
+	reset:u32,
+	voltage:u32,
+	width:u32,
+	clock:u32,
+	removable:bool,
+	isspi:bool,
+
+	gpio_d0:*mut GpioRegT,
+	gpio_d1:*mut GpioRegT,
+	gpio_d2:*mut GpioRegT,
+	gpio_d3:*mut GpioRegT,
+	gpio_cmd:*mut GpioRegT,
+	gpio_clk:*mut GpioRegT,
+
+	sdcard:*mut u32, //адрес по которому хранится структура для SD карты
+}

src/uart/mod.rs

@@ -0,0 +1,131 @@
+
+use crate::ccu;
+use crate::gpio;
+use core::fmt;
+
+pub const UART_BASE: u32 = 0x0250_0000;
+const UART_MX: u32 = 0x400;
+pub const UART_0_BASE: u32 = UART_BASE + UART_MX * 0;
+// pub const UART_1_BASE: u32 = UART_BASE + UART_MX*1;
+// pub const UART_2_BASE: u32 = UART_BASE + UART_MX*2;
+// pub const UART_3_BASE: u32 = UART_BASE + UART_MX*3;
+// pub const UART_4_BASE: u32 = UART_BASE + UART_MX*4;
+// pub const UART_5_BASE: u32 = UART_BASE + UART_MX*5;
+
+// pub const UART_RBR:u32= 0x0000;             //UART Receive Buffer Register
+// pub const UART_THR:u32= 0x0000;             //UART Transmit Holding Register
+// pub const UART_DLL:u32= 0x0000;             //UART Divisor Latch Low Register
+// pub const UART_DLH:u32= 0x0004;             //UART Divisor Latch High Register
+// pub const UART_IER:u32= 0x0004;             //UART Interrupt Enable Register
+// pub const UART_IIR:u32= 0x0008;             //UART Interrupt Identity Register
+// pub const UART_FCR:u32= 0x0008;             //UART FIFO Control Register
+// pub const UART_LCR:u32= 0x000C;             //UART Line Control Register
+// pub const UART_MCR:u32= 0x0010;             //UART Modem Control Register
+// pub const UART_LSR:u32= 0x0014;             //UART Line Status Register
+// pub const UART_MSR:u32= 0x0018;             //UART Modem Status Register
+// pub const UART_SCH:u32= 0x001C;             //UART Scratch Register
+// pub const UART_USR:u32= 0x007C;             //UART Status Register
+// pub const UART_TFL:u32= 0x0080;             //UART Transmit FIFO Level Register
+// pub const UART_RFL:u32= 0x0084;             //UART Receive FIFO Level Register
+// pub const UART_HSK:u32= 0x0088;             //UART DMA Handshake Configuration Register
+// pub const UART_DMA_REQ_EN:u32= 0x008C;      //UART DMA Request Enable Register
+// pub const UART_HALT:u32= 0x00A4;            //UART Halt TX Register
+// pub const UART_DBG_DLL:u32=0x00B0;          //UART Debug DLL Register
+// pub const UART_DBG_DLH:u32=0x00B4;          //UART Debug DLH Register
+// pub const UART_A_FCC:u32=0x00F0;            //UART FIFO Clock Control Register
+// pub const UART_A_RXDMA_CTRL:u32=0x0100;     //UART RXDMA Control Register
+// pub const UART_A_RXDMA_STR:u32=0x0104;      //UART RXDMA Start Register
+// pub const UART_A_RXDMA_STA:u32=0x0108;      //UART RXDMA Status Register
+// pub const UART_A_RXDMA_LMT:u32=0x010C;      //UART RXDMA Limit Register
+// pub const UART_A_RXDMA_SADDRL:u32=0x0110;   //UART RXDMA Buffer Start Address Low Register
+// pub const UART_A_RXDMA_SADDRH:u32=0x0114;   //UART RXDMA Buffer Start Address High Register
+// pub const UART_A_RXDMA_BL:u32=0x0118;       //UART RXDMA Buffer Length Register
+// pub const UART_A_RXDMA_IE:u32=0x0120;       //UART RXDMA Interrupt Enable Register
+// pub const UART_A_RXDMA_IS:u32=0x0124;       //UART RXDMA Interrupt Status Register
+// pub const UART_A_RXDMA_WADDRL:u32=0x0128;   //UART RXDMA Write Address Low Register
+// pub const UART_A_RXDMA_WADDRH:u32=0x012C;   //UART RXDMA Write Address high Register
+// pub const UART_A_RXDMA_RADDRL:u32=0x0130;   //UART RXDMA Read Address Low Register
+// pub const UART_A_RXDMA_RADDRH:u32=0x0134;   //UART RXDMA Read Address high Register
+// pub const UART_A_RXDMA_DCNT:u32=0x0138;     //UART RADMA Data Count Register
+
+#[derive(Default)]
+#[repr(C)]
+pub struct UartRegT;
+
+impl fmt::Write for UartRegT {
+    #[inline(always)]
+    fn write_str(&mut self, s: &str) -> fmt::Result {
+        for c in s.chars() {
+            let addr = (UART_0_BASE + 0x7c) as *mut u32;
+            unsafe {
+                while (core::ptr::read_volatile(addr) & (0x1 << 1)) == 0 {}
+                core::ptr::write_volatile((UART_0_BASE) as *mut u32, c as u32);
+                let addr = (UART_0_BASE + 0x7c) as *mut u32;
+                while core::ptr::read_volatile(addr) & (0x1 << 0) == 1 {}
+            }
+        }
+
+        Ok(())
+    }
+}
+pub fn console() -> impl core::fmt::Write {
+    UartRegT {}
+}
+
+pub fn init() {
+    /* Config usart TXD and RXD pins */
+    let gpio_e = gpio::GPIO_E as *mut gpio::GpioRegT;
+    gpio::init(gpio_e, 2, gpio::PE2_Select::Uart0Tx as u8);
+    gpio::init(gpio_e, 3, gpio::PE3_Select::Uart0Rx as u8);
+
+    /* Open the clock gate for usart */
+    let addr = (ccu::BASE + ccu::USART_BGR_REG) as *mut u32;
+    unsafe {
+        let mut val = core::ptr::read_volatile(addr);
+        val |= 1 << 0;
+        core::ptr::write_volatile(addr, val);
+        /* Deassert USART reset */
+        let mut val = core::ptr::read_volatile(addr);
+        val |= 1 << (16 + 0);
+        core::ptr::write_volatile(addr, val);
+    }
+
+    /* Config USART to 115200-8-1-0 */
+    let addr = (UART_0_BASE + 0x04) as *mut u32;
+    unsafe {
+        core::ptr::write_volatile(addr, 0x0);
+    }
+    let addr = (UART_0_BASE + 0x08) as *mut u32;
+    unsafe {
+        core::ptr::write_volatile(addr, 0xf7);
+    }
+    let addr = (UART_0_BASE + 0x10) as *mut u32;
+    unsafe {
+        core::ptr::write_volatile(addr, 0x0);
+    }
+    let addr = (UART_0_BASE + 0x0c) as *mut u32;
+    unsafe {
+        let mut val = core::ptr::read_volatile(addr);
+        val |= 1 << 7;
+        core::ptr::write_volatile(addr, val);
+    }
+    let addr = (UART_0_BASE + 0x00) as *mut u32;
+    unsafe {
+        core::ptr::write_volatile(addr, 0xd & 0xff);
+    }
+    let addr = (UART_0_BASE + 0x04) as *mut u32;
+    unsafe {
+        core::ptr::write_volatile(addr, (0xd >> 8) & 0xff);
+    }
+
+    let addr = (UART_0_BASE + 0x0c) as *mut u32;
+    unsafe {
+        let mut val = core::ptr::read_volatile(addr);
+        val &= !(1 << 7);
+        core::ptr::write_volatile(addr, val);
+        val = core::ptr::read_volatile(addr);
+        val &= !(0x1f);
+        val |= (0x3 << 0) | (0 << 2) | (0x0 << 3);
+        core::ptr::write_volatile(addr, val);
+    }
+}

xfel.bat

@@ -0,0 +1,6 @@
+@REM xfel ddr t113-s3
+@REM xfel write 0x40000000 xboot.bin
+@REM xfel exec 0x40000000;
+xfel write 0x00028000 app.bin
+xfel exec 0x00028000;
+pause

План.txt

@@ -0,0 +1,11 @@
+1) Инит LED (<=GPIO)
+2) UART
+3) CLK Init (sunxi_clk_init)
+3.1) <=Инит модулей 
+4) какая-то магия перед DRAM Init
+5) DRAM Init
+6) SDHC Init
+7) Монтирование файловой системы
+8) Загрузка ядра в DRAM
+9) Прыг на адрес ядра и старт
+